Updated on 2024/06/24

写真a

 
TANZAWA, Toru
 
Affiliation
Faculty of Science and Engineering, Graduate School of Information, Production, and Systems
Job title
Professor
Degree
Ph. D ( 2002.03 University of Tokyo )

Committee Memberships

  • 2017.06
    -
    2023.05

    電子情報通信学会エレクトロニクスソサエティ  集積回路研究専門委員会 専門委員

  • 2020.11
    -
    2021.07

    電子情報通信学会  集積回路設計技術に関する小特集編集委員会

  • 2013.05
    -
    2019.09

    IEEE ESSCIRC  Technical program committee

Professional Memberships

  •  
     
     

    IEICE

  •  
     
     

    IEEE

Research Areas

  • Electron device and electronic equipment

Research Interests

  • Energy harvesting

  • IoT

  • Circuit design

Awards

  • Test of Time Award

    2023.06   Symposium on VLSI Technology and Circuits  

    Winner: H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi, K. Sakui

  • IEEE Fellow

    2016.01   IEEE  

 

Papers

  • A Low-Power BL Path Design for NAND Flash Based on an Existing NAND Interface

    Hikaru Makino, Toru Tanzawa

    Journal of Low Power Electronics and Applications   14 ( 1 ) 1 - 16  2024.02  [Refereed]

     View Summary

    This paper is an extended version of a previously reported conference paper regarding a low-power design for NAND Flash. As the number of bits per NAND Flash die increases with cost scaling, the IO data path speed increases to minimize the page access time with a scaled CMOS in IOs. The power supply for IO buffers, namely, VDDQ, decreases from 3 V to 1.2 V, accordingly. In this paper, the way in which a reduction in VDDQ can contribute to power reduction in the BL path is discussed and validated. Conventionally, a BL voltage of about 0.5 V has been supplied from a supply voltage source (VDD) of 3 V. The BL path power can be reduced by a factor of VDDQ to VDD when the BL voltage is supplied by VDDQ. To maintain a sense margin at the sense amplifiers, the supply source for BLs is switched from VDDQ to VDD before sensing. As a result, power reduction and an equivalent sense margin can be realized at the same time. The overhead of implementing this operation is an increase in the BL access time of about 2% for switching the power supply from VDDQ to VDD and an increase in the die size of about 0.01% for adding the switching circuit, both of which are not significant in comparison to the significant power reduction in the BL path power of the NAND die of about 60%. The BL path is then designed in 180 nm CMOS to validate the design. When the cost for powering the SSD becomes quite significant, especially for data centers, an additional lower voltage supply, such as 0.8 V, dedicated to BL charging for read and program verifying operations may be the best option for future applications.

    DOI

    Scopus

  • Battery-Assisted Battery Charger with Maximum Power Point Tracking for Thermoelectric Generator: Concept and Experimental Proof

    S. Tanabe, T. Tanzawa

    Electronics   ( 19 )  2023.09  [Refereed]

    DOI

    Scopus

  • A −31.7 dBm Sensitivity 0.011mm2 CMOS On-Chip Rectifier for Microwave Wireless Power Transfer

    Takuma Hashimoto, Hikaru Nekozuka, Yoshitaka Toeda, Masayuki Otani, Yasuhiko Fukuoka, Toru Tanzawa

    Electronics   ( 6 )  2023.03  [Refereed]

    DOI

    Scopus

    1
    Citation
    (Scopus)
  • One-Dimensional Maximum Power Point Tracking Design of Switched-Capacitor Charge Pumps for Thermoelectric Energy Harvesting

    K. Nono, T. Tanzawa

    Electronics   ( 5 )  2023.03  [Refereed]

    DOI

    Scopus

    3
    Citation
    (Scopus)
  • A Charge Loss Aware Advanced Model of Dickson Voltage Multipliers

    Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo, Toru Tanzawa

    IEEE Access   10  2022.11  [Refereed]

    DOI

    Scopus

    8
    Citation
    (Scopus)
  • A Design of a Thermoelectric Energy Harvester for Minimizing Sensor Module Cost

    Koketsu, K., Tanzawa, T.

    Electronics (Switzerland)   11 ( 21 )  2022.10  [Refereed]

    DOI

    Scopus

    3
    Citation
    (Scopus)
  • Design Space Exploration of Antenna Impedance and On-Chip Rectifier for Microwave Wireless Power Transfer

    Hashimoto, T., Tanzawa, T.

    Electronics (Switzerland)   11 ( 19 )  2022.10  [Refereed]

    DOI

    Scopus

    2
    Citation
    (Scopus)
  • More Enhanced Swing Colpitts Oscillators: A Circuit Analysis

    Nomura, T., Tanzawa, T.

    Electronics (Switzerland)   11 ( 18 )  2022.09  [Refereed]

    DOI

    Scopus

  • Pre-Emphasis Pulse Design for Reducing Bit-Line Access Time in NAND Flash Memory

    Kondo, J., Tanzawa, T.

    Electronics (Switzerland)   11 ( 13 ) 1926  2022.06  [Refereed]

    DOI

    Scopus

    1
    Citation
    (Scopus)
  • Design of Switched-Capacitor DC-DC Voltage-Down Converters Driven by Highly Resistive Energy Transducer

    Demura, Y., Tanzawa, T.

    Electronics (Switzerland)   11 ( 12 ) 1874  2022.06  [Refereed]

    DOI

    Scopus

  • An optimum structure of scalable capacitors in 3d crosspoint memory technology

    Tone, Y., Tanzawa, T.

    Electronics (Switzerland)   10 ( 22 ) 2755  2021.11  [Refereed]

    DOI

    Scopus

  • Charge Pumps for Ultra-Low-Power Applications: Analysis, Design, and New Solutions

    Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo, Toru Tanzawa

    IEEE Transactions on Circuits and Systems II: Express Briefs   68 ( 8 )  2021.08  [Refereed]

    DOI

    Scopus

    26
    Citation
    (Scopus)
  • Pre-emphasis pulse design for random-access memory

    Sugiura, Y., Tanzawa, T.

    Electronics (Switzerland)   10 ( 12 )  2021.06  [Refereed]

    DOI

    Scopus

    1
    Citation
    (Scopus)
  • A circuit analysis of pre-emphasis pulses for RC delay lines

    Matsuyama, K., Tanzawa, T.

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   1 ( 6 ) 912 - 926  2021.06  [Refereed]

    DOI

    Scopus

    2
    Citation
    (Scopus)
  • 8
    Citation
    (Scopus)
  • 5
    Citation
    (Scopus)
  • An optimum design of clocked AC-DC charge pump circuits for vibration energy harvesting

    Ye, J., Tanzawa, T.

    Electronics (Switzerland)   9 ( 12 )  2020.12  [Refereed]

    DOI

    Scopus

    3
    Citation
    (Scopus)
  • A fully integrated clocked AC-DC charge pump for mignetostrictive vibration energy harvesting

    Kawauchi, H., Tanzawa, T.

    Electronics (Switzerland)   9 ( 12 )  2020.12  [Refereed]

    DOI

    Scopus

    5
    Citation
    (Scopus)
  • Linear distribution of capacitance in Dickson charge pumps to reduce rise time

    Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo, Toru Tanzawa

    International Journal of Circuit Theory and Applications   48 ( 4 )  2020.04  [Refereed]

    DOI

    Scopus

    20
    Citation
    (Scopus)
  • A Design Window for Device Parameters of Rectifying Diodes in 2.4 GHz Micro-watt RF Energy Harvesting

    Toru Tanzawa

    Proceedings of the Ieee Asia-pacific Microwave Conference (apmc)    2019

  • Toward a Minimum-Operating-Voltage Design of DC-DC Charge Pump Circuits for Energy Harvesting

    Toru Tanzawa

    IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS    2019

    DOI

    Scopus

    8
    Citation
    (Scopus)
  • Design of Pre-Emphasis Pulses for Large Memory Arrays with Minimal Word-Line Delay Time

    Toru Tanzawa

    IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS    2019

  • On the Output Impedance and an Output Current–Power Efficiency Relationship of Dickson Charge Pump Circuits

    Toru Tanzawa

    IEEE Transactions on Circuits and Systems II: Express Briefs   65 ( 11 ) 1664 - 1667  2018.11  [Refereed]

    DOI

    Scopus

    17
    Citation
    (Scopus)
  • Design considerations on power, performance, reliability and yield in 3D NAND technology

    Toru Tanzawa

    IEICE Transactions on Electronics   E101C ( 1 ) 78 - 81  2018.01  [Refereed]

     View Summary

    This paper discusses design challenges and possible solutions for 3D NAND. A 3D NAND array inherently has a larger parasitic capacitance and thereby critical area in terms of product yield. To mitigate such issues associated with 3D NAND technology, array control and divided array architecture for improving reliability and yield and for reducing area overhead, program time, energy per bit and array noise are proposed.

    DOI

    Scopus

    1
    Citation
    (Scopus)
  • An Analytical Model of Charge Pump DC-DC Voltage Multiplier Using Diodes

    Toru Tanzawa

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E100A ( 5 ) 1137 - 1144  2017.05  [Refereed]

     View Summary

    An output voltage - current equation of charge pump DC-DC voltage multiplier using diodes is provided to cover wide clock frequency and output current ranges for designing energy harvester operating at a near-threshold voltage or in sub-threshold region. Equivalent circuits in slow and fast switching limits are extracted. The effective threshold voltage of the diode in slow switching limit is also derived as a function of electrical characteristics of the diodes, such as the saturation current and voltage slope parameter, and design parameters such as the number of stages, capacitance per stage, parasitic capacitance at the top plate of the main boosting capacitor, and the clock frequency. The model is verified compared with SPICE simulation.

    DOI

    Scopus

    7
    Citation
    (Scopus)
  • An Analytical Model of AC-DC Charge Pump Voltage Multipliers

    Toru Tanzawa

    IEICE TRANSACTIONS ON ELECTRONICS   E99C ( 1 ) 108 - 118  2016.01  [Refereed]

     View Summary

    This paper proposes an analytical, closed-form AC-DC voltage multiplier model and investigates the dependency of output current and input power on circuit and device parameters. The model uses no fitting parameters and a frequency term applicable to both multipliers using diodes and metal-oxide semiconductor field effect transistors (MOSFETs). Analysis enables circuit designers to estimate circuit parameters, such as the number of stages and capacitance per stages, and device parameters such as saturation current (in the case of diodes) or transconductance (in the case of MOSFETs). Comparisons of the proposed model with SPICE simulation results as well as other models are also provided for validation. In addition, design optimizations and the impact of AC power source impedance on output power are also investigated.

    DOI

    Scopus

    2
    Citation
    (Scopus)
  • Basics of charge pump circuit

    Tanzawa, T.

    Analog Circuits and Signal Processing    2016

    DOI

    Scopus

  • system overview and key design considerations

    Tanzawa, T.

    Analog Circuits and Signal Processing    2016

    DOI

    Scopus

  • Pump control circuits

    Tanzawa, T.

    Analog Circuits and Signal Processing    2016

    DOI

    Scopus

  • Charge pump state of the art

    Tanzawa, T.

    Analog Circuits and Signal Processing    2016

    DOI

    Scopus

  • Design of ac–dc charge pump

    Tanzawa, T.

    Analog Circuits and Signal Processing    2016

    DOI

    Scopus

  • Design of dc-dc dickson charge pump

    Tanzawa, T.

    Analog Circuits and Signal Processing    2016

    DOI

    Scopus

  • System design

    Tanzawa, T.

    Analog Circuits and Signal Processing    2016

    DOI

    Scopus

  • Preface

    Tanzawa, T.

    Analog Circuits and Signal Processing    2016

  • On-chip High-Voltage Generator Design: Design Methodology for Charge Pumps: Second Edition

    Tanzawa, T.

    On-chip High-Voltage Generator Design: Design Methodology for Charge Pumps: Second Edition    2015

    DOI

    Scopus

    21
    Citation
    (Scopus)
  • A Comprehensive Optimization Methodology for Designing Charge Pump Voltage Multipliers

    Toru Tanzawa

    2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)     1358 - 1361  2015  [Refereed]

     View Summary

    This paper proposes a comprehensive optimization methodology to simultaneously determine the clock frequency, area ratio of pump capacitor to switching circuit, number of stages, and capacitor size of integrated switched-capacitor charge pump voltage multipliers. Power efficiency of the charge pump is also discussed in various views. How the top and bottom plate parasitic capacitance and the threshold voltage of the switching circuit affect power efficiency is reviewed. The optimization methodology is demonstrated. Comparisons of the model with SPICE simulation results are also provided for validation.

  • An Optimum Design for Integrated Switched-Capacitor Dickson Charge Pump Multipliers With Area Power Balance

    Toru Tanzawa

    IEEE TRANSACTIONS ON POWER ELECTRONICS   29 ( 2 ) 534 - 538  2014.02  [Refereed]

     View Summary

    This letter expands upon an optimum design of integrated switched-capacitor Dickson charge pump multipliers for minimizing the power, which considers the parasitic capacitance of both the top and bottom plates of pump capacitors. This letter also discusses an optimum design with area power balance, and suggests that the number of stages should be epsilon N-MIN, where e is 1.5-1.7 and N-MIN is the minimum number of stages required to meet the condition that the output current is zero at a given output voltage.

    DOI

    Scopus

    36
    Citation
    (Scopus)
  • An Analytical Model of AC-DC Voltage Multipliers

    Toru Tanzawa

    2014 21ST IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS)     323 - 326  2014  [Refereed]

     View Summary

    This paper proposes an analytical, closed-form AC-DC voltage multiplier model and investigates the dependency of output current and input power on circuit and device parameters. The model uses no fitting parameters and a frequency term applicable to both multipliers using diodes and metal-oxide semiconductor field effect transistors (MOSFETs). Analysis enables circuit designers to estimate circuit parameters, such as the number of stages and capacitance per stages, and device parameters such as saturation current (in the case of diodes) or transconductance (in the case of MOSFETs). Comparisons of the proposed model with SPICE simulation results as well as other models are also provided for validation.

  • Design of DC-DC Switched-Capacitor Voltage Multiplier driven by DC Energy Transducer

    Toru Tanzawa

    2014 21ST IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS)     327 - 330  2014  [Refereed]

     View Summary

    This paper proposes a model to help designers maximize output power in systems that contain a DC energy transducer and a DC-DC multiplier charge pump by identifying initial circuit and device parameter estimates for SPICE simulations. This model also enables designers to use simple equations to estimate the sensitivity of the DC transducer's characteristic parameters, like short circuit current and output impedance, on the charge pump's output power.

  • On-chip High-Voltage Generator Design

    Tanzawa, T.

    On-chip High-Voltage Generator Design    2013

    DOI

    Scopus

    8
    Citation
    (Scopus)
  • A Behavior Model of an On-Chip High Voltage Generator for Fast, System-Level Simulation

    Toru Tanzawa

    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS   20 ( 12 ) 2351 - 2355  2012.12  [Refereed]

     View Summary

    This brief discusses modeling of a high-voltage generator, including a charge pump circuit and a regulator for accelerating system-level simulations. Event-driven simulators become slow when hard switching frequently occurs to enable charge pump circuits even with a conventional model. A current mirror is added to the pump model and is connected to an output node of a comparator in the voltage detector to make every node in the feedback loop fully analog. Simulation results show that the simulation time for voltage generators' system is reduced by a factor of about 10 with an error of 5% in comparison with the conventional model.

    DOI

    Scopus

    12
    Citation
    (Scopus)
  • A Switch-Resistance-Aware Dickson Charge Pump Model for Optimizing Clock Frequency

    Toru Tanzawa

    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS   58 ( 6 ) 336 - 340  2011.06  [Refereed]

     View Summary

    This brief proposes an explicit Dickson charge pump model, including the effect of the resistance of switching devices on the pump performance. Using this model, one can estimate an optimum clock frequency and the size of the transferring transistors in terms of the main pump capacitors, the auxiliary capacitors, and the transfer transistors to maximize the output current under the same silicon area in a given technology.

    DOI

    Scopus

    36
    Citation
    (Scopus)
  • A Program Disturb Model and Channel Leakage Current Study for Sub-20 nm NAND Flash Cells

    Alessandro Torsi, Yijie Zhao, Haitao Liu, Toru Tanzawa, Akira Goda, Pranav Kalavade, Krishna Parat

    IEEE TRANSACTIONS ON ELECTRON DEVICES   58 ( 1 ) 11 - 16  2011.01  [Refereed]

     View Summary

    We have developed a program-disturb model to characterize the channel potential of the program-inhibited string during NAND flash cell programming. This model includes cell-to-cell capacitances from 3-D technology computer-aided design simulation and leakage currents associated with the boosted channel. We studied the program-disturb characteristics of sub-30-nm NAND cells using a delayed programming pulse method. The simulation results agree with the experimental data very well and show quantitative impacts of junction leakage current, band-to-band tunneling (BTBT) current, Fowler-Nordheim tunneling current, and channel capacitance on the program disturb. We further discuss the cell-scaling trend and identify that the BTBT current can be a dominant mechanism for the program disturb of sub-20-nm NAND cells.

    DOI

    Scopus

    42
    Citation
    (Scopus)
  • On Two-Phase Switched-Capacitor Multipliers With Minimum Circuit Area

    Toru Tanzawa

    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS   57 ( 10 ) 2602 - 2608  2010.10  [Refereed]

     View Summary

    This paper compares the performance among two-phase switched-capacitor multipliers to identify the optimum topology with the smallest circuit area. The optimum number of stages is calculated for every multiplier to minimize the circuit area under the condition that a certain current is outputted with a given output voltage. Then, the circuit areas of the serial-parallel, linear (LIN), Fibonacci, and 2(N) multipliers are compared. Results show that the LIN cell is the best for integration because of the smallest total capacitor area and the highest current efficiency under the assumption that the parasitic capacitance is not smaller than 10% of the multiplier capacitance, and the Fibonacci cell is the best for discrete application because of the minimum number of capacitor components with moderate current efficiency under the assumption that the parasitic capacitance is not larger than 1% of the multiplier capacitance.

    DOI

    Scopus

    47
    Citation
    (Scopus)
  • A Behavior Model of a Dickson Charge Pump Circuit for Designing a Multiple Charge Pump System Distributed in LSIs

    Toru Tanzawa

    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS   57 ( 7 ) 527 - 530  2010.07  [Refereed]

     View Summary

    This brief discusses how each of multiple charge pump circuits in LSIs is designed in case where the power and ground line resistance is not negligible. A behavior model for a charge pump, including the local power and ground voltages as input parameters, is proposed and a systematic design methodology is then presented. A system designer can use the behavior model to determine the specifications on each pump and power and ground resistance for minimizing overall area.

    DOI

    Scopus

    13
    Citation
    (Scopus)
  • Dickson Charge Pump Circuit Design with Parasitic Resistance in Power Lines

    Toru Tanzawa

    IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS    2009

    DOI

    Scopus

    15
    Citation
    (Scopus)
  • A process- and temperature-tolerant power-on reset circuit with a flexible detection level higher than the bandgap voltage

    Toru Tanzawa

    IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS    2008

  • A 2.4-GHz temperature-compensated CMOS LC-VCO for low frequency drift low-power direct-modulation GFSK transmitters

    T Tanzawa, K Agawa, H Shibayama, R Terauchi, K Hisano, H Ishikuro, S Kousai, H Kobayashi, H Majima, T Takayama, M Koizumi, F Hatori

    IEICE TRANSACTIONS ON ELECTRONICS   E88C ( 4 ) 490 - 495  2005.04  [Refereed]

     View Summary

    A frequency drift of open-loop PLL is an issue for the direct-modulation applications such as Bluetooth transceiver. The drift mainly comes from a temperature variation of VCO during the transmission operation. In this paper, we propose the optimum location of the VCO, considering the temperature gradient through the whole-chip thermal analysis. Moreover, a novel temperature-compensated VCO, employing a new biasing scheme, is proposed. The combination of these two techniques enables the power reduction of the transmitter by 33% without sacrificing the performance.

    DOI

    Scopus

    2
    Citation
    (Scopus)
  • A 44-mm(2) four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller

    T Tanzawa, A Umezawa, T Taura, H Shiga, T Hara, Y Takano, T Miyaba, N Tokiwa, K Watanabe, H Watanabe, K Masuda, K Naruke, H Kato, S Atsumi

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   37 ( 11 ) 1485 - 1492  2002.11  [Refereed]

     View Summary

    The highest bit-density 64-Mb NOR flash memory with dual-operation function of 44 mm(2) was developed by introducing negative-gate channel-erase NOR flash memory cell technology, 0.16-mum CMOS flash memory process technology, and four-bank hierarchical word-line and bit-line architecture. The chip has flexible block redundancy for high yield, a fast accurate word-line voltage controller for a fast erasing time of 0.5 s, and an eight-word page-read access capability for high read performance of an effective access time of 30 ns at a wide supply voltage range of 2.3-3.6 V.

    DOI

    Scopus

    3
    Citation
    (Scopus)
  • High-voltage transistor scaling circuit techniques for high-density negative-gate, channel-erasing NOR flash memories

    T Tanzawa, Y Takano, K Watanabe, S Atsumi

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   37 ( 10 ) 1318 - 1325  2002.10  [Refereed]

     View Summary

    In order to scale high-voltage transistors for high-density negative-gate channel-erasing NOR flash memories, two circuit techniques were developed. A proposed level shifter with low operating voltage is composed of three parts, a latch holding the negative erasing voltage, two coupling capacitors connected with the latched nodes in the latch, and high-voltage drivers inverting the latch, resulting in reduction of the maximum internal voltage by 0.5 V. A proposed high-voltage generator adds a path-gate logic to a conventional high-voltage generator to realize both low noise and low ripple voltage, resulting in a reduction of the maximum internal voltage by 0.5 V. As a result, these circuit techniques along with high coupling-ratio cell technology can scale down the high-voltage transistors by 15% and can realize higher density negative-gate channel-erase NOR flash memories in comparison with the source-erase NOR flash memories.

    DOI

    Scopus

    31
    Citation
    (Scopus)
  • Circuit techniques for a 1.8-V-only NAND flash memory

    T Tanzawa, T Tanaka, K Takeuchi, H Nakamura

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   37 ( 1 ) 84 - 89  2002.01  [Refereed]

     View Summary

    Focusing on internal high-voltage (V-pp) switching and generation for low-voltage NAND flash memories, this paper describes a V-pp switch, row decoder, and charge-pump circuit. The proposed nMOS V-pp switch is composed of only intrinsic high-voltage transistors without channel implantation, which realizes both reduction of the minimum operating voltage and elimination of the V-pp leakage current. The proposed row decoder scheme is described in which all blocks are in selected state in standby so as to prevent standby current from flowing through the proposed V-pp switches in the row decoder. A merged charge-pump scheme generates a plurality of voltage levels with an individually optimized efficiency, which reduces circuit area in comparison with the conventional scheme that requires a separate charge-pump circuit for each voltage level. The proposed circuits were implemented on an experimental NAND flash memory. The charge pump and V-pp switch successfully operated at a supply voltage of 1.8 V with a standby current of 10 muA. The proposed pump scheme reduced the area required for charge-pump circuits by 40%.

  • Wordline voltage generating system for low-power low-voltage flash memories

    T Tanzawa, A Umezawa, M Kuriyama, T Taura, H Banba, T Miyaba, H Shiga, Y Takano, S Atsumi

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   36 ( 1 ) 55 - 63  2001.01  [Refereed]

     View Summary

    A low-power wordline voltage generating system is developed for low-voltage flash memories, The limit for the stand-by current including the operation current for the band-gap reference and the stand-by wordline voltage generator is discussed. The system was implemented on a 1.8-V 32-Mb flash memory Fabricated with a 0.25-mum flash memory process and achieved with very low stand-by current of 2 muA typically, and high operating frequency of 25 MHz in read operation at 1.8 V, A low-voltage level shifter with high-speed switching is also proposed.

  • A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme

    S Atsumi, A Umezawa, T Tanzawa, T Taura, H Shiga, Y Takano, T Miyaba, M Matsui, H Watanabe, K Isobe, S Kitamura, S Yamada, M Saito, S Mori, T Watanabe

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   35 ( 11 ) 1648 - 1654  2000.11  [Refereed]

     View Summary

    A 1.8-V-only 32-Mb NOR flash EEPROM has been developed based on the 0.25-mum triple-well double-metal CMOS process. A channel-erasing scheme has been implemented to realize a cell size of 0.49 mum(2), the smallest yet reported for 0.25-mum CMOS technology. A block decoder circuit with a novel erase-reset sequence has been designed for the channel-erasing operation. A bitline direct sensing scheme and a wordline boosted voltage pooling method have been developed to obtain high-speed reading operation at low voltage. Access time of 90 ns at 1.8 V has been realized.

  • Design of a sense circuit for low-voltage flash memories

    T Tanzawa, Y Takano, T Taura, S Atsumi

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   35 ( 10 ) 1415 - 1421  2000.10  [Refereed]

     View Summary

    A new sense circuit directly sensing the bitline voltage is proposed for low-voltage flash memories. A simple reference voltage generation method and a dataline switching method with matching of the stray capacitance between the dataline pairs are also proposed. A design method for the bitline clamp load transistors is described, taking bitline charging speed and process margins into account. The sense circuit was implemented in a 32-Mb flash memory fabricated with a 0.25-mu m flash memory process and successfully operated at a low voltage of 1.5 V.

  • Optimization of word-line booster circuits for low-voltage flash memories

    T Tanzawa, S Atsumi

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   34 ( 8 ) 1091 - 1098  1999.08  [Refereed]

     View Summary

    Two word-line booster circuits, which output a word-line voltage for reading dash memory data, are analyzed and optimized. A capacitor-switched booster circuit outputs a voltage higher than the supply voltage by switching the connection state of one or more boosting capacitors with the load capacitor from parallel to series. The optimum number of capacitors and Capacitance per boosting capacitor are obtained as a function of the voltage ratio of the required high voltage to the supply voltage. The operation current consumed by the boosting operation is also analytically derived. In addition, another booster circuit-Dickson charge-pump circuit-is optimized under the condition to maximize the output current at a high word-line voltage. Characteristics of the booster circuits are compared, and the selection of booster circuit for low-voltage flash memory is discussed.

  • A CMOS bandgap reference circuit with sub-1-V operation

    H Banba, H Shiga, A Umezawa, T Miyaba, T Tanzawa, S Atsumi, K Sakui

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   34 ( 5 ) 670 - 674  1999.05  [Refereed]

     View Summary

    This paper proposes a CMOS bandgap reference (BGR) circuit, which can successfully operate with sub-1-V supply, Zn the conventional BGR circuit, the output voltage V-ref is the sum of the built-in voltage of the diode V-f and the thermal voltage V-T Of kT/q multiplied by a constant. Therefore, V-ref is about 1.25 V, which limits a low supply-voltage operation below 1 V, Conversely, in the proposed BGR circuit, V-ref has been converted From the sum of two currents; one is proportional to V-f and the other is proportional to V-T. An experimental BGR circuit, which is simply composed of a CMOS op-amp, diodes, and resistors, has been fabricated in a conventional 0.4-mu m flash memory process. Measured V-ref is 518 +/- 15 mV (3 sigma) for 23 samples on the same wafer at 27-125 degrees C.

  • A multipage cell architecture for high-speed programming multilevel NAND flash memories

    K Takeuchi, T Tanaka, T Tanzawa

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   33 ( 8 ) 1228 - 1238  1998.08  [Refereed]

     View Summary

    To realize low-cost, highly reliable, high-speed programming, and high-density multilevel flash memories, a multipage cell architecture has been proposed. This architecture enables both precise control of the V-th Of a memory cell and fast programming without any area penalty. In the case of a four-level cell, a high programming speed of 236 mu s/512 bytes or 2.2 Mbytes/s can be obtained, which is 2.3 times faster than the conventional method. A small die size can be achieved with the newly developed compact four-level column latch circuit, A preferential page select method has also been proposed so as to improve the data retention characteristics. The IC error rate can be decreased by as much as 43%, and a highly reliable operation can be realized.

  • A dynamic analysis of the Dickson charge pump circuit

    T Tanzawa, T Tanaka

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   32 ( 8 ) 1231 - 1240  1997.08  [Refereed]

     View Summary

    Dynamics of the Dickson charge pump circuit have been analyzed. The analytical results enable the estimation of the rise time of the output voltage and that of the power consumption during boosting. By using this analysis, the optimum number of stages to minimize the rise time has been estimated as 1.4 N-min, where N-min is the minimum value of the number of stages necessary for a given parameter set of a supply voltage, threshold voltages of transfer diodes, and a boosted voltage. Moreover, the self-load capacitance of the charge pump, which should be charged up at the same time as the output load capacitance of the charge pump, has been estimated as about one-third of the total charge pump capacitance. As a result, the equivalent circuit of the charge pump has been modified. The analytical results have been in good agreement with the simulation results by the iteration method, typically within 10% for the rise time and within 2% for the power consumption. In case of a charge pump with MOS transfer transistors, the analytical result of the rise time has agreed with the SPICE simulation within 10%.

  • A stable programming pulse generator for single power supply flash memories

    T Tanzawa, T Tanaka

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   32 ( 6 ) 845 - 851  1997.06  [Refereed]

     View Summary

    A stable programming pulse generator has been developed for single power supply, high-speed programming, and low-power Flash memories, The newly developed delay circuit operates by amplifying the difference between the reference voltage and the capacitor voltage raised by the charging current which is proportional to the reference voltage, Linearity between the capacitor voltage swing and the driving current enables us to make the delay circuit supply voltage-, temperature-, and process-tolerant, Thus, the proposed delay circuit stably controls a programming pulse width through all operational ranges of supply voltage and temperature, The output frequency of the newly developed oscillator is inversely proportional to the supply voltage, This oscillator stably drives charge pump circuits which generate high programming voltages on chip since dependence of charge pump characteristics on frequency and supply voltage can be canceled, As a result, the programming pulse generator including the delay circuit and the oscillator has reduced the total programming time under the slowest condition, i.e., high temperature and low voltage condition, by 30% and the power consumption under,the fastest condition, i.e., low temperature and high voltage condition, by 20%, for a 3.3 V-only Flash memory.

  • A compact on-chip ECC for low cost flash memories

    T Tanzawa, T Tanaka, K Takeuchi, R Shirota, S Aritome, H Watanabe, G Kemink, K Shimizu, S Sato, Y Takeucki, K Ohuchi

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   32 ( 5 ) 662 - 669  1997.05  [Refereed]

     View Summary

    A compact on-chip error correcting circuit (ECC) for low cost Flash memories has been developed,The total increase in chip area is 2%, including all cells, sense amplifiers, logic, and wiring associated with the ECC, The proposed on-chip ECC, employing 10 check bits for 512 data bits, has been implemented on an experimental 64M-bit NAND Flash memory, The cumulative sector error rate has been improved from 10(-1) to 10(-10). By transferring read data from the sense amplifiers to the ECC twice, 522-Byte temporary buffers, which are required for the conventional ECC and occupy a large part of the ECC area, have been eliminated, As a result, the area for the circuit has been drastically reduced by a factor of 25, The proposed on-chip ECC has been optimized in consideration of balance between the reliability improvement and the cell area overhead, The power increase has been suppressed to less than 1 mA.

  • QUANTUM-MECHANICS OF A PARTICLE CONFINED TO A TWISTED RING

    S TAKAGI, T TANZAWA

    PROGRESS OF THEORETICAL PHYSICS   87 ( 3 ) 561 - 568  1992.03  [Refereed]

     View Summary

    We derive an effective Hamiltonian for a particle confined to a thin tube which is gently twisted and curved to form a closed loop. The Hamiltonian describes the effect of both the curvature and the torsion of the loop correctly to the second order. Applied to the case of a tube of circular cross section, it reveals complete analogy with the Aharonov-Bohm effect. We also discuss eigenmodes for Mobius-like rings formed by a tube of non-circular cross section.

  • QUANTUM-MECHANICS OF A PARTICLE ON A CURVED SURFACE - COMPARISON OF 3 DIFFERENT APPROACHES

    Toru Tanzawa

    Progress of Theoretical Physics   88 ( 2 ) 229 - 249  1992.02  [Refereed]

    DOI

▼display all

Books and Other Publications

  • Fully-Integrated Power Management Circuits for Thermoelectric Energy Harvesting

    Toru Tanzawa( Part: Sole author)

    Springer Nature  2024.06 ISBN: 9783031597886

  • On-chip High-Voltage Generator Design: Design Methodology for Charge Pumps, 2nd edition

    T. Tanzawa( Part: Sole author)

    Springer  2015.10

  • Power Aware Design Methodologies

    T. Tanzawa( Part: Joint author)

    Kluwer Academic Publishers  2002.01

Presentations

▼display all

Research Projects

  • 極低電圧から昇圧可能な電力変換回路の動作原理解明とIoT端末への応用

    基盤研究(C)

    Project Year :

    2022.04
    -
     
     

Misc

Industrial Property Rights

  • 昇圧回路及び電源装置

    特許第7356713号

    丹沢 徹, 野村 達也

    Patent

    J-GLOBAL

  • 駆動回路及び電子デバイス

    特許第7351532号

    丹沢 徹, 松山 和樹

    Patent

    J-GLOBAL

  • レクテナ装置及びレクテナ装置を設計する方法

    特許第7290219号

    丹沢 徹, 田渕 侑幹

    Patent

    J-GLOBAL

  • 電源装置及び電源システム

    丹沢 徹, 内田 秀樹

    Patent

  • 電力変換装置及び電源装置

    特許第7165997号

    丹沢 徹

    Patent

    J-GLOBAL

  • 電源装置、昇圧回路の制御装置、及び昇圧回路の出力評価装置

    丹沢 徹, 内田 秀樹, 濃野 公一

    Patent

    J-GLOBAL

  • 電源装置

    丹沢 徹, 内田 秀樹

    Patent

  • 半導体装置及びその製造方法

    特許第7109795号

    丹沢 徹

    Patent

    J-GLOBAL

  • ソースのエッジに隣接するソースコンタクトを有するメモリアレイを含む装置

    特許第7053548号

    丹沢 徹

    Patent

    J-GLOBAL

  • 昇圧回路及び電源装置

    丹沢 徹, 野村 達也

    Patent

    J-GLOBAL

  • メモリセル内で負のボディ電位を確立することを含む装置および方法

    特許第6934048号

    作井 康司, ホーズ,マーク, 丹沢 徹, ビンフェット,ジェレミー

    Patent

    J-GLOBAL

  • メモリアクセス動作中に、メモリの複数のメモリプレーンに同時にアクセスするための装置および方法

    特許第6931674号

    ラジェード,シャンタヌ アール., カラヴァド,プラナフ, 丹沢 徹

    Patent

    J-GLOBAL

  • 読み出し回路及びメモリシステム

    丹沢 徹

    Patent

  • レクテナ装置及びレクテナ装置を設計する方法

    丹沢 徹, 田渕 侑幹

    Patent

    J-GLOBAL

  • 電源装置、昇圧回路の制御装置、及び昇圧回路の出力評価装置

    丹沢 徹, 内田 秀樹, 濃野 公一

    Patent

  • ランダムアクセス型メモリ回路及びメモリシステム

    丹沢 徹

    Patent

  • Semiconductor device and manufacturing method for same

    US 11,258,008

    Toru Tanzawa

    Patent

  • 駆動回路及び電子デバイス

    丹沢 徹, 松山 和樹

    Patent

    J-GLOBAL

  • ソースのエッジに隣接するソースコンタクトを有するメモリアレイを含む装置

    丹沢 徹

    Patent

    J-GLOBAL

  • ランダムアクセス型メモリ回路及びメモリシステム

    丹沢 徹

    Patent

  • 昇圧回路及び電源装置

    丹沢 徹, 野村 達也

    Patent

  • メモリセル内で負のボディ電位を確立することを含む装置および方法

    作井 康司, ホーズ,マーク, 丹沢 徹, ビンフェット,ジェレミー

    Patent

    J-GLOBAL

  • 電力変換回路及び電源装置

    丹沢 徹

    Patent

    J-GLOBAL

  • インピーダンス調整回路、電力変換素子及び電源素子

    丹沢 徹

    Patent

    J-GLOBAL

  • 電源装置

    丹沢 徹, 内田 秀樹

    Patent

  • ソースのエッジに隣接するソースコンタクトを有するメモリアレイを含む装置

    特許第6599880号

    丹沢 徹

    Patent

    J-GLOBAL

  • メモリアクセス動作中に、メモリの複数のメモリプレーンに同時にアクセスするための装置および方法

    ラジェード,シャンタヌ アール., カラヴァド,プラナフ, 丹沢 徹

    Patent

    J-GLOBAL

  • レクテナ装置及びレクテナ装置を設計する方法

    丹沢 徹, 田渕 侑幹

    Patent

  • 電力変換装置及び電源装置

    丹沢 徹

    Patent

    J-GLOBAL

  • インピーダンス調整回路、電力変換素子及び電源素子

    丹沢徹

    Patent

  • 半導体装置及びその製造方法

    丹沢 徹

    Patent

    J-GLOBAL

  • 電力変換装置及び電源装置

    丹沢徹

    Patent

  • 駆動回路及び電子デバイス

    丹沢徹, 松山和樹

    Patent

  • 消去デバイアスを用いてメモリを動作させる装置、及び方法

    丹沢 徹

    Patent

    J-GLOBAL

  • 半導体装置及びその製造方法

    丹沢徹

    Patent

  • メモリアクセス動作中に、メモリの複数のメモリプレーンに同時にアクセスするための装置および方法

    ラジェード,シャンタヌ アール., カラヴァド,プラナフ, 丹沢 徹

    Patent

    J-GLOBAL

  • 電力変換回路及び電源装置

    丹沢徹

    Patent

  • インピーダンス調整回路、電力変換素子及び電源素子

    丹沢徹

    Patent

  • メモリセルの分散されたサブブロックにアクセスすることを伴う装置および方法

    特許第6321650号

    丹沢 徹

    Patent

    J-GLOBAL

  • 電力変換装置及び電源装置

    丹沢徹

    Patent

  • 半導体装置及びその製造方法

    7109795

    丹沢徹

    Patent

  • ソースのエッジに隣接するソースコンタクトを有するメモリアレイを含む装置

    丹沢 徹

    Patent

    J-GLOBAL

  • 有効化回路を含むデバイスおよびシステム

    特許第6047153号

    丹沢 徹, ガーラム,アリ フェイズ ザリン

    Patent

    J-GLOBAL

  • 多数の層を備える半導体装置および方法

    特許第5894261号

    丹沢 徹

    Patent

    J-GLOBAL

  • メモリセルの分散されたサブブロックにアクセスすることを伴う装置および方法

    丹沢 徹

    Patent

    J-GLOBAL

  • コントロールゲートに挿通する接続部を有するメモリアレイ

    丹沢 徹, ムラコシ タモツ, シムゴーダ,ディーパク

    Patent

    J-GLOBAL

  • 車外監視装置

    特許第4914233号

    齋藤 徹, 丹沢 勉

    Patent

    J-GLOBAL

  • 不揮発性半導体メモリ

    丹沢 徹, 渥美 滋

    Patent

    J-GLOBAL

  • 電圧調整系

    特許第4565283号

    丹沢 徹

    Patent

    J-GLOBAL

  • 電圧調整系

    丹沢 徹

    Patent

    J-GLOBAL

  • 不揮発性半導体メモリ

    特許第4398541号

    高野 芳徳, 丹沢 徹, 田浦 忠行, 宮葉 武史, 渥美 滋

    Patent

    J-GLOBAL

  • 静電容量式水分センサ及びその製造方法

    茗荷谷 徹, 丹沢 孝直, 高橋 宏滋

    Patent

    J-GLOBAL

  • 半導体集積回路

    特許第4284343号

    梅沢 明, 高野 芳徳, 丹沢 徹

    Patent

    J-GLOBAL

  • 高電圧スイッチング回路

    特許第4199765号

    丹沢 徹

    Patent

    J-GLOBAL

  • 車外監視装置

    齋藤 徹, 丹沢 勉

    Patent

    J-GLOBAL

  • 不揮発性半導体メモリ

    特許第4157285号

    丹沢 徹, 渥美 滋, 梅沢 明, 田浦 忠行, 志賀 仁, 高野 芳徳

    Patent

    J-GLOBAL

  • 半導体装置

    特許第4149637号

    丹沢 徹, 宮葉 武史, 渥美 滋

    Patent

    J-GLOBAL

  • 半導体集積回路及び周波数変調装置

    特許第4091576号

    丹沢 徹

    Patent

    J-GLOBAL

  • 定電圧発生回路及び半導体記憶装置

    特許第4090817号

    丹沢 徹, 梅沢 明, 高野 芳徳

    Patent

    J-GLOBAL

  • 電圧減算回路及びそれを用いた強度検波回路

    特許第4088247号

    丹沢 徹

    Patent

    J-GLOBAL

  • フラッシュメモリ

    特許第4074029号

    田中 智晴, 柴田 昇, 丹沢 徹

    Patent

    J-GLOBAL

  • 不揮発性半導体メモリ

    特許第4047673号

    丹沢 徹, 渥美 滋

    Patent

    J-GLOBAL

  • 不揮発性メモリにおける読み取り・検証動作を生成する方法及び装置

    丹沢 徹

    Patent

    J-GLOBAL

  • 半導体記憶装置

    特許第4033438号

    梅沢 明, 渥美 滋, 丹沢 徹, 田浦 忠行, 志賀 仁, 高野 芳徳

    Patent

    J-GLOBAL

  • 記憶システム

    特許第3999822号

    丹沢 徹, 田中 智晴

    Patent

    J-GLOBAL

  • 電圧発生回路

    特許第3993354号

    宮葉 武史, 丹沢 徹, 栗山 正男

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    特許第3990393号

    ヘミンク・ゲルトヤン, 丹沢 徹, 田中 智晴

    Patent

    J-GLOBAL

  • 高電圧スイッチング回路

    丹沢 徹

    Patent

    J-GLOBAL

  • 信号強度検波回路およびそれを用いた増幅率制御システム。

    特許第3971368号

    丹沢 徹, 濱田 基嗣

    Patent

    J-GLOBAL

  • 温度係数が小さいパワー・オン・リセットを生成する方法及び装置

    丹沢 徹

    Patent

    J-GLOBAL

  • 温度補償された読み出し・検証動作をフラッシュ・メモリにおいて生成するための方法及び装置

    丹沢 徹

    Patent

    J-GLOBAL

  • バンド・ギャップ基準から可変出力電圧を生成する方法及び装置

    丹沢 徹

    Patent

    J-GLOBAL

  • ポンプ回路を有する半導体装置

    特許第3908415号

    丹沢 徹, 渥美 滋

    Patent

    J-GLOBAL

  • 不揮発性半導体メモリ

    特許第3906189号

    丹沢 徹

    Patent

    J-GLOBAL

  • 不揮発性半導体メモリ

    特許第3905979号

    丹沢 徹, 渥美 滋, 番場 博則, 山田 誠司, 森 誠一, 栗山 正男, 大塚 伸朗

    Patent

    J-GLOBAL

  • 半導体記憶装置

    丹沢 徹, 梅沢 明, 高野 芳徳

    Patent

    J-GLOBAL

  • 半導体集積回路

    梅沢 明, 高野 芳徳, 丹沢 徹

    Patent

    J-GLOBAL

  • 半導体装置

    特許第3892612号

    渥美 滋, 田浦 忠行, 丹沢 徹

    Patent

    J-GLOBAL

  • 半導体記憶装置

    特許第3886669号

    丹沢 徹, 渥美 滋

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    特許第3887064号

    丹沢 徹

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    特許第3884420号

    ヘミンク・ゲルトヤン, 丹沢 徹, 田中 智晴

    Patent

    J-GLOBAL

  • 不揮発性半導体メモリ

    丹沢 徹, 渥美 滋, 番場 博則, 山田 誠司, 森 誠一, 栗山 正男, 大塚 伸朗

    Patent

    J-GLOBAL

  • 不揮発性半導体メモリ

    丹沢 徹, 渥美 滋, 番場 博則, 山田 誠司, 森 誠一, 栗山 正男, 大塚 伸朗

    Patent

    J-GLOBAL

  • 昇圧回路

    特許第3872927号

    丹沢 徹

    Patent

    J-GLOBAL

  • 半導体記憶装置

    丹沢 徹, 渥美 滋

    Patent

    J-GLOBAL

  • 記憶システム

    特許第3866674号

    丹沢 徹, 田中 智晴

    Patent

    J-GLOBAL

  • 半導体集積回路

    特許第3866481号

    梅沢 明, 高野 芳徳, 丹沢 徹

    Patent

    J-GLOBAL

  • 遅延回路

    特許第3857542号

    丹沢 徹

    Patent

    J-GLOBAL

  • 半導体装置

    特許第3857461号

    丹沢 徹, 栗山 正男, 田浦 忠行

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    特許第3854025号

    志賀 仁, 丹沢 徹, 斎藤 雅伸

    Patent

    J-GLOBAL

  • 量子効果装置とBLトンネル素子を用いた装置

    特許第3853905号

    渡辺 浩志, 安田 直樹, 鳥海 明, 丹沢 徹, 田中 智晴

    Patent

    J-GLOBAL

  • 不揮発性半導体メモリ

    特許第3845051号

    丹沢 徹, 梅沢 明

    Patent

    J-GLOBAL

  • キャパシタアレイ回路及び電圧制御発振器

    丹 沢 徹, 香 西 昌 平

    Patent

    J-GLOBAL

  • 半導体記憶装置

    特許第3840193号

    田中 智晴, 中村 寛, 丹沢 徹

    Patent

    J-GLOBAL

  • 半導体装置

    特許第3836787号

    丹沢 徹

    Patent

    J-GLOBAL

  • 半導体記憶装置及びその制御方法

    特許第3825596号

    高野 芳徳, 丹沢 徹, 田浦 忠行

    Patent

    J-GLOBAL

  • 不揮発性半導体メモリ

    特許第3808656号

    丹沢 徹

    Patent

    J-GLOBAL

  • 電圧制御発振器

    丹沢 徹

    Patent

    J-GLOBAL

  • 周波数直接変調装置及び通信システム

    特許第3774454号

    丹沢 徹

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    特許第3762114号

    丹沢 徹, 渥美 滋, 梅沢 明, 田浦 忠行

    Patent

    J-GLOBAL

  • 半導体集積回路及び周波数変調装置

    丹沢 徹

    Patent

    J-GLOBAL

  • 半導体集積回路

    丹沢 徹, 羽鳥 文敏

    Patent

    J-GLOBAL

  • 半導体集積回路装置

    特許第3708912号

    森 誠一, 丹沢 徹

    Patent

    J-GLOBAL

  • 電圧減算回路及びそれを用いた強度検波回路

    丹沢 徹

    Patent

    J-GLOBAL

  • 半導体集積回路装置

    特許第3695967号

    丹沢 徹

    Patent

    J-GLOBAL

  • 信号強度検波回路およびそれを用いた増幅率制御システム。

    丹沢 徹, 濱田 基嗣

    Patent

    J-GLOBAL

  • アナログレベルシフタ

    丹沢 徹

    Patent

    J-GLOBAL

  • 周波数直接変調装置及び通信システム

    丹沢 徹

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    特許第3660503号

    丹沢 徹

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    特許第3648304号

    丹沢 徹, 竹内 健, 田中 智晴

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    ヘミンク・ゲルトヤン, 丹沢 徹, 田中 智晴

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    特許第3626221号

    ヘミンク・ゲルトヤン, 丹沢 徹, 田中 智晴

    Patent

    J-GLOBAL

  • 発振回路

    特許第3607319号

    丹沢 徹, 田中 智晴

    Patent

    J-GLOBAL

  • 半導体記憶装置

    特許第3600562号

    丹沢 徹, 田中 智晴, 大内 和則, 白田 理一郎

    Patent

    J-GLOBAL

  • 誤り訂正検出回路と半導体記憶装置

    特許第3600561号

    丹沢 徹, 田中 智晴, 大内 和則, 白田 理一郎

    Patent

    J-GLOBAL

  • 半導体装置

    特許第3583703号

    丹沢 徹

    Patent

    J-GLOBAL

  • 半導体記憶装置

    特許第3563702号

    田中 智晴, 丹沢 徹, 竹内 健

    Patent

    J-GLOBAL

  • パルス発生回路

    特許第3559749号

    河合 鉱一, 今宮 賢一, 中村 寛, 丹沢 徹, 志賀 仁

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    特許第3557078号

    佐藤 信司, 白田 理一郎, 丹沢 徹

    Patent

    J-GLOBAL

  • 不揮発性半導体メモリ

    丹沢 徹

    Patent

    J-GLOBAL

  • 不揮発性半導体メモリ

    丹沢 徹, 梅沢 明

    Patent

    J-GLOBAL

  • 半導体記憶装置

    特許第3519542号

    丹沢 徹, 田中 智晴

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    ヘミンク・ゲルトヤン, 丹沢 徹, 田中 智晴

    Patent

    J-GLOBAL

  • 不揮発性半導体メモリ装置

    高野 芳徳, 本多 泰彦, 丹沢 徹, 栗山 正男

    Patent

    J-GLOBAL

  • 半導体記憶装置

    田中 智晴, 中村 寛, 丹沢 徹

    Patent

    J-GLOBAL

  • 半導体記憶装置

    特許第3481817号

    田中 智晴, 中村 寛, 丹沢 徹

    Patent

    J-GLOBAL

  • 半導体装置

    丹沢 徹

    Patent

    J-GLOBAL

  • 記憶システム

    丹沢 徹, 田中 智晴

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    特許第3447886号

    丹沢 徹, 田中 智晴, 大内 和則

    Patent

    J-GLOBAL

  • 半導体メモリ装置

    高野 芳徳, 渥美 滋, 丹沢 徹

    Patent

    J-GLOBAL

  • 定電圧発生回路及び半導体記憶装置

    丹沢 徹, 梅沢 明, 高野 芳徳

    Patent

    J-GLOBAL

  • 半導体集積回路装置

    森 誠一, 丹沢 徹

    Patent

    J-GLOBAL

  • 不揮発性半導体メモリ

    丹沢 徹, 渥美 滋

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置およびその不良救済方法

    田浦 忠行, 渥美 滋, 丹沢 徹

    Patent

    J-GLOBAL

  • 半導体記憶装置

    梅沢 明, 渥美 滋, 丹沢 徹, 田浦 忠行, 志賀 仁, 高野 芳徳

    Patent

    J-GLOBAL

  • 不揮発性半導体メモリ

    丹沢 徹, 渥美 滋, 梅沢 明, 田浦 忠行, 志賀 仁, 高野 芳徳

    Patent

    J-GLOBAL

  • 遅延回路

    丹沢 徹

    Patent

    J-GLOBAL

  • 半導体装置

    丹沢 徹

    Patent

    J-GLOBAL

  • 半導体記憶装置

    梅沢 明, 丹沢 徹

    Patent

    J-GLOBAL

  • 半導体記憶装置

    志賀 仁, 高野 芳徳, 丹沢 徹, 渥美 滋

    Patent

    J-GLOBAL

  • レベルシフタ及びレベルシフタを備えた半導体記憶装置

    丹沢 徹, 渡邊 健太郎

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    高野 芳徳, 丹沢 徹, 田浦 忠行

    Patent

    J-GLOBAL

  • 遅延回路

    特許第3321306号

    丹沢 徹, 作井 康司, 田中 智晴, 山村 俊雄

    Patent

    J-GLOBAL

  • 半導体記憶装置

    丹沢 徹, 田中 智晴, 大内 和則, 白田 理一郎

    Patent

    J-GLOBAL

  • 誤り訂正検出回路と半導体記憶装置

    丹沢 徹, 田中 智晴, 大内 和則, 白田 理一郎

    Patent

    J-GLOBAL

  • 不揮発性半導体メモリ

    丹沢 徹, 渥美 滋

    Patent

    J-GLOBAL

  • 半導体装置

    丹沢 徹

    Patent

    J-GLOBAL

  • 半導体メモリ

    特許第3294153号

    丹沢 徹, 田中 智晴, 竹内 健

    Patent

    J-GLOBAL

  • 誤り訂正検出回路と半導体記憶装置

    特許第3272903号

    丹沢 徹, 田中 智晴, 大内 和則, 白田 理一郎

    Patent

    J-GLOBAL

  • 半導体集積回路装置

    高野 芳徳, 丹沢 徹

    Patent

    J-GLOBAL

  • パルス発生回路

    河合 鉱一, 今宮 賢一, 中村 寛, 丹沢 徹, 志賀 仁

    Patent

    J-GLOBAL

  • 半導体装置

    丹沢 徹, 宮葉 武史, 渥美 滋

    Patent

    J-GLOBAL

  • 半導体集積回路

    梅沢 明, 高野 芳徳, 丹沢 徹

    Patent

    J-GLOBAL

  • 半導体記憶装置

    田中 智晴, 丹沢 徹, 竹内 健

    Patent

    J-GLOBAL

  • 昇圧回路

    丹沢 徹

    Patent

    J-GLOBAL

  • 電圧発生回路

    宮葉 武史, 丹沢 徹, 栗山 正男

    Patent

    J-GLOBAL

  • 高電圧切り換え回路

    特許第3197161号

    丹沢 徹, 田中 智晴

    Patent

    J-GLOBAL

  • 半導体記憶装置及びその制御方法

    高野 芳徳, 丹沢 徹, 田浦 忠行

    Patent

    J-GLOBAL

  • 半導体記憶装置

    特許第3192344号

    中村 寛, 丹沢 徹

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶部を含む記憶システム

    特許第3176019号

    白 田 理一郎, 丹 沢 徹, 金 箱 和 範, 百 冨 正 樹

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    特許第3176016号

    丹沢 徹, 田中 智晴

    Patent

    J-GLOBAL

  • 半導体記憶装置

    特許第3176011号

    田中 智晴, 丹沢 徹, 竹内 健

    Patent

    J-GLOBAL

  • 半導体記憶装置

    丹沢 徹, 田浦 忠行, 渥美 滋

    Patent

    J-GLOBAL

  • 昇圧回路及び昇圧回路を備えた不揮発性半導体記憶装置

    特許第3162564号

    丹沢 徹, 田中 智晴, 中村 寛, 田中 義幸

    Patent

    J-GLOBAL

  • 不揮発性半導体メモリ

    高野 芳徳, 丹沢 徹, 田浦 忠行, 宮葉 武史, 渥美 滋

    Patent

    J-GLOBAL

  • フラッシュメモリ

    田中 智晴, 柴田 昇, 丹沢 徹

    Patent

    J-GLOBAL

  • 半導体記憶装置

    丹沢 徹, 渥美 滋

    Patent

    J-GLOBAL

  • 半導体装置

    渥美 滋, 田浦 忠行, 丹沢 徹

    Patent

    J-GLOBAL

  • 不揮発性半導体メモリ

    丹沢 徹

    Patent

    J-GLOBAL

  • 半導体装置と定電圧発生方法

    丹沢 徹, 栗山 正男, 田浦 忠行

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    志賀 仁, 丹沢 徹, 斎藤 雅伸

    Patent

    J-GLOBAL

  • 半導体集積回路装置

    丹沢 徹

    Patent

    J-GLOBAL

  • ポンプ回路を有する半導体装置

    丹沢 徹, 渥美 滋

    Patent

    J-GLOBAL

  • 半導体記憶装置

    丹沢 徹

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    丹沢 徹, 渥美 滋, 梅沢 明, 田浦 忠行

    Patent

    J-GLOBAL

  • 不揮発性半導体メモリ

    渥美 滋, 梅沢 明, 丹沢 徹, 山田 誠司

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    丹沢 徹

    Patent

    J-GLOBAL

  • 半導体記憶装置

    高野 芳徳, 丹沢 徹

    Patent

    J-GLOBAL

  • 不揮発性半導体メモリ

    丹沢 徹, 渥美 滋, 番場 博則, 山田 誠司, 森 誠一, 栗山 正男, 大塚 伸朗

    Patent

    J-GLOBAL

  • 半導体集積回路装置

    今宮 賢一, 田中 智晴, 中村 寛, 丹沢 徹, 竹内 健

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    竹内 健, 田中 智晴, 丹沢 徹

    Patent

    J-GLOBAL

  • 基準電圧発生回路およびその調整方法

    丹沢 徹, 今宮 賢一

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    佐藤 信司, 白田 理一郎, 丹沢 徹

    Patent

    J-GLOBAL

  • 半導体メモリ

    丹沢 徹, 田中 智晴, 竹内 健

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    丹沢 徹

    Patent

    J-GLOBAL

  • 半導体記憶装置

    田中 智晴, 中村 寛, 丹沢 徹

    Patent

    J-GLOBAL

  • 量子効果装置及び半導体複合基板

    渡辺 浩志, 安田 直樹, 鳥海 明, 丹沢 徹, 田中 智晴

    Patent

    J-GLOBAL

  • 半導体記憶装置及び画像入力処理装置

    渡辺 重佳, 丹沢 徹

    Patent

    J-GLOBAL

  • 不揮発性半導体メモリ

    丹沢 徹, 田中 智晴

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    丹沢 徹, 田中 智晴, 竹内 健

    Patent

    J-GLOBAL

  • 3値記憶半導体記憶システム

    田中 智晴, 丹沢 徹

    Patent

    J-GLOBAL

  • 半導体記憶装置

    丹沢 徹, 田中 智晴

    Patent

    J-GLOBAL

  • 半導体記憶装置

    丹沢 徹, 田中 智晴

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    丹沢 徹, 田中 智晴, 大内 和則

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    丹沢 徹, 竹内 健, 田中 智晴

    Patent

    J-GLOBAL

  • 電圧リミット回路

    丹沢 徹, 福田 良

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置及び記憶システム

    丹沢 徹

    Patent

    J-GLOBAL

  • 昇圧回路及びそれを用いた不揮発性半導体記憶装置

    丹沢 徹

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶部を含む記憶システム

    白 田 理一郎, 丹 沢 徹, 金 箱 和 範, 百 冨 正 樹

    Patent

    J-GLOBAL

  • 誤り訂正検出回路と半導体記憶装置

    丹沢 徹, 田中 智晴, 大内 和則, 白田 理一郎

    Patent

    J-GLOBAL

  • 半導体記憶装置

    中村 寛, 丹沢 徹

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    丹沢 徹, 田中 智晴

    Patent

    J-GLOBAL

  • 遅延回路

    丹沢 徹, 作井 康司, 田中 智晴, 山村 俊雄

    Patent

    J-GLOBAL

  • 発振回路

    丹沢 徹, 田中 智晴

    Patent

    J-GLOBAL

  • 高電圧切り換え回路

    丹沢 徹, 田中 智晴

    Patent

    J-GLOBAL

  • 半導体記憶装置

    田中 智晴, 丹沢 徹, 竹内 健

    Patent

    J-GLOBAL

  • 記憶システム

    丹沢 徹, 田中 智晴

    Patent

    J-GLOBAL

  • 不揮発性半導体記憶装置

    ヘミンク・ゲルトヤン, 丹沢 徹, 田中 智晴

    Patent

    J-GLOBAL

  • 昇圧回路及び昇圧回路を備えた不揮発性半導体記憶装置

    丹沢 徹, 田中 智晴, 中村 寛, 田中 義幸

    Patent

    J-GLOBAL

  • Non-volatile semiconductor memory device

    5555204

    Endoh; Tetsuo, Tanaka; Yoshiyuki, Aritome; Seiichi, Shirota; Riichiro, Shuto; Susumu, Tanaka; Tomoharu, Hemink; Gertjan, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Memory system

    5621682

    Tanzawa; Toru, Tanaka; Tomoharu

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Delay circuit, oscillation circuit and semiconductor memory device

    5627488

    Tanzawa; Toru, Tanaka; Tomoharu, Yamamura; Toshio, Sakui; Koji

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Eeprom semiconductor memory device including circuit for generating a voltage higher than a power supply voltage

    5706241

    Nakamura; Hiroshi , Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor memory device and high-voltage switching circuit

    5708606

    Tanzawa; Toru, Tanaka; Tomoharu, Takeuchi; Ken

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Memory system

    5719888

    Tanzawa; Toru, Tanaka; Tomoharu

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Non-volatile semiconductor memory device and method of programming a non-volatile memory cell to a predetermined state

    5774397

    Endoh; Tetsuo, Tanaka; Yoshiyuki, Aritome; Seiichi, Shirota; Riichiro, Shuto; Susumu, Tanaka; Tomoharu, Hemink; Gertjan, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor memory device and high-voltage switching circuit

    5828621

    Tanzawa; Toru, Tanaka; Tomoharu, Takeuchi; Ken

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Nonvolatile semiconductor memory with temperature compensation for read/verify referencing scheme

    5864504

    Tanzawa; Toru, Tanaka; Tomoharu, Takeuchi; Ken

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Three-value data storing semiconductor memory system

    5901152

    Tanaka; Tomoharu, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor memory

    5905691

    Tanzawa; Toru , Takeuchi; Ken , Tanaka; Tomoharu

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor memory device and high-voltage switching circuit

    5909398

    Tanzawa; Toru, Tanaka; Tomoharu, Takeuchi; Ken

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Error correction/detection circuit and semiconductor memory device using the same

    5933436

    Tanzawa; Toru, Tanaka; Tomoharu, Shirota; Riichiro, Ohuchi; Kazunori

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Non-volatile semiconductor memory device

    5946231

    Endoh; Tetsuo, Tanaka; Yoshiyuki, Aritome; Seiichi, Shirota; Riichiro, Shuto; Susumu, Tanaka; Tomoharu Hemink; Gertjan Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Delay circuit, oscillation circuit and semiconductor memory device

    5969557

    Tanzawa; Toru, Tanaka; Tomoharu, Yamamura; Toshio, Sakui; Koji

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Nonvolatile semiconductor memory device

    5969985

    Tanaka; Tomoharu, Ohuchi; Kazunori, Tanzawa; Toru, Takeuchi; Ken

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Voltage multiplier circuit and nonvolatile semiconductor memory device having voltage multiplier

    5969988

    Tanzawa; Toru, Tanaka; Tomoharu, Nakamura; Hiroshi, Tanaka; Yoshiyuki

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Memory system

    5996108

    Tanzawa; Toru, Tanaka; Tomoharu

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Non-volatile semiconductor memory device

    6014330

    Endoh; Tetsuo , Tanaka; Yoshiyuki, Aritome; Seiichi, Shirota; Riichiro, Shuto; Susumu, Tanaka; Tomoharu Hemink; Gertjan, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Nonvolatile semiconductor memory device

    6044013

    Tanaka; Tomoharu, Ohuchi; Kazunori, Tanzawa; Toru, Takeuchi; Ken

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor memory device

    6064611

    Tanaka; Tomoharu, Nakamura; Hiroshi, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor memory device

    6072719

    Tanzawa; Toru, Tanaka; Tomoharu

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Nonvolatile semiconductor memory having improved source line drive circuit

    6084799

    Tanzawa; Toru, Tanaka; Tomoharu

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Quantum tunneling effect device and semiconductor composite substrate

    6111288

    Watanabe; Hiroshi , Yasuda; Naoki , Toriumi; Akira, Tanaka; Tomoharu, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor memory preventing sense amplifier malfunctions due to effects of noise generated in output buffer

    6141277

    Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor memory device

    6154403

    Tanzawa; Toru, Tanaka; Tomoharu

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Non-volatile semiconductor memory device

    6188611

    Endoh; Tetsuo, Tanaka; Yoshiyuki , Aritome; Seiichi, Shirota; Riichiro, Shuto; Susumu, Tanaka; Tomoharu Hemink; Gertjan Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor memory device

    6208573

    Tanaka; Tomoharu, Nakamura; Hiroshi, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Data-erasable non-volatile semiconductor memory device

    6222774

    Tanzawa; Toru , Umezawa; Akira , Taura; Tadayuki, Atsumi; Shigeru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor memory device

    6233189

    Tanzawa; Toru, Atsumi; Shigeru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Nonvolatile semiconductor memory

    6236609

    Tanzawa; Toru , Taura; Tadayuki , Kuriyama; Masao

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Non-volatile semiconductor memory device having a function for controlling the range of distribution of memory cell threshold voltages

    6240019

    Shiga; Hitoshi, Tanzawa; Toru, Saito; Masanobu

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor memory device

    6249479

    Tanzawa; Toru, Tanaka; Tomoharu

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Nonvolatile semiconductor memory device capable of controlling mutual timing of write voltage pulse and transfer voltage pulse

    6252798

    Satoh; Shinji , Shirota; Riichiro, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Non-volatile semiconductor memory having column sub-selector layout pattern adaptable to miniaturization of memory cell

    6256227

    Atsumi; Shigeru , Umezawa; Akira , Tanzawa; Toru, Yamada; Seiji

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Pump circuit with reset circuitry

    6278316

    Tanzawa; Toru, Atsumi; Shigeru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Nonvolatile semiconductor memory device

    6282117

    Tanaka; Tomoharu, Ohuchi; Kazunori, Tanzawa; Toru, Takeuchi; Ken

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Quantum tunneling effect device and semiconductor composite substrate

    6320220

    Watanabe; Hiroshi, Yasuda; Naoki, Toriumi; Akira, Tanaka; Tomoharu , Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor memory device

    6337825

    Tanzawa; Toru, Atsumi; Shigeru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor integrated circuit device

    6344764

    Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor memory device

    6344996

    Tanaka; Tomoharu , Nakamura; Hiroshi , Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Non-volatile semiconductor memory device having a function for controlling the range of distribution of memory cell threshold voltages and method of erasing data thereof

    6351417

    Shiga; Hitoshi , Tanzawa; Toru, Saito; Masanobu

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Nonvolatile semiconductor memory device

    6363010

    Tanaka; Tomoharu, Ohuchi; Kazunori, Tanzawa; Toru, Takeuchi; Ken

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Channel-erase nonvolatile semiconductor memory device

    6373749

    Atsumi; Shigeru , Taura; Tadayuki, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Pump circuit with active-mode and stand-by mode booster circuits

    6429725

    Tanzawa; Toru, Atsumi; Shigeru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Non-volatile semiconductor memory device controlling the range of distribution of memory cell threshold voltages

    6434054

    Shiga; Hitoshi, Tanzawa; Toru , Saito; Masanobu

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor device

    6438034

    Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Nonvolatile semiconductor memory

    6442080

    Tanzawa; Toru , Taura; Tadayuki, Kuriyama; Masao

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Channel-erase nonvolatile semiconductor memory device

    6445618

    Atsumi; Shigeru, Taura; Tadayuki, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Booster circuit for raising voltage by sequentially transferring charges from input terminals of booster units to output terminals thereof in response to clock signals having different phases

    6456541

    Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Boosted voltage generating circuit and semiconductor memory device having the same

    6487120

    Tanzawa; Toru , Miyaba; Takeshi, Atsumi; Shigeru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor memory device

    6525964

    Tanaka; Tomoharu, Nakamura; Hiroshi, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Nonvolatile semiconductor memory device with initialization circuit and control method thereof

    6535427

    Takano; Yoshinori, Tanzawa; Toru, Taura; Tadayuki

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Nonvolatile semiconductor memory device

    6545909

    Tanaka; Tomoharu, Ohuchi; Kazunori, Tanzawa; Toru, Takeuchi; Ken

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor storage apparatus

    6552936

    Shiga; Hitoshi, Takano; Yoshinori, Tanzawa; Toru, Atsumi; Shigeru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor device

    6567309

    Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Channel-erase nonvolatile semiconductor memory device

    6577538

    Atsumi; Shigeru, Taura; Tadayuki, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Level shifter for converting a voltage level and a semiconductor memory device having the level shifter

    6600679

    Tanzawa; Toru, Watanabe; Kentaro

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor device with a voltage regulator

    6600692

    Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Boosted voltage generating circuit and semiconductor memory device having the same

    6605986

    Tanzawa; Toru, Miyaba; Takeshi, Atsumi; Shigeru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Flash memory

    6611938

    Tanaka; Tomoharu, Shibata; Noboru, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Booster circuit for raising voltage by sequentially transferring charges from input terminals of booster units to output terminals thereof in response to clock signals having different phases

    6614699

    Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor memory device

    6621738

    Tanaka; Tomoharu, Nakamura; Hiroshi, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Non-volatile semiconductor memory device

    6639837

    Takano; Yoshinori, Taura; Tadayuki, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Channel-erase nonvolatile semiconductor memory device

    6643183

    Atsumi; Shigeru, Taura; Tadayuki, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Non-volatile semiconductor memory

    6650570

    Tanzawa; Toru, Atsumi; Shigeru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Nonvolatile semiconductor memory having page mode with a plurality of banks

    6671203

    Tanzawa; Toru, Atsumi; Shigeru, Umezawa; Akira, Taura; Tadayuki, Shiga; Hitosh), Takano; Yoshinori

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor storage apparatus

    6693818

    Shiga; Hitoshi, Takano; Yoshinor), Tanzawa; Tor), Atsumi; Shigeru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Nonvolatile semiconductor memory device and method of retrieving faulty in the same

    6711057

    Taura; Tadayuki, Atsumi; Shigeru, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Nonvolatile semiconductor memory

    6711066

    Tanzawa; Toru, Taura; Tadayuki, Kuriyama; Masao

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Constant voltage generation circuit and semiconductor memory device

    6734719

    Tanzawa; Toru, Takano; Yoshinori

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • High-speed data programmable nonvolatile semiconductor memory device

    6762956

    Mori; Seiichi, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Boosted voltage generating circuit and semiconductor memory device having the same

    6771547

    Tanzawa; Toru, Miyaba; Takeshi, Atsumi; Shigeru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Memory device pump circuit with two booster circuits

    6781439

    Tanzawa; Toru, Atsumi; Shigeru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Nonvolatile semiconductor memory with a page mode

    6781879

    Tanzawa; Toru, Atsumi; Shigeru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor memory device and current mirror circuit

    6788601

    Takano; Yoshinori, Atsumi; Shigeru, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Nonvolatile semiconductor memory having page mode with a plurality of banks

    6795352

    Tanzawa; Toru, Atsumi; Shigeru, Umezawa; Akira, Taura; Tadayuki, Shiga; Hitoshi, Takano; Yoshinori

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Non-volatile semiconductor memory

    6801457

    Tanzawa; Toru, Atsumi; Shigeru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Non-volatile semiconductor memory device

    6807097

    Takano; Yoshinori, Taura; Tadayuki, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Nonvolatile semiconductor memory capable of generating read-mode reference current and verify-mode reference current from the same reference cell

    6816413

    Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Nonvolatile semiconductor memory

    6816421

    Tanzawa; Toru, Umezawa; Akira

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Fast data readout semiconductor storage apparatus

    6826068

    Shiga; Hitoshi, Takano; Yoshinori, Tanzawa; Toru, Atsumi; Shigeru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Nonvolatile semiconductor memory device with first and second read modes

    6842377

    Takano; Yoshinori, Honda; Yasuhiko, Tanzawa; Toru, Kuriyama; Masao

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Nonvolatile semiconductor memory device and method of retrieving faulty in the same

    6850437

    Taura; Tadayuki, Atsumi; Shigeru, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Nonvolatile semiconductor memory

    6856548

    Tanzawa; Toru, Taura; Tadayuki, Kuriyama; Masao

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Non-volatile semiconductor memory

    6865125

    Tanzawa; Toru, Atsumi; Shigeru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor memory device

    6868013

    Tanaka; Tomoharu, Nakamura; Hiroshi, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor device having switch circuit to supply voltage

    6977850

    Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Boosted voltage generating circuit and semiconductor memory device having the same

    6996024

    Tanzawa; Toru, Miyaba; Takeshi, Atsumi; Shigeru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor memory device and current mirror circuit

    6999365

    Takano; Yoshinori, Atsumi; Shigeru, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Direct frequency modulation apparatus which modulates frequency by applying data-dependent voltage to control terminal of voltage-controlled oscillator without mediacy of PLL, and communication system

    7005936

    Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor device having switch circuit to supply voltage

    7050339

    Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor memory device

    7061807

    Tanaka; Tomoharu, Shibata; Noboru, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Current difference divider circuit

    7071771

    Takano; Yoshinori , Taura; Tadayuki, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Analog level shifter

    7148734

    Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Boosted voltage generating circuit and semiconductor memory device having the same

    7180796

    Tanzawa; Toru, Miyaba; Takeshi, Atsumi; Shigeru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Boosted voltage generating circuit and semiconductor memory device having the same

    7203120

    Tanzawa; Toru, Miyaba; Takeshi, Atsumi; Shigeru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Flash memory

    7219285

    Tanaka; Tomoharu, Shibata; Noboru, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Voltage subtracting circuit carrying out voltage subtraction by converting input voltage into current, intensity detecting circuit, and semiconductor integrated circuit device using the same

    7233190

    Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • High voltage switching circuit

    7272046

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Method and apparatus for generating temperature-compensated read and verify operations in flash memories

    7277355

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Semiconductor device having switch circuit to supply voltage

    7336545

    Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor memory device

    7349259

    Tanaka; Tomoharu, Nakamura; Hiroshi, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor integrated circuit device and frequency modulation device

    7474139

    Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Method and apparatus for generating read and verify operations in non-volatile memories

    7489556

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Flash memory

    7509566

    Tanaka; Tomoharu, Shibata; Noboru, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Semiconductor memory device

    7535762

    Tanaka; Tomoharu, Nakamura; Hiroshi, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • High voltage switching circuit

    7609554

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Semiconductor memory device

    7649780

    Tanaka; Tomoharu, Nakamura; Hiroshi, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Adjustable voltage regulator for providing a regulated output voltage

    7764563

    Tanzawa; Toru, Harrington; Peter B.

    Rights holder: Micron Technology, Inc.

    Patent

  • Compensation capacitor network for divided diffused resistors for a voltage divider

    7902907

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Flash memory

    7908529

    Tanaka; Tomoharu, Shibata; Noboru, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Random telegraph signal noise reduction scheme for semiconductor memories

    7916544

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Semiconductor memory device

    7952933

    Tanaka; Tomoharu, Nakamura; Hiroshi, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Adjustable voltage regulator for providing a regulated output voltage

    7957214

    Tanzawa; Toru, Harrington; Peter B.

    Rights holder: Micron Technology, Inc.

    Patent

  • Method and apparatus for generating temperature-compensated read and verify operations in flash memories

    7957215

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Voltage trimming

    8013579

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Voltage regulator system

    8026702

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Biasing system and method

    8125829

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Semiconductor memory device

    8154922

    Tanaka; Tomoharu, Nakamura; Hiroshi, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Level shifting circuit

    8184489

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Random telegraph signal noise reduction scheme for semiconductor memories

    8194459

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Arrangement of pairs of NAND strings that share bitline contacts while utilizing distinct sources lines

    8208305

    Tanzawa; Toru

    Rights holder: Intel Corporation

    Patent

  • Devices for shielding a signal line over an active region

    8253198

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Voltage regulator system

    8253396

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Flash memory

    8365025

    Tanaka; Tomoharu, Shibata; Noboru, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Level shifting circuit

    8446784

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Voltage trimming

    8466664

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Random telegraph signal noise reduction scheme for semiconductor memories

    8537620

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Voltage generation and adjustment in a memory device

    8547746

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods including memory array and data line architecture

    8593869

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Biasing system and method

    8611153

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods including memory array data line selection

    8619471

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Devices and systems including enabling circuits

    8675420

    Tanzawa; Toru, Ghalam; Ali Feiz Zarrin

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods including memory write operation

    8681561

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory devices and programming methods that program a memory cell with a data value, read the data value from the memory cell and reprogram the memory cell with the read data value

    8743622

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory devices having data lines included in top and bottom conductive lines

    8780631

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Random telegraph signal noise reduction scheme for semiconductor memories

    8780638

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods including memory with top and bottom data lines

    8792263

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods for transposing select gates

    8796778

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Vertical memory with body connection

    8797804

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory array with power-efficient read architecture

    8811084

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Methods and apparatuses including a select transistor having a body region including monocrystalline semiconductor material and/or at least a portion of its gate located in a substrate

    8837222

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Devices for shielding a signal line over an active region

    8853778

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Semiconductor apparatus with multiple tiers of memory cells with peripheral transistors, and methods

    8860117

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Compensating for off-current in a memory

    8861274

    Tanzawa; Toru

    Rights holder: Intel Corporation

    Patent

  • Apparatuses and methods involving accessing distributed sub-blocks of memory cells

    8891305

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Three-dimensional devices having reduced contact length

    8952482

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatus and methods for applying a non-zero voltage differential across a memory cell not involved in an access operation

    8971117

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory read apparatus and methods

    8976594

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Sharing support circuitry in a memory

    8995188

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Voltage generator circuit

    9000836

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Biasing system and method

    9019766

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Voltage generation and adjustment in a memory device

    9025385

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods including memory array data line selection

    9030882

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Charge pump redundancy in a memory

    9042180

    Tanzawa; Toru, Tanaka; Tomoharu

    Rights holder: Intel Corporation

    Patent

  • Method of error correction of a memory

    9053043

    Tanaka; Tomoharu, Shibata; Noboru, Tanzawa; Toru

    Rights holder: Kabushiki Kaisha Toshiba

    Patent

  • Apparatuses and methods for coupling load current to a common source

    9064551

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods for transposing select gates

    9064576

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods to control body potential in memory operations

    9064577

    Zhao; Han, Goda; Akira, Parat; Krishna K., Mauri; Aurelio Giancarlo, Liu; Haitao, Tanzawa; Toru, Yamada; Shigekazu, Sakui; Koji

    Rights holder: Micron Technology, Inc.

    Patent

  • Enable/disable of memory chunks during memory access

    9064578

    Tanzawa; Toru, Tamada; Satoru, Kawai; Koichi, Manabe; Tetsuji

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods including memory array and data line architecture

    9082485

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Interconnections for 3D memory

    9111591

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory having memory cell string and coupling components

    9111620

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Short-checking methods

    9136017

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Vertical memory with body connection

    9171587

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods including memory with top and bottom data lines

    9177614

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory array with power-efficient read architecture

    9208891

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods for coupling load current to a common source

    9224477

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Random telegraph signal noise reduction scheme for semiconductor memories

    9257180

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Methods and apparatuses including a select transistor having a body region including monocrystalline semiconductor material and/or at least a portion of its gate located in a substrate

    9263460

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses including memory arrays with source contacts adjacent edges of sources

    9263461

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Independently selective tile group access with data structuring

    9285997

    Tanzawa; Toru

    Rights holder: Intel Corporation

    Patent

  • Apparatuses and methods including memory write operation

    9299437

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Methods applying a non-zero voltage differential across a memory cell not involved in an access operation

    9305656

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information

    9318173

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods including memory array data line selection

    9318211

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Compensating for off-current in a memory

    9324443

    Tanzawa; Toru

    Rights holder: Intel Corporation

    Patent

  • Short-checking methods

    9330789

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Three-dimensional devices having reduced contact length

    9343479

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory read apparatus and methods

    9349470

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Interconnections for 3D memory

    9368216

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Programming a memory cell to a voltage to indicate a data value and after a relaxation time programming the memory cell to a second voltage to indicate the data value

    9378823

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Devices and systems including enabling circuits

    9401188

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods using dummy cells programmed to different states

    9412451

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Current leakage reduction in 3D NAND memory

    9424936

    Toru Tanzawa, Akira Goda, Shigekazu Yamada, Hiroyuki Sanda

    Rights holder: Intel Corporation

    Patent

  • Sequential memory access operations

    9430417

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory devices having data lines included in top and bottom conductive lines

    9437253

    Tanzawa; Toru

    Rights holder: Micron Technology, Inc.

    Patent

  • Enable/disable of memory chunks during memory access

    9536582

    Toru Tanzawa, Satoru Tamada, Koichi Kawai, Tetsuji Manabe

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods to control body potential in memory operations

    9536618

    Han Zhao, Akira Goda, Krishna K. Parat, Aurielo Giancarlo Mauri, Haitao Liu, Toru Tanzawa, Shigekazu Yamada, Koji Sakui

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory array having connections going through control gates

    9595533

    Toru Tanzawa, Tamotsu Murakoshi, Deepak Thimmegowda

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods for charging a global access line prior to accessing a memory

    9607705

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Devices for shielding a signal line over an active region

    9614516

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Voltage generator circuit

    9641068

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Selectable memory access time

    9646660

    Toru Tanzawa

    Rights holder: Intel Corporation

    Patent

  • Apparatuses and methods using dummy cells programmed to different states

    9697907

    Toru Tanzawa, Aaron Yip

    Rights holder: Micron Technology, Inc.

    Patent

  • Semiconductor apparatus with multiple tiers, and methods

    9704876

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Devices including memory arrays, row decoder circuitries and column decoder circuitries

    9711224

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Methods and apparatuses including a select transistor having a body region including monocrystalline semiconductor material and/or at least a portion of its gate located in a substrate

    9711514

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatus and methods of operating memory with erase de-bias

    9711228

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Data line arrangement and pillar arrangement in apparatuses

    9721960

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Chunk redundancy architecture for memory

    9727417

    Toru Tanzawa

    Rights holder: Intel Corporation

    Patent

  • Three-dimensional devices having reduced contact length

    9728538

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Random telegraph signal noise reduction scheme for semiconductor memories

    9747991

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory read apparatus and methods

    9773564

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Segmented memory and operation

    9773553

    Toru Tanzawa, Han Zhao

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods involving accessing distributed sub-blocks of memory cells

    9779791

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory having memory cell string and coupling components

    9780110

    Toru Tanzawa

    Rights holder: Micron Technology

    Patent

  • Connecting memory cells to a data line sequentially while applying a program voltage to the memory cells

    9779819

    Qiang Tang, Ramin Ghodsi, Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Sequential memory access operations

    9778846

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Interconnections for 3D memory

    9786334

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory array with power-efficient read architecture

    9842652

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods to control body potential in 3D non-volatile memory operations

    9881686

    Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu, Toru Tanzawa, Shigekazu Yamada, Koji Sakui

    Rights holder: Micron Technology, Inc.

    Patent

  • Interconnections for 3D memory

    9881651

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods for charging a global access line prior to accessing a memory

    9892797

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Semiconductor device structures including staircase structures, and related methods and electronic systems

    9905514

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation

    9910594

    Shantanu R. Rajwade, Pranav Kalavade, Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Methods of operating memory under erase conditions

    9953711

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Chunk redundancy architecture for memory

    9996438

    Toru Tanzawa

    Rights holder: Intel Corporation

    Patent

  • Devices including memory arrays, row decoder circuitries and column decoder circuitries

    10014057

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses including memory arrays with source contacts adjacent edges of sources

    10050049

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Methods including establishing a negative body potential in a memory cell

    10049750

    Koji Sakui, Mark Hawes, Toru Tanzawa, Jeremy Binfet

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods using dummy cells programmed to different states

    10079064

    Toru Tanzawa, Aaron Yip

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods for charging a global access line prior to accessing a memory

    10079063

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information

    10083265

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory array with power-efficient read architecture

    10090051

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Field effect transistors having a fin

    10096696

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Random telegraph signal noise reduction scheme for semiconductor memories

    10102914

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Interconnections for 3D memory

    10109325

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Connecting memory cells to a data line sequentially while applying a program voltage to the memory cells

    10121544

    Qiang Tang, Ramin Ghodsi, Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Three dimensional memory device with access signal triggering from voltage pump output levels

    10127991

    Toru Tanzawa

    Rights holder: Intel Corporation

    Patent

  • Methods of programming and sensing in a memory device

    10153043

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory having memory cell string and coupling components

    10163928

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory device including pass transistors in memory tiers

    10170490

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods involving accessing distributed sub-blocks of memory cells

    10170169

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods to control body potential in 3D non-volatile memory operations

    10170196

    Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu, Toru Tanzawa, Shigekazu Yamada, Koji Sakui

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatus and methods of operating memory for negative gate to body conditions

    10170193

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory device including mixed non-volatile memory cell types

    10203885

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory read apparatus and methods

    10210940

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory devices with a transistor that selectively connects a data line to another data line

    10224103

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Segmented memory and operation

    10242742

    Toru Tanzawa, Han Zhao

    Rights holder: Micron Technology, Inc.

    Patent

  • Devices including memory arrays, row decoder circuitries and column decoder circuitries

    10262739

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods using dummy cells programmed to different states

    10262745

    Toru Tanzawa, Aaron Yip

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory devices having selectively electrically connected data lines

    10269431

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Sequential memory access operations

    10282093

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Interconnections for 3D memory

    10304498

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Tier mode for access operations to 3D memory

    10310734

    Toru Tanzawa

    Rights holder: Intel Corporation

    Patent

  • Apparatuses and methods for charging a global access line prior to accessing a memory

    10340015

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information

    10354030

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory devices having selectively electrically connected data lines

    10366759

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation

    10379738

    Shantanu R. Rajwade, Pranav Kalavade, Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatus and methods including establishing a negative body potential in a memory cell

    10453538

    Koji Sakui, Mark Hawes, Toru Tanzawa, Jeremy Binfet

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory having memory cell string and coupling components

    10484718

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods to control body potential in 3D non-volatile memory operations

    10490292

    Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu, Toru Tanzawa, Shigekazu Yamada, Koji Sakui

    Rights holder: Micron Technology, Inc.

    Patent

  • Connecting memory cells to a data line sequentially while applying a read voltage to the memory cells and programming the read data to a single memory cell

    10504599

    Qiang Tang, Ramin Ghodsi, Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Random telegraph signal noise reduction scheme for semiconductor memories

    10510420

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory device including mixed non-volatile memory cell types

    10521130

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Field effect transistors having a fin

    10573728

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Semiconductor apparatus with multiple tiers, and methods

    10580790

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory read apparatus and methods

    10580502

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Segmented memory and operation

    10672477

    Toru Tanzawa, Han Zhao

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods for charging a global access line prior to accessing a memory

    10685721

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Three-dimensional devices having reduced contact length

    10692870

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Interconnections for 3D memory

    10706895

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods involving accessing distributed sub-blocks of memory cells

    10734049

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods using dummy cells programmed to different states

    10741259

    Toru Tanzawa, Aaron Yip

    Rights holder: Micron Technology, Inc.

    Patent

  • Methods of forming semiconductor device structures including staircase structures

    10748918

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory array having connections going through control gates

    10770470

    Toru Tanzawa, Tamotsu Murakoshi, Deepak Thimmegowda

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory device including pass transistors in memory tiers

    10784269

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods to control body potential in 3D non-volatile memory operations

    10796778

    Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu, Toru Tanzawa, Shigekazu Yamada, Koji Sakui

    Rights holder: Micron Technology, Inc.

    Patent

  • Sequential memory access operations

    10824336

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Segmented memory operation

    10854293

    Toru Tanzawa, Han Zhao

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses including memory arrays with source contacts adjacent edges of sources

    10879255

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory device including mixed non-volatile memory cell types

    10901623

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatus and methods including establishing a negative body potential in a memory cell

    10916313

    Koji Sakui, Mark Hawes, Toru Tanzawa, Jeremy Binfet

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information

    10956642

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory read apparatus and methods

    10964400

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Random telegraph signal noise reduction scheme for semiconductor memories

    10998054

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Three-dimensional devices having reduced contact length

    11018135

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Semiconductor apparatus with multiple tiers, and methods

    11145673

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation

    11182074

    Shantanu R. Rajwade, Pranav Kalavade, Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Semiconductor device and manufacturing method for same

    11258008

    Toru Tanzawa

    Rights holder: National University Corporation Shizuoka University

    Patent

  • Interconnections for 3D memory

    11276437

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Apparatuses and methods involving accessing distributed sub-blocks of memory cells

    11282556

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory device including mixed non-volatile memory cell types

    11347401

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory array having connections going through control gates

    11398489

    Toru Tanzawa, Tamotsu Murakoshi, Deepak Thimmegowda

    Rights holder: Micron Technology, Inc.

    Patent

  • Memory device including pass transistors in memory tiers

    11417671

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Field effect transistors having a fin

    11462629

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

  • Random telegraph signal noise reduction scheme for semiconductor memories

    11462277

    Toru Tanzawa

    Rights holder: Micron Technology, Inc.

    Patent

▼display all

 

Syllabus

▼display all

Teaching Experience

  • 電子回路II

    静岡大学  

  • 電子回路I

    静岡大学  

  • 電子回路Ⅰ

    静岡大学  

  • 電気電子工学研究第二

    静岡大学  

  • 電気電子工学研究第一

    静岡大学  

  • 電気電子工学概論

    静岡大学  

  • 電気電子工学セミナー第一

    静岡大学  

  • 電気電子工学セミナー第ニ

    静岡大学  

  • 電気回路Ⅰ

    静岡大学  

  • 卒業研究

    静岡大学  

  • 数値シミュレーション

    静岡大学  

  • 集積回路工学

    静岡大学  

  • 集積回路プロセス工学特論

    静岡大学  

  • 集積プロセス・デバイス工学特論

    静岡大学  

  • セミナー1

    静岡大学  

  • キャリアデザイン

  • 電気電子工学セミナー第二

    静岡大学  

  • 社会と製造業

    静岡大学  

  • プロセッサ工学

    静岡大学  

▼display all

 

Research Institute

  • 2024
     
     

    Waseda Research Institute for Science and Engineering   Concurrent Researcher