Committee Memberships
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2017.06-2023.05
電子情報通信学会エレクトロニクスソサエティ 集積回路研究専門委員会 専門委員
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2020.11-2021.07
電子情報通信学会 集積回路設計技術に関する小特集編集委員会
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2013.05-2019.09
IEEE ESSCIRC Technical program committee
Details of a Researcher
Updated on 2024/12/07
電子情報通信学会エレクトロニクスソサエティ 集積回路研究専門委員会 専門委員
電子情報通信学会 集積回路設計技術に関する小特集編集委員会
IEEE ESSCIRC Technical program committee
IEICE
IEEE
Low power analog
Energy harvesting
Greening of integrated circuits
IoT
Power management
Circuit design
Test of Time Award
2023.06 Symposium on VLSI Technology and Circuits
Winner: H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi, K. Sakui
IEEE Fellow
2016.01 IEEE
Toru Tanzawa
IEEE Solid-State Circuits Magazine 16 ( 4 ) 83 - 95 2024.11 [Refereed]
Authorship:Lead author, Last author, Corresponding author
A Low-Power BL Path Design for NAND Flash Based on an Existing NAND Interface
Hikaru Makino, Toru Tanzawa
Journal of Low Power Electronics and Applications 14 ( 1 ) 1 - 16 2024.02 [Refereed]
Modeling of Cross-Coupled AC–DC Charge Pump Operating in Subthreshold Region
Ryoma Kotsubo, Toru Tanzawa
Electronics 12 ( 24 ) 5031 - 5031 2023.12 [Refereed]
Authorship:Corresponding author
Battery-Assisted Battery Charger with Maximum Power Point Tracking for Thermoelectric Generator: Concept and Experimental Proof
S. Tanabe, T. Tanzawa
Electronics ( 19 ) 2023.09 [Refereed]
A −31.7 dBm Sensitivity 0.011mm2 CMOS On-Chip Rectifier for Microwave Wireless Power Transfer
Takuma Hashimoto, Hikaru Nekozuka, Yoshitaka Toeda, Masayuki Otani, Yasuhiko Fukuoka, Toru Tanzawa
Electronics ( 6 ) 2023.03 [Refereed]
One-Dimensional Maximum Power Point Tracking Design of Switched-Capacitor Charge Pumps for Thermoelectric Energy Harvesting
K. Nono, T. Tanzawa
Electronics ( 5 ) 2023.03 [Refereed]
A Charge Loss Aware Advanced Model of Dickson Voltage Multipliers
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo, Toru Tanzawa
IEEE Access 10 2022.11 [Refereed]
A Design of a Thermoelectric Energy Harvester for Minimizing Sensor Module Cost
Koketsu, K., Tanzawa, T.
Electronics (Switzerland) 11 ( 21 ) 2022.10 [Refereed]
Hashimoto, T., Tanzawa, T.
Electronics (Switzerland) 11 ( 19 ) 2022.10 [Refereed]
More Enhanced Swing Colpitts Oscillators: A Circuit Analysis
Nomura, T., Tanzawa, T.
Electronics (Switzerland) 11 ( 18 ) 2022.09 [Refereed]
Pre-Emphasis Pulse Design for Reducing Bit-Line Access Time in NAND Flash Memory
Kondo, J., Tanzawa, T.
Electronics (Switzerland) 11 ( 13 ) 1926 2022.06 [Refereed]
Demura, Y., Tanzawa, T.
Electronics (Switzerland) 11 ( 12 ) 1874 2022.06 [Refereed]
An optimum structure of scalable capacitors in 3d crosspoint memory technology
Tone, Y., Tanzawa, T.
Electronics (Switzerland) 10 ( 22 ) 2755 2021.11 [Refereed]
Charge Pumps for Ultra-Low-Power Applications: Analysis, Design, and New Solutions
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo, Toru Tanzawa
IEEE Transactions on Circuits and Systems II: Express Briefs 68 ( 8 ) 2021.08 [Refereed]
Pre-emphasis pulse design for random-access memory
Sugiura, Y., Tanzawa, T.
Electronics (Switzerland) 10 ( 12 ) 2021.06 [Refereed]
A circuit analysis of pre-emphasis pulses for RC delay lines
Matsuyama, K., Tanzawa, T.
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 1 ( 6 ) 912 - 926 2021.06 [Refereed]
Koketsu, K., Tanzawa, T.
Electronics (Switzerland) 10 ( 10 ) 2021.05 [Refereed]
Ishida, Y., Tanzawa, T.
Electronics (Switzerland) 10 ( 10 ) 2021.05 [Refereed]
An optimum design of clocked AC-DC charge pump circuits for vibration energy harvesting
Ye, J., Tanzawa, T.
Electronics (Switzerland) 9 ( 12 ) 2020.12 [Refereed]
A fully integrated clocked AC-DC charge pump for mignetostrictive vibration energy harvesting
Kawauchi, H., Tanzawa, T.
Electronics (Switzerland) 9 ( 12 ) 2020.12 [Refereed]
Linear distribution of capacitance in Dickson charge pumps to reduce rise time
Andrea Ballo, Alfio Dario Grasso, Gaetano Palumbo, Toru Tanzawa
International Journal of Circuit Theory and Applications 48 ( 4 ) 2020.04 [Refereed]
Toru Tanzawa
Proceedings of the Ieee Asia-pacific Microwave Conference (apmc) 2019
Toward a Minimum-Operating-Voltage Design of DC-DC Charge Pump Circuits for Energy Harvesting
Toru Tanzawa
IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS 2019
Design of Pre-Emphasis Pulses for Large Memory Arrays with Minimal Word-Line Delay Time
Toru Tanzawa
IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS 2019
Toru Tanzawa
IEEE Transactions on Circuits and Systems II: Express Briefs 65 ( 11 ) 1664 - 1667 2018.11 [Refereed]
Design considerations on power, performance, reliability and yield in 3D NAND technology
Toru Tanzawa
IEICE Transactions on Electronics E101C ( 1 ) 78 - 81 2018.01 [Refereed]
An Analytical Model of Charge Pump DC-DC Voltage Multiplier Using Diodes
Toru Tanzawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E100A ( 5 ) 1137 - 1144 2017.05 [Refereed]
An Analytical Model of AC-DC Charge Pump Voltage Multipliers
Toru Tanzawa
IEICE TRANSACTIONS ON ELECTRONICS E99C ( 1 ) 108 - 118 2016.01 [Refereed]
system overview and key design considerations
Tanzawa, T.
Analog Circuits and Signal Processing 2016
Toru Tanzawa
IEEE Solid-State Circuits Magazine 16 ( 4 ) 83 - 95 2015.11 [Refereed]
Authorship:Lead author, Last author, Corresponding author
On-chip High-Voltage Generator Design: Design Methodology for Charge Pumps: Second Edition
Tanzawa, T.
On-chip High-Voltage Generator Design: Design Methodology for Charge Pumps: Second Edition 2015
A Comprehensive Optimization Methodology for Designing Charge Pump Voltage Multipliers
Toru Tanzawa
2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) 1358 - 1361 2015 [Refereed]
An Optimum Design for Integrated Switched-Capacitor Dickson Charge Pump Multipliers With Area Power Balance
Toru Tanzawa
IEEE TRANSACTIONS ON POWER ELECTRONICS 29 ( 2 ) 534 - 538 2014.02 [Refereed]
An Analytical Model of AC-DC Voltage Multipliers
Toru Tanzawa
2014 21ST IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS) 323 - 326 2014 [Refereed]
Design of DC-DC Switched-Capacitor Voltage Multiplier driven by DC Energy Transducer
Toru Tanzawa
2014 21ST IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS) 327 - 330 2014 [Refereed]
A Behavior Model of an On-Chip High Voltage Generator for Fast, System-Level Simulation
Toru Tanzawa
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 20 ( 12 ) 2351 - 2355 2012.12 [Refereed]
A Switch-Resistance-Aware Dickson Charge Pump Model for Optimizing Clock Frequency
Toru Tanzawa
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 58 ( 6 ) 336 - 340 2011.06 [Refereed]
A Program Disturb Model and Channel Leakage Current Study for Sub-20 nm NAND Flash Cells
Alessandro Torsi, Yijie Zhao, Haitao Liu, Toru Tanzawa, Akira Goda, Pranav Kalavade, Krishna Parat
IEEE TRANSACTIONS ON ELECTRON DEVICES 58 ( 1 ) 11 - 16 2011.01 [Refereed]
On Two-Phase Switched-Capacitor Multipliers With Minimum Circuit Area
Toru Tanzawa
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 57 ( 10 ) 2602 - 2608 2010.10 [Refereed]
A Behavior Model of a Dickson Charge Pump Circuit for Designing a Multiple Charge Pump System Distributed in LSIs
Toru Tanzawa
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 57 ( 7 ) 527 - 530 2010.07 [Refereed]
Dickson Charge Pump Circuit Design with Parasitic Resistance in Power Lines
Toru Tanzawa
IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS 2009
Toru Tanzawa
IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS 2008
A 2.4-GHz temperature-compensated CMOS LC-VCO for low frequency drift low-power direct-modulation GFSK transmitters
T Tanzawa, K Agawa, H Shibayama, R Terauchi, K Hisano, H Ishikuro, S Kousai, H Kobayashi, H Majima, T Takayama, M Koizumi, F Hatori
IEICE TRANSACTIONS ON ELECTRONICS E88C ( 4 ) 490 - 495 2005.04 [Refereed]
A 44-mm(2) four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller
T Tanzawa, A Umezawa, T Taura, H Shiga, T Hara, Y Takano, T Miyaba, N Tokiwa, K Watanabe, H Watanabe, K Masuda, K Naruke, H Kato, S Atsumi
IEEE JOURNAL OF SOLID-STATE CIRCUITS 37 ( 11 ) 1485 - 1492 2002.11 [Refereed]
High-voltage transistor scaling circuit techniques for high-density negative-gate, channel-erasing NOR flash memories
T Tanzawa, Y Takano, K Watanabe, S Atsumi
IEEE JOURNAL OF SOLID-STATE CIRCUITS 37 ( 10 ) 1318 - 1325 2002.10 [Refereed]
Circuit techniques for a 1.8-V-only NAND flash memory
T Tanzawa, T Tanaka, K Takeuchi, H Nakamura
IEEE JOURNAL OF SOLID-STATE CIRCUITS 37 ( 1 ) 84 - 89 2002.01 [Refereed]
Wordline voltage generating system for low-power low-voltage flash memories
T Tanzawa, A Umezawa, M Kuriyama, T Taura, H Banba, T Miyaba, H Shiga, Y Takano, S Atsumi
IEEE JOURNAL OF SOLID-STATE CIRCUITS 36 ( 1 ) 55 - 63 2001.01 [Refereed]
A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme
S Atsumi, A Umezawa, T Tanzawa, T Taura, H Shiga, Y Takano, T Miyaba, M Matsui, H Watanabe, K Isobe, S Kitamura, S Yamada, M Saito, S Mori, T Watanabe
IEEE JOURNAL OF SOLID-STATE CIRCUITS 35 ( 11 ) 1648 - 1654 2000.11 [Refereed]
Design of a sense circuit for low-voltage flash memories
T Tanzawa, Y Takano, T Taura, S Atsumi
IEEE JOURNAL OF SOLID-STATE CIRCUITS 35 ( 10 ) 1415 - 1421 2000.10 [Refereed]
Optimization of word-line booster circuits for low-voltage flash memories
T Tanzawa, S Atsumi
IEEE JOURNAL OF SOLID-STATE CIRCUITS 34 ( 8 ) 1091 - 1098 1999.08 [Refereed]
A CMOS bandgap reference circuit with sub-1-V operation
H Banba, H Shiga, A Umezawa, T Miyaba, T Tanzawa, S Atsumi, K Sakui
IEEE JOURNAL OF SOLID-STATE CIRCUITS 34 ( 5 ) 670 - 674 1999.05 [Refereed]
A multipage cell architecture for high-speed programming multilevel NAND flash memories
K Takeuchi, T Tanaka, T Tanzawa
IEEE JOURNAL OF SOLID-STATE CIRCUITS 33 ( 8 ) 1228 - 1238 1998.08 [Refereed]
A dynamic analysis of the Dickson charge pump circuit
T Tanzawa, T Tanaka
IEEE JOURNAL OF SOLID-STATE CIRCUITS 32 ( 8 ) 1231 - 1240 1997.08 [Refereed]
A stable programming pulse generator for single power supply flash memories
T Tanzawa, T Tanaka
IEEE JOURNAL OF SOLID-STATE CIRCUITS 32 ( 6 ) 845 - 851 1997.06 [Refereed]
A compact on-chip ECC for low cost flash memories
T Tanzawa, T Tanaka, K Takeuchi, R Shirota, S Aritome, H Watanabe, G Kemink, K Shimizu, S Sato, Y Takeucki, K Ohuchi
IEEE JOURNAL OF SOLID-STATE CIRCUITS 32 ( 5 ) 662 - 669 1997.05 [Refereed]
QUANTUM-MECHANICS OF A PARTICLE CONFINED TO A TWISTED RING
S TAKAGI, T TANZAWA
PROGRESS OF THEORETICAL PHYSICS 87 ( 3 ) 561 - 568 1992.03 [Refereed]
QUANTUM-MECHANICS OF A PARTICLE ON A CURVED SURFACE - COMPARISON OF 3 DIFFERENT APPROACHES
Toru Tanzawa
Progress of Theoretical Physics 88 ( 2 ) 229 - 249 1992.02 [Refereed]
Fully-Integrated Power Management Circuits for Thermoelectric Energy Harvesting
Toru Tanzawa( Part: Sole author)
Springer Nature 2024.06 ISBN: 9783031597886
On-chip High-Voltage Generator Design: Design Methodology for Charge Pumps, 2nd edition
T. Tanzawa( Part: Sole author)
Springer 2015.10
Power Aware Design Methodologies
T. Tanzawa( Part: Joint author)
Kluwer Academic Publishers 2002.01
Evolution of integrated switched-capacitor converters (Keynote)
Toru Tanzawa [Invited]
39th Conference on Design of Circuits and Integrated Systems (DCIS 2024)
Presentation date: 2024.11
Design of Switched-Capacitor AC-DC Voltage Down Converters Driven by Highly Resistive Energy Transducers
Naoto Miyazaki, Toru Tanzawa
39th Conference on Design of Circuits and Integrated Systems (DCIS 2024)
Presentation date: 2024.11
Circuit design of power converters for long operating life IoT edge devices
Toru Tanzawa [Invited]
IEICE Society Conference
Presentation date: 2024.09
A Design of Battery Charger Boost Converters Operating at Input Voltages Below 10 mV for Energy Harvesting
Wataru Saito, Toru Tanzawa
TJCAS2024
Presentation date: 2024.08
NAND Flash Design for 30% Power Reduction
Toru Tanzawa
FMS (Previously "Flash Memory Summit", Currently "Future of Memory and Storage")
Presentation date: 2024.08
電圧振幅拡大型コルピッツ・オシレータを用いた昇圧回路の設計と動作実証
稲葉泰誠, 丹沢徹
LSIとシステムワークショップ 2024
Presentation date: 2024.05
低電圧電源バッテリ充電器のスイッチング・レギュレータ設計
齋藤航, 丹沢徹
LSIとシステムワークショップ 2024
Presentation date: 2024.05
熱電素子バッテリ直列接続型バッテリ充電回路の充電効率最大化
山本 究太郎, 丹沢 徹
電子情報通信学会総合大会
Presentation date: 2024.03
論理回路電源電圧下限の解析
平野 敬祐, 丹沢 徹
電子情報通信学会総合大会
Presentation date: 2024.03
100mV以下の電源から1.5Vバッテリを充電するチャージポンプの設計
樋口 愛莉, 丹沢 徹
電子情報通信学会総合大会
Presentation date: 2024.03
NANDフラッシュの高速化と低電力化を同時に実現する動的ビット線分割方式
杉澤 有右太, 丹沢 徹
電子情報通信学会総合大会
Presentation date: 2024.03
バッテリ充電器用バッテリ電圧監視回路の回路面積最小化設計
佐藤 光翼, 丹沢 徹
電子情報通信学会総合大会
Presentation date: 2024.03
高インピーダンス発電素子用Switched capacitor降圧コンバータの性能比較: 直並切替型対Dickson型
宮崎 直人, 丹沢 徹
電子情報通信学会総合大会
Presentation date: 2024.03
電圧振幅拡大型コルピッツオシレータを用いたDC-DC昇圧回路の動作実証
稲葉 泰誠, 丹沢 徹
電子情報通信学会総合大会
Presentation date: 2024.03
熱電素子バッテリ直列接続型バッテリ充電回路のMPPT回路設計
田辺 駿介, 丹沢 徹
電子情報通信学会総合大会
Presentation date: 2024.03
差動型LC発振器駆動チャージポンプの昇圧特性評価
植村寛太, 丹沢 徹
電子情報通信学会総合大会
Presentation date: 2024.03
Fully-Integrated Power Management Circuits for Thermoelectric Energy Harvesting: Fundamentals and Challenges
Toru Tanzawa [Invited]
Tutorial at the IEEE 30th International Conference on Electronics, Circuits and Systems (ICECS)
Presentation date: 2023.12
高い電力変換効率と低コスト化を目指したエナジーハーベスト用電源回路
丹沢 徹 [Invited]
電子情報技術産業協会にてスマートセンシングとその社会実装技術分科会
Presentation date: 2023.11
IoT端末 環境発電でバッテリー交換の手間を省きます!
丹沢 徹
イノベーション・ジャパン2023
Presentation date: 2023.08
A Hybrid Thermoelectric Generator – Battery Power Supply System Toward Replacement-Free Battery
S. Tanabe, Y. Sakamoto, H. Uchida, T. Tanzawa
International Conference on Power Electronics - ECCE Asia
Presentation date: 2023.05
静電振動発電用降圧コンバータの設計
宮崎直人, 丹沢徹
LSIとシステムのワークショップ
Presentation date: 2023.05
極低電圧電源動作バッテリ充電器の設計
齋藤航, 丹沢徹
LSIとシステムのワークショップ
Presentation date: 2023.05
振幅拡大型コルピッツ・オシレータとそれを利用したオンチップ昇圧回路の設計
稲葉泰誠, 野村達也, 丹沢 徹
LSIとシステムのワークショップ
Presentation date: 2023.05
LC発振器駆動チャージポンプの設計
植村寛太, 丹沢 徹
LSIとシステムのワークショップ
Presentation date: 2023.05
高入力感度マイクロ波無線電力伝送用CMOSオンチップ整流回路の設計
橋本拓磨, 猫塚 光, 戸枝佳駿, 大谷昌幸, 福岡泰彦, 丹沢 徹
電子情報通信学会総合大会
Presentation date: 2023.03
NANDフラッシュ用ブースト・コンバータの高速昇圧動作設計
金山湧司, 丹沢 徹
電子情報通信学会/電子通信エネルギー技術研究会
Presentation date: 2023.01
無線電力伝送用ラッチ型RF-DCチャージポンプの回路モデル
小坪稜麻, 丹沢 徹
電子情報通信学会/電子通信エネルギー技術研究会
Presentation date: 2023.01
バッテリーと熱電発電素子からなるハイブリッド電源用DC-DCコンバータ設計
田辺駿介, 丹沢 徹
電子情報通信学会/電子通信エネルギー技術研究会
Presentation date: 2023.01
CMOSクロスカップル型RF-DCチャージポンプの回路モデル
小坪稜麻, 丹沢 徹
Young CAS Researchers Workshop
Presentation date: 2022.11
NANDフラッシュ用ブースト・コンバータの高速昇圧動作方式
金山湧司, 丹沢 徹
Young CAS Researchers Workshop
Presentation date: 2022.11
IoT端末のバッテリ交換を不要とするハイブリッド電源回路
田辺駿介, 酒本陽介, 丹沢 徹
Young CAS Researchers Workshop
Presentation date: 2022.11
H. Makino, T. Tanzawa
Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) in 2022 IEEE the 18th Asia Pacific Conference on Circuits and Systems
Presentation date: 2022.11
バッテリー交換不要の熱電発電用電源回路
丹沢 徹
イノベーション・ジャパン2022
Presentation date: 2022.10
熱電素子・バッテリーのハイブリッド電源用DC/DCコンバータのコンセプト実証
田辺駿介, 酒本陽介, 丹沢徹
2022年電子情報通信学会ソサイエティ大会
Presentation date: 2022.09
Antenna/On-Chip-Rectifier Co-Design Methodology for Micro-Watt Microwave Wireless Power Transfer
T. Hashimoto, T. Tanzawa
65th IEEE International Midwest Symposium on Circuits and Systems(MWSCAS 2022)
Presentation date: 2022.08
マイクロ波無線電力伝送レクテナの入力パワー最小化設計
橋本拓磨, 丹沢 徹
LSIとシステムのワークショップ
Presentation date: 2022.05
NANDフラッシュ用ブースト・コンバータの最速昇圧方式の提案
金山湧司, 丹沢 徹
LSIとシステムのワークショップ
Presentation date: 2022.05
CMOSラッチ型チャージポンプの出力抵抗モデル
小坪稜麻, 丹沢 徹
LSIとシステムのワークショップ
Presentation date: 2022.05
熱電素子・バッテリーのハイブリッド電源用DC/DC コンバータの設計
田辺駿介, 酒本陽介, 丹沢 徹
LSIとシステムのワークショップ
Presentation date: 2022.05
環境温度が変動時しても常に出力電力を最大にする熱電発電用チャージポンプ回路システムの設計
濃野公一, 丹沢 徹
LSIとシステムのワークショップ
Presentation date: 2022.05
NANDフラッシュの読み出し動作に伴うビット線パスの電力を60%削減する回路設計
牧野 耀, 丹沢 徹
LSIとシステムのワークショップ
Presentation date: 2022.05
インターフェースの変更なしにアレイアクセスの消費電力を30%低減するNANDフラッシュ用センス回路設計
牧野 耀, 丹沢 徹
電子情報通信学会・集積回路研究会
Presentation date: 2022.04
スイッチト・キャパシタ・コンバータ特性の電源インピーダンスの 影響:静電発電用電力変換回路の最適設計に向けて
出村洋介, 丹沢 徹
2022年電子情報通信学会総合大会
Presentation date: 2022.03
回路面積最小でMPPTを実現する熱電発電用チャージポンプ電源回路システムの設計
濃野公一, 丹沢 徹
2021年電子情報通信学会ソサイエティ大会
Presentation date: 2021.09
マイクロワットレベルのマイクロ波無線電力伝送受信アンテナとオンチップ整流器の最適設計
橋本拓磨, 丹沢 徹
2021年電子情報通信学会ソサイエティ大会
Presentation date: 2021.09
熱電素子を用いてバッテリー寿命を延ばすバッテリー・熱電素子直列接続型DC/DCコンバーターの設計
酒本陽介, 丹沢 徹
2021年電子情報通信学会ソサイエティ大会
Presentation date: 2021.09
開放交流電圧が10V を超える静電発電素子から1V トランジスタだけで直流1V に変換するインターフェース回路の設計
石田 遥祐, 丹沢 徹
電子情報通信学会 集積回路研究会
Presentation date: 2021.08
大メモリアレイのWL遅延を最小化するプリエンファシスパルス:回路理論と最適パルス発生回路の提案
丹沢 徹, 松山 和樹 [Invited]
電子情報通信学会集積回路研究会
Presentation date: 2021.04
K. Nono, T. Tanzawa
IEICE general conference
Presentation date: 2021.03
A Design Guideline of Scalable Capacitors in 3D Cross-Point Memory
Y. Tone, T. Tanzawa
IEICE general conference
Presentation date: 2021.03
A Study of Sensing Schemes for NAND Flash: Shielded Bit-Line vs. All Bit-Line
H. Makino, T. Tanzawa
IEICE general conference
Presentation date: 2021.03
T. Hashimoto, T. Tanzawa
IEICE general conference
Presentation date: 2021.03
A Design of Cold Start Charge Pump for Flexible Thermoelectric Generator with High Output Impedance
Kazuma Koketsu, Toru Tanzawa
IEEE International Conference on Electronics Circuits and Systems
Presentation date: 2020.11
Rectenna with Serially Connected Diodes for Micro-watt Energy Harvesting
Yuki Tabuchi, Toru Tanzawa
IEEE Wireless Power Transfer Conference
Presentation date: 2020.11
IoTエッジ端末の小型化低コスト化振動発電用電源回路
丹沢 徹
イノベーション・ジャパン2020
Presentation date: 2020.09
バッテリー・熱電素子直列接続型電力変換回路システムの バッテリー長寿命化コンセプトの実証
Y. Sakamoto, T. Tanzawa
IEICE society conference, C-12-9
Presentation date: 2020.09
静電振動発電用耐プロセス温度変動 完全集積化シャント・レギュレータの設計
Y. Ishida, T. Tanzawa
IEICE society conference, C-12-8
Presentation date: 2020.09
マイクロワット・レクテナ最適回路トポロジーの 出力電圧電流平面へのマッピング
Y. Tabuchi, T. Tanzawa
IEICE society conference, C-2-11
Presentation date: 2020.09
An Optimum Circuit Design of clocked AC-DC charge pumps
J. Ye, T. Tanzawa
IEICE general conference
Presentation date: 2020.03
T. Nomura, T. Tanzawa
IEICE general conference
Presentation date: 2020.03
An Optimum Pre-Emphasis Pulse Design for Random Access Memory
Y. Sugiura, T. Tanzawa
IEICE general conference
Presentation date: 2020.03
A Power Converter System for Energy Harvesting Toward Zero Net Battery Power
Y. Sakamoto, H. Uchida, T. Tanzawa
IEICE general conference
Presentation date: 2020.03
Y. Yamazaki, M. Tsuchiaki, T. Tanzawa
IEEE Asia-Pacific Microwave Conference (APMC)
Presentation date: 2019.12
A 2V 3.8μW Fully-Integrated Clocked AC-DC Charge Pump with 0.5V 500Ω Vibration Energy Harvester
H. Kawauchi, T. Tanzawa
IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
Presentation date: 2019.11
K. Matsuyama, T. Tanzawa
IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
Presentation date: 2019.11
Design of Pre-Emphasis Pulses for Large Memory Arrays with Minimal Word-Line Delay Time
K. Matsuyama, T. Tanzawa
IEEE International Symposium on Circuits and Systems (ISCAS)
Presentation date: 2019.05
Toward a minimum-operating-voltage design of DC-DC charge pump circuits for energy harvesting
S. Tokuda, T. Tanzawa
IEEE International Symposium on Circuits and Systems (ISCAS)
Presentation date: 2019.05
Y. Yamazaki, T. Tanzawa
IEICE general conference
Presentation date: 2019.03
An Optimum Design of Micro-watt RF Energy Harvesters with RF-DC and DC-DC Conversions
Y. Tabuchi, T. Tanzawa
IEICE general conference
Presentation date: 2019.03
K. Koketsu, T. Tanzawa
IEICE general conference
Presentation date: 2019.03
Y. Ishida, T. Tanzawa
IEICE general conference
Presentation date: 2019.03
(Invited) Interface Circuit Design for Energy Harvesting: State of the Art and Challenges
T. Tanzawa [Invited]
IEICE society conference, CI-3-1
Presentation date: 2018.09
Formulation of minimal delay time with pre-emphasis pulses for dense parallel RC lines
K. Matsuyama, T. Tanzawa
IEICE society conference, C-12-5
Presentation date: 2018.09
A system design of clocked AC-DC converter for vibration energy harvesting
H. Kawauchi, T. Tanzawa
IEICE society conference, C-12-9
Presentation date: 2018.09
A closed-form expression for pre-emphasis pulses with minimal RC delay time
K. Matsuyama, T. Tanzawa
IEICE general conference, C-12-35
Presentation date: 2018.03
Toward a minimum-operating-voltage design of DC-DC charge pump circuits for energy harvesting
S. Tokuda, T. Tanzawa
IEICE general conference, C-12-18
Presentation date: 2018.03
An analysis on lower bounds of supply voltages for enhanced-swing Colpitts oscillators
Y. Kawakami, T. Tanzawa
IEICE general conference, C-12-17
Presentation date: 2018.03
H. Kawauchi, T. Tanzawa
IEICE general conference, C-12-16
Presentation date: 2018.03
On-Chip Switched-Capacitor DC-DC Converter in Memory Technology: State of the Art and Challenges
T. Tanzawa
IEEE ECCTD (European Conference on Circuit Theory and Design)
Presentation date: 2017.09
T. Tanzawa
IEEE Asian Solid-State Circuits Conference
Presentation date: 2016.11
An Analytical Model of Multi-Sine AC-DC Voltage Multiplier
T. Tanzawa
IEEE International Conference on Circuits and Systems
Presentation date: 2015.05
A Comprehensive Optimization Methodology for Designing Charge Pump Voltage Multipliers
T. Tanzawa
IEEE International Conference on Circuits and Systems
Presentation date: 2015.05
Design of DC-DC Switched-Capacitor Voltage Multiplier driven by DC Energy Transducer
T. Tanzawa
IEEE International Conference on Electronics Circuits and Systems
Presentation date: 2014.12
An Analytical Model of AC-DC Voltage Multipliers
T. Tanzawa
IEEE International Conference on Electronics Circuits and Systems
Presentation date: 2014.12
A temperature compensation word-line voltage generator for multi-level cell NAND Flash memories
T. Tanzawa
IEEE ESSCIRC
Presentation date: 2010.09
NBTI stress relaxation design for scaling high-voltage transistors in NAND Flash memories
T. Tanzawa
IEEE International Memory Workshop
Presentation date: 2010.08
Dickson charge pump circuit design with parasitic resistance in power lines
T. Tanzawa
IEEE International Conference on Circuits and Systems
Presentation date: 2009.05
A 172mm2 32Gb MLC NAND flash memory in 34nm CMOS
R. Zeng
IEEE International Solid-State Circuits Conference
Presentation date: 2009.01
A process- and temperature-tolerant power-on reset circuit with a flexible detection level higher than the bandgap voltage
T. Tanzawa
IEEE International Conference on Circuits and Systems
Presentation date: 2008.01
A low-IF CMOS single-chip Bluetooth EDR transmitter with digital I/Q mismatch trimming circuit
D. Miyashita
Symposium on VLSI Circuits
Presentation date: 2005.06
A temperature-compensated CMOS LC-VCO enabling the direct modulation architecture in 2.4GHz GFSK transmitter
T. Tanzawa
IEEE Custom Integrated Circuits Conference
Presentation date: 2004.09
A 44mm2 4-bank 8-word page read 64Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller
T. Tanzawa
IEEE International Solid-State Circuits Conference
Presentation date: 2002.02
A channel-erasing 1.8 V-only 32 Mb NOR flash EEPROM with a bit-line direct-sensing scheme
S. Atsumi
IEEE International Solid-State Circuits Conference
Presentation date: 2000.02
A sampling weak-program method to tighten Vth-distribution of 0.5 V for low-voltage flash memories
H. Shiga
Symposium on VLSI Circuits
Presentation date: 1999.06
Novel 0.44 μm2 Ti-salicide STI cell technology for high-density NOR flash memories and high performance embedded application
H. Watanabe
IEEE International Electron Devices Meeting
Presentation date: 1998.12
A CMOS band-gap reference circuit with sub 1 V operation
H. Banba
IEEE Symposium on VLSI Circuits
Presentation date: 1998.06
A novel isolation-scaling technology for NAND EEPROMs with the minimized program disturbance
S. Satoh
IEEE IEDM
Presentation date: 1997.12
A 3.4-Mbyte/sec Programming 3-level NAND Flash Memory Saving 40% Die Size Per Bit
T. Tanaka
IEEE Symposium on VLSI Circuits
Presentation date: 1997.06
A Multi-page Cell Architecture For High-speed Programming Multi-level NAND Flash Memories
K. Takeuchi
IEEE Symposium on VLSI Circuits
Presentation date: 1997.06
Circuit Technologies For A Single-1.8V Flash Memory
T. Tanzawa
IEEE Symposium on VLSI Circuits
Presentation date: 1997.06
A compact on-chip ECC for low cost flash memories
T. Tanzawa
IEEE Symposium on VLSI Circuits
Presentation date: 1996.06
A stable programming pulse generator for high-speed programming single power supply voltage flash memories
T. Tanzawa
IEEE Symposium on VLSI Circuits
Presentation date: 1995.01
A Quick Boosting Charge Pump Circuit for High Density and Low Voltage Flash Memories
T. Tanzawa
IEEE Symposium on VLSI Circuits
Presentation date: 1994.06
極低電圧から昇圧可能な電力変換回路の動作原理解明とIoT端末への応用
基盤研究(C)
Project Year :
Address-Dependent Divided-Bit-Line NAND Flash Memory for Reduction in Latency and Energy
Yuta Sugisawa, Toru Tanzawa
2024.08
Authorship:Last author, Corresponding author
Evolution of Reconfigurable Switched-Capacitor DC-DC Converters
Toru Tanzawa
2024.08
Authorship:Lead author, Last author, Corresponding author
What I have learned through the research on integrated charge pump circuits
丹沢 徹
101 ( 3 ) 320 - 324 2018.03
T. Tanzawa
IEEE Solid-State Circuits Magazine vol. 8 ( No. 3 ) 63 - 73 2016.08
Innovation of Switched-Capacitor Voltage Multiplier: Part 2: Fundamentals of the charge pump
T. Tanzawa
IEEE Solid-State Circuits Magazine vol. 8 ( No. 2 ) 83 - 92 2016.06
Innovation of Switched-Capacitor Voltage Multiplier: Part 1: A Brief History
T. Tanzawa
IEEE Solid-State Circuits Magazine vol. 8 ( No. 1 ) 51 - 59 2016.01
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Non-volatile semiconductor memory device
5555204
Endoh; Tetsuo, Tanaka; Yoshiyuki, Aritome; Seiichi, Shirota; Riichiro, Shuto; Susumu, Tanaka; Tomoharu, Hemink; Gertjan, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Memory system
5621682
Tanzawa; Toru, Tanaka; Tomoharu
Rights holder: Kabushiki Kaisha Toshiba
Patent
Delay circuit, oscillation circuit and semiconductor memory device
5627488
Tanzawa; Toru, Tanaka; Tomoharu, Yamamura; Toshio, Sakui; Koji
Rights holder: Kabushiki Kaisha Toshiba
Patent
Eeprom semiconductor memory device including circuit for generating a voltage higher than a power supply voltage
5706241
Nakamura; Hiroshi , Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor memory device and high-voltage switching circuit
5708606
Tanzawa; Toru, Tanaka; Tomoharu, Takeuchi; Ken
Rights holder: Kabushiki Kaisha Toshiba
Patent
Memory system
5719888
Tanzawa; Toru, Tanaka; Tomoharu
Rights holder: Kabushiki Kaisha Toshiba
Patent
Non-volatile semiconductor memory device and method of programming a non-volatile memory cell to a predetermined state
5774397
Endoh; Tetsuo, Tanaka; Yoshiyuki, Aritome; Seiichi, Shirota; Riichiro, Shuto; Susumu, Tanaka; Tomoharu, Hemink; Gertjan, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor memory device and high-voltage switching circuit
5828621
Tanzawa; Toru, Tanaka; Tomoharu, Takeuchi; Ken
Rights holder: Kabushiki Kaisha Toshiba
Patent
Nonvolatile semiconductor memory with temperature compensation for read/verify referencing scheme
5864504
Tanzawa; Toru, Tanaka; Tomoharu, Takeuchi; Ken
Rights holder: Kabushiki Kaisha Toshiba
Patent
Three-value data storing semiconductor memory system
5901152
Tanaka; Tomoharu, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor memory
5905691
Tanzawa; Toru , Takeuchi; Ken , Tanaka; Tomoharu
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor memory device and high-voltage switching circuit
5909398
Tanzawa; Toru, Tanaka; Tomoharu, Takeuchi; Ken
Rights holder: Kabushiki Kaisha Toshiba
Patent
Error correction/detection circuit and semiconductor memory device using the same
5933436
Tanzawa; Toru, Tanaka; Tomoharu, Shirota; Riichiro, Ohuchi; Kazunori
Rights holder: Kabushiki Kaisha Toshiba
Patent
Non-volatile semiconductor memory device
5946231
Endoh; Tetsuo, Tanaka; Yoshiyuki, Aritome; Seiichi, Shirota; Riichiro, Shuto; Susumu, Tanaka; Tomoharu Hemink; Gertjan Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Delay circuit, oscillation circuit and semiconductor memory device
5969557
Tanzawa; Toru, Tanaka; Tomoharu, Yamamura; Toshio, Sakui; Koji
Rights holder: Kabushiki Kaisha Toshiba
Patent
Nonvolatile semiconductor memory device
5969985
Tanaka; Tomoharu, Ohuchi; Kazunori, Tanzawa; Toru, Takeuchi; Ken
Rights holder: Kabushiki Kaisha Toshiba
Patent
Voltage multiplier circuit and nonvolatile semiconductor memory device having voltage multiplier
5969988
Tanzawa; Toru, Tanaka; Tomoharu, Nakamura; Hiroshi, Tanaka; Yoshiyuki
Rights holder: Kabushiki Kaisha Toshiba
Patent
Memory system
5996108
Tanzawa; Toru, Tanaka; Tomoharu
Rights holder: Kabushiki Kaisha Toshiba
Patent
Non-volatile semiconductor memory device
6014330
Endoh; Tetsuo , Tanaka; Yoshiyuki, Aritome; Seiichi, Shirota; Riichiro, Shuto; Susumu, Tanaka; Tomoharu Hemink; Gertjan, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Nonvolatile semiconductor memory device
6044013
Tanaka; Tomoharu, Ohuchi; Kazunori, Tanzawa; Toru, Takeuchi; Ken
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor memory device
6064611
Tanaka; Tomoharu, Nakamura; Hiroshi, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor memory device
6072719
Tanzawa; Toru, Tanaka; Tomoharu
Rights holder: Kabushiki Kaisha Toshiba
Patent
Nonvolatile semiconductor memory having improved source line drive circuit
6084799
Tanzawa; Toru, Tanaka; Tomoharu
Rights holder: Kabushiki Kaisha Toshiba
Patent
Quantum tunneling effect device and semiconductor composite substrate
6111288
Watanabe; Hiroshi , Yasuda; Naoki , Toriumi; Akira, Tanaka; Tomoharu, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor memory preventing sense amplifier malfunctions due to effects of noise generated in output buffer
6141277
Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor memory device
6154403
Tanzawa; Toru, Tanaka; Tomoharu
Rights holder: Kabushiki Kaisha Toshiba
Patent
Non-volatile semiconductor memory device
6188611
Endoh; Tetsuo, Tanaka; Yoshiyuki , Aritome; Seiichi, Shirota; Riichiro, Shuto; Susumu, Tanaka; Tomoharu Hemink; Gertjan Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor memory device
6208573
Tanaka; Tomoharu, Nakamura; Hiroshi, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Data-erasable non-volatile semiconductor memory device
6222774
Tanzawa; Toru , Umezawa; Akira , Taura; Tadayuki, Atsumi; Shigeru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor memory device
6233189
Tanzawa; Toru, Atsumi; Shigeru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Nonvolatile semiconductor memory
6236609
Tanzawa; Toru , Taura; Tadayuki , Kuriyama; Masao
Rights holder: Kabushiki Kaisha Toshiba
Patent
Non-volatile semiconductor memory device having a function for controlling the range of distribution of memory cell threshold voltages
6240019
Shiga; Hitoshi, Tanzawa; Toru, Saito; Masanobu
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor memory device
6249479
Tanzawa; Toru, Tanaka; Tomoharu
Rights holder: Kabushiki Kaisha Toshiba
Patent
Nonvolatile semiconductor memory device capable of controlling mutual timing of write voltage pulse and transfer voltage pulse
6252798
Satoh; Shinji , Shirota; Riichiro, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Non-volatile semiconductor memory having column sub-selector layout pattern adaptable to miniaturization of memory cell
6256227
Atsumi; Shigeru , Umezawa; Akira , Tanzawa; Toru, Yamada; Seiji
Rights holder: Kabushiki Kaisha Toshiba
Patent
Pump circuit with reset circuitry
6278316
Tanzawa; Toru, Atsumi; Shigeru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Nonvolatile semiconductor memory device
6282117
Tanaka; Tomoharu, Ohuchi; Kazunori, Tanzawa; Toru, Takeuchi; Ken
Rights holder: Kabushiki Kaisha Toshiba
Patent
Quantum tunneling effect device and semiconductor composite substrate
6320220
Watanabe; Hiroshi, Yasuda; Naoki, Toriumi; Akira, Tanaka; Tomoharu , Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor memory device
6337825
Tanzawa; Toru, Atsumi; Shigeru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor integrated circuit device
6344764
Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor memory device
6344996
Tanaka; Tomoharu , Nakamura; Hiroshi , Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Non-volatile semiconductor memory device having a function for controlling the range of distribution of memory cell threshold voltages and method of erasing data thereof
6351417
Shiga; Hitoshi , Tanzawa; Toru, Saito; Masanobu
Rights holder: Kabushiki Kaisha Toshiba
Patent
Nonvolatile semiconductor memory device
6363010
Tanaka; Tomoharu, Ohuchi; Kazunori, Tanzawa; Toru, Takeuchi; Ken
Rights holder: Kabushiki Kaisha Toshiba
Patent
Channel-erase nonvolatile semiconductor memory device
6373749
Atsumi; Shigeru , Taura; Tadayuki, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Pump circuit with active-mode and stand-by mode booster circuits
6429725
Tanzawa; Toru, Atsumi; Shigeru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Non-volatile semiconductor memory device controlling the range of distribution of memory cell threshold voltages
6434054
Shiga; Hitoshi, Tanzawa; Toru , Saito; Masanobu
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor device
6438034
Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Nonvolatile semiconductor memory
6442080
Tanzawa; Toru , Taura; Tadayuki, Kuriyama; Masao
Rights holder: Kabushiki Kaisha Toshiba
Patent
Channel-erase nonvolatile semiconductor memory device
6445618
Atsumi; Shigeru, Taura; Tadayuki, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Booster circuit for raising voltage by sequentially transferring charges from input terminals of booster units to output terminals thereof in response to clock signals having different phases
6456541
Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Boosted voltage generating circuit and semiconductor memory device having the same
6487120
Tanzawa; Toru , Miyaba; Takeshi, Atsumi; Shigeru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor memory device
6525964
Tanaka; Tomoharu, Nakamura; Hiroshi, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Nonvolatile semiconductor memory device with initialization circuit and control method thereof
6535427
Takano; Yoshinori, Tanzawa; Toru, Taura; Tadayuki
Rights holder: Kabushiki Kaisha Toshiba
Patent
Nonvolatile semiconductor memory device
6545909
Tanaka; Tomoharu, Ohuchi; Kazunori, Tanzawa; Toru, Takeuchi; Ken
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor storage apparatus
6552936
Shiga; Hitoshi, Takano; Yoshinori, Tanzawa; Toru, Atsumi; Shigeru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor device
6567309
Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Channel-erase nonvolatile semiconductor memory device
6577538
Atsumi; Shigeru, Taura; Tadayuki, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Level shifter for converting a voltage level and a semiconductor memory device having the level shifter
6600679
Tanzawa; Toru, Watanabe; Kentaro
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor device with a voltage regulator
6600692
Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Boosted voltage generating circuit and semiconductor memory device having the same
6605986
Tanzawa; Toru, Miyaba; Takeshi, Atsumi; Shigeru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Flash memory
6611938
Tanaka; Tomoharu, Shibata; Noboru, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Booster circuit for raising voltage by sequentially transferring charges from input terminals of booster units to output terminals thereof in response to clock signals having different phases
6614699
Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor memory device
6621738
Tanaka; Tomoharu, Nakamura; Hiroshi, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Non-volatile semiconductor memory device
6639837
Takano; Yoshinori, Taura; Tadayuki, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Channel-erase nonvolatile semiconductor memory device
6643183
Atsumi; Shigeru, Taura; Tadayuki, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Non-volatile semiconductor memory
6650570
Tanzawa; Toru, Atsumi; Shigeru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Nonvolatile semiconductor memory having page mode with a plurality of banks
6671203
Tanzawa; Toru, Atsumi; Shigeru, Umezawa; Akira, Taura; Tadayuki, Shiga; Hitosh), Takano; Yoshinori
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor storage apparatus
6693818
Shiga; Hitoshi, Takano; Yoshinor), Tanzawa; Tor), Atsumi; Shigeru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Nonvolatile semiconductor memory device and method of retrieving faulty in the same
6711057
Taura; Tadayuki, Atsumi; Shigeru, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Nonvolatile semiconductor memory
6711066
Tanzawa; Toru, Taura; Tadayuki, Kuriyama; Masao
Rights holder: Kabushiki Kaisha Toshiba
Patent
Constant voltage generation circuit and semiconductor memory device
6734719
Tanzawa; Toru, Takano; Yoshinori
Rights holder: Kabushiki Kaisha Toshiba
Patent
High-speed data programmable nonvolatile semiconductor memory device
6762956
Mori; Seiichi, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Boosted voltage generating circuit and semiconductor memory device having the same
6771547
Tanzawa; Toru, Miyaba; Takeshi, Atsumi; Shigeru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Memory device pump circuit with two booster circuits
6781439
Tanzawa; Toru, Atsumi; Shigeru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Nonvolatile semiconductor memory with a page mode
6781879
Tanzawa; Toru, Atsumi; Shigeru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor memory device and current mirror circuit
6788601
Takano; Yoshinori, Atsumi; Shigeru, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Nonvolatile semiconductor memory having page mode with a plurality of banks
6795352
Tanzawa; Toru, Atsumi; Shigeru, Umezawa; Akira, Taura; Tadayuki, Shiga; Hitoshi, Takano; Yoshinori
Rights holder: Kabushiki Kaisha Toshiba
Patent
Non-volatile semiconductor memory
6801457
Tanzawa; Toru, Atsumi; Shigeru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Non-volatile semiconductor memory device
6807097
Takano; Yoshinori, Taura; Tadayuki, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Nonvolatile semiconductor memory capable of generating read-mode reference current and verify-mode reference current from the same reference cell
6816413
Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Nonvolatile semiconductor memory
6816421
Tanzawa; Toru, Umezawa; Akira
Rights holder: Kabushiki Kaisha Toshiba
Patent
Fast data readout semiconductor storage apparatus
6826068
Shiga; Hitoshi, Takano; Yoshinori, Tanzawa; Toru, Atsumi; Shigeru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Nonvolatile semiconductor memory device with first and second read modes
6842377
Takano; Yoshinori, Honda; Yasuhiko, Tanzawa; Toru, Kuriyama; Masao
Rights holder: Kabushiki Kaisha Toshiba
Patent
Nonvolatile semiconductor memory device and method of retrieving faulty in the same
6850437
Taura; Tadayuki, Atsumi; Shigeru, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Nonvolatile semiconductor memory
6856548
Tanzawa; Toru, Taura; Tadayuki, Kuriyama; Masao
Rights holder: Kabushiki Kaisha Toshiba
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Non-volatile semiconductor memory
6865125
Tanzawa; Toru, Atsumi; Shigeru
Rights holder: Kabushiki Kaisha Toshiba
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Semiconductor memory device
6868013
Tanaka; Tomoharu, Nakamura; Hiroshi, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
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Semiconductor device having switch circuit to supply voltage
6977850
Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Boosted voltage generating circuit and semiconductor memory device having the same
6996024
Tanzawa; Toru, Miyaba; Takeshi, Atsumi; Shigeru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor memory device and current mirror circuit
6999365
Takano; Yoshinori, Atsumi; Shigeru, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
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Direct frequency modulation apparatus which modulates frequency by applying data-dependent voltage to control terminal of voltage-controlled oscillator without mediacy of PLL, and communication system
7005936
Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor device having switch circuit to supply voltage
7050339
Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Semiconductor memory device
7061807
Tanaka; Tomoharu, Shibata; Noboru, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Current difference divider circuit
7071771
Takano; Yoshinori , Taura; Tadayuki, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
Patent
Analog level shifter
7148734
Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
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Boosted voltage generating circuit and semiconductor memory device having the same
7180796
Tanzawa; Toru, Miyaba; Takeshi, Atsumi; Shigeru
Rights holder: Kabushiki Kaisha Toshiba
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Boosted voltage generating circuit and semiconductor memory device having the same
7203120
Tanzawa; Toru, Miyaba; Takeshi, Atsumi; Shigeru
Rights holder: Kabushiki Kaisha Toshiba
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Flash memory
7219285
Tanaka; Tomoharu, Shibata; Noboru, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
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Voltage subtracting circuit carrying out voltage subtraction by converting input voltage into current, intensity detecting circuit, and semiconductor integrated circuit device using the same
7233190
Tanzawa; Toru
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7272046
Tanzawa; Toru
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7277355
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Semiconductor device having switch circuit to supply voltage
7336545
Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
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Semiconductor memory device
7349259
Tanaka; Tomoharu, Nakamura; Hiroshi, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
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Semiconductor integrated circuit device and frequency modulation device
7474139
Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
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Method and apparatus for generating read and verify operations in non-volatile memories
7489556
Tanzawa; Toru
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Flash memory
7509566
Tanaka; Tomoharu, Shibata; Noboru, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
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Semiconductor memory device
7535762
Tanaka; Tomoharu, Nakamura; Hiroshi, Tanzawa; Toru
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High voltage switching circuit
7609554
Tanzawa; Toru
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Semiconductor memory device
7649780
Tanaka; Tomoharu, Nakamura; Hiroshi, Tanzawa; Toru
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7764563
Tanzawa; Toru, Harrington; Peter B.
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Compensation capacitor network for divided diffused resistors for a voltage divider
7902907
Tanzawa; Toru
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Flash memory
7908529
Tanaka; Tomoharu, Shibata; Noboru, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
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Random telegraph signal noise reduction scheme for semiconductor memories
7916544
Tanzawa; Toru
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Semiconductor memory device
7952933
Tanaka; Tomoharu, Nakamura; Hiroshi, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
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Adjustable voltage regulator for providing a regulated output voltage
7957214
Tanzawa; Toru, Harrington; Peter B.
Rights holder: Micron Technology, Inc.
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Method and apparatus for generating temperature-compensated read and verify operations in flash memories
7957215
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Voltage trimming
8013579
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Voltage regulator system
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Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Biasing system and method
8125829
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Semiconductor memory device
8154922
Tanaka; Tomoharu, Nakamura; Hiroshi, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
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Level shifting circuit
8184489
Tanzawa; Toru
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Random telegraph signal noise reduction scheme for semiconductor memories
8194459
Tanzawa; Toru
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Arrangement of pairs of NAND strings that share bitline contacts while utilizing distinct sources lines
8208305
Tanzawa; Toru
Rights holder: Intel Corporation
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Devices for shielding a signal line over an active region
8253198
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Voltage regulator system
8253396
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Flash memory
8365025
Tanaka; Tomoharu, Shibata; Noboru, Tanzawa; Toru
Rights holder: Kabushiki Kaisha Toshiba
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Level shifting circuit
8446784
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Voltage trimming
8466664
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Random telegraph signal noise reduction scheme for semiconductor memories
8537620
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Voltage generation and adjustment in a memory device
8547746
Tanzawa; Toru
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Apparatuses and methods including memory array and data line architecture
8593869
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Biasing system and method
8611153
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Apparatuses and methods including memory array data line selection
8619471
Tanzawa; Toru
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Devices and systems including enabling circuits
8675420
Tanzawa; Toru, Ghalam; Ali Feiz Zarrin
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8681561
Tanzawa; Toru
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Memory devices and programming methods that program a memory cell with a data value, read the data value from the memory cell and reprogram the memory cell with the read data value
8743622
Tanzawa; Toru
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8780631
Tanzawa; Toru
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8780638
Tanzawa; Toru
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8792263
Tanzawa; Toru
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Tanzawa; Toru
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Vertical memory with body connection
8797804
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Memory array with power-efficient read architecture
8811084
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Methods and apparatuses including a select transistor having a body region including monocrystalline semiconductor material and/or at least a portion of its gate located in a substrate
8837222
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Devices for shielding a signal line over an active region
8853778
Tanzawa; Toru
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Semiconductor apparatus with multiple tiers of memory cells with peripheral transistors, and methods
8860117
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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8861274
Tanzawa; Toru
Rights holder: Intel Corporation
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8891305
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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8971117
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Memory read apparatus and methods
8976594
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Voltage generator circuit
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Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Biasing system and method
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Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Voltage generation and adjustment in a memory device
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Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Apparatuses and methods including memory array data line selection
9030882
Tanzawa; Toru
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Charge pump redundancy in a memory
9042180
Tanzawa; Toru, Tanaka; Tomoharu
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9053043
Tanaka; Tomoharu, Shibata; Noboru, Tanzawa; Toru
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9064551
Tanzawa; Toru
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Apparatuses and methods for transposing select gates
9064576
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Apparatuses and methods to control body potential in memory operations
9064577
Zhao; Han, Goda; Akira, Parat; Krishna K., Mauri; Aurelio Giancarlo, Liu; Haitao, Tanzawa; Toru, Yamada; Shigekazu, Sakui; Koji
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9064578
Tanzawa; Toru, Tamada; Satoru, Kawai; Koichi, Manabe; Tetsuji
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Apparatuses and methods including memory array and data line architecture
9082485
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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9111591
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Vertical memory with body connection
9171587
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Apparatuses and methods including memory with top and bottom data lines
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Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Memory array with power-efficient read architecture
9208891
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Apparatuses and methods for coupling load current to a common source
9224477
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Random telegraph signal noise reduction scheme for semiconductor memories
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Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Methods and apparatuses including a select transistor having a body region including monocrystalline semiconductor material and/or at least a portion of its gate located in a substrate
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Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Apparatuses including memory arrays with source contacts adjacent edges of sources
9263461
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Independently selective tile group access with data structuring
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Tanzawa; Toru
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Apparatuses and methods including memory write operation
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Tanzawa; Toru
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Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information
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Tanzawa; Toru
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Apparatuses and methods including memory array data line selection
9318211
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Compensating for off-current in a memory
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Tanzawa; Toru
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Short-checking methods
9330789
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Three-dimensional devices having reduced contact length
9343479
Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Memory read apparatus and methods
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Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Tanzawa; Toru
Rights holder: Micron Technology, Inc.
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Tanzawa; Toru
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Devices and systems including enabling circuits
9401188
Tanzawa; Toru
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9412451
Tanzawa; Toru
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Toru Tanzawa, Akira Goda, Shigekazu Yamada, Hiroyuki Sanda
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Tanzawa; Toru
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Memory devices having data lines included in top and bottom conductive lines
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Tanzawa; Toru
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Enable/disable of memory chunks during memory access
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Toru Tanzawa, Satoru Tamada, Koichi Kawai, Tetsuji Manabe
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Han Zhao, Akira Goda, Krishna K. Parat, Aurielo Giancarlo Mauri, Haitao Liu, Toru Tanzawa, Shigekazu Yamada, Koji Sakui
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Toru Tanzawa, Tamotsu Murakoshi, Deepak Thimmegowda
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Toru Tanzawa
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Toru Tanzawa
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Voltage generator circuit
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Toru Tanzawa
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Selectable memory access time
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Toru Tanzawa
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Apparatuses and methods using dummy cells programmed to different states
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Toru Tanzawa, Aaron Yip
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Semiconductor apparatus with multiple tiers, and methods
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Toru Tanzawa
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Devices including memory arrays, row decoder circuitries and column decoder circuitries
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Toru Tanzawa
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Methods and apparatuses including a select transistor having a body region including monocrystalline semiconductor material and/or at least a portion of its gate located in a substrate
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Toru Tanzawa
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Toru Tanzawa
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Toru Tanzawa
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Chunk redundancy architecture for memory
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Toru Tanzawa
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Three-dimensional devices having reduced contact length
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Toru Tanzawa
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Random telegraph signal noise reduction scheme for semiconductor memories
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Toru Tanzawa
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Memory read apparatus and methods
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Toru Tanzawa
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Segmented memory and operation
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Toru Tanzawa, Han Zhao
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Apparatuses and methods involving accessing distributed sub-blocks of memory cells
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Toru Tanzawa
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Memory having memory cell string and coupling components
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Toru Tanzawa
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Qiang Tang, Ramin Ghodsi, Toru Tanzawa
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Sequential memory access operations
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Toru Tanzawa
Rights holder: Micron Technology, Inc.
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Interconnections for 3D memory
9786334
Toru Tanzawa
Rights holder: Micron Technology, Inc.
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Memory array with power-efficient read architecture
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Toru Tanzawa
Rights holder: Micron Technology, Inc.
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Apparatuses and methods to control body potential in 3D non-volatile memory operations
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Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu, Toru Tanzawa, Shigekazu Yamada, Koji Sakui
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Interconnections for 3D memory
9881651
Toru Tanzawa
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Toru Tanzawa
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Toru Tanzawa
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Shantanu R. Rajwade, Pranav Kalavade, Toru Tanzawa
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Toru Tanzawa
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Chunk redundancy architecture for memory
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Toru Tanzawa
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Toru Tanzawa
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Apparatuses including memory arrays with source contacts adjacent edges of sources
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Toru Tanzawa
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Koji Sakui, Mark Hawes, Toru Tanzawa, Jeremy Binfet
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Toru Tanzawa, Aaron Yip
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Apparatuses and methods for charging a global access line prior to accessing a memory
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Toru Tanzawa
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Toru Tanzawa
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Memory array with power-efficient read architecture
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Toru Tanzawa
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Field effect transistors having a fin
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Toru Tanzawa
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Random telegraph signal noise reduction scheme for semiconductor memories
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Toru Tanzawa
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Interconnections for 3D memory
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Toru Tanzawa
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Qiang Tang, Ramin Ghodsi, Toru Tanzawa
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Three dimensional memory device with access signal triggering from voltage pump output levels
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Toru Tanzawa
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Toru Tanzawa
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Memory having memory cell string and coupling components
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Toru Tanzawa
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Memory device including pass transistors in memory tiers
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Toru Tanzawa
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Apparatuses and methods involving accessing distributed sub-blocks of memory cells
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Toru Tanzawa
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Apparatuses and methods to control body potential in 3D non-volatile memory operations
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Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu, Toru Tanzawa, Shigekazu Yamada, Koji Sakui
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Toru Tanzawa
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Memory device including mixed non-volatile memory cell types
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Toru Tanzawa
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Memory read apparatus and methods
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Toru Tanzawa
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Memory devices with a transistor that selectively connects a data line to another data line
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Toru Tanzawa
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Segmented memory and operation
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Toru Tanzawa, Han Zhao
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Devices including memory arrays, row decoder circuitries and column decoder circuitries
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Toru Tanzawa
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Apparatuses and methods using dummy cells programmed to different states
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Toru Tanzawa, Aaron Yip
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Memory devices having selectively electrically connected data lines
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Toru Tanzawa
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Sequential memory access operations
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Toru Tanzawa
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Interconnections for 3D memory
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Toru Tanzawa
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Tier mode for access operations to 3D memory
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Toru Tanzawa
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Apparatuses and methods for charging a global access line prior to accessing a memory
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Toru Tanzawa
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Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information
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Toru Tanzawa
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Memory devices having selectively electrically connected data lines
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Toru Tanzawa
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Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation
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Shantanu R. Rajwade, Pranav Kalavade, Toru Tanzawa
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Koji Sakui, Mark Hawes, Toru Tanzawa, Jeremy Binfet
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Memory having memory cell string and coupling components
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Toru Tanzawa
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Apparatuses and methods to control body potential in 3D non-volatile memory operations
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Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu, Toru Tanzawa, Shigekazu Yamada, Koji Sakui
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Qiang Tang, Ramin Ghodsi, Toru Tanzawa
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Random telegraph signal noise reduction scheme for semiconductor memories
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Toru Tanzawa
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Memory device including mixed non-volatile memory cell types
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Toru Tanzawa
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Field effect transistors having a fin
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Toru Tanzawa
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Semiconductor apparatus with multiple tiers, and methods
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Toru Tanzawa
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Memory read apparatus and methods
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Toru Tanzawa
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Segmented memory and operation
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Toru Tanzawa, Han Zhao
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Apparatuses and methods for charging a global access line prior to accessing a memory
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Toru Tanzawa
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Three-dimensional devices having reduced contact length
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Toru Tanzawa
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Interconnections for 3D memory
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Toru Tanzawa
Rights holder: Micron Technology, Inc.
Patent
Apparatuses and methods involving accessing distributed sub-blocks of memory cells
10734049
Toru Tanzawa
Rights holder: Micron Technology, Inc.
Patent
Apparatuses and methods using dummy cells programmed to different states
10741259
Toru Tanzawa, Aaron Yip
Rights holder: Micron Technology, Inc.
Patent
Methods of forming semiconductor device structures including staircase structures
10748918
Toru Tanzawa
Rights holder: Micron Technology, Inc.
Patent
Memory array having connections going through control gates
10770470
Toru Tanzawa, Tamotsu Murakoshi, Deepak Thimmegowda
Rights holder: Micron Technology, Inc.
Patent
Memory device including pass transistors in memory tiers
10784269
Toru Tanzawa
Rights holder: Micron Technology, Inc.
Patent
Apparatuses and methods to control body potential in 3D non-volatile memory operations
10796778
Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu, Toru Tanzawa, Shigekazu Yamada, Koji Sakui
Rights holder: Micron Technology, Inc.
Patent
Sequential memory access operations
10824336
Toru Tanzawa
Rights holder: Micron Technology, Inc.
Patent
Segmented memory operation
10854293
Toru Tanzawa, Han Zhao
Rights holder: Micron Technology, Inc.
Patent
Apparatuses including memory arrays with source contacts adjacent edges of sources
10879255
Toru Tanzawa
Rights holder: Micron Technology, Inc.
Patent
Memory device including mixed non-volatile memory cell types
10901623
Toru Tanzawa
Rights holder: Micron Technology, Inc.
Patent
Apparatus and methods including establishing a negative body potential in a memory cell
10916313
Koji Sakui, Mark Hawes, Toru Tanzawa, Jeremy Binfet
Rights holder: Micron Technology, Inc.
Patent
Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information
10956642
Toru Tanzawa
Rights holder: Micron Technology, Inc.
Patent
Memory read apparatus and methods
10964400
Toru Tanzawa
Rights holder: Micron Technology, Inc.
Patent
Random telegraph signal noise reduction scheme for semiconductor memories
10998054
Toru Tanzawa
Rights holder: Micron Technology, Inc.
Patent
Three-dimensional devices having reduced contact length
11018135
Toru Tanzawa
Rights holder: Micron Technology, Inc.
Patent
Semiconductor apparatus with multiple tiers, and methods
11145673
Toru Tanzawa
Rights holder: Micron Technology, Inc.
Patent
Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation
11182074
Shantanu R. Rajwade, Pranav Kalavade, Toru Tanzawa
Rights holder: Micron Technology, Inc.
Patent
Semiconductor device and manufacturing method for same
11258008
Toru Tanzawa
Rights holder: National University Corporation Shizuoka University
Patent
Interconnections for 3D memory
11276437
Toru Tanzawa
Rights holder: Micron Technology, Inc.
Patent
Apparatuses and methods involving accessing distributed sub-blocks of memory cells
11282556
Toru Tanzawa
Rights holder: Micron Technology, Inc.
Patent
Memory device including mixed non-volatile memory cell types
11347401
Toru Tanzawa
Rights holder: Micron Technology, Inc.
Patent
Memory array having connections going through control gates
11398489
Toru Tanzawa, Tamotsu Murakoshi, Deepak Thimmegowda
Rights holder: Micron Technology, Inc.
Patent
Memory device including pass transistors in memory tiers
11417671
Toru Tanzawa
Rights holder: Micron Technology, Inc.
Patent
Field effect transistors having a fin
11462629
Toru Tanzawa
Rights holder: Micron Technology, Inc.
Patent
Random telegraph signal noise reduction scheme for semiconductor memories
11462277
Toru Tanzawa
Rights holder: Micron Technology, Inc.
Patent
Integrated Circuit Engineering
Graduate School of Information, Production and Systems
2024 fall semester
Green Integrated Systems Research (Doctor's Thesis)
Graduate School of Information, Production and Systems
2024 full year
Green Integrated Systems Research (Fall)
Graduate School of Information, Production and Systems
2024 fall semester
Green Integrated Systems Research (Spring)
Graduate School of Information, Production and Systems
2024 spring semester
Graduate School of Information, Production and Systems
2024 fall semester
Graduate School of Information, Production and Systems
2024 spring semester
Graduate School of Information, Production and Systems
2024 spring semester
Graduate School of Information, Production and Systems
2024 fall semester
Semiconductor Device Technology and Engineering
Graduate School of Information, Production and Systems
2024 fall semester
Semiconductor Memory Technology and Engineering
Graduate School of Information, Production and Systems
2024 spring semester
Green Integrated Systems Research (Spring)
Graduate School of Information, Production and Systems
2024 spring semester
Green Integrated Systems Research (Fall)
Graduate School of Information, Production and Systems
2024 fall semester
Master's Thesis (Integrated Systems)(Fall)
Graduate School of Information, Production and Systems
2024 fall semester
Master's Thesis (Integrated Systems)(Spring)
Graduate School of Information, Production and Systems
2024 spring semester
電子回路II
静岡大学
電子回路I
静岡大学
電子回路Ⅰ
静岡大学
電気電子工学研究第二
静岡大学
電気電子工学研究第一
静岡大学
電気電子工学概論
静岡大学
電気電子工学セミナー第一
静岡大学
電気電子工学セミナー第ニ
静岡大学
電気回路Ⅰ
静岡大学
卒業研究
静岡大学
数値シミュレーション
静岡大学
集積回路工学
静岡大学
集積回路プロセス工学特論
静岡大学
集積プロセス・デバイス工学特論
静岡大学
セミナー1
静岡大学
キャリアデザイン
電気電子工学セミナー第二
静岡大学
社会と製造業
静岡大学
プロセッサ工学
静岡大学
Waseda Research Institute for Science and Engineering Concurrent Researcher
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