Research Experience
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2022.02-Now
Waseda Research Institute for Science and Engineering Senior Reseacher
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2017.02-2021.03
Japan Science and Technology Agency
Details of a Researcher
Updated on 2024/12/22
Waseda Research Institute for Science and Engineering Senior Reseacher
Japan Science and Technology Agency
A Variability-Aware Adaptive Test Flow for Test Quality Improvement.
Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu, Takashi Sato
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33 ( 7 ) 1056 - 1066 2014
Generation of Diagnostic Tests for Transition Faults Using a Stuck-At ATPG Tool.
Yoshinobu Higami, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi, Yoshihiro Shimizu, Takashi Aikyo
IEICE Transactions on Information & Systems 95-D ( 4 ) 1093 - 1100 2012
Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara
IEICE Transactions on Information & Systems 94-D ( 6 ) 1216 - 1226 2011
Test Challenge for Deep Sub-micron Era - Test & Diagnosis Platform: STARCAD-Clouseau.
Takashi Aikyo
25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems(DFT) 227 - 227 2010
A Study of Capture-Safe Test Generation Flow for At-Speed Testing.
Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Atsushi Takashima, Hiroshi Furukawa, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 93-A ( 7 ) 1309 - 1318 2010
Small Delay Fault Model for Intra-Gate Resistive Open Defects.
Masayuki Arai, Akifumi Suto, Kazuhiko Iwasaki, Katsuyuki Nakano, Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo
27th IEEE VLSI Test Symposium(VTS) 27 - 32 2009
Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC.
Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu
VLSI Design 2009: Improving Productivity through Higher Abstraction 91 - 96 2009
A Novel Approach for Improving the Quality of Open Fault Diagnosis.
Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume
VLSI Design 2009: Improving Productivity through Higher Abstraction 85 - 90 2009
Diagnostic test generation for transition faults using a stuck-at ATPG tool.
Yoshinobu Higami, Yosuke Kurose, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi, Yoshihiro Shimizu, Takashi Aikyo, Yuzo Takamatsu
2009 IEEE International Test Conference(ITC) 1 - 9 2009
Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara
2009 International Conference on Computer-Aided Design(ICCAD) 97 - 104 2009
An Adaptive Test for Parametric Faults Based on Statistical Timing Information.
Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Hiroyuki Ueyama, Takashi Sato, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu
Proceedings of the Eighteentgh Asian Test Symposium 151 - 156 2009
Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara
2008 International Conference on Computer-Aided Design(ICCAD) 52 - 58 2008
A Capture-Safe Test Generation Scheme for At-Speed Scan Testing.
Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, H. Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja
13th European Test Symposium(ETS) 55 - 60 2008
Estimation of Delay Test Quality and Its Application to Test Generation.
Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo
IPSJ Transactions on System LSI Design Methodology 1 104 - 115 2008
Post-BIST Fault Diagnosis for Multiple Faults.
Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato
IEICE Transactions on Information & Systems 91-D ( 3 ) 771 - 775 2008
Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate.
Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Tatsuru Matsuo, Takahisa Hiraide, Hideaki Konishi, Michiaki Emori, Takashi Aikyo
IEICE Transactions on Information & Systems 91-D ( 3 ) 726 - 735 2008
Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information.
Yuzo Takamatsu, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Koji Yamazaki
IEICE Transactions on Information & Systems 91-D ( 3 ) 675 - 682 2008
Clues for modeling and diagnosing open faults with considering adjacent lines
Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume
PROCEEDINGS OF THE 16TH ASIAN TEST SYMPOSIUM 0 ( 0 ) 39 - + 2007 [Refereed]
Estimation of delay test quality and its application to test generation.
Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo
2007 International Conference on Computer-Aided Design(ICCAD) 413 - 417 2007
Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines.
Hiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume
22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)(DFT) 243 - 251 2007
Timing-Aware Diagnosis for Small Delay Defects.
Takashi Aikyo, Hiroshi Takahashi, Yoshinobu Higami, Junichi Ootsu, Kyohei Ono, Yuzo Takamatsu
22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)(DFT) 223 - 234 2007
Test Data Compression of 100x for Scan-Based BIST.
Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Tatsuru Matsuo, Takahisa Hiraide, Hideaki Konishi, Michiaki Emori, Takashi Aikyo
2006 IEEE International Test Conference(ITC) 1 - 10 2006
Effective Post-BIST Fault Diagnosis for Multiple Faults.
Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato
21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006)(DFT) 401 - 109 2006
Issues on SOC testing in DSM area: embedded tutorial.
Takashi Aikyo
Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000(ASP-DAC) 515 - 516 2000
A Test Synthesis Approach to Reducing BALLAST DFT Overhead.
Douglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang-Ting Cheng
Proceedings of the 34st Conference on Design Automation(DAC) 466 - 471 1997
ATREX : Design for Testability System for Mega Gate LSIs.
Michiaki Emori, Junko Kumagai, Koichi Itaya, Takashi Aikyo, Tomoko Anan, Junichi Niimi
6th Asian Test Symposium (ATS '97) 126 1997
ASIC CAD system based on hierarchical design-for-testability.
Michiaki Emori, Takashi Aikyo, Yasuhide Machida, Jun-ichi Shikatani
Proceedings IEEE International Test Conference 1990(ITC) 404 - 409 1990
An Automatic Test Generation System for Large Scale Gate Arrays.
Takashi Aikyo, Y. Hatano, J. Ishii, N. Karasawa, S. Fujii
Spring COMPCON'86(COMPCON) 445 - 451 1986
Research on Extra-Low-Power Self-Test for LSI Circuits in Implantable Medical Devices
Japan Society for the Promotion of Science Grants-in-Aid for Scientific Research
Project Year :
WEN XIAOQING, KINOSHITA Kozo, Saluja K. K., Tehranipoor M., Girard P., AIKYO Takashi, TAKAGI Noriaki, Keller B., Varma P.
Variation Aware Test Methodology Based on Statistical Static Timing Analysis
新谷道広, 畠山一実, 相京隆
電子情報通信学会技術研究報告 110 ( 413(DC2010 59-69) ) 2011
故障励起関数を利用したオープン故障の診断法
山崎浩二, 堤利幸, 高橋寛, 樋上喜信, 相京隆, 四柳浩之, 橋爪正樹, 高松雄三
電子情報通信学会論文誌 D J93-D ( 11 ) 2010
A method for generating defect oriented test patterns for combinatorial circuit
高橋寛, 樋上喜信, 和泉太佑, 相京隆, 高松雄三
電子情報通信学会技術研究報告 108 ( 431(DC2008 68-78) ) 2009
検出可能な遅延故障サイズを考慮した遅延故障診断法
相京隆, 高橋寛, 樋上喜信, 大津潤一, 小野恭平, 清水隆治, 高松雄三
電子情報通信学会論文誌 D J92-D ( 7 ) 2009
Power & Noise Aware Test Utilizing Preliminary Estimation
埜田健治, 伊藤秀昭, 畠山一実, 相京隆
電子情報通信学会技術研究報告 109 ( 95(DC2009 10-17) ) 2009
Fault Diagnosis for Dynamic Open Faults with Considering Adjacent Lines
高橋寛, 樋上喜信, 相京隆, 門山周平, 渡部哲也, 高松雄三, 堤利幸, 山崎浩二, 四柳浩之, 橋爪正樹
電子情報通信学会技術研究報告 107 ( 482(DC2007 67-83) ) 2008
Improving the Diagnostic Quality of Open Faults
山崎浩二, 堤利幸, 高橋寛, 樋上喜信, 相京隆, 四柳浩之, 橋爪正樹, 高松雄三
電子情報通信学会技術研究報告 108 ( 99(DC2008 11-18) ) 2008
縮退故障ATPGを用いた遷移故障の診断用テスト生成法
相京隆, 樋上喜信, 高橋寛, 黒瀬洋介, 高松雄三
電気関係学会四国支部連合大会講演論文集(CD-ROM) 2008 2008
遅延故障シミュレーションを利用した欠陥診断法
高橋寛, 樋上喜信, 岡山浩士, 小野恭平, 相京隆, 高松雄三
電気関係学会四国支部連合大会講演論文集(CD-ROM) 2008 2008
On generation of high-quality test patterns for transition faults
森島翔平, 山本真裕, 梶原誠司, WEN Xiaoqing, 福永昌勉, 畠山一実, 相京隆
電子情報通信学会技術研究報告 106 ( 528(DC2006 80-90) ) 2007
BAST: BIST Aided Scan Test-A New Method for Test Cost Reduction-
相京隆, 平出貴久, 江守道明
電子情報通信学会論文誌 D-1 J88-D-1 ( 6 ) 2005
A New Method for Test Cost Reduction using ATG and BIST Techniques.
小西秀明, 岡埜靖, 山村一之, 唐沢直子, 板矢剛一, 熊谷淳子, 江守道明, 相京隆, 平出貴久
電子情報通信学会技術研究報告 101 ( 658(FTS2001 77-88) ) 2002
A Parallel Test Pattern Fault Simulator for Partital Scan Design LSI.
丸山大輔, 相京隆, 多田敏彦
電子情報通信学会技術研究報告 97 ( 224(FTS97 30-37) ) 1997
Test pattern compaction in combinational logic circuits using multiple detection method.
小西秀明, 山本剛, 相京隆
情報処理学会シンポジウム論文集 96 ( 4 ) 1996
A Method of Diagnosing Multiple Faults Based on Single Stuck-at Fault Model.
浜田周治, 相京隆, 山本剛
情報処理学会シンポジウム論文集 94 ( 5 ) 1994
A Study on Partial Scan Design.
浜田周治, 相京隆, 町田泰秀
電子情報通信学会技術研究報告 91 ( 261(FTS91 36-44) ) 1991
Special issue : testing technology.Test simplification technology of ASIC using a hierarchical structure.
相京隆, 江守道明, 町田泰秀
月刊Semiconductor World 10 ( 12 ) 1991
A mixed analog/digital simulator MLCS.
水谷徹, 姉歯伸彦, 後藤邦彦, 相京隆, 熊谷淳子, 古山智之
電子情報通信学会技術研究報告 91 ( 192(ICD91 81-90) ) 1991
A study on partial scan design.
浜田周治, 相京隆, 町田泰秀
電子情報通信学会全国大会講演論文集 1991 ( Spring Pt 5 ) 1991
An automatic circuit generation system.
相京隆, 唐沢直子, 高岡晴義, 末広善之
電子情報通信学会全国大会講演論文集 1989 ( Spring Pt.1 ) 1989
A system for LSI fault diagnosis.
山本剛, 西風浩二, 相京隆, 町田泰秀
電子情報通信学会技術研究報告 89 ( 348(ICD89 163-174) ) 1989
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