Updated on 2024/04/18

写真a

 
YOSHIHARA, Tsutomu
 
Affiliation
Faculty of Science and Engineering
Job title
Professor Emeritus
Degree
工学博士 ( 大阪大学 )

Education Background

  •  
    -
    1971

    Osaka University   Graduate School, Division of Natural Science  

  •  
    -
    1969

    Osaka University   Faculty of Science  

Professional Memberships

  •  
     
     

    電気学会

  •  
     
     

    電子情報通信学会

  •  
     
     

    IEEE Solid State

Research Interests

  • システムLSI回路設計

 

Papers

  • A High Efficiency Multi-Channel LED Driver Based on Converter-Free Technique and Load Adaptive Method

    Si FU, Minjie CHEN, Xutao LI, Tsutomu YOSHIHARA

    ISOCC2014    2014.11

    DOI

  • An Output-Capacitorless Low Dropout Regulator without Resistance

    Jie MEI, Hao ZHANG, Tsutomu YOSHIHARA

    ISOCC 2014    2014.11

    DOI

  • Efficiency Improvement of DC-DC Buck Converters

    Ning Li, Xutao Li, Mingjie Chen, Yoshihara Tsutomu

    JCEEE Kyushu 2014    2014.09

  • A High Efficiency Multi-Channel LED Driver Based on Converter-Free Technique and Load Adaptive Method

    Si FU, Minjie CHEN, Xutao LI, Tsutomu YOSHIHARA

    JCEEE Kyushu 2014    2014.09

    DOI

  • An Output-Capacitorless Low Dropout Regulator without Resistance

    Jie MEI, Hao ZHANG, Tsutomu YOSHIHARA

    JCEEE Kyushu 2014    2014.09

    DOI

  • by the Switching Frequency Optimized PWM

    Hao Zhang, Mengshu Huang, Yimeng Zhang, Tsutomu Yoshihara

    Journal of Semiconductor Technology and Science   Vol.14 ( No.1 ) 70 - 82  2014.02

  • A CMOS Low-Voltage Reference Based on Body Effect and Switched-Capacitor Technique

    Yudong Lin, Hao Zhang, Tsutomu Yoshihara

    ISOCC2013    2013.11

    DOI

  • Clocked CMOS Adiabatic Logic with Low-Power Dissipation

    He Li, Yimeng Zhang, Tsutomu Yoshihara

    ISOCC2013    2013.11

    DOI

  • Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System

    Kazuhiro Ueda, Fukashi Morishita, Shunsuke Okura, Leona Okamura, Tsutomu Yoshihara, Kazutami Arimoto

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   48 ( 11 ) 2608 - 2617  2013.11

     View Summary

    A charge-recycling circuit and system that reuses the energy between two or more stacked CPUs is proposed in order to double the life of a battery. In this architecture, CPUs are divided into upper and lower load groups, and electrical charges are shared among the stacked CPUs and a tank capacitor. Charges are temporarily stored in the tank capacitor and are then reused. To control divided loads, a high-speed and energy-efficient regulator is needed. Internal circuit voltage variation between the upper and lower modules is determined by seven low-drop-out (LDO) regulators, a voltage-boosting capacitor circuit, and the tank capacitor. As a result, stable voltage can be supplied to each CPU, even if the upper and lower loads are different or a battery is being used. The LDOs improve the margin of collection in the tank capacitor or task schedule operation, and power efficiency is raised even further. The circuit can be implemented on silicon without a large external control circuit and inductor such as a switching regulator. This circuit was applied to an in-vehicle lock-step system because the upper and lower loads and tasks are the same. Additionally, by using the proposed task scheduling to maximize efficiency, this circuit can be applied not only to lock-step systems but also to general systems. Test chips were fabricated using 90-nm standard CMOS technology. Although the maximum power efficiency of a conventional circuit with a simple LDO is 44.4%, efficiency of the proposed charge-recycling circuit turned out to be as high as 87.1% with the test chips.

    DOI

  • A CMOS Low-Voltage Reference Based on Body Effect and Switched-Capacitor Technique

    Yudong Lin, Hao Zhang, Tsutomu Yoshihara

    JCEE Kyushu 2013    2013.09

    DOI

  • Clocked CMOS Adiabatic Logic with Low-Power Dissipation

    He Li, Yimeng Zhang, Tsutomu Yoshihara

    JCEE Kyushu 2013    2013.09

    DOI

  • “Dynamic Response Improvement of Discrete Sliding Mode Controlled Switching Power Converter via Double Integral”,

    Xutao Li, Minjie Chen, Hao Zhang, Yoshihara Tsutomu

    SICE 2013    2013.09

  • Self-Cascode MOSFET with a Self-Biased Body Effect for Ultra-Low-Power Voltage Reference Generator

    Hao Zhang, Mengshu Huang, Yimeng Zhang, Tsutomu Yoshihara

    IEICE TRANSACTIONS ON ELECTRONICS   E96C ( 6 ) 859 - 866  2013.06

     View Summary

    This paper proposes a novel approach for implementing an ultra-low-power voltage reference using the structure of self-cascode MOSFET, operating in the subthreshold region with a self-biased body effect. The difference between the two gate-source voltages in the structure enables the voltage reference circuit to produce a low output voltage below the threshold voltage. The circuit is designed with only MOSFETs and fabricated in standard 0.18-mu m CMOS technology. Measurements show that the reference voltage is about 107.5 mV, and the temperature coefficient is about 40 ppm/degrees C, at a range from -20 degrees C to 80 degrees C. The voltage line sensitivity is 0.017%/V. The minimum supply voltage is 0.85 V, and the supply current is approximately 24 nA at 80 degrees C. The occupied chip area is around 0.028 mm(2).

    DOI

  • A Low Power Dissipation Real Time Counter for Sensor Network Application

    Yimeng Zhang, Tsutomu Yoshihara

    ICEIC2013    2013.02

  • A High Efficiency Charge Pump with Continuous Frequency Regulation Scheme

    Shuning Wang, Mengshu Huang, Yimeng Zhang, Tsutomu Yoshihara

    ICEIC2013    2013.02

    DOI

  • A method of searching PID controller's optimized coefficients for Buck converter using particle swarm optimization

    Xutao Li, Minjie Chen, Yoshihara Tsutomu

    Proceedings of the International Conference on Power Electronics and Drive Systems     238 - 243  2013

     View Summary

    This paper presents the method of searching optimized PID controller's coefficients for Buck converter using PSO-particle swarm optimization. Recently, PSO, which can be used for parameter optimization, becomes attractive because its computation simplicity relative to other evolutionary algorithms such as GA. A problem is that PID controller's coefficients found with PSO may be not suitable which causes large overshoot and bad robustness. This paper proposed a method to solve this problem by improving the ratio of the proportion term through changing evolution conditions. According to the experimental results, the proposed method is feasible and the effect is good. © 2013 IEEE.

    DOI

  • A high efficiency charge pump with continuous frequency charge sharing scheme

    Shuning Wang, Mengshu Huang, Yimeng Zhang, Tsutomu Yoshihara

    2013 IEEE International Conference on Consumer Electronics - China, ICCE-China 2013     45 - 50  2013

     View Summary

    In this paper, the charge pump efficiency is discussed, and a charge pump with continuous frequency charge sharing scheme is presented. The proposed charge sharing clock generator is able to recover the charge from parasitic-capacitor charging and discharging, so that the dynamic power loss is reduced by half. Furthermore, the proposed frequency regulation structure is able to keep the efficiency of charge pump at the theoretical maximum value without effect of load current. The simulation results show a maximum 10% efficiency increase and the efficiency is kept around 68% when load current decreases, while efficiency of conventional charge pump drops to 23% when load current is 10uA. © 2013 IEEE.

    DOI

  • A Novel quasi-Resonant Soft-Switching Z-Source Inverter

    Yuan ZHU, Minjie CHEN, Yoshihara Tsutomu

    IEEEPECON2012     271 - 276  2012.12

  • A Novel Charge Recovery Logic Structure with Complementary Pass-transistor Network

    Jingyang Li, Yimeng Zhang, Tsutomu Yoshihara

    ISOCC2012     17 - 20  2012.11

    DOI

  • A CMOS Voltage Reference Combining Body Effect with Switched-Current Technique

    Ning REN, Hao ZHANG, Tsutomu YOSHIHARA

    ISOCC2012     92 - 95  2012.11

    DOI

  • High efficiency multi-channel LED driver based on SIMO switch-mode converter

    Yu Luchen, Chen Minjie, Tsutomu Yoshihara

    ISOCC2012     355 - 358  2012.11

    DOI

  • Green semiconductor technology with ultra-low power on-chip charge-recycling power circuit and system

    Kazuhiro Ueda, Okura Syunsuke, Fukashi Morishita, Kazutami Arimoto, Leona Okamura, Tsutomu Yoshihara

    IEEE ASSCC2012     105 - 108  2012.11

    DOI

  • Energy Efficient Processing Engine in LDPC Application with High-Speed Charge Recovery Logic

    Yimeng Zhang, Mengshu Huang, Nan Wang, Satoshi Goto, Tsutomu Yoshihara

    JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE   12 ( 3 ) 341 - 352  2012.09

     View Summary

    This paper presents a Processing Engine (PE) which is used in Low Density Parity Codec (LDPC) application with a novel charge-recovery logic called pseudo-NMOS boost logic (pNBL), to achieve high-speed and low power dissipation. pNBL is a high-overdriven and low area consuming charge recovery logic, which belongs to boost logic family. Proposed Processing Engine is used in LDPC circuit to reduce operating power dissipation and increase the processing speed. To demonstrate the performance of proposed PE, a test chip is designed and fabricated with 0.18 mu m CMOS technology. Simulation results indicate that proposed PE with pNBL dissipates only 1 pJ/cycle when working at the frequency of 403 MHz, which is only 36% of PE with the conventional static CMOS gates. The measurement results show that the test chip can work as high as 609 MHz with the energy dissipation of 2.1 pJ/cycle.

    DOI

  • A Novel Charge Recovery Logic Structure with Complementary Pass-transistor Network

    Jingyang Li, Yimeng Zhang, Tsutomu Yoshihara

       2012.09

    DOI

  • A CMOS Voltage Reference Combining Body Effect with Switched-Current Technique

    Ning REN, Hao ZHANG, Tsutomu YOSHIHARA

       2012.09

    DOI

  • High efficiency multi-channel LED driver based on SIMO switch-mode converter

    Yu Luchen, Chen Minjie, Tsutomu Yoshihara

       2012.09

    DOI

  • A Novel quasi-Resonant Soft-Switching Z-Source Inverter

    Yuan ZHU, Minjie CHEN, Yoshihara Tsutomu

       2012.09

    DOI

  • An Efficient Dual Charge Pump Circuit Using Charge Sharing Clock Scheme

    Mengshu Huang, Yimeng Zhang, Tsutomu Yoshihara

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E95A ( 2 ) 439 - 446  2012.02

     View Summary

    In this paper, the charge pump efficiency is discussed, and a dual charge pump circuit with complementary architecture using charge sharing clock scheme is presented. The proposed charge sharing clock generator is able to recover the charge from parasitic-capacitor charging and discharging, so that the dynamic power loss in the pumping process is reduced by a half. To preserve the overlapping period of the four-phase clock used for threshold cancellation technique, two complementary sets of clocks are generated from the proposed clock generator, and each set feeds a certain branch of the dual charge pump to achieve the between-branch charge sharing. A test chip is fabricated in 0.18 mu m process, and the area penalty of the proposed charge sharing clock generator is 1%. From the measurement results, the proposed charge pump shows an overall power efficiency increase with a peak value of 63.7% comparing to 52.3% of a conventional single charge pump without charge sharing, and the proposed clock scheme shows no degradation on the driving capability while the output ripple voltage is reduced by 43%.

    DOI

  • A Novel Charge Sharing Charge Pump for Energy Harvesting Application

    Jiemin ZHOU, Mengshu HUANG, Yimeng ZHANG, Tsutomu YOSHIHARA

    ISOCC2011     373 - 376  2011.11

  • Double charge pump circuit with triple charge sharing clock scheme

    Mengshu HUANG, Yimeng Zhang, Tsutomu Yoshihara

    IEEE ASICON 2011     148 - 152  2011.10

  • An Area Efficiency Hybrid Decoupling Scheme for Charge Pump Noise Suppression in Non-volatile Memory

    Mengshu Huang, Leona Okamura, Tsutomu Yoshihara

    IEICE TRANSACTIONS ON ELECTRONICS   E94C ( 6 ) 968 - 976  2011.06

     View Summary

    An area efficiency hybrid decoupling scheme is proposed to suppress the charge pump noise during F-N tunneling program in nonvolatile memory (NVM). The proposed scheme is focused on suppressing the average noise power in frequency domain aspect, which is more suitable for the program error reduction in NVMs. The concept of active capacitor is utilized. Feed forward effect of the amplifier is firstly considered in the impedance analysis, and a trade-off relation between in-band and out-band frequency noise decoupling performance is shown. A fast optimization based on average noise power is made to achieve minimum error in the F-N tunneling program. Simulation results show very stable output voltage in different load conditions, the average ripple voltage is 17 mV with up to 20 dB noise-suppression-ratio (NSR), and the F-N tunneling program error is less than 5 mV for a 800 mu s program pulse. A test chip is also fabricated in 0.18 mu m technology. The area overhead of the proposed scheme is 2%. The measurement results show 24.4 mV average ripple voltage compared to 72.3 mV of the conventional one with the same decoupling capacitance size, while the noise power suppression achieves 15.4 dB.

    DOI

  • An Energy Efficiency 4-bit Multiplier with Two-Phase Non-overlap Clock Driven Charge Recovery Logic

    Yimeng Zhang, Leona Okamura, Tsutomu Yoshihara

    IEICE TRANSACTIONS ON ELECTRONICS   E94C ( 4 ) 605 - 612  2011.04

     View Summary

    A novel charge-recovery logic structure called Pulse Boost Logic (PBL) is proposed in this paper. PBL is a high-speed low-energy-dissipation charge-recovery logic with dual-rail evaluation tree structure. It is driven by 2-phase non-overlap clock, and requires no DC power supply. PBL belongs to boost logic family, which includes boost logic, enhanced boost logic and subthreshold boost logic. In this paper, PBL has been compared with other charge-recovery logic technologies. To demonstrate the performance of PBL structure, a 4-bit pipeline multiplier is designed and fabricated with 0.18 mu m CMOS process technology. The simulation results indicate that the 4-bit multiplier can work at a frequency of 1.8 GHz, while the measurement of test chip is at operation frequency of 161 MHz, and the power dissipation at 161 MHz is 772 mu W.

    DOI

  • A 4-phase cross-coupled charge pump with charge sharing clock scheme

    Hui Zhu, Mengshu Huang, Yimeng Zhang, Tsutomu Yoshihara

    International Conference on Electronic Devices, Systems, and Applications     73 - 76  2011

     View Summary

    A 4-phase cross-coupled charge pump with charge sharing clock scheme is proposed in this paper. Four phase clock is utilized to prevent the reverse leakage current. A charge sharing clock control circuit is constructed, and the consumption in charging or discharging the bottom plate parasitic capacitance of the boost capacitors is reduced by half. The proposed charge pump is overstress free and compatible for standard CMOS process. Simulation results show a maximum 10% efficiency increase more than that of conventional charge pump without charge sharing. © 2011 IEEE.

    DOI

  • An innovative invert charge recovery logic structure

    Nan Wang, Yimeng Zhang, Tsutomu Yoshihara

    International Conference on Electronic Devices, Systems, and Applications     25 - 28  2011

     View Summary

    In this paper, we propose a new energy saving boost logic structure named Invert Boost Logic(IBL). This design belongs to the Boost Logic family and inherits the same two-phase structure. Transistor numbers, layout area and power consumption reduce significantly by virtue of this novel design. Driven by two opposite phased power clocks, it can maximize its gate drivability by increasing the logic power supply voltage thanks to the recycling ability of the AC energy sources as well as two latches. Energy cut could be as high as 60% at GHz-Class frequencies. © 2011 IEEE.

    DOI

  • A non-rectifier wireless power transmission system using on-chip inductor

    Yimeng Zhang, Mengshu Huang, Tsutomu Yoshihara

    Proceedings of International Conference on ASIC     112 - 115  2011

     View Summary

    In this paper a wireless power transmission system is designed and implemented with 0.18μm CMOS technology. A novel structure without rectifier is developed in order to improve the power transmission efficiency. The coupled inductors are a pair of highly optimized 700μmx700μm on-chip inductors, and with the proposed structure, simulation achieves wireless transmitted power of 32mW, while the measurement of test chip shows the achieved transmission power is 22mW. © 2011 IEEE.

    DOI

  • Word error control algorithm through multi-reading for NAND flash memories

    Chong Zhang, Tsutomu Yoshihara

    Proceedings of International Conference on ASIC     236 - 239  2011

     View Summary

    This paper presents one error control scheme for NAND Flash memories with error correction code (ECC). With the increasing array bit error rates, multi bits ECCs like binary Bose-Chaudhuri-Hocquenghem (BCH) code, have been used widely to improve endurance and improve retention. However, with the correction ability and codeword length raise, the parity bits cost increase at the same time. With erasure concept, which means the read data is unstable for erasure cells, this paper proposes a codeword error decrease scheme for NAND Flash memories. This method with no more bits cost could provides more than 70% error decrease by altering reading data if errors exceed correction capability. It could be combined with BCH code or one-bits ECC like hamming code, for both 1-bit/cell or multi-bits/cell memories. © 2011 IEEE.

    DOI

  • CMOS low-power subthreshold reference voltage utilizing self-biased body effect

    Hao Zhang, Yimeng Zhang, Mengshu Huang, Yoshihara Tsutomu

    Proceedings of International Conference on ASIC     516 - 519  2011

     View Summary

    Two novel voltage reference using self-biased body effect are discussed in this paper. The proposed circuits based on the weighted difference of two gate-source voltages of two MOSFETs operated in subthreshold region and one of them with forward-biased body effect, can generate two ultra-low reference voltages of 171.1 mV and 243.2 mV with temperature coefficients of 15.6 ppm/°C and 14.8 ppm/°C in a range from -25°C∼80°C, respectively. The voltage line sensitivities are 0.0025%/V and 0.0019%/V. The power supply rejection ratio (PSRR) are -110 dB and -105 dB at 100 Hz. The power dissipations are 0.74 W and 1.4 μW at a 1.4-V power supply. The circuits were designed and simulated in 0.18 μm CMOS technology. The layouts illustrate the chip area are 0.016 mm 2 and 0.014 mm 2. © 2011 IEEE.

    DOI

  • A 1pJ/cycle Processing Engine in LDPC application with charge recovery logic

    Yimeng Zhang, Mengshu Huang, Nan Wang, Satoshi Goto, Tsutomu Yoshihara

    2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011     213 - 216  2011

     View Summary

    This paper presents a Processing Engine (PE) which is used in Low Density Parity Codec (LDPC) application with a novel charge-recovery logic called pseudo-NMOS boost logic (pNBL), to achieve high-speed and low power dissipation. pNBL is a high-overdriven, low area consuming charge recovery logic, which belongs to boost logic family. Proposed Processing Engine is used in LDPC circuit to reduce power dissipation and increase the processing speed. To demonstrate the performance of proposed PE, a test chip is designed and fabricated with 0.18μm CMOS technology. Simulation results indicate that proposed PE with pNBL dissipates only 1pJ/cycle when working at the frequency of 403MHz, which is only 36% of PE with conventional static CMOS gates. The measurement results shows that the test chip can work as high as 609MHz with the energy dissipation of 2.1pJ/cycle. © 2011 IEEE.

    DOI

  • A novel soft-switching grid-connected PV inverter and its implementation

    Minjie Chen, Xutao Lee, Yoshihara Tsutomu

    Proceedings of the International Conference on Power Electronics and Drive Systems     373 - 378  2011

     View Summary

    This paper proposes a novel soft-switching PV inverter formed by a ZVT-PWM boost converter, a ZVS-ZCS-PWM buck converter and a low frequency full-bridge inverter. The ZVT-PWM boost converter maintains the dc-bus voltage and provides an auxiliary current source for the soft-switching cell of the buck converter. The buck converter consists of a main switch and an auxiliary switch, with ZVS and ZCS features respectively, which generates a semi-sinusoidal current output. The semi-sinusoidal current is inverted into sinusoidal and fed to the utility grid by the low frequency full-bridge inverter. The overall efficiency is improved and the size is dramatically reduced due to high frequency operation. The operating principles are presented and the circuit is implemented to a 1000W prototype machine. The experimental results with a maximum overall efficiency up to 97% at 100 kHz, about 1.5%'s improvement compared to the hard-switching one, verify the proposal. © 2011 IEEE.

    DOI

  • 逆電流制御による高効率DC/DCコンバータ

    関世棟, 岡村怜王奈, 張藝蒙, 黄孟枢, 吉原務

    JCEE Kyushu 2010    2010.09

    DOI

  • A new precharge structure for Charge-Transfer-Switch (CTS) Converter

    Zhu Hui, Huang Mengshu, Okamura Leona, Yoshihara Tsutomu

    JCEE Kyushu 2010    2010.09

  • A Novel Asymmetric Charge Recovery Logic

    Nan WANG, Yimeng ZHANG, Tsutomu YOSHIHARA

    JCEE Kyushu 2010    2010.09

  • Power analysis of distributed differential oscillator

    Yimeng Zhang, Leona Okamura, Mengshu Huang, Tsutomu Yoshihara

    2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings     179 - 182  2010

     View Summary

    Power dissipation performance of distributed differential oscillator (DDO) is investigated. The architecture of DDO and factors affecting performance are introduced. Power dissipation analysis with a physical model was implemented. The relationship between power dissipation performance and quality factor Q is discussed. Moreover, the result is compared with nonresonant clocking system to demonstrate DDO has a better power dissipation performance. Simulation is implemented to examine whether power dissipation performance is consistent to the analysis result. ©2010 IEEE.

    DOI

  • A new 7-transistor SRAM cell design with high read stability

    Yen Hsiang Tseng, Yimeng Zhang, Leona Okamura, Tsutomu Yoshihara

    2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings     43 - 47  2010

     View Summary

    The conventional SRAMs, namely four-transistor SRAM (4T) and six-transistor SRAM (6T), suffered from the external noise, because they have direct paths through bit-line(BL) to their storage nodes. This paper proposes seven-transistor (7T) SRAM which has no direct path through BL to the data storage nodes and has higher endurance against external noise. The proposed cell is composed of two separate data access mechanisms
    one is for the read operation and another is for the write one. Based upon our SRAM design, data destruction never occurs in the read operation. Simulation result shows that the read Static-Noise-Margin (SNM) of the proposed cell is enhanced by 1.6X and 0.31X with the conventional 4T and 6T SRAM cell respectively. We also manufactured a chip and confirmed its performance. ©2010 IEEE.

    DOI

  • A novel structure of energy efficiency charge recovery logic

    Yimeng Zhang, Leona Okamura, Mengshu Huang, Tsutomu Yoshihara

    1st International Conference on Green Circuits and Systems, ICGCS 2010     133 - 136  2010

     View Summary

    A novel charge-recovery logic structure called Pulse Boost Logic (PBL) is proposed in this paper. PBL is a highspeed low-energy-dissipation charge-recovery logic with dual-rail evaluation tree structure. It is driven by 2-phase non-overlap clock, and requires no DC power supply. To demonstrate the performance of PBL structure, 4-bit counters designed with both PBL gates and conventional static CMOS. Post-layout simulation is applied to compare energy dissipation performance between PBL and conventional static CMOS in a frequency range of 500MHz to 1GHz. The simulation result indicates that PBL dissipates only 15% energy per cycle at 1GHz, and for sequential circuits such as counter, PBL is less area consuming than static CMOS. © 2010 IEEE.

    DOI

  • Error rate decrease through hamming weight change for NAND flash

    Chong Zhang, Mengshu Huang, Leona Okamura, Tsutomu Yoshihara

    ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies     1079 - 1082  2010

     View Summary

    NAND Flash memory is widely used in recent SoCs. High density NAND Flash requires Error Correcting Code (ECC) mechanism to guarantee data integrity. We propose an efficient ECC model which decrease multi bit errors by considering the Flash memory's characteristic. According to the Flash memory mechanism, 0's error is more likely to happen than 1's error. The proposed error control code counts the number of '1' in a word and inverts all bits to keep the number of 1 is more than that of 0s, which signify a high quantity of Hamming weight. We confirm that the proposed method is not only effective for single error but also dramatically effective for multi bit error. ©2010 IEEE.

    DOI

  • Charge sharing clock scheme for high efficiency double charge pump circuit

    Mengshu Huang, Leona Okamura, Tsutomu Yoshihara

    ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings     248 - 250  2010

     View Summary

    A charge sharing clock scheme is proposed to feed a 5-stage double charge pump circuit. By reusing the charges in charging or discharging the parasitic capacitance during the pumping process, dynamic power loss is able to be reduced by nearly a half. Under 1V supply, simulation results show a maximum 10% efficiency increase, and the ripple noise is also reduced by a half comparing to the conventional charge pumps. ©2010 IEEE.

    DOI

  • Design and optimization of hybrid decoupling scheme for charge pump circuit in non-volatile memory application

    Mengshu Huang, Leona Okamura, Tsutomu Yoshihara

    2010 International SoC Design Conference, ISOCC 2010     205 - 208  2010

     View Summary

    A high area efficiency hybrid decoupling scheme using both passive and active capacitors is designed to suppress the program noise of charge pump in non-volatile memory. Through the decoupling impedance analysis and noise power calculation, an optimized ratio between the passive and active capacitors is obtained to achieve maximum noise suppression performance. The proposed hybrid decoupling charge pump is fabricated in 0.18μm technology with 1V supply voltage. The results show a nearly 20dB noise-suppression-ratio (NSR) to the conventional method and the ripple voltage reduction is 73%. The area overhead is only 2%. ©2010 IEEE.

    DOI

  • A 160MHz 4-bit pipeline multiplier using charge recovery logic technology

    Yimeng Zhang, Leona Okamura, Nan Wang, Tsutomu Yoshihara

    2010 International SoC Design Conference, ISOCC 2010     127 - 130  2010

     View Summary

    In this paper a 4-bit pipeline multiplier is designed using a novel charge-recovery logic technology called Pulse Boost Logic (PBL), and fabricated out with Rohm 0.18μm CMOS process. Cadence Spectre simulation indicates that energy dissipation of proposed PBL multiplier is 79% of Enhanced Boost Logic with almost the same number of transistors. The test chip is using a LC resonant system for AC power supply, since PBL structure requires two phase non-overlap clock as power supply. The measurement result shows that operation frequency of PBL 4-bit pipeline multiplier is up to 161MHz, while the energy dissipation is 4.81pJ/cycle. ©2010 IEEE.

    DOI

  • High efficiency Autonomous Controlled Cascaded LDOs for Green Battery System

    Leona OKAMURA, Fukashi MORISHITA, Kazutami ARIMOTO, Tsutomu YOSHIHARA

    IEEE ASICON 2009     336 - 339  2009.10

    DOI

  • アクティブデカップリング回路によるオンチップ電源ノイズの低減

    李哲, 岡村玲王奈, 吉原務

    電気関係学会九州支部連合大会    2009.09

    DOI

  • Clock Amplitude Modulation to Improve Carge Pump's Power Integrity

    Li Jiashen, Leona Okamura, Tsutomu Yoshihara

    JCEE Kyushu 2009    2009.09

    DOI

  • Decrease Error Rate by Group Count Code for NAND Flash Memory

    Zhang Chong, Leona Okamura, Tsutomu Yoshihara

    JCEE Kyushu 2009    2009.09

  • A 1.5V Four Phase Switched Polarity Charge Pump

    Mengshu HUANG, Leona OKAMURA, Yuzhe WANG, Tsutomu YOSHIHARA

    IEEE ICCCAS2009     688 - 692  2009.07

  • A 0.5V Constant-gm Rail-to-Rail OPAMP Using a Bulk-Driven Signal Compressor

    Xiao Zhang, Leona Okamura, Tsukasa Ooishi, Yuzhe Wang, Tsutomu Yoshihara

    IEEE ICCCAS2009     657 - 660  2009.07

  • 1.8V動作4MビットフローティングゲートNOR型B4‐Flashテストチップを用いた100MB/sプログラムの考察

    三原雅章, 川尻良樹, 小林和男, 小倉卓, 宿利章二, 味香夏夫, 中島盛義, 吉原務

    電子情報通信学会論文誌(C)   Vol.J87-C ( No.4 ) 130 - 138  2009.04

  • オンチップサンプリングによる電源補償回路の検討

    石坂耕助, 岡村怜王奈, 吉原務

    電気関係学会九州支部連合大会    2008.09

    DOI

  • A New Four Phase PMOS Dickson Type Charge Pump with Threshold Voltage and Body Effect Cancellation Scheme

    Mengshu HUANG, Leona OKAMURA, Tsutomu YOSHIHARA, Toyoki TAGUCHI

    電気関係学会九州支部連合大会    2008.09

    DOI

  • A constant gm input stage for 0.8V rail-to-rail OP.Amp.

    Xiao Zhang, Leona Okamura, Tsutomu Yoshihara

    電気関係学会九州支部連合大会    2008.09

  • A 65 nm embedded SRAM with wafer level burn-in mode, leak-bit redundancy and Cu E-trim fuse for known good die

    Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   43 ( 1 ) 96 - 108  2008.01

     View Summary

    We propose a wafer level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair for an embedded 6T-SRAM to achieve a known good die (KGD) SoC. We fabricated a 16 Mb SRAM with these techniques using 65 nm LSTP technology, and confirmed the efficient operations of these techniques. The WLBI mode enables simultaneous write operation for 6T-SRAM, and has no area penalty and a speed penalty of only 50 ps. The leak-bit redundancy for 6T-SRAM can reduce the infant mortality of the bare die, and improves the standby current distribution. The area penalty is less than 2%. The Cu E-trim fuse can be used beyond the 45 nm advanced process technology. The fuse requires no additional wafer process steps. Using only 1.2 V core transistors will allow CMOS technology scaling to enable fuse circuit size reduction. The trimming transistor is placed under the fuse due to there being no cracking around the trimmed position. We achieve the small fuse circuit size of 6 x 36 mu m(2) using 65 nm technology.

    DOI

  • A Fast Lock Phase-Locked Loop Using a Continuous-Time Phase Frequency Detector

    Jun Pan, Tsutomu Yoshihara

    IEEE EDSSC2007     393 - 396  2007.12

    DOI

  • A Charge Pump Circuit Without Overstress in Low-Voltage CMOS Standard Process

    Jun Pan, Tsutomu Yoshihara

    IEEE EDSSC2007     501 - 504  2007.12

    DOI

  • 新型高効率高速高電圧発生可能なチャージポンプ発生回路

    車元春, 岡村怜王奈, 吉原務

    電気関連学会九州支部学生講演会    2007.09

  • 昇圧型DC/DCコンバータの制御回路の検討

    西川和磨, 岡村怜王奈, 吉原務

    電気関連学会九州支部学生講演会    2007.09

  • Self-Compensating Power Supply Circuit for Low Voltage SOI

    Leona Okamura, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, TsutomuYoshihara

    IEEE ICCCAS 2007   ( #8 01-30 ) 1 - 4  2007.07

  • Simulation of thermal-neutron-induced single-event upset using particle and heavy-ion transport code system

    Yutaka Arita, Koji Niita, Yuji Kihara, Junich Mitsuhasi, Mikio Takai, Izumi Ogawa, Tadafumi Kishimoto, Tsutomu Yoshihara

    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS   46 ( 6A ) 3377 - 3379  2007.06

     View Summary

    The simulation of a thermal-neutron-induced single-event upset (SEU) was performed on a 0.4-mu m-design-rule 4 Mbit static 14 random access memory (SRAM) using particle and heavy-ion transport code system (PHITS). The SEU rates obtained by the simulation were in very good agreement with the result of experiments. PHITS is a useful tool for simulating SEUs in semiconductor devices. To further improve the accuracy of the simulation, additional methods for tallying the energy deposition are required for PHITS.

    DOI

  • ソフトエラー対策としてのSuperSRAM技術

    木原雄二, 有田豊, 岡村怜王奈, 中嶋康, 佐藤広利, 吉原務

    電子情報通信学会論文誌(C)   9 ( No.4 ) 378 - 389  2007.04

  • A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits

    Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinobara

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   42 ( 4 ) 820 - 829  2007.04

     View Summary

    In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-mu m(2) SRAM cell with a beta ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology.

    DOI

  • DRAM技術を使用した新型SRAM

    木原雄二, 岡村怜王奈, 中嶋泰, 井筒隆, 中本正幸, 吉原務

    電子情報通信学会論文誌(C)   J89-C ( No.10 ) 725 - 734  2006.10

  • Investigations of Thermal Neutron Induced Single Event Upsets by Using PHITS

    Y.Arita, K.Niita, M.Takai, T.Yoshihara

    7th International Workshop on Radiation Effects on Semiconductor    2006.10

  • A 100MHz MRAM implementation with simultaneous operation function and high chip density

    Hu Li, Leona Okamura, Tsutomu Yoshihara, Tsukasa Ooishi, Yuji Kihara

    IEEE ISCIT 2006   ( W2D-2 ) 1 - 4  2006.10

  • An Automatic Source/Body Level Controllable 0.5V level SOI Circuit Technique for Mobile and Wireless Network Applications

    Leona Okamura, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, TsutomuYoshihara

    IEEE ISCIT 2006   ( T4D-6 ) 1 - 4  2006.10

  • DRAM技術を用いて特性を改善した16MSRAM

    木原雄二, 中嶋泰, 井筒隆, 中本正幸, 吉原務

    電子情報通信学会技術研究報告   信学技報 ( Vol.106 No.2 ) 79 - 82  2006.04

     View Summary

    A 16Mbit Low power SRAM with 0.98um^2 cells using 0.15um DRAM and TFT technology has been developed. A new type memory cell technology achieves enough low power, low cost and high soft error immunity with out large investment. By these improved characteristics some customers at industrial machines and handy devices decided to use this new type of SRAM by compatibility with SRAM.

    CiNii

  • MRAMに適したセルフリファレンス型センス手法の検討

    岡村怜王奈, 木原雄二, 金泰潤, 木村史法, 松井悠亮, 大石司, 吉原務

      信学技報 ( Vol.106 No.2 ) 55 - 60  2006.04

  • A 75MHz MRAM with Pipe-Lined Self-Reference Read Scheme for Mobile/Robotics Memory System

    Tae Yun Kim, Fuminori Kimura, Yusuke Matsui, Tsutomu Yoshihara, Tsukasa Ooishi, Yuji Kihara, Masahiro Hatanaka

    ASSCC2005   Proceedings of Technical Paper   117 - 120  2005.11

    DOI

  • A 16M SRAM with Improved Characteristics Using DRAM Technology

    Yuji.Kihara, Yasushi Nakashima, Takashi Izutsu, Masayuki Nakamoto, Yasuhiro Konishi, Tsutomu Yoshihara

    ASSCC2005   Proceedings of Technical Paper   17 - 20  2005.11

    DOI

  • A study of sense-voltage margins in low-voltage-operating embedded DRAM macros

    A Yamazaki, F Morishita, N Watanabe, T Amano, M Haraguchi, H Noda, A Hachisuka, K Dosaka, K Arimoto, S Wake, H Ozaki, T Yoshihara

    IEICE TRANSACTIONS ON ELECTRONICS   E88C ( 10 ) 2020 - 2027  2005.10

     View Summary

    The voltage margin of an embedded DRAM's sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In this paper, the voltage margin of the sense operation is theoretically analyzed. The accuracy of the proposed voltage margin model was confirmed on a 0.13-mu m eDRAM test chip, and the results of calculation were generally in agreement with the measured results.

    DOI

  • MRAMメモリセルを用いたデュアルポートメモリの検討

    松井, 岡村, 大石, 吉原

    電気関係学会九州支部連合大会     162  2005.09

  • 低電圧動作に適したレベルシフト型シリーズレギュレータの検討

    木村, 岡村, 森下, 吉原

    電気関係学会九州支部連合大会     599  2005.09

  • Embedded low-power dynamic TCAM architecture with transparently scheduled refresh

    H Noda, K Inoue, HJ Mattausch, T Koide, K Dosaka, K Arimoto, K Fujishima, K Anami, T Yoshihara

    IEICE TRANSACTIONS ON ELECTRONICS   E88C ( 4 ) 622 - 629  2005.04

     View Summary

    This paper describes a dynamic TCAM architecture with planar complementary capacitors, transparently scheduled refresh (TSR), autonomous power management (APM) and address-input-free writing scheme. The complementary cell structure of the planar dynamic TCAM (PD-TCAM) allows small cell size of 4.79 mu m(2) in 130 nm CMOS technology, and realizes stable TCAM operation even with very small storage capacitance. Due to the TSR architecture, the PD-TCAM maintains functional compatibility with a conventional SRAM-based TCAM. The combined effects of the compact PD-TCAM array matrix and the APM technique result in up to 50% reduction of the total power consumption during search operation. In addition, an intelligent address-input-free writing scheme is also introduced to facilitate the PD-TCAM application for the user. Consequently the proposed architecture is quite attractive for realizing compact and low-power embedded TCAM macros for the design of system VLSI solutions in the field of networking applications.

    DOI

  • メモリ高速インターフェースのスルーレート制御手法

    韓峰, 小西康弘, 大石司, 松井悠亮, 吉原 務

    電子情報通信学会全国大会    2005.03

  • Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memory

    Kiyohiro FURUTANI, Takeshi Hamamoto, Takeo,MIKI, MasayaNAKANO, Takashi KONO, Shigeru KIKUDA, Yasuhiro KONISHI Tsutomu, YOSHIHARA

    IEICE TRANS.on Electronics   E-88 ( 2 ) 255 - 263  2005.02

    DOI

  • A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications

    F Morishita, Hayashi, I, H Matsuoka, K Takahashi, K Shigeta, T Gyohten, M Nliro, H Noda, M Okamoto, A Hachisuka, A Amo, H Shinkawata, T Kasaoka, K Dosaka, K Arimoto, K Fujishima, K Anami, T Yoshihara

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   40 ( 1 ) 204 - 212  2005.01

     View Summary

    An embedded DRAM macro with a self-adjustable timing control (STC) scheme, a negative edge transmission scheme (NET), and a power-down data retention (PDDR) mode is developed. A 13.98-mm(2) 16-Mb embedded DRAM macro is fabricated in 0.13 mum logic-based embedded DRAM process. Co-salicide word lines and MIM capacitors are used for high-speed array operation. The delay timing variation of 36% for an RC delay can be reduced to 3.8% by using the STC scheme. The NET scheme transfers array control signals to local array blocks with high accuracy. Thereby, the test chip achieves 1.2-V 312-MHz random cycle operation even in the low-power process. 73-muW data retention power is realized by using the PDDR mode, which is 5% of conventional schemes.

    DOI

  • A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture

    H Noda, K Inoue, M Kuroiwa, F Igaue, K Yamamoto, HJ Mattausch, T Koide, A Amo, A Hachisuka, S Soeda, Hayashi, I, F Morishita, K Dosaka, K Arimoto, K Fujishimia, K Anami, T Yoshihara

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   40 ( 1 ) 245 - 253  2005.01

     View Summary

    This paper describes a 4.5-Mb dynamic ternary CAM (DTCAM) which is suitable for networking applications. A dynamic TCAM cell structure in 130-nm embedded DRAM technology is used to realize the small cell size of 3.59 mum(2). In addition, a novel array architecture of TCAM, the pipelined hierarchical searching (PHS) architecture, is proposed. The PHS architecture is found to be suitable for realizing small area penalty high-throughput searching and low-voltage operation simultaneously. With the combination of the DTCAM cell and the PHS architecture, small silicon area of 32 mm(2) for a fabricated 4.5-Mb DTCAM chip, high performance of 143 M searches per second and low power dissipation of 1.1 W have been achieved. To Improve the yield of TCAMs, a novel shift redundancy technique is applied and estimated to result in 3.6-times yield improvement. These techniques and architectures described in this report are attractive for realizing cost-efficient, large-scale, high-performance TCAM chips.

    DOI

  • MRAMに適したセルフリファレンス型センス手法の検討

    米田健司, 大石司, 吉原務

    電気関係学会九州支部連合大会     310  2004.09

  • A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM

    T Hamamoto, K Furutani, T Kubo, S Kawasaki, H Iga, T Kono, Y Konishi, T Yoshihara

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   39 ( 1 ) 194 - 206  2004.01

     View Summary

    This paper describes an all-digital delay-locked loop (DLL) architecture for over 667 Mb/s operating double-data-rate (DDR) type SDRAMs, which suppresses skews and jitters. Two novel replica adjusting techniques are introduced, in which timing skews caused by the clock input and data output circuits Are reduced by a hierarchical phase comparing architecture and a replica check method with slow tester. Further, an improved phase interpolating method, suppresses jitters caused by a boundary of the fine and coarse delays.-A 512-Mb test device is fabricated using a 0.13-mum DRAM process technology, in which skew and jitter suppressed 667-Mb/s (333-MHz) DDR operation has been verified.

    DOI

  • Evaluation of a Microcontroller in Body-Tied SOI Technology

    Y.Nunomura, H.Sato, N.Itoh, K.Nii, K.Yoshida, C.Nakanishi, H.Ito, J.Nakanishi, H.Takata, Y.Nakase, H.Makino, A. Yamada, T.Arakawa, T.Yoshihara, S.Iwade

    Cool Chips IV,2003    2003.04

  • A 600-MHz 54x54-bit multiplier with rectangular-styled Wallace tree

    N Itoh, Y Naemura, H Makino, Y Nakase, T Yoshihara, Y Horiba

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   36 ( 2 ) 249 - 257  2001.02

     View Summary

    This paper presents an efficient layout method for a high-speed multiplier. The Wallace-tree method is generally used far high-speed multipliers. In the conventional Wallace tree, however, every partial product is added in a single direction from top to bottom. Therefore, the number of adders increases as the adding stage moves forward, As a result, it generates a dead area when the multiplier is laid out in a rectangle.
    To solve this problem, we propose a rectangular Wallace-tree construction method. In our method, the partial products are divided into two groups and added in the opposite direction. The partial products in the first group are added downward, and the partial products in the second group are added upward. Using this method, we eliminate the dead area. Also, we optimized the carry propagation between the two groups to realize high speed and a simple layout. We applied it to a 54 x 54-bit multiplier. The 980 mum x 1000 I-tm area size and the 600-MHz clock speed have been achieved using 0.18-mum CMOS technology.

    DOI

  • Design methodology of embedded DRAM with virtual-socket architecture

    T Yamauchi, M Kinoshita, T Amano, K Dosaka, K Arimoto, H Ozaki, M Yamada, T Yoshihara

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   36 ( 1 ) 46 - 54  2001.01

     View Summary

    This paper proposes the virtual-socket architecture in order to reduce the design turn-around time (TAT) of the embedded DRAM. The required memory density and the function of the embedded DRAM are system dependent. In the conventional design, the DRAM control circuitry with the DRAM memory array is handled as a hardware macro, resulting in the increase in design TAT,On the other hand, our proposed architecture provides the DRAM control circuitry as a software macro to take advantage of the automated tools based on synchronous circuit design. With array-generator technology, this architecture can achieve high quality and quick turn-around time (QTAT) of flexible embedded DRAM that is almost the same as the CMOS ASIC.
    We applied this virtual-socket architecture to the development of the 64-Mb synchronous DRAM core using 0.18-mum design rule and confirmed the high-speed operation, 166 MHz at CAS latency of two, and 180 MHz at that of three. The experimental results show that our proposed architecture can be applied to the development of the high-performance embedded DRAM with design QTAT.

    DOI

  • Residual Gas Measurements in Plasma Display Panels

    Sawada T, Kawarazaki H, Yoshihara T, Hosogane A, Ohba A, Terada Y, Ajika N, Kunori Y, Yuzuriha K, Hatanaka M, Miyoshi H, Yoshihara T, Uji T, Matsuo A, Taniguchi Y, Kiguchi Y

    Proceedings of 7th International Display Workshops    2000.11

  • A 0.18-mu m 256-mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica

    S Kuge, T Kato, K Furutani, S Kikuda, K Mitsui, T Hamamoto, J Setogawa, K Hamade, Y Komiya, S Kawasaki, T Kono, T Amano, T Kubo, M Haraguchi, Y Nakaoka, M Akiyama, Y Konishi, H Ozaki, T Yoshihara

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   35 ( 11 ) 1680 - 1689  2000.11

     View Summary

    A 200-MHz double-data-rate synchronous-DRAM (DDR-SDRAM) was developed. The chip contains. a delay-locked loop (DLL) which performs over a wide range of operating conditions. Post-mold-tuning allows precise replica programming. A 200-MHz intra-chip data bus is suitable for DDR operation.

    DOI

  • Dynamic Floating Body Control SOI CMOS for Power Managed Multimedia ULSIs

    F.Morishita, K.Arimoto, K.Fujishima, Tsutomu Yoshihara, Hideyuki Ozaki

    IEEE Transactions on Electron Devices   84-C ( 2 ) 253 - 258  2000.11

  • A precharged-capacitor-assisted sensing (PCAS) scheme with novel level controllers for low-power DRAM's

    T Kono, T Hamamoto, K Mitsui, Y Konishi, T Yoshihara, H Ozaki

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   35 ( 8 ) 1179 - 1185  2000.08

     View Summary

    A precharged-capacitor-assisted sensing (PCAS) scheme suitable for Low-power DRAM using boosted-sense ground (BSG) is proposed. In this scheme, the data on bitlines are sensed with the assistance of precharged capacitors. Precise data Level generation is achieved with sense speed 4.2 ns faster than the conventional scheme in the case that bitline swing is 1.4 V, Necessary decoupling capacitors can be efficiently implemented in memory arrays by using junction capacitors between well and substrate so that the area penalty of decoupling capacitors can be minimized. To keep sensed data stable, two types of level controllers are introduced. A voltage downconverter (VDC) with a current mirror discharger (CMD) compensates for the change of both data levels during write/read operations. A level controller with charge transfer amplifier (CTA) prevents the BSG level from falling during the row active period. The two level controllers greatly improve data-retention characteristics.

    DOI

  • High-performance embedded SOI DRAM architecture for the low-power supply

    T Yamauchi, F Morisita, S Maeda, K Arimoto, K Fujishima, H Ozaki, T Yoshihara

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   35 ( 8 ) 1169 - 1178  2000.08

     View Summary

    This paper presents the high-performance DRAM array and logic architecture for a sub-1.2-V embedded silicon-on-insulator (SOI) DRAM, The degradation of the transistor performance caused by boosted wordline voltage level is distinctly apparent in the low voltage range, In our proposed stressless SOT DRAM array, the applied electric field to the gate oxide of the memory-cell transistor can be relaxed. The crucial problem that the gate oxide of the embedded-DRAM process must be thicker than that of the logic process can be solved. As a result, the performance degradation of the logic transistor can be avoided without forming the gate oxides of the memory-cell array and the logic circuits individually. In addition, the data retention characteristics can be improved. Secondly, we propose the body-bias-controlled SOI-circuit architecture which enhances the performance of the logic circuit at sub-1.2-V power supply voltage. Experimental results verify that the proposed circuit architecture has the potential to reduce the gate-delay time up to 30% compared to the conventional one. This proposed architecture could provide high performance in the low-voltage embedded SOI DRAM.

    DOI

  • A 3.6-Gb/s 340-mW 16 : 1 pipe-lined multiplexer using 0.18 mu m SOI-CMOS technology

    T Nakura, K Ueda, K Kubo, Y Matsuda, K Mashiko, T Yoshihara

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   35 ( 5 ) 751 - 756  2000.05

     View Summary

    This paper describes a 16:1 multiplexer using 0.18 mu m SOI-CMOS technology. To realize ultra-high-speed operations, the multiplexer adapts a pipeline structure and a phase shift technique together with a selector architecture, This architecture takes advantage of the small junction capacitances of the SOI-CMOS devices, The multiplexer achieves 3.6 Gbls at a supply voltage of 2.0 V, while dissipating only 30 mW at the core circuit and 340 mW for the whole chip which includes the I/O buffers.

    DOI

  • A 3.3V-ONLY 16 MB DINOR FLASH MEMORY

    S KOBAYASHI, M MIHARA, Y MIYAWAKI, M ISHII, T FUTATSUYA, A HOSOGANE, A OHBA, Y TERADA, N AJIKA, Y KUNORI, K YUZURIHA, M HATANAKA, H MIYOSHI, T YOSHIHARA, Y UJI, A MATSUO, Y TANIGUCHI, Y KIGUCHI

    1995 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS   38 ( 38 ) 122 - 123  1995

  • AN SOI-DRAM WITH WIDE OPERATING VOLTAGE RANGE BY CMOS/SIMOX TECHNOLOGY

    K SUMA, T TSURUDA, H HIDAKA, T EIMORI, T OASHI, Y YAMAGUCHI, T IWAMATSU, M HIROSE, F MORISHITA, K ARIMOTO, K FUJISHIMA, Y INOUE, T NISHIMURA, T YOSHIHARA

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   29 ( 11 ) 1323 - 1329  1994.11

     View Summary

    An SOI-DRAM test device (64-Kb scale) with 100-nm-thick SOI film has been fabricated in 0.5-mu m CMOS/SIMOX technology and the basic DRAM function has been successfully observed. A partially depleted transistor was used to solve the floating-body effect, resulting in improved operation. The newly introduced body-synchronized sensing scheme enhances the lower V-cc margin.
    The p-n junction capacitance between source/drain and a substrate for SOI structure is reduced by 25%. RAS access time tRAC is 70 ns with a 2.7-V power supply, which is as fast as the equivalent bulk-Si device with a 4-V power supply. The active current consumption is 1.1 mA (V-cc = 3.0 V, 260-ns cycle) for this SOI-DRAM, which is a reduction of 65%, compared with 3.2 mA for the reference bulk-Si DRAM. The mean value of data retention time for this chip at 80 degrees C is longer than 20 s (V-cc = 3.3 V), which is the same value as mass-produced 16-Mb DRAM's. The SOI-DRAM has an operating V-cc range from 2.3 V to 4.0 V. The observed speed enhancement and the wide operating voltage range indicate high performance at the low voltage operation suitable for battery-operated DRAM's.

    DOI

  • AN EXPERIMENTAL 256-MB DRAM WITH BOOSTED SENSE-GROUND SCHEME

    M ASAKURA, T OOISHI, M TSUKUDE, S TOMISHIMA, T EIMORI, H HIDAKA, Y OHNO, K ARIMOTO, K FUJISHIMA, T NISHIMURA, T YOSHIHARA

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   29 ( 11 ) 1303 - 1309  1994.11

     View Summary

    In developing the 256-Mb DRAM, the data retention characteristics must inevitably be improved. In order for DRAM's to remain the semiconductor device with the largest production volume in the 256-Mb era, we must develop a cost effective device with a small chip size and a large process tolerance. In this paper, we propose the BSG (Boosted Sense-Ground) scheme for data retention and FOGOS (FOlded Global and Open Segment bit-line) structure for chip size reduction. We have fabricated an experimental 256-Mb DRAM with these technologies and obtained a chip size of 304 mm(2) and a performance of 34 ns access time.

    DOI

  • MEMORY ARRAY ARCHITECTURE AND DECODING SCHEME FOR 3-V ONLY SECTOR ERASABLE DINOR FLASH MEMORY

    S KOBAYASHI, H NAKAI, Y KUNORI, T NAKAYAMA, Y MIYAWAKI, Y TERADA, H ONODA, N AJIKA, M HATANAKA, H MIYOSHI, T YOSHIHARA

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   29 ( 4 ) 454 - 460  1994.04

     View Summary

    A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low V(cc) and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 mum, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8 x 1.6 mum2 and the chip measures 5.8 x 5.0 mm2. The divided bit line structure realizes a small NOR type memory cell.

  • ROW-REDUNDANCY SCHEME FOR HIGH-DENSITY FLASH MEMORY

    M MIHARA, T NAKAYAMA, M OHKAWA, S KAWAI, Y MIYAWAKI, Y TERADA, M OHI, H ONODA, N AJIKA, M HATANAKA, H MIYOSHI, T YOSHIHARA

    1994 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - DIGEST OF TECHNICAL PAPERS   37 ( 37 ) 150 - 151  1994

  • AN OVER-ERASURE DETECTION TECHNIQUE FOR TIGHTENING 5TH DISTRIBUTION FOR LOW-VOLTAGE OPERATION NOR TYPE FLASH MEMORY

    Y MIYAWAKI, T NAKAYAMA, M MIHARA, S KAWAI, M OHKAWA, N AJIKA, M HATANAKA, Y TERADA, T YOSHIHARA

    1994 SYMPOSIUM ON VLSI CIRCUITS     63 - 64  1994

  • AN SOI-DRAM WITH WIDE OPERATING VOLTAGE RANGE BY CMOS/SIMOX TECHNOLOGY

    K SUMA, T TSURUDA, H HIDAKA, T EIMORI, T OASHI, Y YAMAGUCHI, T IWAMATSU, M HIROSE, K FUJISHIMA, Y INOUE, T NISHIMURA, T YOSHIHARA

    1994 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - DIGEST OF TECHNICAL PAPERS   37 ( 37 ) 138 - 139  1994

  • A 34NS 256MB DRAM WITH BOOSTED SENSE-GROUND SCHEME

    M ASAKURA, T OHISHI, M TSUKUDE, S TOMISHIMA, H HIDAKA, K ARIMOTO, K FUJISHIMA, T EIMORI, Y OHNO, T NISHIMURA, M YASUNAGA, T KONDOH, S SATOH, T YOSHIHARA, K DEMIZU

    1994 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - DIGEST OF TECHNICAL PAPERS   37 ( 37 ) 140 - 141  1994

  • MEMORY ARRAY ARCHITECTURE AND DECODING SCHEME FOR 3V ONLY SECTOR ERASABLE DINOR FLASH MEMORY

    S KOBAYASHI, H NAKAI, Y KUNORI, T NAKAYAMA, Y MIYAWAKI, Y TERADA, H ONODA, N AJIKA, M HATANAKA, H MIYOSHI, T YOSHIHARA

    1993 SYMPOSIUM ON VLSI CIRCUITS     97 - 98  1993

  • A 100-MHZ 4-MB CACHE DRAM WITH FAST COPY-BACK SCHEME

    K DOSAKA, Y KONISHI, K HAYANO, K HIMUKASHI, A YAMAZAKI, H IWAMOTO, M KUMANOYA, H HAMANO, T YOSHIHARA

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   27 ( 11 ) 1534 - 1539  1992.11

     View Summary

    A 4-Mb cache DRAM (CDRAM), which integrates 16-kb SRAM as a cache memory and 4-Mb DRAM into a monolithic circuit, will be described. This CDRAM has a 100-MHz operating cache, newly proposed fast copy-back (FCB) scheme that realizes a three times faster miss access time over with the conventional copy-back method, and maximized mapping flexibility. The process technology is a quad-polysilicon double-metal 0.7-mum CMOS process, which is the same as used in a conventional 4-Mb DRAM. The chip size of 82.9 mm2 is only a 7% increase over the conventional 4-Mb DRAM. The simulated system performance indicated better performance than a conventional cache system with eight times the cache capacity.

    DOI

  • ULSI DRAM技術

    サイエンスフォーラム社    1992.06

  • A new decoding scheme and erase sequence for 5V only sector erasable flash memory

    Nakayama T, Kobayashi S, Miyawaki Y, Futastuya T, Terada Y, Ajika N, Yoshihara T

    IEEE Symposium on VLSI Circuits     22 - 23  1992.05

  • A New Erasing and Row Decoding Scheme for Low Supply Voltage Operation 16Mb/64Mb Flash Memories

    Miyawaki Y, Nakayama T, Kobayashi S, Ajika N, Ohi M, Terada Y, Arima H, Yoshihara T

    IEEE Journal of Solid-State Circuits   27 ( 4 ) 583 - 588  1992.04

    DOI

  • A 100 MHz 4Mb Cache DRAM with Fast Copy-Back Scheme

    Dosaka K, Konishi Y, Hayano K, Yamazaki A, Kumanoya M, Hamano H, Yoshihara T

    IEEE International Solid State Circuits Conference   ( 35 ) 148 - 149  1992.02

  • A 60-NS 16-MB FLASH EEPROM WITH PROGRAM AND ERASE SEQUENCE CONTROLLER

    T NAKAYAMA, S KOBAYASHI, Y MIYAWAKI, Y TERADA, N AJIKA, M OHI, H ARIMA, T MATSUKAWA, T YOSHIHARA, K SUZUKI

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   26 ( 11 ) 1600 - 1605  1991.11

     View Summary

    An erase and program control system has been implemented in a 60-ns 16-Mb flash EEPROM. The memory array is divided into 64 blocks, and in each block, erase pulse application and erase-verify operation are employed individually. The erase and program sequence is controlled by an internal sequence controller which is composed of a synchronous circuit with an on-chip oscillator. A 60-ns access time has been achieved with a differential sensing scheme utilizing dummy cells. The cell size is 1.8-mu-m x 2.0-mu-m and the chip size is 6.5 mm x 18.4 mm using a simple stacked gate cell structure and 0.6-mu-m CMOS process.

    DOI

  • A 45-NS 64-MB DRAM WITH A MERGED MATCH-LINE TEST ARCHITECTURE

    S MORI, H MIYAMOTO, Y MOROOKA, S KIKUDA, M SUWA, M KINOSHITA, A HACHISUKA, H ARIMA, M YAMADA, T YOSHIHARA, S KAYANO

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   26 ( 11 ) 1486 - 1492  1991.11

     View Summary

    A single 3.3-V 64-Mb DRAM with a chip size of 233.8 mm2 has been fabricated using 0.4-mu-m CMOS technology with double-level metallization. The dual-cell-plate (DCP) cell structure is applied with a cell size of 1.7-mu-m2, and 30-fF cell capacitance has been achieved using an oxynitride layer (t(eff) = 5 nm) as the gate insulator. The RAM implements a new data-line architecture called the merged match-line test (MMT) to achieve faster access time and shorter test time with the least chip-area penalty. The MMT architecture makes it possible to get an RAS access time of 45 ns, and reduces test time by 1/16000. A parallel MMT technique, which is an extended mode of MMT, leads to the further test-time reduction of 1/64000. Therefore, all 64 Mb are tested in only 1024 cycles, and the test time is only 150-mu-s with 150-ns cycle time.

    DOI

  • A new erasing and row decoding scheme for low supply voltage operation16 Mb/64 Mb flash EEPROM

    Miyawaki Y, Nakayama T, Kobayashi K, Ajika N, Ohi M, Terada Y, Arima H, Yoshihara T

    IEEE Symposium on VLSI Circuits     85 - 86  1991.05

  • A 60ns 16Mb Flash EEPROM with Program and Erase Sequence Controller

    Nakayama T, Kobayashi S, Miyawaki Y, Terada Y, Ajika N, Ohi M, Arima H, Matsukawa T, Yoshihara T

    IEEE International Solid State Circuits Conference   ( 34 ) 260 - 261  1991.02

  • A 34ns 16 MbDRAM with controllable voltage down converter

    Arimoto K, Hidaka H, Hayashikoshi M, Asakura M, Fujishima K, Yoshihara T

    IEEE European Solid State Circuits Conference     21 - 24  1990.09

  • High speed page mode sensing scheme for EPROM's and flash EPROM's using divided bit line architecture

    Terada Y, Nakayama T, Kobayashi K, Hayashikoshi M, Kobayashi S, Miyawaki Y, Ajika N, Arima H, Yoshihara T

    IEEE Symposium on VLSI Circuits     97 - 98  1990.05

     View Summary

    A novel high-speed page mode sense scheme for EPROMs and flash EEPROMs has been developed. A divided bit line architecture makes it possible to adopt a folded bit line architecture in which sense amplifiers are located at the end of the bit lines. Dynamic sensing avoids the soft write problem by reducing bit line voltage and the current flow through the memory cell. An experimental 1-Mb flash EEPROM using a 0.6-μm design rule has been designed. Simulated results show that a high-speed address access time of 60 ns and a page mode access time of 15 ns can be achieved.

  • A 38ns 4Mb DRAM with a battery back-up(BBU) mode

    Konishi Y, Dosaka K, Komatsu T, Inoue Y, Kumanoya M, Tobita Y, Genjo H, Nagatomo M, Yoshihara T

    IEEE International Solid State Circuits Conference   ( 33 ) 230 - 231  1990.02

  • A High-Speed Parallel Sensing Architecture for Multi-Megabit Flash E<sup>2</sup> PROM’s

    Kazuo Kobayashi, Takeshi Nakayama, Yoshikazu Miyawaki, Masanori Hayashikoshi, Yasushi Terada, Tsutomu Yoshihara

    IEEE Journal of Solid-State Circuits   25 ( 1 ) 79 - 83  1990

     View Summary

    — A high-speed parallel sensing architecture for high-density 5-V-only flash E&lt
    sup&gt
    2&lt
    /sup&gt
    PROM’s is described. A source-biasing technique enhances the cell current while minimizing the read disturbance problem. Flip-flop-type differential sense amplifiers are arranged between every two pairs of bit lines, so that half the memory cells on the same word line are sensed simultaneously. Self-timed dynamic sensing was developed for high speed and stable sensing and also decreases read disturbance and operating current. Simulated results show that a sub-10- μA cell current is successfully sensed in 40 ns. In the program mode, the differential amplifier acts as a column latch, which substantially reduces the chip size. © 1990 IEEE

    DOI

  • A 38-ns 4-Mb DRAM with a Battery-Backup (BBU) Mode

    Yasuhiro Konishi, Katsumi Dosaka, Takahiro Komatsu, Yoshinori Inoue, Masaki Kumanoya, Youichi Tobita, Hideki Genjyo, Masao Nagatomo, Tsutomu Yoshihara

    IEEE Journal of Solid-State Circuits   25 ( 5 ) 1112 - 1117  1990

     View Summary

    Portable computers operated by batteries have become popular these days, and there is a great demand for low-power LSI memories for battery backup application. This paper describes a DRAM with a battery-backup (BBU) mode, which enables automatic data retention with extremely reduced power consumption. The circuit techniques to reduce the refresh current and the back-bias-generator current are developed, and the dissipated current required for data retention of 44 uA is achieved under typical conditions. This DRAM was fabricated with quad-poly and double-metal CMOS process technology. The memory array is divided into 4X32 subarrays. This finely divided array architecture is suitable for the fast access time and the multibit test mode. © 1990 IEEE

    DOI

  • 半導体実装技術ハンドブック「α線対策」

    サイエンスフォーラム社    1986.09

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Books and Other Publications

  • ULSI DRAM技術

    サイエンスフォーラム社  1992.06

Research Projects

  • Study of basic characteristics and application of Non-volatile Memory

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research

    Project Year :

    2004
    -
    2006
     

    YOSHIHARA Tsutomu

     View Summary

    We propose a pipe-lined selfreference read scheme of MRAM with read modify write which can make an operation period short. It also brings continuous read out accompanied with a mixed mat architecture. A new self-reference sense amplifier supported by a voltage transferred circuit has a wide margin. It is able to tolerate 50% MTJ resistance variation for sensing operation, and makes 75MHz operation at 1.2V Vcc possible. It brings a robust memory module for embedded memory system and suits mobile/robotics synchronous memory system.
    We proposed two kinds of implementation of the DP-MRAM, one (RWDP) is for read/write concurrent operation, while another (R2DP)enables simultaneous read operation in addition to the above read/write concurrent operation. For the simultaneous read case with the bitline clamped by a 0VVref, the high speed operation is realized. Besides this, a swing-less bit-line sensing (SLBS) technique makes read period much shorter and keeps the operation frequency as same as the single port MRAM. From simulation we can see that the data can be successfully recognized with enough margin by sense amplifier under the conditions of Vcc=1.0V and the operation frequency of 100MHz. With the advantage in chip density it can be used as anavailable implementation to replace the SRAM in the application of cache memory area.

  • 文部科学省知的クラスタ(ユビキタスネットワーク用システムLSIの開発)

 

Internal Special Research Projects

  • 電力回収可能な低消費電力チャージリカバリロジックの基本回路と応用に関する研究

    2014  

     View Summary

      Charge Recovery Logicの応用研究のため、リアルタイムカウンタへ  の適用を図った。  センサーネットワークでは待機している時間が長く、バッテリ寿命  を伸ばすにはリアルタイムカウンタの消費電力を低減することが有  効である。リアルタイムカウンタをChargeRecovery Logic で設計し  チップ試作を行い特性を評価した。 このため16bitのカウンタを設計し  た。 ChargeRecovery Logicによる構成では、100KHzでの動作では、  92%の消費電力削減となり、Charge Recovery Logicの有用性を検証でき   た。

  • 電力回収可能なAC電源駆動チャージリカバリロジック回路とその応用に関する研究

    2012  

     View Summary

    1)研究の目的および背景 集積回路の大規模化と動作周波数の高速化に伴い、消費電力が急速に増加しており、低消費電力化が大きな技術課題となっている。スケーリングで素子の微細化とともに低消費電力化を達成するアプローチは素子の微細化の限界を迎えている。 回路に充電したエネルギーを再利用し消費電力を低減するという、Charge Recovery Logic回路が提案され研究が進んでいる[1]。Charge Recovery Logic回路は、回路の電源を従来のDC電源からAC電源に置き換えるものであり、共振回路によるAC電源を利用することでエネルギーを回収し低消費電力化を可能とする。図1にエネルギー回収の原理を示す。AC電源が低電圧から高電圧に変化する時、回路負荷を充電し、高電圧から低電圧に変化する時、回路の負荷は放電し、エネルギーは回収される。本研究はCharge Recovery Logicの基本回路と応用に関する研究である。2)研究課題 研究課題は下記の二つである。 1)低消費電力・高速のパルスブースト回路の検討   Charge Recovery LogicリカバリロジックはAC電源で論理回路を駆動するため、  論理判定する回路とその結果を増幅する回路からなる、ブーストロジックが必要で  ある。ブーストロジック回路の課題は、論理判定部回路の低電力化、高速化の課題が  あり、各種の回路が提案されているが、従来回路は論理判定部には依然としてDC電  源供給がなさてれおり、完全なCharge Recovery Logicになっていないという問題  がある。 2)チャージリカバリロジックの応用回路の検討     チャージリカバリロジックの利点を生かした応用回路の検討が課題である。3)研究内容  2相クロック駆動疑似NMOSパルスブースト回路(PNBL)を提案、応用としてLDPC(Low   Density Parity Check)に適用し、チップを試作した。4)研究成果  ・チャージリカバリロジック回路の新規なブースト回路 PNBL(Pseudo NMOS Pulse    Boost Logic)を提案した。  ・上記PNBLを大規模ロジック回路LDPC(Low Density Parity Check)に適用、チップ     試作を行い、1pJ/cycleの低消費電力を実現した。