Education Background

1971
Osaka University Graduate School, Division of Natural Science

1969
Osaka University Faculty of Science
Details of a Researcher
Updated on 2024/04/18
Osaka University Graduate School, Division of Natural Science
Osaka University Faculty of Science
電気学会
電子情報通信学会
IEEE Solid State
システムLSI回路設計
A High Efficiency MultiChannel LED Driver Based on ConverterFree Technique and Load Adaptive Method
Si FU, Minjie CHEN, Xutao LI, Tsutomu YOSHIHARA
ISOCC2014 2014.11
An OutputCapacitorless Low Dropout Regulator without Resistance
Jie MEI, Hao ZHANG, Tsutomu YOSHIHARA
ISOCC 2014 2014.11
Efficiency Improvement of DCDC Buck Converters
Ning Li, Xutao Li, Mingjie Chen, Yoshihara Tsutomu
JCEEE Kyushu 2014 2014.09
A High Efficiency MultiChannel LED Driver Based on ConverterFree Technique and Load Adaptive Method
Si FU, Minjie CHEN, Xutao LI, Tsutomu YOSHIHARA
JCEEE Kyushu 2014 2014.09
An OutputCapacitorless Low Dropout Regulator without Resistance
Jie MEI, Hao ZHANG, Tsutomu YOSHIHARA
JCEEE Kyushu 2014 2014.09
by the Switching Frequency Optimized PWM
Hao Zhang, Mengshu Huang, Yimeng Zhang, Tsutomu Yoshihara
Journal of Semiconductor Technology and Science Vol.14 ( No.1 ) 70  82 2014.02
A CMOS LowVoltage Reference Based on Body Effect and SwitchedCapacitor Technique
Yudong Lin, Hao Zhang, Tsutomu Yoshihara
ISOCC2013 2013.11
Clocked CMOS Adiabatic Logic with LowPower Dissipation
He Li, Yimeng Zhang, Tsutomu Yoshihara
ISOCC2013 2013.11
LowPower OnChip ChargeRecycling DCDC Conversion Circuit and System
Kazuhiro Ueda, Fukashi Morishita, Shunsuke Okura, Leona Okamura, Tsutomu Yoshihara, Kazutami Arimoto
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 48 ( 11 ) 2608  2617 2013.11
A CMOS LowVoltage Reference Based on Body Effect and SwitchedCapacitor Technique
Yudong Lin, Hao Zhang, Tsutomu Yoshihara
JCEE Kyushu 2013 2013.09
Clocked CMOS Adiabatic Logic with LowPower Dissipation
He Li, Yimeng Zhang, Tsutomu Yoshihara
JCEE Kyushu 2013 2013.09
“Dynamic Response Improvement of Discrete Sliding Mode Controlled Switching Power Converter via Double Integral”,
Xutao Li, Minjie Chen, Hao Zhang, Yoshihara Tsutomu
SICE 2013 2013.09
SelfCascode MOSFET with a SelfBiased Body Effect for UltraLowPower Voltage Reference Generator
Hao Zhang, Mengshu Huang, Yimeng Zhang, Tsutomu Yoshihara
IEICE TRANSACTIONS ON ELECTRONICS E96C ( 6 ) 859  866 2013.06
A Low Power Dissipation Real Time Counter for Sensor Network Application
Yimeng Zhang, Tsutomu Yoshihara
ICEIC2013 2013.02
A High Efficiency Charge Pump with Continuous Frequency Regulation Scheme
Shuning Wang, Mengshu Huang, Yimeng Zhang, Tsutomu Yoshihara
ICEIC2013 2013.02
A method of searching PID controller's optimized coefficients for Buck converter using particle swarm optimization
Xutao Li, Minjie Chen, Yoshihara Tsutomu
Proceedings of the International Conference on Power Electronics and Drive Systems 238  243 2013
A high efficiency charge pump with continuous frequency charge sharing scheme
Shuning Wang, Mengshu Huang, Yimeng Zhang, Tsutomu Yoshihara
2013 IEEE International Conference on Consumer Electronics  China, ICCEChina 2013 45  50 2013
A Novel quasiResonant SoftSwitching ZSource Inverter
Yuan ZHU, Minjie CHEN, Yoshihara Tsutomu
IEEEPECON2012 271  276 2012.12
A Novel Charge Recovery Logic Structure with Complementary Passtransistor Network
Jingyang Li, Yimeng Zhang, Tsutomu Yoshihara
ISOCC2012 17  20 2012.11
A CMOS Voltage Reference Combining Body Effect with SwitchedCurrent Technique
Ning REN, Hao ZHANG, Tsutomu YOSHIHARA
ISOCC2012 92  95 2012.11
High efficiency multichannel LED driver based on SIMO switchmode converter
Yu Luchen, Chen Minjie, Tsutomu Yoshihara
ISOCC2012 355  358 2012.11
Green semiconductor technology with ultralow power onchip chargerecycling power circuit and system
Kazuhiro Ueda, Okura Syunsuke, Fukashi Morishita, Kazutami Arimoto, Leona Okamura, Tsutomu Yoshihara
IEEE ASSCC2012 105  108 2012.11
Energy Efficient Processing Engine in LDPC Application with HighSpeed Charge Recovery Logic
Yimeng Zhang, Mengshu Huang, Nan Wang, Satoshi Goto, Tsutomu Yoshihara
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 12 ( 3 ) 341  352 2012.09
A Novel Charge Recovery Logic Structure with Complementary Passtransistor Network
Jingyang Li, Yimeng Zhang, Tsutomu Yoshihara
2012.09
A CMOS Voltage Reference Combining Body Effect with SwitchedCurrent Technique
Ning REN, Hao ZHANG, Tsutomu YOSHIHARA
2012.09
High efficiency multichannel LED driver based on SIMO switchmode converter
Yu Luchen, Chen Minjie, Tsutomu Yoshihara
2012.09
A Novel quasiResonant SoftSwitching ZSource Inverter
Yuan ZHU, Minjie CHEN, Yoshihara Tsutomu
2012.09
An Efficient Dual Charge Pump Circuit Using Charge Sharing Clock Scheme
Mengshu Huang, Yimeng Zhang, Tsutomu Yoshihara
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E95A ( 2 ) 439  446 2012.02
A Novel Charge Sharing Charge Pump for Energy Harvesting Application
Jiemin ZHOU, Mengshu HUANG, Yimeng ZHANG, Tsutomu YOSHIHARA
ISOCC2011 373  376 2011.11
Double charge pump circuit with triple charge sharing clock scheme
Mengshu HUANG, Yimeng Zhang, Tsutomu Yoshihara
IEEE ASICON 2011 148  152 2011.10
An Area Efficiency Hybrid Decoupling Scheme for Charge Pump Noise Suppression in Nonvolatile Memory
Mengshu Huang, Leona Okamura, Tsutomu Yoshihara
IEICE TRANSACTIONS ON ELECTRONICS E94C ( 6 ) 968  976 2011.06
An Energy Efficiency 4bit Multiplier with TwoPhase Nonoverlap Clock Driven Charge Recovery Logic
Yimeng Zhang, Leona Okamura, Tsutomu Yoshihara
IEICE TRANSACTIONS ON ELECTRONICS E94C ( 4 ) 605  612 2011.04
A 4phase crosscoupled charge pump with charge sharing clock scheme
Hui Zhu, Mengshu Huang, Yimeng Zhang, Tsutomu Yoshihara
International Conference on Electronic Devices, Systems, and Applications 73  76 2011
An innovative invert charge recovery logic structure
Nan Wang, Yimeng Zhang, Tsutomu Yoshihara
International Conference on Electronic Devices, Systems, and Applications 25  28 2011
A nonrectifier wireless power transmission system using onchip inductor
Yimeng Zhang, Mengshu Huang, Tsutomu Yoshihara
Proceedings of International Conference on ASIC 112  115 2011
Word error control algorithm through multireading for NAND flash memories
Chong Zhang, Tsutomu Yoshihara
Proceedings of International Conference on ASIC 236  239 2011
CMOS lowpower subthreshold reference voltage utilizing selfbiased body effect
Hao Zhang, Yimeng Zhang, Mengshu Huang, Yoshihara Tsutomu
Proceedings of International Conference on ASIC 516  519 2011
A 1pJ/cycle Processing Engine in LDPC application with charge recovery logic
Yimeng Zhang, Mengshu Huang, Nan Wang, Satoshi Goto, Tsutomu Yoshihara
2011 Proceedings of Technical Papers: IEEE Asian SolidState Circuits Conference 2011, ASSCC 2011 213  216 2011
A novel softswitching gridconnected PV inverter and its implementation
Minjie Chen, Xutao Lee, Yoshihara Tsutomu
Proceedings of the International Conference on Power Electronics and Drive Systems 373  378 2011
A new precharge structure for ChargeTransferSwitch (CTS) Converter
Zhu Hui, Huang Mengshu, Okamura Leona, Yoshihara Tsutomu
JCEE Kyushu 2010 2010.09
A Novel Asymmetric Charge Recovery Logic
Nan WANG, Yimeng ZHANG, Tsutomu YOSHIHARA
JCEE Kyushu 2010 2010.09
Power analysis of distributed differential oscillator
Yimeng Zhang, Leona Okamura, Mengshu Huang, Tsutomu Yoshihara
2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010  Proceedings 179  182 2010
A new 7transistor SRAM cell design with high read stability
Yen Hsiang Tseng, Yimeng Zhang, Leona Okamura, Tsutomu Yoshihara
2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010  Proceedings 43  47 2010
A novel structure of energy efficiency charge recovery logic
Yimeng Zhang, Leona Okamura, Mengshu Huang, Tsutomu Yoshihara
1st International Conference on Green Circuits and Systems, ICGCS 2010 133  136 2010
Error rate decrease through hamming weight change for NAND flash
Chong Zhang, Mengshu Huang, Leona Okamura, Tsutomu Yoshihara
ISCIT 2010  2010 10th International Symposium on Communications and Information Technologies 1079  1082 2010
Charge sharing clock scheme for high efficiency double charge pump circuit
Mengshu Huang, Leona Okamura, Tsutomu Yoshihara
ICSICT2010  2010 10th IEEE International Conference on SolidState and Integrated Circuit Technology, Proceedings 248  250 2010
Design and optimization of hybrid decoupling scheme for charge pump circuit in nonvolatile memory application
Mengshu Huang, Leona Okamura, Tsutomu Yoshihara
2010 International SoC Design Conference, ISOCC 2010 205  208 2010
A 160MHz 4bit pipeline multiplier using charge recovery logic technology
Yimeng Zhang, Leona Okamura, Nan Wang, Tsutomu Yoshihara
2010 International SoC Design Conference, ISOCC 2010 127  130 2010
High efficiency Autonomous Controlled Cascaded LDOs for Green Battery System
Leona OKAMURA, Fukashi MORISHITA, Kazutami ARIMOTO, Tsutomu YOSHIHARA
IEEE ASICON 2009 336  339 2009.10
Clock Amplitude Modulation to Improve Carge Pump's Power Integrity
Li Jiashen, Leona Okamura, Tsutomu Yoshihara
JCEE Kyushu 2009 2009.09
Decrease Error Rate by Group Count Code for NAND Flash Memory
Zhang Chong, Leona Okamura, Tsutomu Yoshihara
JCEE Kyushu 2009 2009.09
A 1.5V Four Phase Switched Polarity Charge Pump
Mengshu HUANG, Leona OKAMURA, Yuzhe WANG, Tsutomu YOSHIHARA
IEEE ICCCAS2009 688  692 2009.07
A 0.5V Constantgm RailtoRail OPAMP Using a BulkDriven Signal Compressor
Xiao Zhang, Leona Okamura, Tsukasa Ooishi, Yuzhe Wang, Tsutomu Yoshihara
IEEE ICCCAS2009 657  660 2009.07
1.8V動作4MビットフローティングゲートNOR型B4‐Flashテストチップを用いた100MB/sプログラムの考察
三原雅章, 川尻良樹, 小林和男, 小倉卓, 宿利章二, 味香夏夫, 中島盛義, 吉原務
電子情報通信学会論文誌(C) Vol.J87C ( No.4 ) 130  138 2009.04
A New Four Phase PMOS Dickson Type Charge Pump with Threshold Voltage and Body Effect Cancellation Scheme
Mengshu HUANG, Leona OKAMURA, Tsutomu YOSHIHARA, Toyoki TAGUCHI
電気関係学会九州支部連合大会 2008.09
A constant gm input stage for 0.8V railtorail OP.Amp.
Xiao Zhang, Leona Okamura, Tsutomu Yoshihara
電気関係学会九州支部連合大会 2008.09
A 65 nm embedded SRAM with wafer level burnin mode, leakbit redundancy and Cu Etrim fuse for known good die
Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 43 ( 1 ) 96  108 2008.01
A Fast Lock PhaseLocked Loop Using a ContinuousTime Phase Frequency Detector
Jun Pan, Tsutomu Yoshihara
IEEE EDSSC2007 393  396 2007.12
A Charge Pump Circuit Without Overstress in LowVoltage CMOS Standard Process
Jun Pan, Tsutomu Yoshihara
IEEE EDSSC2007 501  504 2007.12
新型高効率高速高電圧発生可能なチャージポンプ発生回路
車元春, 岡村怜王奈, 吉原務
電気関連学会九州支部学生講演会 2007.09
昇圧型DC/DCコンバータの制御回路の検討
西川和磨, 岡村怜王奈, 吉原務
電気関連学会九州支部学生講演会 2007.09
SelfCompensating Power Supply Circuit for Low Voltage SOI
Leona Okamura, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, TsutomuYoshihara
IEEE ICCCAS 2007 ( #8 0130 ) 1  4 2007.07
Simulation of thermalneutroninduced singleevent upset using particle and heavyion transport code system
Yutaka Arita, Koji Niita, Yuji Kihara, Junich Mitsuhasi, Mikio Takai, Izumi Ogawa, Tadafumi Kishimoto, Tsutomu Yoshihara
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 46 ( 6A ) 3377  3379 2007.06
ソフトエラー対策としてのSuperSRAM技術
木原雄二, 有田豊, 岡村怜王奈, 中嶋康, 佐藤広利, 吉原務
電子情報通信学会論文誌(C) 9 ( No.4 ) 378  389 2007.04
A 65nm SoC embedded 6TSRAM designed for manufacturability with read and write operation stabilizing circuits
Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinobara
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 42 ( 4 ) 820  829 2007.04
DRAM技術を使用した新型SRAM
木原雄二, 岡村怜王奈, 中嶋泰, 井筒隆, 中本正幸, 吉原務
電子情報通信学会論文誌(C) J89C ( No.10 ) 725  734 2006.10
Investigations of Thermal Neutron Induced Single Event Upsets by Using PHITS
Y.Arita, K.Niita, M.Takai, T.Yoshihara
7th International Workshop on Radiation Effects on Semiconductor 2006.10
A 100MHz MRAM implementation with simultaneous operation function and high chip density
Hu Li, Leona Okamura, Tsutomu Yoshihara, Tsukasa Ooishi, Yuji Kihara
IEEE ISCIT 2006 ( W2D2 ) 1  4 2006.10
An Automatic Source/Body Level Controllable 0.5V level SOI Circuit Technique for Mobile and Wireless Network Applications
Leona Okamura, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, TsutomuYoshihara
IEEE ISCIT 2006 ( T4D6 ) 1  4 2006.10
木原雄二, 中嶋泰, 井筒隆, 中本正幸, 吉原務
電子情報通信学会技術研究報告 信学技報 ( Vol.106 No.2 ) 79  82 2006.04
MRAMに適したセルフリファレンス型センス手法の検討
岡村怜王奈, 木原雄二, 金泰潤, 木村史法, 松井悠亮, 大石司, 吉原務
信学技報 ( Vol.106 No.2 ) 55  60 2006.04
A 75MHz MRAM with PipeLined SelfReference Read Scheme for Mobile/Robotics Memory System
Tae Yun Kim, Fuminori Kimura, Yusuke Matsui, Tsutomu Yoshihara, Tsukasa Ooishi, Yuji Kihara, Masahiro Hatanaka
ASSCC2005 Proceedings of Technical Paper 117  120 2005.11
A 16M SRAM with Improved Characteristics Using DRAM Technology
Yuji.Kihara, Yasushi Nakashima, Takashi Izutsu, Masayuki Nakamoto, Yasuhiro Konishi, Tsutomu Yoshihara
ASSCC2005 Proceedings of Technical Paper 17  20 2005.11
A study of sensevoltage margins in lowvoltageoperating embedded DRAM macros
A Yamazaki, F Morishita, N Watanabe, T Amano, M Haraguchi, H Noda, A Hachisuka, K Dosaka, K Arimoto, S Wake, H Ozaki, T Yoshihara
IEICE TRANSACTIONS ON ELECTRONICS E88C ( 10 ) 2020  2027 2005.10
MRAMメモリセルを用いたデュアルポートメモリの検討
松井, 岡村, 大石, 吉原
電気関係学会九州支部連合大会 162 2005.09
低電圧動作に適したレベルシフト型シリーズレギュレータの検討
木村, 岡村, 森下, 吉原
電気関係学会九州支部連合大会 599 2005.09
Embedded lowpower dynamic TCAM architecture with transparently scheduled refresh
H Noda, K Inoue, HJ Mattausch, T Koide, K Dosaka, K Arimoto, K Fujishima, K Anami, T Yoshihara
IEICE TRANSACTIONS ON ELECTRONICS E88C ( 4 ) 622  629 2005.04
メモリ高速インターフェースのスルーレート制御手法
韓峰, 小西康弘, 大石司, 松井悠亮, 吉原 務
電子情報通信学会全国大会 2005.03
Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memory
Kiyohiro FURUTANI, Takeshi Hamamoto, Takeo,MIKI, MasayaNAKANO, Takashi KONO, Shigeru KIKUDA, Yasuhiro KONISHI Tsutomu, YOSHIHARA
IEICE TRANS.on Electronics E88 ( 2 ) 255  263 2005.02
A 312MHz 16Mb randomcycle embedded DRAM macro with a powerdown data retention mode for mobile applications
F Morishita, Hayashi, I, H Matsuoka, K Takahashi, K Shigeta, T Gyohten, M Nliro, H Noda, M Okamoto, A Hachisuka, A Amo, H Shinkawata, T Kasaoka, K Dosaka, K Arimoto, K Fujishima, K Anami, T Yoshihara
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 40 ( 1 ) 204  212 2005.01
A costefficient highperformance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture
H Noda, K Inoue, M Kuroiwa, F Igaue, K Yamamoto, HJ Mattausch, T Koide, A Amo, A Hachisuka, S Soeda, Hayashi, I, F Morishita, K Dosaka, K Arimoto, K Fujishimia, K Anami, T Yoshihara
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 40 ( 1 ) 245  253 2005.01
MRAMに適したセルフリファレンス型センス手法の検討
米田健司, 大石司, 吉原務
電気関係学会九州支部連合大会 310 2004.09
A 667Mb/s operating digital DLL architecture for 512Mb DDR SDRAM
T Hamamoto, K Furutani, T Kubo, S Kawasaki, H Iga, T Kono, Y Konishi, T Yoshihara
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 39 ( 1 ) 194  206 2004.01
Evaluation of a Microcontroller in BodyTied SOI Technology
Y.Nunomura, H.Sato, N.Itoh, K.Nii, K.Yoshida, C.Nakanishi, H.Ito, J.Nakanishi, H.Takata, Y.Nakase, H.Makino, A. Yamada, T.Arakawa, T.Yoshihara, S.Iwade
Cool Chips IV,2003 2003.04
A 600MHz 54x54bit multiplier with rectangularstyled Wallace tree
N Itoh, Y Naemura, H Makino, Y Nakase, T Yoshihara, Y Horiba
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 36 ( 2 ) 249  257 2001.02
Design methodology of embedded DRAM with virtualsocket architecture
T Yamauchi, M Kinoshita, T Amano, K Dosaka, K Arimoto, H Ozaki, M Yamada, T Yoshihara
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 36 ( 1 ) 46  54 2001.01
Residual Gas Measurements in Plasma Display Panels
Sawada T, Kawarazaki H, Yoshihara T, Hosogane A, Ohba A, Terada Y, Ajika N, Kunori Y, Yuzuriha K, Hatanaka M, Miyoshi H, Yoshihara T, Uji T, Matsuo A, Taniguchi Y, Kiguchi Y
Proceedings of 7th International Display Workshops 2000.11
A 0.18mu m 256mb DDRSDRAM with lowcost postmold tuning method for DLL replica
S Kuge, T Kato, K Furutani, S Kikuda, K Mitsui, T Hamamoto, J Setogawa, K Hamade, Y Komiya, S Kawasaki, T Kono, T Amano, T Kubo, M Haraguchi, Y Nakaoka, M Akiyama, Y Konishi, H Ozaki, T Yoshihara
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 35 ( 11 ) 1680  1689 2000.11
Dynamic Floating Body Control SOI CMOS for Power Managed Multimedia ULSIs
F.Morishita, K.Arimoto, K.Fujishima, Tsutomu Yoshihara, Hideyuki Ozaki
IEEE Transactions on Electron Devices 84C ( 2 ) 253  258 2000.11
A prechargedcapacitorassisted sensing (PCAS) scheme with novel level controllers for lowpower DRAM's
T Kono, T Hamamoto, K Mitsui, Y Konishi, T Yoshihara, H Ozaki
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 35 ( 8 ) 1179  1185 2000.08
Highperformance embedded SOI DRAM architecture for the lowpower supply
T Yamauchi, F Morisita, S Maeda, K Arimoto, K Fujishima, H Ozaki, T Yoshihara
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 35 ( 8 ) 1169  1178 2000.08
A 3.6Gb/s 340mW 16 : 1 pipelined multiplexer using 0.18 mu m SOICMOS technology
T Nakura, K Ueda, K Kubo, Y Matsuda, K Mashiko, T Yoshihara
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 35 ( 5 ) 751  756 2000.05
A 3.3VONLY 16 MB DINOR FLASH MEMORY
S KOBAYASHI, M MIHARA, Y MIYAWAKI, M ISHII, T FUTATSUYA, A HOSOGANE, A OHBA, Y TERADA, N AJIKA, Y KUNORI, K YUZURIHA, M HATANAKA, H MIYOSHI, T YOSHIHARA, Y UJI, A MATSUO, Y TANIGUCHI, Y KIGUCHI
1995 IEEE INTERNATIONAL SOLIDSTATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS 38 ( 38 ) 122  123 1995
AN SOIDRAM WITH WIDE OPERATING VOLTAGE RANGE BY CMOS/SIMOX TECHNOLOGY
K SUMA, T TSURUDA, H HIDAKA, T EIMORI, T OASHI, Y YAMAGUCHI, T IWAMATSU, M HIROSE, F MORISHITA, K ARIMOTO, K FUJISHIMA, Y INOUE, T NISHIMURA, T YOSHIHARA
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 29 ( 11 ) 1323  1329 1994.11
AN EXPERIMENTAL 256MB DRAM WITH BOOSTED SENSEGROUND SCHEME
M ASAKURA, T OOISHI, M TSUKUDE, S TOMISHIMA, T EIMORI, H HIDAKA, Y OHNO, K ARIMOTO, K FUJISHIMA, T NISHIMURA, T YOSHIHARA
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 29 ( 11 ) 1303  1309 1994.11
MEMORY ARRAY ARCHITECTURE AND DECODING SCHEME FOR 3V ONLY SECTOR ERASABLE DINOR FLASH MEMORY
S KOBAYASHI, H NAKAI, Y KUNORI, T NAKAYAMA, Y MIYAWAKI, Y TERADA, H ONODA, N AJIKA, M HATANAKA, H MIYOSHI, T YOSHIHARA
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 29 ( 4 ) 454  460 1994.04
ROWREDUNDANCY SCHEME FOR HIGHDENSITY FLASH MEMORY
M MIHARA, T NAKAYAMA, M OHKAWA, S KAWAI, Y MIYAWAKI, Y TERADA, M OHI, H ONODA, N AJIKA, M HATANAKA, H MIYOSHI, T YOSHIHARA
1994 IEEE INTERNATIONAL SOLIDSTATE CIRCUITS CONFERENCE  DIGEST OF TECHNICAL PAPERS 37 ( 37 ) 150  151 1994
AN OVERERASURE DETECTION TECHNIQUE FOR TIGHTENING 5TH DISTRIBUTION FOR LOWVOLTAGE OPERATION NOR TYPE FLASH MEMORY
Y MIYAWAKI, T NAKAYAMA, M MIHARA, S KAWAI, M OHKAWA, N AJIKA, M HATANAKA, Y TERADA, T YOSHIHARA
1994 SYMPOSIUM ON VLSI CIRCUITS 63  64 1994
AN SOIDRAM WITH WIDE OPERATING VOLTAGE RANGE BY CMOS/SIMOX TECHNOLOGY
K SUMA, T TSURUDA, H HIDAKA, T EIMORI, T OASHI, Y YAMAGUCHI, T IWAMATSU, M HIROSE, K FUJISHIMA, Y INOUE, T NISHIMURA, T YOSHIHARA
1994 IEEE INTERNATIONAL SOLIDSTATE CIRCUITS CONFERENCE  DIGEST OF TECHNICAL PAPERS 37 ( 37 ) 138  139 1994
A 34NS 256MB DRAM WITH BOOSTED SENSEGROUND SCHEME
M ASAKURA, T OHISHI, M TSUKUDE, S TOMISHIMA, H HIDAKA, K ARIMOTO, K FUJISHIMA, T EIMORI, Y OHNO, T NISHIMURA, M YASUNAGA, T KONDOH, S SATOH, T YOSHIHARA, K DEMIZU
1994 IEEE INTERNATIONAL SOLIDSTATE CIRCUITS CONFERENCE  DIGEST OF TECHNICAL PAPERS 37 ( 37 ) 140  141 1994
MEMORY ARRAY ARCHITECTURE AND DECODING SCHEME FOR 3V ONLY SECTOR ERASABLE DINOR FLASH MEMORY
S KOBAYASHI, H NAKAI, Y KUNORI, T NAKAYAMA, Y MIYAWAKI, Y TERADA, H ONODA, N AJIKA, M HATANAKA, H MIYOSHI, T YOSHIHARA
1993 SYMPOSIUM ON VLSI CIRCUITS 97  98 1993
A 100MHZ 4MB CACHE DRAM WITH FAST COPYBACK SCHEME
K DOSAKA, Y KONISHI, K HAYANO, K HIMUKASHI, A YAMAZAKI, H IWAMOTO, M KUMANOYA, H HAMANO, T YOSHIHARA
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 27 ( 11 ) 1534  1539 1992.11
ULSI DRAM技術
サイエンスフォーラム社 1992.06
A new decoding scheme and erase sequence for 5V only sector erasable flash memory
Nakayama T, Kobayashi S, Miyawaki Y, Futastuya T, Terada Y, Ajika N, Yoshihara T
IEEE Symposium on VLSI Circuits 22  23 1992.05
A New Erasing and Row Decoding Scheme for Low Supply Voltage Operation 16Mb/64Mb Flash Memories
Miyawaki Y, Nakayama T, Kobayashi S, Ajika N, Ohi M, Terada Y, Arima H, Yoshihara T
IEEE Journal of SolidState Circuits 27 ( 4 ) 583  588 1992.04
A 100 MHz 4Mb Cache DRAM with Fast CopyBack Scheme
Dosaka K, Konishi Y, Hayano K, Yamazaki A, Kumanoya M, Hamano H, Yoshihara T
IEEE International Solid State Circuits Conference ( 35 ) 148  149 1992.02
A 60NS 16MB FLASH EEPROM WITH PROGRAM AND ERASE SEQUENCE CONTROLLER
T NAKAYAMA, S KOBAYASHI, Y MIYAWAKI, Y TERADA, N AJIKA, M OHI, H ARIMA, T MATSUKAWA, T YOSHIHARA, K SUZUKI
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 26 ( 11 ) 1600  1605 1991.11
A 45NS 64MB DRAM WITH A MERGED MATCHLINE TEST ARCHITECTURE
S MORI, H MIYAMOTO, Y MOROOKA, S KIKUDA, M SUWA, M KINOSHITA, A HACHISUKA, H ARIMA, M YAMADA, T YOSHIHARA, S KAYANO
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 26 ( 11 ) 1486  1492 1991.11
A new erasing and row decoding scheme for low supply voltage operation16 Mb/64 Mb flash EEPROM
Miyawaki Y, Nakayama T, Kobayashi K, Ajika N, Ohi M, Terada Y, Arima H, Yoshihara T
IEEE Symposium on VLSI Circuits 85  86 1991.05
A 60ns 16Mb Flash EEPROM with Program and Erase Sequence Controller
Nakayama T, Kobayashi S, Miyawaki Y, Terada Y, Ajika N, Ohi M, Arima H, Matsukawa T, Yoshihara T
IEEE International Solid State Circuits Conference ( 34 ) 260  261 1991.02
A 34ns 16 MbDRAM with controllable voltage down converter
Arimoto K, Hidaka H, Hayashikoshi M, Asakura M, Fujishima K, Yoshihara T
IEEE European Solid State Circuits Conference 21  24 1990.09
High speed page mode sensing scheme for EPROM's and flash EPROM's using divided bit line architecture
Terada Y, Nakayama T, Kobayashi K, Hayashikoshi M, Kobayashi S, Miyawaki Y, Ajika N, Arima H, Yoshihara T
IEEE Symposium on VLSI Circuits 97  98 1990.05
A 38ns 4Mb DRAM with a battery backup(BBU) mode
Konishi Y, Dosaka K, Komatsu T, Inoue Y, Kumanoya M, Tobita Y, Genjo H, Nagatomo M, Yoshihara T
IEEE International Solid State Circuits Conference ( 33 ) 230  231 1990.02
A HighSpeed Parallel Sensing Architecture for MultiMegabit Flash E<sup>2</sup> PROM’s
Kazuo Kobayashi, Takeshi Nakayama, Yoshikazu Miyawaki, Masanori Hayashikoshi, Yasushi Terada, Tsutomu Yoshihara
IEEE Journal of SolidState Circuits 25 ( 1 ) 79  83 1990
A 38ns 4Mb DRAM with a BatteryBackup (BBU) Mode
Yasuhiro Konishi, Katsumi Dosaka, Takahiro Komatsu, Yoshinori Inoue, Masaki Kumanoya, Youichi Tobita, Hideki Genjyo, Masao Nagatomo, Tsutomu Yoshihara
IEEE Journal of SolidState Circuits 25 ( 5 ) 1112  1117 1990
半導体実装技術ハンドブック「α線対策」
サイエンスフォーラム社 1986.09
ULSI DRAM技術
サイエンスフォーラム社 1992.06
Study of basic characteristics and application of Nonvolatile Memory
Japan Society for the Promotion of Science GrantsinAid for Scientific Research
Project Year :
YOSHIHARA Tsutomu
文部科学省知的クラスタ（ユビキタスネットワーク用システムLSIの開発）