Updated on 2024/12/22

写真a

 
OHTSUKI, Tatsuo
 
Affiliation
Faculty of Science and Engineering
Job title
Professor Emeritus
Degree
Doctor of Engineering ( Waseda University )
Homepage URL
http://www.ohtsuki.comm.waseda.ac.jp/index.html

Research Experience

  • 1985
    -
    　

    - カリフォルニア大学バークレー校 客員教授

  • 1985
    -
    　

    - Visiting Professor, Univ. of Calif., Berkeley

  • 1980
    -
    　

    - 早稲田大学理工学部 教授

  • 1980
    -
    　

    - Professor, School of Science and Engineering, Waseda University

  • 1965
    -
    1980

    NEC Corporation

Education Background

  • 　
    -
    1965

    Waseda University  

  • 　
    -
    1965

    Waseda University   Graduate School, Divison of Science and Engineering   Electrical Engineering  

  • 　
    -
    1963

    Waseda University   School of Science and Engineering  

  • 　
    -
    1963

    Waseda University   Faculty of Science and Engineering   Dept. of Electrical Communication Engineering  

Committee Memberships

  • 2005
    -
    　

    NEDO 電子・情報技術戦略調査委員会 技術委員 2005 －

  • 2002
    -
    2004

    NEDO 技術評価委員会 技術委員 2002 － 2004

  • 2001
    -
    　

    電子情報通信学会 フェローノミネーション委員会 委員 2001

  • 1998
    -
    2001

    電子情報通信学会 功績賞・業績賞委員会 委員 1998 － 2001

  • 2000
    -
    　

    東京工業大学 工学部電気系 外部評価委員 2000

  • 2000
    -
    　

    文部省 大学設置・学校法人審議会（大学設置分科会） 専門委員 2000

  • 1995
    -
    1997

    プリント回路学会 監事 1995 － 1997

  • 1995
    -
    1996

    東京工業大学 工学部電気系 外部評価委員 1995 － 1996

  • 1995
    -
    　

    第1回 Asia and S. Pacific Design Automation Conference General Chair 1995

  • 1992
    -
    1995

    IFIP TC-10 WG10.5  Vice-Chairman

  • 1992
    -
    1995

    IFIP TC-10 WG10.5  Vice-Chairman

  • 1991
    -
    1994

    IEEE  VP-Region 10,CAS Society

  • 1991
    -
    1994

    IEEE CAS Society VP-Region 10 1991 － 1994

  • 1991
    -
    1994

    IEEE  VP-Region 10,CAS Society

  • 1991
    -
    1993

    電子情報通信学会 調査理事 1991 － 1993

  • 1991
    -
    1992

    日本工学会  監事

  • 1991
    -
    1992

    電子情報通信学会  理事

  • 1991
    -
    1992

    電子情報通信学会 回路とシステム専門委員会 委員長 1991 － 1992

  • 1991
    -
    1992

    日本工学会 監事 1991 － 1992

  • 1989
    -
    1992

    IFIP TC-10 WG10.5 Vice-Chairman 1989 － 1992

  • 1981
    -
    1992

    日本電信電話（株）電気通信技術委員会 特別専門委員 1981 － 1992

  • 1988
    -
    1990

    プリント回路学会（現 エレクトロニクス実装学会）  理事

  • 1988
    -
    1990

    IEEE CAS Society AdCom member 1988 － 1990

  • 1988
    -
    1990

    プリント回路学会 理事 1988 － 1990

  • 1988
    -
    1989

    電子情報通信学会 VLSI設計技術専門委員会 委員長 1988 － 1989

  • 1987
    -
    1989

    IEEE International Symposium on CAD アジア代表 1987 － 1989

  • 1987
    -
    1988

    電子情報通信学会 編集理事 1987 － 1988

  • 1987
    -
    　

    IFIP Workshop on CAD Engines Chairman 1987

  • 1986
    -
    1987

    電子情報通信学会  理事

  • 1985
    -
    1987

    IEEE 東京支部CASソサィアティ Chairman 1985 － 1987

  • 1985
    -
    1987

    電子通信学会ニューネットワーク論研究会 委員長 1985 － 1987

  • 1984
    -
    1985

    （財）新機能素子研究開発協会 三次元回路素子技術動向調査委員会 委員長 1984 － 1985

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Professional Memberships

  • 　
    　
    　

    応用数理学会

  • 　
    　
    　

    ACM

  • 　
    　
    　

    IFIP TC-10 WG10.5

  • 　
    　
    　

    日本工学会

  • 　
    　
    　

    プリント回路学会（現 エレクトロニクス実装学会）

  • 　
    　
    　

    電気学会

  • 　
    　
    　

    情報処理学会

  • 　
    　
    　

    IEEE

  • 　
    　
    　

    電子情報通信学会

  • 　
    　
    　

    ACM

  • 　
    　
    　

    IFIP TC-10 WG10.5

  • 　
    　
    　

    IEEE

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Research Areas

  • Control and system engineering / Communication and network engineering

Research Interests

  • 情報通信工学

  • Information and Communication Engineering

Awards

  • Golden Jubilee Medal, IEEE CAS Society

    2000  

  • 3rd Millennium Medal, IEEE

    2000  

  • 電子情報通信学会 フェロー

    2000  

  • Golden Jubilee Medal, IEEE CAS Society

    2000  

  • 3rd Millennium Medal, IEEE

    2000  

  • 電子情報通信学会 フェロ-

    2000  

  • Meritorious Senvice Award,IEEE CAS Society

    1995  

  • Meritorious Senvice Award,IEEE CAS Society

    1995  

  • 電子通信学会論文賞

    1986  

  • IEEE Fellow

    1984  

  • IEEE Fellow

    1984  

  • Gullmin-Cauer Prize Paper Award,IEEE CAS Society

    1974  

  • Gullmin-Cauer Prize Paper Award,IEEE CAS Society

    1974  

  • 電子情報通信学会 業績賞

  • 1995

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Books and Other Publications

  • 電気回路論[2版改訂]

    電気学会  2002

  • 回路工学

    昭晃堂  1998

  • 過渡回路解析

    電気学会大学講座  1989

  • Lalyout Design and Verification

    North-Holland  1986

  • Advances in CAD for VLSI

    North-Holland  1985

  • VLSIの設計I

    岩波講座マイクロエレクトロニクス  1985

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Works

  • DSMテクノロジーを想定したEmbedded Processor のハードウェア/ソフトウェア協調設計環境

    2004
    -
    2006

  • 歩行者を対象とする地図情報システム

    2000
    -
    2003

  • 移動パーソナルエリアネットワークにおける1対多, 多対多マルチメディア通信方式

    2000
    -
    　

  • ハードウェア/ソフトウェア協調設計に関する研究

    2000
    -
    　

  • A Survey on Recent Advances in VLSI Layout

    1985
    -
    　

  • LSIの配置配線設計に関する基礎研究

    1981
    -
    　

  • 電子回路の数値シミュレーションに関する基礎研究

    1979
    -
    　

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Research Projects

  • 地図情報処理

  • 移動体通信網のプロトコル

  • 画像処理のハードウェア／ソフトウェア アルゴリスム

  • システムLSI設計手法

  • モバイルネットワーク

  • ディジタル信号処理アーキテクチャ

  • VLSIシステムの設計手法

  • Mobile communication network protocol

  • Hardware/software algorithms for image processing

  • System LSI Design Methodology

  • mobile networks

  • Digital Signal Processing Architecture

  • VLSI System Design Methodology

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Misc

  • Scalable Unified Dual-Radix Architecture for Montgomery Multiplication in GF(P) and GF(2n)

    Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    Proc. of the ASP-DAC 2008     697 - 702  2008

  • GECOM: Test Data Compression Combined with All Unknown Response Masking

    Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    Proc. of the ASP-DAC 2008     577 - 582  2008

  • LAMR : アドホックネットワークにおける負荷分散を考慮したマルチパスルーティング

    清水悠司, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会 NS研究会     51 - 56  2008

  • MAPドメイン間移動のためのハンドオフ時間とパケットロスの削減手法

    田中敦樹, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会 NS研究会     41 - 46  2008

  • エニーキャストにおけるルータの負荷に基づく経路選択手法

    横田雅之, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会 NS研究会     13 - 18  2008

  • アプリケーションプロセッサのカーネル自動生成手法

    日浦敏宏, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会 VLD研究会     83 - 88  2008

  • レジスタ分散型アーキテクチャを対象とした高位合成のためのマルチプレクサ削減手法

    遠藤哲弥, 大智輝, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会 VLD研究会     7 - 12  2008

  • アプリケーションプロセッサのL1データキャッシュ最適化手法

    東條信明, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会 VLD研究会   Vol.107   77 - 82  2008

  • 歩行者向けデフォルメ地図生成ハードウェアエンジンの設計

    荒幡明, 奈良竜太, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会 VLD研究会   Vol.107 ( No.336 ) 61 - 66  2008

  • 列処理演算法に着目したマルチレート対応イレギュラーLDPC符号復号器

    今井優太, 清水一範, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会RECONF研究会   Vol.107 ( No.342 ) 19 - 24  2008

  • AESにおける合成体SubBytes向けパワーマスキング乗算回路の設計

    川畑伸幸, 奈良竜太, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会 VLD研究会   Vol.107 ( No.335 ) 37 - 42  2008

  • SIMD プロセッサコアの面積/遅延見積もり手法

    山崎大輔, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

    情報処理学会 組込みシステム研究会 組込みシステムシンポジウム2007     233 - 240  2008

  • 応用指向動的再構成なネットワークプロセッサ設計手法

    大田元則, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

    情報処理学会 組込みシステム研究会 組込みシステムシンポジウム2007     141 - 150  2008

  • Scalable Unified Dual-Radix Architecture for Montgomery Multiplication in GF(P) and GF(2n)

    Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    Proc. of the ASP-DAC 2008     697 - 702  2008

  • GECOM: Test Data Compression Combined with All Unknown Response Masking

    Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    Proc. of the ASP-DAC 2008     577 - 582  2008

  • Floorplan-aware High-Level Synthesis for Distributed/Shared-Register Architectures

    Akira Ohchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    Proc. of the IEICE ITC-CSCC 2007     1049 - 1050  2007

  • An Area-Efficient GF(2m) MSD Multiplier Based on an MSB Multiplier for Elliptic Curve LSI

    Ryuta Nara, Kazunori Shimizu, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    Proc. of the IEICE ITC-CSCC 2007     36 - 37  2007

  • 楕円曲線暗号用SIMD型MSD乗算器の設計

    奈良竜太, 清水一範, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

    情報処理学会 組込みシステム研究会 組込みシステムシンポジウム2007     90 - 99  2007

  • 移動体を対象としたアプリケーションとデータサイズによる階層型Network Mobilityの負荷分散方式

    月木英治, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会ITS研究会   Vol.107 ( No.216 ) 21 - 26  2007

  • 歩行者ナビゲーションにおける携帯電話カメラ機能とランドマークを利用した位置補正手法

    本田聖人, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会ITS研究会   Vol.107 ( No.216 ) 33 - 38  2007

  • 歩行者ナビゲーションにおけるGPS誤差補正のための道路標識による現在位置測位手法

    大平英貴, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会ITS研究会   Vol.107 ( No.216 ) 27 - 32  2007

  • 進路方向によって異なる混雑度を考慮した旅行時間算出手法

    大高宏介, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会ITS研究会   Vol.107 ( No.215 ) 15 - 20  2007

  • GF（2m）上のSIMD型MSD乗算器を用いた楕円曲線暗号回路の実装

    奈良竜太, 清水一範, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

    情報処理学会 システムLSI設計技術研究会 情報処理学会DAシンポジウム2007     221 - 226  2007

  • HW/SW協調合成におけるASIPの面積/遅延見積もり手法

    山崎大輔, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

    情報処理学会 システムLSI設計技術研究会 情報処理学会DAシンポジウム2007     31 - 36  2007

  • アプリケーションに特化した動的再構成可能なネットワークプロセッサ

    大田元則, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

    情報処理学会 システムLSI設計技術研究会 情報処理学会DAシンポジウム2007     37 - 42  2007

  • GF(2n)及びGF(P)におけるスケーラブル双基数ユニファイド型モンゴメリ乗算器

    谷村和幸, 奈良竜太, 小原俊逸, 史又華, 戸川望, 柳沢政生, 大附辰夫

    電子情報通信学会VLD研究会   Vol.107 ( No.105 ) 43 - 48  2007

  • 再構成型プロセッサFE-GAへのフィルタマッピングとその自動化手法

    本間雅行, 戸川望, 柳澤政生, 大附辰夫, 佐藤真琴

    電子情報通信学会VLD研究会   Vol.107 ( No.100 ) 67 - 72  2007

  • An SIMD MSD Multiplier based on variable GF(2^m) for Elliptic Curve Cryptosystems

    NARA Ryuta, SHIMIZU Kazunori, KOHARA Shunitsu, TOGAWA Nozomu, YANAGISAWA Masao, OHTSUKI Tatsuo

    IEICE technical report   Vol.107 ( No.32 ) 25 - 29  2007

    　View Summary

    Originally elliptic curve cryptosystem (ECC) hardware are often required to operate variable key length. Digit-serial multipliers for ECC enable the hardware to accelerale the finite field operation. However, the lack of flexibility of digit-serial multipliers is major challenge for building the ecc hardware which operates variable key length. In this paper, we propose a SIMD MSD multiplier based on variable GF(2^m) for ECC. Adjusting the parallellizm of the SIMD MSD multiplier according to the field length enables us to accelarate the ecc scalar multiplication throughput. The proposed multiplier operates 5 types of field length which are recommended by NIST, where 2 multiplications can be operated simultaneously for the small field length. Implementation results show that the proposed multiplier reduces the hardware area by up to 1/3 compared to the same throughput. while achieving up to about 2 times multiplication throughput compared to the conventional multipliers for the variable field length.

    CiNii

  • GF(2n)上のMSB乗算器をベースにした楕円曲線暗号LSI向けMSD乗算器の実装

    奈良竜太, 小原俊逸, 清水一範, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会 第20回回路とシステム軽井沢ワークショップ     355 - 360  2007

  • 携帯機器向けMPEG-A Photo Playerのメタデータ生成システムのハードウェア化に関する一考察

    元橋雅人, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   VLD2006  2007

  • アプリケーションプロセッサ向けデータキャッシュ構成最適化システムとその評価

    堀内一央, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   VLD2006  2007

  • SIMD型プロセッサコア最適化設計のための多重ループに対応したSIMD命令合成手法

    中島裕貴, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   VLD2006  2007

  • SIMD型プロセッサコアを対象としたハードウェア/ソフトウェア分割フレームワーク

    大東真崇, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   VLD2006  2007

  • SIMD型プロセッサコア設計におけるプロセッシングユニット最適化手法

    繁田裕之, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   VLD2006  2007

  • XMLをベースとしたCDFGマニピュレーションフレームワーク: CoDaMa

    小原俊逸, 史又華, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   VLD2006-97  2007

  • 楕円曲線暗号向けGF(2m)上のDigit-Serial乗算器の設計

    奈良竜太, 小原俊逸, 清水一範, 戸川望, 池永剛, 柳澤政生, 後藤敏, 大附辰夫

    電子情報通信学会技術研究報告   VLD2006-89  2007

  • Floorplan-aware High-Level Synthesis for Distributed/Shared-Register Architectures

    Akira Ohchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    Proc. of the IEICE ITC-CSCC 2007     1049 - 1050  2007

  • An Area-Efficient GF(2m) MSD Multiplier Based on an MSB Multiplier for Elliptic Curve LSI

    Ryuta Nara, Kazunori Shimizu, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    Proc. of the IEICE ITC-CSCC 2007     36 - 37  2007

  • Selective low-care coding: A means for test data compression in circuits with multiple scan chains

    YH Shi, N Togawa, S Kimura, M Yanagisawa, T Ohtsuki

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E89A ( 4 ) 996 - 1004  2006.04

    　View Summary

    This paper presents a test input data compression technique, Selective Low-Care Coding (SLC), which can be used to significantly reduce input test data volume as well as the external test channel requirement for multiscan-based designs. In the proposed SLC scheme, we explored the linear dependencies of the internal scan chains, and instead of encoding all the specified bits in test cubes, only a smaller amount of specified bits are selected for encoding, thus greater compression can be expected. Experiments on the larger benchmark circuits show drastic reduction in test data volume with corresponding savings on test application time can be indeed achieved even for the well-compacted test set.

    DOI

  • Selective low-care coding: A means for test data compression in circuits with multiple scan chains

    YH Shi, N Togawa, S Kimura, M Yanagisawa, T Ohtsuki

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E89A ( 4 ) 996 - 1004  2006.04

    　View Summary

    This paper presents a test input data compression technique, Selective Low-Care Coding (SLC), which can be used to significantly reduce input test data volume as well as the external test channel requirement for multiscan-based designs. In the proposed SLC scheme, we explored the linear dependencies of the internal scan chains, and instead of encoding all the specified bits in test cubes, only a smaller amount of specified bits are selected for encoding, thus greater compression can be expected. Experiments on the larger benchmark circuits show drastic reduction in test data volume with corresponding savings on test application time can be indeed achieved even for the well-compacted test set.

    DOI CiNii

  • A fast elliptic curve cryptosystem LSI embedding word-based Montgomery multiplier

    J Uchida, N Togawa, M Yanagisawa, T Ohtsuki

    IEICE TRANSACTIONS ON ELECTRONICS   E89C ( 3 ) 243 - 249  2006.03

    　View Summary

    Elliptic curve cryptosystems are expected to be a next standard of public-key cryptosystems. A security level of elliptic curve cryptosystems depends on a difficulty of a discrete logarithm problem on elliptic curves. The security level of a elliptic curve cryptosystem which has a public-key of 160-bit is equivalent to that of a RSA system which has a public-key of 1024-bit. We propose an elliptic curve cryptosystem LSI architecture embedding word-based Montgomery multipliers. A Montgomery multiplication is an efficient method for a finite field multiplication. We can design a scalable architecture for an elliptic curve cryptosystem by selecting structure of word-based Montgomery multipliers. Experimental results demonstrate effectiveness and efficiency of the proposed architecture. In the hardware evaluation using 0.18 mu m CMOS library, the highspeed design using 126 Kgates with 20 x 8-bit multipliers achieved operation times of 3.6 ms for a 160-bit point multiplication.

    DOI

  • A parallel LSI architecture for LDPC decoder improving message-passing schedule

    Proc. IEEE International Symposium on Circuits and Systems 2006 (ISCAS 2006)    2006

  • A pipelined functional unit generation method in HW/SW cosynthesis for SIMD processor cores

    Proc. Synthesis and System Integration of Mixed Technologies (SASIMI 2006)    2006

  • A fast elliptic curve cryptosystem LSI embedding word-based montgomery multiplier

    Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    IEICE Transactions on Electronics   E89-C ( 3 ) 243 - 249  2006

    　View Summary

    Elliptic curve cryptosystems are expected to be a next standard of public-key cryptosystems. A security level of elliptic curve cryptosystems depends on a difficulty of a discrete logarithm problem on elliptic curves. The security level of a elliptic curve cryptosystem which has a public-key of 160-bit is equivalent to that of a RSA system which has a public-key of 1024-bit. We propose an elliptic curve cryptosystem LSI architecture embedding word-based Montgomery multipliers. A Montgomery multiplication is an efficient method for a finite field multiplication. We can design a scalable architecture for an elliptic curve cryptosystem by selecting structure of word-based Montgomery multipliers. Experimental results demonstrate effectiveness and efficiency of the proposed architecture. In the hardware evaluation using 0.18 μ m CMOS library, the high-speed design using 126 Kgates with 20 × 8-bit multipliers achieved operation times of 3.6 ms for a 160-bit point multiplication. Copyright © 2006 The Institute of Electronics, Information and Communication Engineers.

    DOI

  • FCSCAN: An efficient multiscan-based data compression technique for test cost reduction

    Proc. IEEE Asia and South Pacific Design Automation Conference 2006 (ASP-DAC 2006)     653 - 658  2006

  • An interface-circuit synthesizer with configurable processor core in IP-based SOC design

    Proc. IEEE Asia and South Pacific Design Automation Conference 2006 (ASP-DAC 2006)     594 - 599  2006

  • MPEG-4形状符号化/復号化に対応したDSP組み込み向け専用演算器の設計

    古宇多朋史, 小原俊逸, 史又華, 戸川望, 柳澤政生, 大附辰夫

    情報処理学会組込みシステムシンポジウム2006論文集(ESS2006)    2006

  • 連携処理を考慮したネットワークプロセッサ合成システム

    中山敬史, 戸川望, 柳澤政生, 大附辰夫

    情報処理学会DAシンポジウム2006論文集    2006

  • レジスタ分散・共有併用型アーキテクチャを対象としたフロアプランを考慮した高位合成手法

    大智輝, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

    情報処理学会DAシンポジウム2006論文集    2006

  • SIMD型プロセッサコアの自動合成のためのパイプライン演算ユニット生成手法

    栗原輝, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    情報処理学会論文誌   vol. 47 ( no. 6 )  2006

  • アプリケーションプロセッサのフォワーディングユニット最適化手法

    日浦敏俊, 小原俊逸, 史又華, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   ( VLD2006-80 )  2006

  • 動的再構成可能なマルチレート対応LDPC符号復号器の実装

    今井優太, 清水一範, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   RECONF2006-43  2006

  • 歩行者ナビゲーションにおける微小画面での視認性とユーザの迷いにくさを考慮した略地図生成手法

    二宮直也, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   ITS2006-34  2006

  • 屋内用歩行者ナビゲーションにおける歩行者の嗜好を反映させる経路探索手法

    荒井亨, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   ITS2006-33  2006

  • 屋内向け歩行者ナビゲーションにおけるユーザの嗜好性と混雑状況を考慮した目的地決定手法

    小林和馬, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   ITS2006-32  2006

  • 車車間・路車間通信技術を用いた車線別の渋滞情報の検出手法

    大高宏介, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   ITS2006-18  2006

  • H.264符号化向けDSPにおける動き予測演算器の設計

    高橋豊和, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   ( VLD2006 )  2006

  • アプリケーションプロセッサの面積/遅延見積もり手法

    山崎大輔, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   CAS2006-1 ( VLD2006-14, SIP2006-24 )  2006

  • A pipelined functional unit generation method in HW/SW cosynthesis for SIMD processor cores

    小原俊逸, 栗原輝, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    Proc. Synthesis and System Integration of Mixed Technologies (SASIMI 2006)    2006

  • アプリケーションプロセッサのデータキャッシュ構成最適化手法

    堀内一央, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会第19回回路とシステム軽井沢ワークショップ論文集     583 - 588  2006

  • 歩行者向け地図情報配信システムにおける道路交通標識を用いた位置特定手法

    中口智史, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   ( ITS2005-114 )  2006

  • SIMD型プロセッサコアの自動合成におけるパイプライン構成最適化手法

    栗原輝, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   ( VLD2005-115, ICD2005-232 )  2006

  • 動的フローに対応したネットワークプロセッサの改良とその評価

    田淵英孝, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   ( VLD2005-112, ICD2005-229 )  2006

  • 設計ナビゲーション機構を有するシステムLSI設計のためのHW/SW分割システム

    小島洋平, 戸川望, 橘昌良, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   ( VLD2005-111, ICD2005-228 )  2006

  • 高速移動体のためのハンドオフメッセージ数を最小化した高速ハンドオフ手法

    伊藤光司, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   ( IN2005-222 )  2006

  • A fast elliptic curve cryptosystem LSI embedding word-based montgomery multiplier

    内田純平, 戸川望, 柳澤政生, 大附辰夫

    IEICE Trans. on Electronics, vol. E89-C   E89-C ( 3 ) 243 - 249  2006

    DOI

  • FCSCAN: An Efficient Multiscan-based Data Compression Technique for Test Cost Reduction

    史又華, 戸川望, 木村晋二, 柳澤政生, 大附辰夫

    第11回アジア南太平洋設計自動化会議 (ASP-DAC 2006）     653 - 658  2006

  • An Interface-Circuit Synthesis Method with Configurable Processor Core in IP-Based SoC Design

    小原俊逸, 友野直紀, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    第11回アジア南太平洋設計自動化会議 (ASP-DAC 2006）     594 - 599  2006

  • A parallel LSI architecture for LDPC decoder improving message-passing schedule

    Proc. IEEE International Symposium on Circuits and Systems 2006 (ISCAS 2006)    2006

  • A pipelined functional unit generation method in HW/SW cosynthesis for SIMD processor cores

    Proc. Synthesis and System Integration of Mixed Technologies (SASIMI 2006)    2006

  • FCSCAN: An efficient multiscan-based data compression technique for test cost reduction

    Proc. IEEE Asia and South Pacific Design Automation Conference 2006 (ASP-DAC 2006)     653 - 658  2006

  • An interface-circuit synthesizer with configurable processor core in IP-based SOC design

    Proc. IEEE Asia and South Pacific Design Automation Conference 2006 (ASP-DAC 2006)     594 - 599  2006

  • A SIMD instruction set and functional unit synthesis algorithm with SIMD operation decomposition

    N Togawa, K Tachikake, Y Miyaoka, M Yanagisawa, T Ohtsuki

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS   E88D ( 7 ) 1340 - 1349  2005.07

    　View Summary

    This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algorithm. Given an initial assembly code and a timing constraint, the proposed algorithm synthesizes an area-optimized processor core with optimal SIMD functional units. It also synthesizes a SIMD instruction set. The input initial assembly code is assumed to run on a full-resource SIMD processor (virtual processor) which has all the possible SIMD functional units. In our algorithm, we introduce the SIMD operation decomposition and apply it to the initial assembly code and the full-resource SIMD processor. By gradually reducing SIMD operations or decomposing SIMD operations, we can finally find a processor core with small area under the given timing constraint. The promising experimental results are also shown.

    DOI

  • Sub-operation parallelism optimization in SIMD processor core synthesis

    H Kawazu, J Uchida, Y Miyaoka, N Togawa, M Yanagisawa, T Ohtsuki

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E88A ( 4 ) 876 - 884  2005.04

    　View Summary

    A b-bit SIMD functional unit has n k-bit sub-functional units in itself, where b = k x n. It can execute n-parallel k-bit operations. However, all the b-bit functional units in a processor core do not necessarily execute n-parallel operations. Depending on an application program, some of them just execute n/2-parallel operations or even n/4-parallel operations. This means that we can modify a b-bit SIMD functional unit so that it has n/2 k-bit sub-functional units or n/4 k-bit sub-functional units. The number of k-bit sub-functional units in a SIMD functional unit is called sub-operation parallelism. We incorporate a sub-operation parallelism optimization algorithm into SIMD functional unit optimization. Our proposed algorithm gradually reduces sub-operation parallelism of a SIMD functional unit while the timing constraint of execution time satisfied. Thereby, we can finally find a processor core with small area under the given timing constraint. We expect that we can obtain processor core configurations of smaller area in the same timing constraint rather than a conventional system. The promising experimental results are also shown.

    DOI

  • A SIMD instruction set and functional unit synthesis algorithm with SIMD operation decomposition

    Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki

    IEICE Transactions on Information and Systems   E88-D ( 7 ) 1340 - 1349  2005

    　View Summary

    This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algorithm. Given an initial assembly code and a timing constraint, the proposed algorithm synthesizes an area-optimized processor core with optimal SIMD functional units. It also synthesizes a SIMD instruction set. The input initial assembly code is assumed to run on a full-resource SIMD processor (virtual processor) which has all the possible SIMD functional units. In our algorithm, we introduce the SIMD operation decomposition and apply it to the initial assembly code and the full-resource SIMD processor. By gradually reducing SIMD operations or decomposing SIMD operations, we can finally find a processor core with small area under the given timing constraint. The promising experimental results are also shown. Copyright © 2005 The Institute of Electronics, Information and Communication Engineers.

    DOI

  • Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations

    N Togawa, Y Miyaoka, H Kawazu, M Yanagisawa, J Uchida, T Ohtsuki

    2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS     3499 - 3502  2005

    　View Summary

    In this paper, we propose a sub-operation parallelism optimization algorithm in SIMD) processor synthesis. Given an initial assembly code and timing constraints, our algorithm synthesizes a processor core with sub-operation parallelism optimization for SIMD) functional units. First we consider an initial processor which has sufficient hardware units for executing an initial assembly code. An initial processor core includes the maximum sub-operation parallelism for each SIMD) functional unit. By gradually reducing sub-operation parallelism, we can finally have a processor core with small area meeting a given timing constraints. We show the effectiveness of our proposed algorithm through experimental results.

    DOI

  • A Processor Core Synthesis System in IP-based SoC Design

    Proceedings of the ASP-DAC 2005    2005

  • 重回帰分析により得られた1次式によるインダクタンスを考慮した配線遅延の見積もり

    鈴木康成, マルタディナタ アンワル, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   Vol.105 ( No.442 ) 67 - 72  2005

  • レジスタ分散・共有アーキテクチャを対象としたフロアプラン指向高位合成手法

    大智輝, 戸川望, 柳澤雅夫, 大附辰夫

    電子情報通信学会技術研究報告   VLD2005-66   31 - 36  2005

  • 画像処理向けシステムLSI設計における設計ナビゲーションを考慮したHW/SW分割システム

    小島洋平, 戸川望, 橘昌良, 柳澤政生, 大附辰夫

    DAシンポジウム２００５     19 - 24  2005

  • SIMD型プロセッサの自動合成におけるパイプライン演算ユニット生成手法

    栗原輝, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    DAシンポジウム２００５     25 - 30  2005

  • A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition

    戸川望, 太刀掛宏一, 宮岡祐一郎, 柳澤政生, 大附辰夫

    IEICE TRANS,INF.&SYST   E88-D ( 7 ) 1340 - 1349  2005

    DOI

  • レジスタ分散型アーキテクチャを対象とするフロアプランとタイミング制御を考慮した高位合成手法

    田中真, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    情報処理学会論文誌   Vol.46 ( NO.6 June 2005 ) 1383 - 1394  2005

  • A Selective Care Bits Coding Method for Test Data Compression

    史又華, 戸川望, 木村晋二, 柳澤政生, 大附辰夫

    第18回 回路とシステム 軽井沢ワークショップ     241 - 246  2005

  • IP再利用を考慮したシステムLSI設計におけるインタフェース回路生成システム

    小原俊逸, 友野直紀, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会第18回回路とシステム軽井沢ワークショップ論文集     581 - 586  2005

  • インダクタンスを考慮した配線遅延の近似式による見積もり

    鈴木康成, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    第18回 回路とシステム 軽井沢ワークショップ     1 - 6  2005

  • SIMD型プロセッサコア向けHW/SW協調合成システムにおけるパイプライン演算ユニット生成手法

    栗原輝, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    第18回 回路とシステム 軽井沢ワークショップ     575 - 580  2005

  • ネットワークプロセッサ合成システムの改良とその評価

    升本英行, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   VLD2004   25 - 30  2005

  • 動的フローに適応したネットワークプロセッサ設計とその評価

    細田宗一郎, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   VLD2004   79 - 84  2005

  • A Fast Elliptic Curve Cryptosystem LSI embedding Word-based Montgomery Multiplier

    UCHIDA Jumpei, NARA Ryuta, MIYAOKA Yuichiro, TOGAWA Nozomu, YANAGISAWA Masao, OHTSUKI Tatsuo

    Technical report of IEICE. VLD   VLD2004 ( 708 ) 5 - 10  2005

    　View Summary

    Elliptic curve cryptosystem is hoped for a next standard public-key cryptosystem. Security of Elliptic curve cryptosystem depends on a difficulty of a discrete logarithm problem over elliptic curves. The security of elliptic curve cryptosystem which has a public-key of 160 bits is equivalent to that of RSA cryptosystem which has a public-key of 1024 bits. We propose an elliptic curve cryptosystem LSI architecture embedding word-based Montgomery multiplier. A Montgomery multiplication is an efficient method for modular multiplication. We can design a scalable architecture for an elliptic curve cryptosystem by selecting structure of word-based Montgomery multipliers. Experimental results demonstrate effectiveness and efficiency of the proposed architecture. In the hardware evaluation using 0.18μm CMOS standard cell library, the high-speed design using 126 Kgates with 8 bits multiplier achieved operation times of 3.6ms.

    CiNii

  • 面積制約を考慮したマルチスレッドプロセッサの合成手法

    麻生雄一, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告     31 - 35  2005

  • A processor core synthesis system in IP-based SoC design

    Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2     286 - 291  2005

    　View Summary

    This paper proposes a new design methodology for SoCs reusing hardware IPs. In our approach, after system-level HW/SW partitioning, we use IPs for hardware parts, but synthesize a new processor core instead of reusing a processor core IP. System performs efficient parallel execution of hardware and software by taking account of a response time of hardware IP obtained by the proposed calculation algorithm. We can use optimal hardware IPs selected by the proposed hardware IPs selection algorithm. The experimental results show effectiveness of our new design methodology.

  • Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations

    Nozomu Togawa, Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki

    Proceedings - IEEE International Symposium on Circuits and Systems     3499 - 3502  2005

    　View Summary

    In this paper, we propose a sub-operation parallelism optimization algorithm in SIMD processor synthesis. Given an initial assembly code and timing constraints, our algorithm synthesizes a processor core with sub-operation parallelism optimization for SIMD functional units. First we consider an initial processor which has sufficient hardware units for executing an initial assembly code. An initial processor core includes the maximum sub-operation parallelism for each SIMD functional unit. By gradually reducing sub-operation parallelism, we can finally have a processor core with small area meeting a given timing constraints. We show the effectiveness of our proposed algorithm through experimental results. © 2005 IEEE.

    DOI

  • A Processor Core Synthesis System in IP-based SoC Design

    Proceedings of the ASP-DAC 2005    2005

  • A selective scan chain reconfiguration through run-length coding for test data compression and scan power reduction

    Y Shi, S Kimura, M Yanagisawa, T Ohtsuki

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E87A ( 12 ) 3208 - 3215  2004.12

    　View Summary

    Test data volume and power consumption for scan-based designs are two major concerns in system-on-a-chip testing. However, test set compaction by filling the don't-cares will invariably increase the scan-in power dissipation for scan testing, then the goals of test data reduction and low-power scan testing appear to be conflicted. Therefore, in this paper we present a selective scan chain reconfiguration method for test data compression and scan-in power reduction. The proposed method analyzes the compatibility of the internal scan cells for a given test set and then divides the scan cells into compatible classes. After the scan chain reconfiguration a dictionary is built to indicate the run-length of each compatible class and only the scan-in data for each class should be transferred from the ATE to the CUT so as to reduce test data volume. Experimental results for the larger ISCAS' 89 benchmarks show that the proposed approach overcomes the limitations of traditional run-length coding techniques, and leads to highly reduced test data volume with significant power savings during scan testing in all cases.

  • A hybrid dictionary test data compression for multiscan-based designs

    Y Shi, S Kimura, M Yanagisawa, T Ohtsuki

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E87A ( 12 ) 3193 - 3199  2004.12

    　View Summary

    In this paper, we present a test data compression technique to reduce test data volume for multiscan-based designs. In our method the internal scan chains are divided into equal sized groups and two dictionaries were build to encode either an entire slice or a subset of the slice. Depending on the codeword, the decompressor may load all scan chains or may load only a group of the scan chains, which can enhance the effectiveness of dictionary-based compression. In contrast to previous dictionary coding techniques, even for the CUT with a large number of scan chains, the proposed approach can achieve satisfied reduction in test data volume with a reasonable smaller dictionary. Experimental results showed the proposed test scheme works particularly well for the large ISCAS'89 benchmarks.

  • FPGA-based reconfigurable adaptive FEC

    K Shimizu, J Uchida, Y Miyaoka, N Togawa, M Yanagisawa, T Ohtsuki

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E87A ( 12 ) 3036 - 3046  2004.12

    　View Summary

    In this paper, we propose a reconfigurable adaptive FEC system. In adaptive FEC schemes, the error correction capability t is changed dynamically according to the communication channel condition. If a particular error correction capability t is given, we can implement an FEC decoder which is optimal for t by taking the number of operations into consideration. Thus, reconfiguring the optimal FEC decoder dynamically for each error correction capability allows us to maximize the throughput of each decoder within a limited hardware resource. Based on this concept, our reconfigurable adaptive FEC system can reduce the packet dropping rate more efficiently than conventional fixed hardware systems. We can improve data transmission throughput for a reliable transport protocol. Practical simulation results are also shown.

  • A Reconfigurable Adaptive FEC System for Reliable Wireless Communications

    2004 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS'2004)     13 - 16  2004

  • Experimental Evaluation of High-Level Energy Optimization Based on Thread Partitioning

    2004 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS'2004)     161 - 164  2004

  • High-Level Power Optimization Based on Thread Partitioning

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E87-A, No. 12   3075 - 3082  2004

  • Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test

    Proc．of IEEE The 13th Asian Test Symposium on Circuits and Systems     432 - 437  2004

    DOI

  • A sub-operation parallelism optimization algorithmin HW/SW partitioning for SIMD processor cores

    SASIMI2004     483 - 490  2004

  • An efficient algorithm/architecture codesign for image encoders

    J Choi, N Togawa, T Ikenaga, S Goto, M Yanagisawa, T Ohtsuki

    2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS     469 - 472  2004

    　View Summary

    We describe the optimization of a complex video encoder systems based on target architecture. We implemented the MPEG-4 encoder using hardware/software codesign approach, mapped together based on a target architecture. We proposed a target architecture template and an optimization methodology. In our design flow, we searched for a bottleneck module constraining the system. After investigating the computational complexity, quality, and the simplicity of algorithms, we chose the best algorithm for hardware implementation, and then mapped the selected algorithm onto the hardware with different architecture, what does the best architecture for the algorithm and which is the best architecture of components. We chose one of the architectures meet the constraints and also made tradeoffs among speed, chip area, and memory bandwidth for different architecture. The proposed system architecture was used to reduce the design decisions and iterations, provided flexible and scalable systems. The evaluations resulted in effective optimization of the motion estimation module and better tradeoffs that optimized the overall system.

  • Reducing Test Data Volume for Multiscan-based Designs through Single/Sequence Mixed Encoding

    47th IEEE International Midwest Symposium On Circuits and Systems     445 - 448  2004

  • A hardware/software cosynthesis algorithm for processors with heterogeneous datapaths

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E87-A, No. 4   830 - 836  2004

  • A cosynthesis algorithm for application specific processors with heterogeneous datapaths

    Proceedings of the ASP-DAC 2004    2004

  • A thread partitioning algorithm in low power high-level synthesis

    Proceedings of the ASP-DAC 2004    2004

  • A reconfigurable adaptive FEC system for reliable wireless communications

    K Shimizu, N Togawa, T Ikenaga, M Yanagisawa, S Goto, T Ohtsuki

    PROCEEDINGS OF THE 2004 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1 AND 2     13 - 16  2004

    　View Summary

    This paper proposes a reconfigurable adaptive FEC system. For adaptive FEC schemes, we can implement an FEC decoder which is optimal for error correction capability t by taking the number of operations into consideration. Reconfiguring the optimal FEC decoder dynamically for each t allows us to maximize the throughput of each decoder within a limited hardware resource. Our system can reduce packet dropping rate more efficiently than conventional fixed hardware systems for a reliable transport protocol.

  • Experimental evaluation of high-level energy optimization based on thread partitioning

    J Uchida, Y Miyaoka, N Togawa, M Yanagisawa, T Ohtsuki

    PROCEEDINGS OF THE 2004 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1 AND 2     161 - 164  2004

    　View Summary

    This paper presents a thread partitioning algorithm for high-level synthesis systems which generate low energy circuits. In the algorithm, we partitions a thread into two sub-threads, one of which has RF and the other does not have RE The partitioned sub-threads need to be synchronized with each other to keep the data dependency of the original thread. Since the partitioned sub-threads have waiting time for synchronization, gated clocks can be applied to each sub-thread. We achieve 33% energy reduction when we apply our proposed algorithm to a JPEG encoder.

  • レジスタ分散型アーキテクチャを対象とするフロアプランを考慮した高位合成手法

    田中真, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   VLD2004   127 - 132  2004

  • High-Level Power Optimization Based on Thread Partitioning

    内田純平, 戸川望, 柳澤政生, 大附辰夫

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E87-A, No. 12   3075 - 3082  2004

  • A Selective Scan Chain Reconfiguration through Run-Length Coding for Test Data Compression and Scan Power Reduction

    史又華, 木村晋二, 柳澤政生, 大附辰夫

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E87-A, No. 12   3208 - 3215  2004

  • A Hybrid Dictionary Test Data Compression for Multiscan-Based Designs

    史又華, 木村晋二, 柳澤政生, 大附辰夫

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E87-A, No. 12   3193 - 3199  2004

  • A sub-operation parallelism optimization algorithmin HW/SW partitioning for SIMD processor cores

    川津秀樹, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    SASIMI2004     483 - 490  2004

  • IP再利用を考慮したシステムLSIにおけるプロセッサコア合成システム

    友野直紀, 小原俊逸, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    情報処理学会 DAシンポジウム 2004     19 - 24  2004

  • フロアプランとタイミング制約に基づくレジスタ間データ転送を考慮した高位合成手法

    田中真, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    情報処理学会 DAシンポジウム 2004     283 - 288  2004

  • An Efficient Algorithm/Architecture Codesign for Image Encoders

    崔鎮求, 戸川望, 池永剛, 後藤敏, 柳澤政生, 大附辰夫

    47th IEEE International Midwest Symposium On Circuits and Systems     469 - 472  2004

  • Reducing Test Data Volume for Multiscan-based Designs through Single/Sequence Mixed Encoding

    史又華, 木村晋二, 戸川望, 柳澤政生, 大附辰夫

    47th IEEE International Midwest Symposium On Circuits and Systems     445 - 448  2004

  • SIMD型プロセッサコア向けHW/SW分割におけるSIMD型演算最適化手法

    川津秀樹, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会第17回 回路とシステム(軽井沢)ワークショップ     579 - 584  2004

  • A hardware/software cosynthesis algorithm for processors with heterogeneous datapaths

    宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E87-A, No. 4   830 - 836  2004

  • ネットワークプロセッサ合成システム

    松浦努, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   VLD2003-145   55 - 60  2004

  • HW/SW分割システムにおける仮想IP類推手法

    小田雄一, 内田純平, 宮岡祐一郎, 戸川望, 橘昌良, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   VLD2003-158   47 - 52  2004

  • Packed SIMD型命令を持つプロセッサ合成システムのためのリターゲッタブルコンパイラ

    加藤久晴, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   VLD2003-157   41 - 46  2004

  • 面積制約を考慮したCAMプロセッサ最適化手法

    石川裕一朗, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   VLD2003-152   13 - 18  2004

  • インターリーブを考慮したReconfigurable Adaptive FEC

    清水一範, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   VLD2003-151   7 - 12  2004

  • 携帯機器を対象としたJava動的コンパイラにおけるプロファイリングシステム

    船田雅史, 内田純平, 戸川望, 柳澤政生, 大附辰夫

    情報処理学会研究報告，2004-MBL-28     55 - 62  2004

  • Instruction set and funcational unit synthesis for SIMD processorcores

    戸川望, 太刀掛宏一, 宮岡祐一郎, 柳澤政生, 大附辰夫

    Proceedings of the ASP-DAC 2004    2004

  • A cosynthesis algorithm for application specific processors with heterogeneous datapaths

    宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    Proceedings of the ASP-DAC 2004    2004

  • A thread partitioning algorithm in low power high-level synthesis

    内田純平, 戸川望, 柳澤政生, 大附辰夫

    Proceedings of the ASP-DAC 2004    2004

  • A Reconfigurable Adaptive FEC System for Reliable Wireless Communications

    2004 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS'2004)     13 - 16  2004

  • Experimental Evaluation of High-Level Energy Optimization Based on Thread Partitioning

    2004 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS'2004)     161 - 164  2004

  • FPGA-Based Reconfigurable Adaptive FEC

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E87-A, No. 12   3036 - 3046  2004

  • High-Level Power Optimization Based on Thread Partitioning

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E87-A, No. 12   3075 - 3082  2004

  • A Selective Scan Chain Reconfiguration through Run-Length Coding for Test Data Compression and Scan Power Reduction

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E87-A, No. 12   3208 - 3215  2004

  • A Hybrid Dictionary Test Data Compression for Multiscan-Based Designs

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E87-A, No. 12   3193 - 3199  2004

  • Alternative run-length coding through scan chain reconfiguration for joint minimization of test data volume and power consumption in scan test

    Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    Proceedings of the Asian Test Symposium     432 - 437  2004

    　View Summary

    Test data volume and scan power are two major concerns in SoC test. In this paper we present an alternative run-length coding method through scan chain reconfiguration to reduce both test data volume and scan-in power consumption. The proposed method analyzes the compatibility of the internal scan cells for a given test set and then divides the scan cells into compatible classes. To extract the compatible scan cells we apply a heuristic algorithm by solving the graph coloring problem
    and then a simple greedy algorithm is used to configure the scan chain for the minimization of scan power. Experimental results for the larger IS-CAS'89 benchmarks show that the proposed approach leads to highly reduced test data volume with significant power savings during scan test.

    DOI

  • A sub-operation parallelism optimization algorithmin HW/SW partitioning for SIMD processor cores

    SASIMI2004     483 - 490  2004

  • An Efficient Algorithm/Architecture Codesign for Image Encoders

    47th IEEE International Midwest Symposium On Circuits and Systems     469 - 472  2004

  • Reducing Test Data Volume for Multiscan-based Designs through Single/Sequence Mixed Encoding

    47th IEEE International Midwest Symposium On Circuits and Systems     445 - 448  2004

  • A hardware/software cosynthesis algorithm for processors with heterogeneous datapaths

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E87-A, No. 4   830 - 836  2004

  • A cosynthesis algorithm for application specific processors with heterogeneous datapaths

    Proceedings of the ASP-DAC 2004    2004

  • A thread partitioning algorithm in low power high-level synthesis

    Proceedings of the ASP-DAC 2004    2004

  • A built-in reseeding technique for LFSR-based test pattern generation

    Y Shi, Z Zhang, S Kimura, M Yanagisawa, T Ohtsuki

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E86A ( 12 ) 3056 - 3062  2003.12

    　View Summary

    Reseeding technique is proposed to improve the fault coverage in pseudo-random testing. However most of previous works on reseeding is based on storing the seeds in an external tester or in a ROM. In this paper we present a built-in reseeding technique for LFSR-based test pattern generation. The proposed structure can run both in pseudorandom mode and in reseeding mode. Besides, our method requires no storage for the seeds since in reseeding mode the seeds can be generated automatically in hardware. In this paper we also propose an efficient grouping algorithm based on simulated annealing to optimize test vector grouping. Experimental results for benchmark circuits indicate the superiority of our technique against other reseeding methods with respect to test length and area overhead. Moreover, since the theoretical properties of LFSRs are preserved, our method could be beneficially used in conjunction with any other techniques proposed so far.

  • A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E86-A, No. 5   1082 - 1092  2003

  • An Instruction-Set Simulator Generator for SIMD Processor Cores

    Proceedings of workshop SASIMI2003     160 - 167  2003

  • System Architecture based on Hardware/Software Codesign for Optimization of Video Encoders

    The 2003 International Technical Conference on Circuits/Systems，Computers and Communications    2003

  • A hardware/software partitioning algorithm for processor cores with packed SIMD-type instructions

    戸川望, 太刀掛宏一, 宮岡祐一郎, 柳澤政生, 大附辰夫

    IEICE Trans. on Fundamentals of Electronics Communications and Computer SciencesVol. E86-A, No. 12   Vol. E86-A, No. 12  2003

  • A retargetable simulator generator for DSP processor cores with packed SIMD-type instructions

    戸川望, 笠原亨介, 宮岡祐一郎, Jinku Choi, 柳澤政生, 大附辰夫

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E86-A, No. 12  2003

  • 面積制約付きCAMプロセッサ合成手法

    石川裕一朗, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術研究報告   VLD2003-89  2003

  • 面積制約を考慮したCAMプロセッサ向けハードウェア/ソフトウェア協調設計手法

    石川裕一朗, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   IE2003-98   83 - 88  2003

  • FPGAを用いたReconfigurable Adaptive FECの実装と評価

    清水一範, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   Reconf2003-9  2003

  • 分岐距離による再送手法選択式マルチキャスト

    山田泰弘, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   CQ2003-58   29 - 32  2003

  • 公共空間におけるハンドオフ時間短縮を考慮したBluetoothネットワークの手順に関する一検討

    寺崎暁, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   CQ2003-58   25 - 28  2003

  • 動的再構成可能システムによるAdaptive FECの実装

    清水一範, 戸川望, 柳澤政生, 大附辰夫

    情報処理学会 DAシンポジウム 2003     25 - 30  2003

  • システムLSI設計における定性的側面を考慮したハードウェア/ソフトウェア分割システム

    小田雄一, 宮岡祐一郎, 戸川望, 橘昌良, 柳澤政生, 大附辰夫

    情報処理学会 DAシンポジウム 2003     169 - 174  2003

  • 冗長記述を利用したVHDLへの透かし埋め込み手法

    久保ゆきこ, 戸川望, 柳澤政生, 大附辰夫

    情報処理学会 DAシンポジウム 2003     37 - 42  2003

  • System Architecture based on Hardware/Software Codesign for Optimization of Video Encoders

    崔鎮求, 戸川望, 柳澤政生, 大附辰夫

    The 2003 International Technical Conference on Circuits/Systems，Computers and Communications    2003

  • A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories

    戸川望, 戸塚崇夫, 涌井達彦, 柳澤政生, 大附辰夫

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E86-A, No. 5   442 - 451  2003

  • ネットワークスイッチング処理を対象としたCAMプロセッサ自動合成システム

    田中英夫, 戸川望, 柳澤政生, 大附辰夫

    回路とシステム(軽井沢)ワークショップ     435 - 440  2003

  • 不規則なデータパスを持つプロセッサのハードウェア/ソフトウェア協調合成手法

    宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    回路とシステム(軽井沢)ワークショップ     441 - 446  2003

  • An Instruction-Set Simulator Generator for SIMD Processor Cores

    宮岡祐一郎, 戸川望, 笠原亨介, 崔鎮求, 柳澤政生, 大附辰夫

    Proceedings of workshop SASIMI2003     160 - 167  2003

  • 閾値検索機能付きCAMプロセッサの最適化手法

    戸塚崇夫, 宮岡祐一郎, 石川裕一朗, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   VLD2002-158   19 - 24  2003

  • SIMD型プロセッサコア向けHW/SW分割におけるSIMD型演算最適化手法

    太刀掛宏一, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   VLD2002-157   13 - 18  2003

  • 高位合成システムにおけるスレッド分割を用いた低消費電力化手法

    内田純平, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   VLD2002-156   7 - 12  2003

  • ハードウェアIPの応答時間を考慮したプロセッサコアのハードウェア/ソフトウェア分割手法

    田川博規, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   VLD2002-136   37 - 42  2003

  • ハードウェアIPの応答時間を考慮したプロセッサコア合成システム

    小原俊逸, 田川博規, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   VLD2002-135   31 - 36  2003

  • MPEG-4コアプロファイル符号化向けDSP

    石本剛, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   VLD2002-134   25 - 30  2003

  • A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E86-A, No. 5   1082 - 1092  2003

  • An Instruction-Set Simulator Generator for SIMD Processor Cores

    Proceedings of workshop SASIMI2003     160 - 167  2003

  • A hardware/software partitioning algorithm for SIMD processor cores

    K. Tachikake, N. Togawa, Y. Miyaoka, Jinku Choi, M. Yanagisawa, T. Ohtsuki

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC   2003-   135 - 140  2003

    　View Summary

    This paper proposes a new hardware/software partitioning algorithm for processor cores with SIMD instructions. Given a compiled assembly code including SIMD instructions, a timing constraint of execution time, and available hardware units, the proposed algorithm synthesizes an area-optimized processor core with a new assembly code. Firstly, we assume an initial processor core on which an input assembly code can run with the shortest execution time. Secondly we reduce a hardware unit added to a processor core one by one while the timing constraint is satisfied. At the same time, we update the assembly code so that it can run on the new processor configuration. By repeating this process, we finally obtain a processor core architecture with small area under the given timing constraint. We expect that vie can obtain a processor core which has appropriate SIMD functional units for running the input application program. The promising experimental results are also shown.

    DOI

  • System Architecture based on Hardware/Software Codesign for Optimization of Video Encoders

    The 2003 International Technical Conference on Circuits/Systems，Computers and Communications    2003

  • An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions

    2002 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS'2002)     2603 - 2611  2002

  • A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E85-A, No. 12   2655 - 2666  2002

  • An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E85-A, No. 12   2603 - 2611  2002

  • A Software/Hardware Codesign for MPEG Encoder

    FIT(Forum on Information Technology)2002    2002

  • System-level Function and Architecture Codesign for Optimization of MPEG Encoder

    ITC-CSCC'02    2002

  • High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E85-A, No. 4   827 - 834  2002

  • An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions

    宮岡祐一郎崔鎮求, 戸川望, 柳澤政生, 大附辰夫

    2002 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS'2002)     2603 - 2611  2002

  • A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation

    野田真一, 戸川望, 柳澤政生, 大附辰夫

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E85-A, No. 12   2655 - 2666  2002

  • An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation

    崔鎮求, 戸川望, 柳澤政生, 大附辰夫

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E85-A, No. 12   2603 - 2611  2002

  • 閾値検索機能を持つCAMプロセッサの自動合成システム

    戸塚崇夫, 石川裕一朗, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   VLD2002-113   197 - 192  2002

  • 動的再構成可能システムによるプロトコルブースタの実装

    清水一範, 陳暁梅, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   VLD2002-103   127 - 132  2002

  • ストリーミングを主目的としたアクセスネットワークでの最大許容遅延を考慮した制御方式

    柳澤政生, 佐藤隆之, 戸川望, 大附辰夫

    電子情報通信学会技術報告，MoMuC   2-Jul   13 - 18  2002

  • 仮想IP類推機構を有する動画像処理向けシステムVLSIのためのハードウェア/ソフトウェア分割システム

    小田雄一, 磯田新平, 戸川望, 橘昌良, 柳澤政生, 大附辰夫

    情報処理学会 DAシンポジウム 2002     173 - 178  2002

  • Packed SIMD 型命令を持つプロセッサを対象としたハードウェア/ソフトウェア協調合成システムのための並列化コンパイル手法

    鈴木伸治, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   VLD2002-78   79 - 84  2002

  • Packed SIMD型命令セットを持った画像処理プロセッサのためのハードウェア/ソフトウェア分割手法

    太刀掛宏一, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   VLD2002-53   85 - 90  2002

  • A Software/Hardware Codesign for MPEG Encoder

    崔鎮求, 戸川望, 柳澤政生, 大附辰夫

    FIT(Forum on Information Technology)2002    2002

  • System-level Function and Architecture Codesign for Optimization of MPEG Encoder

    崔鎮求, 戸川望, 柳澤政生, 大附辰夫

    ITC-CSCC'02    2002

  • モバイル環境における一対多通信 －シミュレーションによるFTPとSRMの比較－

    佐藤隆之, 柳生健吾, 戸川望, 大附辰夫

    電子情報通信学会技術報告，MoMuC   2-Jun   33 - 38  2002

  • ディジタル信号処理向けプロセッサのためのシミュレータ生成手法

    笠原亨介, 戸川望, 柳澤政生, 大附辰夫

    情報処理学会論文誌   vol.43 No.5   1202 - 1213  2002

  • A Hardware Unit Generation Algorithm for a Hardware/Software Cosynthesis System of Digital Signal Processor Cores with Packed SIMD Type Instructions

    MIYAOKA Yuichiro, TOGAWA /Nozomu, YANAGISAWA Masao, OHTSUKI Tatsuo

    Transactions of Information Processing Society of Japan   vol.43 No.5 ( 5 ) 1191 - 1201  2002

    　View Summary

    This paper proposes a hardware unit generation algorithm for a hardware/software cosynthesis system of digital signal processors with packed SIMD type instructions. Given a set of instructions, the proposed algorithm extracts a set of subfunctions to be required by the hardware unit and generates more than one architecture candidates for hardware units. The algorithm also outputs the estimated area and delay of each of the generated hardware units. The execution time of the proposed algorithm is very short and thus it can be easily incorporated into the processor core synthesis system. Experimental results demonstrate effectiveness and efficiency of the alogorithm.

    CiNii

  • DSPプロセッサコアのハードウェア/ソフトウェア協調合成システムのための演算語長縮小化手法

    田川博規, 嶋下和宏, 戸川望, 柳澤政生, 大附辰夫

    回路とシステム軽井沢ワークショップ     429 - 434  2002

  • High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks

    野田真一, 戸川望, 柳澤政生, 大附辰夫

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E85-A, No. 4   827 - 834  2002

  • 制御処理ハードウェア高位合成のためのコントロールデータフローグラフ変形手法

    石井哲雄, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   VLD2001-165   41 - 48  2002

  • IP再利用を考慮した動画像処理システムVLSI向けハードウェア/ソフトウェア分割設計支援システム

    磯田新平, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   VLD2001-164   33 - 40  2002

  • Packed SIMD 型演算器を持つディジタル信号処理プロセッサのためのリターゲッタブルシミュレータ生成手法

    笠原亨介, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   VLD2001-162   24 - 17  2002

  • ロジック入力用レベルシフトコンパレーター設計考察

    宮崎英敏, 戸川望, 柳澤政生, 大附辰夫, 茨木栄武, 新谷悟

    電子回路研究会，ETC-02-16     13 - 17  2002

  • システムVLSIのための高位面積/遅延/消費電力見積もりに基づく低消費電力指向高位合成手法

    野田真一, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   VLD2001-144   93 - 100  2002

  • An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions

    2002 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS'2002)     2603 - 2611  2002

  • A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E85-A, No. 12   2655 - 2666  2002

  • An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E85-A, No. 12   2603 - 2611  2002

  • A Software/Hardware Codesign for MPEG Encoder

    FIT(Forum on Information Technology)2002    2002

  • System-level Function and Architecture Codesign for Optimization of MPEG Encoder

    ITC-CSCC'02    2002

  • High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E85-A, No. 4   827 - 834  2002

  • Area/Delay Estimation for Digital Signal Processor Cores

    Proc.ASP-DAC 2001（IEEE）     156 - 161  2001

  • A New Hardware/Software Partitioning Algorithm for DSP Processor Cores with Two Types of Register Files

    IEICE Trans. on Fundamentals of Electronics Communications and Computer SciencesVol. E84-A, No. 11   Vol. E84-A, No. 11  2001

  • Area and Delay Estimation in Hardware/Software Cosynthesis for Digital Signal Processor Cores

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E84-A, No. 11  2001

  • A Hardware/Software Cosynthesis System for CAM Processors

    SASIMI200１    2001

  • Implementation of Motion Estimation IP Core for MPEG Encoder

    ITC-CSCC 2001    2001

  • An Area/Time Optimizing Algorithm in High-Level Synthesis of Control-Based Hardwares

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E84-A, No. 5   1166 - 1176  2001

  • A Hardware/Software Cosynthesis System for Processors based on Reducing Opration Word Length with Memory Interface Specification

    SHIMASHITA Kazuhiro, TOGAWA Nozomu, YANAGISAWA Masao, OHTSUKI Tatsuo

    Technical report of IEICE. FTS   VLD2001-110 ( 476 ) 127 - 132  2001

    　View Summary

    Let us consider to reduce an area of a processor by shortening the operation word length from n to n/2. In this case, we generally need to excute an operation instruction at least two times in order to obtain n-bit result. However, assume that internal variables in an application program uses only n/2 bits. In this case, we need to execute the operation instruction only once. We have proposed a hardware/software cosynthesis system for processors. In the system, we assume that data length of applications program equals to operation word length of a processor core. This paper proposes an algorithm for shortening an operation word length. The algorithm repeatedly replaces each n bit operation instruction with one or more n/2 bit operation instructions depending on internal variable precision.

    CiNii

  • A New Hardware/Software Partitioning Algorithm for DSP Processor Cores with Two Types of Register Files

    戸川望, 桜井崇志, 柳澤政生, 大附辰夫

    IEICE Trans. on Fundamentals of Electronics Communications and Computer SciencesVol. E84-A, No. 11   Vol. E84-A, No. 11  2001

  • Area and Delay Estimation in Hardware/Software Cosynthesis for Digital Signal Processor Cores

    戸川望, 片岡義治, 宮岡祐一郎, 柳澤政生, 大附辰夫

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E84-A, No. 11  2001

  • A Hardware/Software Cosynthesis System for CAM Processors

    戸川望, 涌井達彦, 柳澤政生, 大附辰夫

    SASIMI200１    2001

  • Packed SIMD型命令を持つプロセッサを対象としたハードウェア／ソフトウェア協調合成システムのためのハードウェアユニット生成手法

    宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    情報処理学会 DAシンポジウム 2001     223 - 228  2001

  • ディジタル信号処理向けプロセッサのためのシミュレータ生成手法

    笠原亨介, 戸川望, 柳澤政生, 大附辰夫

    情報処理学会 DAシンポジウム 2001     137 - 142  2001

  • Implementation of Motion Estimation IP Core for MPEG Encoder

    崔鎮求, 戸川望, 柳澤政生, 大附辰夫

    ITC-CSCC 2001    2001

  • An Area/Time Optimizing Algorithm in High-Level Synthesis of Control-Based Hardwares

    戸川望, 家長真行, 柳澤政生, 大附辰夫

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E84-A, No. 5   1166 - 1176  2001

  • ディジタル信号処理向けプロセッサコアのPacked SIMD型ハードウェアユニット生成手法

    宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   VLD2001-2   7 - 13  2001

  • Gated Clockによる低消費電力化システムVLSIの高位面積／遅延／消費電力見積り

    野田真一, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会第14回 回路とシステム(軽井沢)ワークショップ     591 - 596  2001

  • ソフトIPのための保護アルゴリズム

    堀川哲郎, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会第14回 回路とシステム(軽井沢)ワークショップ     411 - 416  2001

  • システムLSIを対象としたハードウェア／ソフトウェア分割システム

    小田龍之介, 磯田新平, 戸川望, 橘昌良, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   VLD2000-140   37 - 42  2001

  • A Parallelizing Compiler in a Hardware/Software Cosynthesis System for Image/Video Processor with Packed SIMD Type Instruction Sets

    NONOGAKI Nobuhiro, TOGAWA Nozomu, YANAGISAWA Masao, OHTSUKI Tatsuo

    Technical report of IEICE. VLD   VLD2000-139 ( 646 ) 31 - 36  2001

    　View Summary

    Many current general purpose processors and digital signal processors have extended instructions to enhance their performance of image/video processing applications. The extended functionality comes primarily with the addition of packed SIMD type instructions. These instructions aim at exploiting subword parallelism. The packed SIMD type instruction set includes hundreds of instructions but a small subset of them is enough to implement most image/video processing applications. Thus we can significantly reduce area of a processor within a restriction of execution time if application-specific syntyesis is applied to it. In this paper, we propose a hardware/software cosynthesis system for processors with packed SIMD type instruction set and an algorithm of SIMD parallelization in a register for its compiler. The input of the system is an application description written in C and application data, and the output is hardware descriptions of a synthesized processor core, an application binary code executed on the processor core and software environment. Its compiler generates an object code assuming a processor core with all the available hardware units. It exploits instruction level and subword level parallelism, and attempts to minimize its execution time. The experimental results show the effectiveness of the compiler.

    CiNii

  • 制御処理ハードウェアの高位合成システムのための面積／遅延見積もり手法

    余田貴幸, 戸川望, 柳澤政生, 大附辰夫

    情報処理学会研究報告   2001-SLDM-100-4,pp.25-32   25 - 32  2001

  • RC等価回路に基づくクロストーク低減配線手法

    曽根原理仁, 戸川望, 柳澤政生, 大附辰夫

    情報処理学会研究報告   2001-SLDM-100-3,pp.17-24   17 - 24  2001

  • 発見的算法と分枝限定法を用いた時間的予測に基づくリソースバイディング

    中村洋, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   VLD2000-119   17 - 24  2001

  • FPGAを用いた動的再構成可能システムを対象とするスケジューリング手法

    石飛貴志, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   VLD2000-115   33 - 40  2001

  • パラメータ付けされた動的再構成可能システムとその応用

    香西伸治, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   VLD2000-114   25 - 32  2001

  • Area/delay estimation for digital signal processor cores

    Y. Miyaoka, Y. Kataoka, N. Togawa, M. Yanagisawa, T. Ohtsuki

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC   2001-   156 - 161  2001

    　View Summary

    Hardware/software partitioning is one of the key processes in a hardware/software cosynthesis system for digital signal processor cores. In hardware/software partitioning, area and delay estimation of a processor core plays an important role since the hardware/software partitioning process must determine which part of a processor core should be realized by hardware units and which part should be realized by a sequence of instructions based on execution time of an input application program and area of a synthesized processor core. This paper proposes area and delay estimation equations for digital signal processor cores. For area estimation, we show that total area for a processor core can be derived from the sum of area for a processor kernel and area for additional hardware units. Area for a processor kernel can be mainly obtained by minimum area for a processor kernel and overheads for adding hardware units and registers. Area for a hardware unit can be mainly obtained by its type and operation bit width. For delay estimation, we show that critical path delay for a processor core can be derived from the delay of a hardware unit which is on the critical path in the processor core. Experimental results demonstrate that errors of area estimation are less than 2% and errors of delay estimation are less than 2ns when comparing estimated area and delay with logic-synthesized area and delay.

    DOI

  • Area/Delay Estimation for Digital Signal Processor Cores

    Proc.ASP-DAC 2001（IEEE）     156 - 161  2001

  • A New Hardware/Software Partitioning Algorithm for DSP Processor Cores with Two Types of Register Files

    IEICE Trans. on Fundamentals of Electronics Communications and Computer SciencesVol. E84-A, No. 11   Vol. E84-A, No. 11  2001

  • Area and Delay Estimation in Hardware/Software Cosynthesis for Digital Signal Processor Cores

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E84-A, No. 11  2001

  • A Hardware/Software Cosynthesis System for CAM Processors

    SASIMI200１    2001

  • Implementation of Motion Estimation IP Core for MPEG Encoder

    ITC-CSCC 2001    2001

  • An Area/Time Optimizing Algorithm in High-Level Synthesis of Control-Based Hardwares

    Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohsuki

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences   Vol. E84-A, No. 5 ( 5 ) 1166 - 1176  2001

    　View Summary

    This paper proposes an area/time optimizing algorithm in a high-level synthesis system for control-based hardwares. Given a call graph whose node corresponds to a control flow of an application program, the algorithm generates a set of state-transition graphs which represents the input call graph under area and timing constraint. In the algorithm, first state-transition graphs which satisfy only timing constraint are generated and second they are transformed so that they can satisfy area constraint. Since the algorithm is directly applied to control-flow graphs, it can deal with control flows such as bitwise processes and conditional branches. Further, the algorithm synthesizes more than one hardware architecture candidates from a single call graph for an application program. Designers of an application program can select several good hardware architectures among candidates depending on multiple design criteria. Experimental results for several control-based hardwares demonstrate effectiveness and efficiency of the algorithm.

  • CAM processor synthesis based on behavioral descriptions

    N Togawa, T Wakui, T Yoden, M Terajima, M Yanagisawa, T Ohtsuki

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E83A ( 12 ) 2464 - 2473  2000.12

    　View Summary

    CAM (Content Addressable Memory) units are generally designed so that thc) carl be applied to variety of application programs. However, if a particular application runs on CAM units, some functions in CAM units may be often used and other functions may never be used. We consider that appropriate design for CAM units is required depending on the requirements for a given application program. This paper proposes a CAM processor synthesis system based on behavioral descriptions. The input of the system is an application programs written in C including CAM functions, and its output is hardware descriptions of a synthesized processor and a binary code executed on it. Since the system determines functions in CAM units and synthesizes a CAM processor depending on the requirements of an application program, we expect that a synthesized CAM processor can execute the application program with small processor area and delay. Experimental results demonstrate its efficiency and effectiveness.

  • A high performance embedded wavelet video coder

    TR Zhao, M Yanagisawa, T Ohtsuki

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E83A ( 6 ) 979 - 986  2000.06

    　View Summary

    This paper describes a highly performance scalable video coder. Wavelet transform is employed to decompose the video frame into different resolutions. Novel features of this coder are 1) a highly efficient multi-resolution motion estimation that requires minimum compuation and overhead motion information is embedded in this scheme; 2) the wavelet coefficients are organized in an extended zero tree (EZT) which is much more efficient than the simple zerotree. We show with experimental results that this video coder achieves good performances both in processing time and compression ratio when applied to typical test video sequences.

  • A hardware/Software Partitioning Algorithm for Digital Signal Processor Cores with Two Types of Register Files

    Proc. APCCAS 2000（IEEE）     544 - 547  2000

  • A Behavioral Synthesis System for Processors with Content Addressable Memories

    Proc.SASIMI2000     56 - 63  2000

  • A hardware/software cosynthesis system for digital signal processor cores with two types of register files,

    IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences   E83-A/3   442 - 451  2000

  • A hardware/Software Partitioning Algorithm for Digital Signal Processor Cores with Two Types of Register Files

    戸川望, 桜井崇志, 柳澤政生, 大附辰夫

    Proc.APCCAS2000   pp.544-547   544 - 547  2000

  • CAM Processor Synthesis Based on Behavioral Descriptions

    戸川望, 涌井達彦, 余傅達彦, 寺島信, 柳澤政生, 大附辰夫

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences.   E83-A/12   2464 - 2473  2000

  • CAMプロセッサを対象とするハードウェア／ソフトウェア協調合成システム

    涌井達彦, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   VLD2000-84   89 - 94  2000

  • 機能メモリを使用したプロセッサの面積／遅延見積もり手法

    余傅達彦, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   VLD2000-83   83 - 88  2000

  • 制御処理ハードウェアの高位合成システムのための面積／時間最適化アルゴリズム

    家長真行, 戸川望, 柳澤政生, 大附辰夫

    情報処理学会DAシンポジウム2000     27 - 32  2000

  • A High Performance Embedded Wavelet Video Coder

    趙庭榮, 柳澤政生, 大附辰夫

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences.   vol.E83-A ( 6 ) 979 - 986  2000

  • A Behavioral Synthesis System for Processors with Content Addressable Memories

    涌井達彦, 余傅達彦, 寺島信, 戸川望, 柳澤政生, 大附辰夫

    Proc.SASIMI2000     56 - 63  2000

  • システムVLSIの動作合成におけるレイアウト面積・遅延見積もり手法

    諏訪勝, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会第13回回路とシステム（軽井沢）ワークショップ     125 - 130  2000

  • 歩行者を対象とした地図データ配信システムにおける専用プロセッサの設計と評価

    伊澤義貴, 濱未希子, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   VLD99-267   15 - 22  2000

  • FPGAを用いた動的再構成可能システムと暗号化アルゴリズムへの応用

    羽切崇, 戸川望, 柳澤政生, 大附辰夫

    電子情報通信学会技術報告   VLD99-266   7 - 14  2000

  • A hardware/software cosynthesis system for digital signal processor cores with two types of register files,

    戸川望, 柳澤政生, 大附辰夫

    IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences   E83-A/3   442 - 451  2000

  • An area/time optimizing algorithm in high-level synthesis for control-based hardwares

    Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC     309 - 312  2000

    　View Summary

    This paper proposes an area/time optimizing algorithm in high-level synthesis for control-based hardwares. Given a call graph whose node corresponds to a control flow of an application program, the algorithm generates a set of state-transition graphs which represents the input call graph under area and timing constraint. In the algorithm, first state-transition graphs which satisfy only timing constraint are generated and second they are transformed so that they can satisfy area constraint. Since the algorithm is directly applied to control-flow graphs, it can deal with control flows such as bit-wise processes and conditional branches. Further, the algorithm synthesizes more than one hardware architecture candidates from a single call graph for an application program. Designers of an application program can select several good hardware architectures among candidates depending on multiple design criteria. Experimental results for several control-based hardwares demonstrate effectiveness and efficiency of the algorithm. © 2000 IEEE.

    DOI

  • A hardware/Software Partitioning Algorithm for Digital Signal Processor Cores with Two Types of Register Files

    Proc. APCCAS 2000（IEEE）     544 - 547  2000

  • A Behavioral Synthesis System for Processors with Content Addressable Memories

    Proc.SASIMI2000     56 - 63  2000

  • CAM Processor Synthesis Based on Behavioral Descriptions

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences.   E83-A/12   2464 - 2473  2000

  • A High Performance Embedded Wavelet Video Coder

    IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences.   vol.E83-A ( 6 ) 979 - 986  2000

  • A hardware/software cosynthesis system for digital signal processor cores with two types of register files,

    IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences   E83-A/3   442 - 451  2000

  • Fast motion estimation scheme for video coding using feature vector matching and motion vector's correlations

    TR Zhao, M Yanagisawa, T Ohtsuki

    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS   9 ( 1-2 ) 67 - 82  1999.02

    　View Summary

    In this paper, we propose a fast block motion estimation scheme by exploiting the correlations of motion vectors (MV) existing in spatially- and temporally-adjacent as well as hierarchically-related blocks. The basic idea is to use the information obtained from the corresponding block at a coarser resolution level and spatio-temporal neighboring blocks at the same level in order to select a good set of initial MV candidates and then perform further local search to find the best matching MV. In order to further reduce computational complexity, the sign pattern vector (SPV) is defined and used for block matching, as opposed to the pixel intensity values used in the conventional block matching methods. By using the SPV definition, a data block can be presented by a mean and a set of binary sign patterns with a much reduced data set. The block matching motion estimation is then divided into mean matching and binary phase matching. The proposed technique enables a significant reduction in computational complexity compared with the conventional block matching motion estimation (ME) because binary phase matching only involves Boolean logic operations. This scheme also significantly reduces the data transfer time between the frame buffer and motion estimator. Our test results indicate that the performance of the proposed scheme is comparable with the full-search block matching under the same search ranges, however, the proposed scheme has a speed-up factor ranging from 250 to 370 in comparison with full search.

    DOI CiNii

  • A simultaneous placement and global routing algorithm for FPGAS with power optimization

    N Togawa, K Ukai, M Yanagisawa, T Ohtsuki

    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS   9 ( 1-2 ) 99 - 112  1999.02

    　View Summary

    This paper proposes a simultaneous placement and global routing algorithm for FPGAs with power optimization. The algorithm is based on hierarchical bipartitioning of layout regions and sets of logic-blocks. When bipartitioning a layout region, pseudo-blocks are introduced to preserve connections if there exist connections between bipartitioned logic-block sets. A global route is represented by a sequence of pseudo-blocks. Since pseudo-blocks and logic-blocks can be dealt with equally, placement and global routing are processed simultaneously. The algorithm gives weights to nets with high switching probabilities and attempts to assign the blocks connected by weighted nets to the same region. Thus their length is shortened and the power consumption of a whole circuit can be reduced. The experimental results demonstrate the effectiveness and efficiency of the algorithm.

    DOI

  • A hardware/software cosynthesis system for digital signal processor cores

    IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences   E82-A/11   2325 - 2337  1999

  • A simultaneous placement and routing algorithm for FPGAs with power optimization

    TOGAWA N, UKAI K, YANAGISAWA M, OHTSUKI T

    Journal of Circuits, Systems and Computers   9 ( 1/2 ) 99 - 112  1999

    DOI CiNii

  • A Depth-Constrained Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Structured LUTs

    TOGAWA Nozomu, ARA Koji, YANAGISAWA Masao, OHTSUKI Tatsuo

    IEICE transactions on fundamentals of electronics, communications and computer sciences   E82-A/3 ( 3 ) 473 - 482  1999

    　View Summary

    This paper proposes a fast depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured lookup tables. First, we propose a technology mapping algorithm which minimizes the number of logic-blocks if an input Boolean network is a tree. Second, we propose a technology mapping algorithm which minimizes logic depth for any input Boolean network. Finally, we combine those two technology mapping algorithms and propose an algorithm which realizes technology mapping whose depth is bounded by a given upper bound d_c. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.

    CiNii

  • ２種類のレジスタファイルを持つディジタル信号処理向けプロセッサのハードウェア/ソフトウェア分割手法

    電子情報通信学会技術報告   VLD99-76  1999

  • ディジタル信号処理向けプロセッサコアの面積/遅延見積り手法

    電子情報通信学会技術報告   VLD99-75  1999

  • A hardware/software cosynthesis system for digital signal processor cores

    IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences   E82-A; 11, pp.2325-2337   2325 - 2337  1999

  • 制御処理ハードウェアの高位合成システムのための面積/時間最適化アルゴリム

    電子情報通信学会技術報告   VLD99-66  1999

  • 制御処理を主体としたハードウェア記述生成手法

    情報処理学会DAシンポジウム'99論文集    1999

  • 制御処理を主体としたハードウェアを対象とする高位合成システムとその適用

    情報処理学会DAシンポジウム'99論文集    1999

  • ２種類のレジスタファイルを持ったディジタル信号処理向けプロセッサのハードウェア/ソフトウェア協調合成システム

    電子情報通信学会第12回回路とシステム軽井沢ワークショップ論文集    1999

  • 分枝限定法に基づく最適解を保証するリソースバインディング手法

    情報処理学会論文誌   40; 4, pp.1565-1577   1565 - 1577  1999

  • ＦＰＧＡを用いた動的再構成可能システムとその応用

    電子情報通信学会ＶＬＳＩ設計技術研究会   98;143   17 - 24  1999

  • A Depth-Constrained Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Structured LUTs

    TOGAWA Nozomu, ARA Koji, YANAGISAWA Masao, OHTSUKI Tatsuo

    IEICE transactions on fundamentals of electronics, communications and computer sciences   E82-A;3,pp.473-482 ( 3 ) 473 - 482  1999

    　View Summary

    This paper proposes a fast depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured lookup tables. First, we propose a technology mapping algorithm which minimizes the number of logic-blocks if an input Boolean network is a tree. Second, we propose a technology mapping algorithm which minimizes logic depth for any input Boolean network. Finally, we combine those two technology mapping algorithms and propose an algorithm which realizes technology mapping whose depth is bounded by a given upper bound d_c. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.

    CiNii

  • ２種類のレジスタファイルを持ったディジタル信号処理向けプロセッサのハードウェア／ソフトウェア協調合成システムとその並列化コンパイラ

    電子情報通信学会フォールトトレラントシステム研究会   98;132   71 - 78  1999

  • A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing

    Proc. ASP-DAC'99     335 - 338  1999

  • A hardware/software cosynthesis system for digital signal processor cores

    IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences   E82-A/11   2325 - 2337  1999

  • A simultaneous placement and routing algorithm for FPGAs with power optimization

    Journal of Circuits, Systems and Computers   9 ( 1/2 ) 99 - 112  1999

    DOI CiNii

  • A depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured LUTs

    TOGAWA Nozomu, ARA Koji, YANAGISAWA Masao, OHTSUKI Tatsuo

    IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences   E82-A/3 ( 3 ) 473 - 482  1999

    　View Summary

    This paper proposes a fast depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured lookup tables. First, we propose a technology mapping algorithm which minimizes the number of logic-blocks if an input Boolean network is a tree. Second, we propose a technology mapping algorithm which minimizes logic depth for any input Boolean network. Finally, we combine those two technology mapping algorithms and propose an algorithm which realizes technology mapping whose depth is bounded by a given upper bound d_c. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.

    CiNii

  • A high-level synthesis system for digital signal Processing based on data-flow graph enumeration

    IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences   E81-A/12   2563 - 2575  1998

  • Maple-opt : A Performance-Oriented Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGA's

    TOGAWA N, YANAGISAWA M, OHTSUKI T

    IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems   17 ( 9 ) 803 - 818  1998

    DOI CiNii

  • A Fast Scheduling Algorithm Based on Gradual Time-Frame Reduction for Datapath Synthesis

    IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences   E81-A/6   1231 - 1240  1998

  • An FPGA Layout Reconfiguration Algorithm Based on Global Routes for Engineering Changes in System Design Spectifications

    IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences   E81-A/5   873 - 884  1998

  • ＦＰＧＡのマクロブロックを対象とした配置概略配線同時処理手法

    電子情報通信学会ＶＬＳＩ設計技術研究会   98;115   123 - 130  1998

  • A High-Level Synthesis System for Digital Signal Processing Based on Data-Flow Graph Enumeration

    IEICE Trans. on Fundamentals   E81-A;12,pp.2563-2575   2563 - 2575  1998

  • A Fast Motion-Compensation Scheme for Video Coding Using Feature Vector Matching

    Proc. APCCAS'98     635 - 638  1998

  • A Simultaneous Placement and Global Routing Algorithm for FPGAs with Power Optimization

    Proc. APCCAS'98     125 - 128  1998

  • 機能メモリを使用したプロセッサを対象とするハードウェア／ソフトウェア協調合成システム

    電子情報通信学会コンピュータシステム研究会   98;85   31 - 38  1998

  • Mapleopt : A performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGA's

    TOGAWA N.

    IEEE Trans.Comput.-Aided Des.   17 ( 9 ) 803 - 818  1998

    DOI CiNii

  • 最適解を保証するリソースバインディング手法

    情報処理学会DAシンポジウム'98論文集     245 - 250  1998

  • A Fast Scheduling Algorithm Based on Gradual Time-Frame Reduction for Datapath Synthesis

    IEICE Trans. on Fundamentals   E81-A;6   1231 - 1241  1998

  • 分布定数回路の遅延感度解析に基づくクロック配線最適化手法

    情報処理学会設計自動化研究会   88;4   21 - 28  1998

  • An FPGA Layout Reconfiguration Algorithm Based on Global Routes for Engineering Changes in System Design Specifications

    IEICE Trans. on Fundamentals   E81-A;5   873 - 884  1998

  • ツリー状に接続されたＬＵＴを対象とした深さ制約付きテクノロジーマッピング手法

    電子情報通信学会回路とシステム（軽井沢）ワークショップ論文集     343 - 348  1998

  • パイプラインプロセッサのハードウェア記述自動生成手法

    電子情報通信学会VLSI設計技術研究会   97;117   33 - 40  1998

  • ディジタル信号処理向けプロセッサの自動合成システムにおける並列化コンパイラ

    電子情報通信学会VLSI設計技術研究会   97;116   25 - 32  1998

  • ディジタル信号処理向けプロセッサのハードウェア／ソフトウェア協調合成システム

    電子情報通信学会VLSI設計技術研究会   97;115   17 - 24  1998

  • An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays

    Proc. ASP-DAC'98     519 - 526  1998

  • A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs

    Proc. ASP-DAC'98     265 - 274  1998

  • A high-level synthesis system for digital signal Processing based on data-flow graph enumeration

    Nozomu Togawa, Takafumi Hisakl, Masao Yanagisawa, Tatsuo Ohtsuku

    IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences   E81-A/12 ( 12 ) 2563 - 2575  1998

    　View Summary

    This paper proposes a high-level synthesis system for datapath design of digital signal processing hardwares. The system consists of four phases: (1) DFG (data-flow graph) generation, (2) scheduling, (3) resource binding, and (4) HDL (hardware description language) generation. In (1), the system does not generate only one best DFG representing a given behavioral description of a hardware, but more than one good DFGs representing it. In (2) and (3), several synthesis tools can be incorporated into the system depending on the required objectives. Thus we can obtain more than one datapath candidates for a behavioral description with their area and performance evaluation. In (4), the best datapath design is selected among those candidates and its hardware description is generated. The experimental results for applying the system to several benchmarks show the effectiveness and efficiency.

  • Maple-opt : A Performance-Oriented Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGA's

    TOGAWA N.

    IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems   17 ( 9 ) 803 - 818  1998

    DOI CiNii

  • A Fast Scheduling Algorithm Based on Gradual Time-Frame Reduction for Datapath Synthesis

    IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences   E81-A/6   1231 - 1240  1998

  • An FPGA Layout Reconfiguration Algorithm Based on Global Routes for Engineering Changes in System Design Spectifications

    IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences   E81-A/5   873 - 884  1998

  • Fast scheduling and allocation algorithms for entropy CODEC

    K Suzuki, N Togawa, M Sato, T Ohtsuki

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS   E80D ( 10 ) 982 - 992  1997.10

    　View Summary

    Entropy coding/decoding are implemented on FPGAs as a fast and flexible system in which high-level synthesis technologies are key issues. In this paper, we propose scheduling and allocation algorithms for behavioral descriptions of entropy CODEC. The scheduling algorithm employs a control-flow graph as input and finds a solution with minimal hardware cost and execution time by merging nodes in the control-flow graph. The allocation algorithm assigns operations to operators with various bit lengths. As a result, register-transfer level descriptions are efficiently obtained from behavioral descriptions of entropy CODEC with complicated control flow and variable bit lengths. Experimental results demonstrate that our algorithms synthesize the same circuits as manually designed within one second.

  • IEICE Trans. on Information and Systems

       1997

  • A Performance-Oriented Simultaneous Placement and Global Routing Algorithm for Transport-Processing FPGAs

    IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences Fast Scheduling and Allocation Algorithms for Entropy CODEC   E-80A/10   1795 - 1806  1997

  • A Circuit Partioning Algorithm with Path Delay Constraints for Multi-FPGA Systems

    IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences   E-80A/3   494 - 505  1997

  • A Circuit Partitioning Alglrithm with Replication Capability for Multi-FPGA Systems

    IEICE Trans,on Fundementals of Eledtronics,Communications and Computer Sciences   E78-A/13   1118 - 1123  1997

  • ツリー構造を持つ論理ブロックを対象としたテクノロジマッピング手法

    電子情報通信学会VLSI設計技術研究会   97;104   29 - 36  1997

  • 連想メモリを搭載したハードウェアエンジンによる故障回路並列故障シミュレーションの高速化手法

    情報処理学会設計自動化研究会   97;103   81 - 88  1997

  • A Performance-Oriented Simultaneous Placement and Global Routing Algorithm for Transport-Processing FPGAs

    IEICE Trans. on Fundamentals   E80-A;10   1795 - 1806  1997

  • An Efficient Hierarchical Visual Pattern Block Truncation Coding Scheme

    Proc. of IPSJ International Symp. on Information Systems and Technologies for Network Society     151 - 154  1997

  • ディジタル信号処理を対象とした高位合成システムにおける高速なスケジューリングアルゴリズム

    情報処理学会DAシンポジウム'97論文集     167 - 172  1997

  • A BGA Package Routing Algorithm on Sketch Layout System

    SHIBATA Shuuichi, UKAI Kaoru, TOGAWA Nozomu, SATO Masao, OHTSUKI Tatsuo

    The Journal of Japan Institute for Interconnecting and Packaging Electronic Circuits   12 ( 4 ) 241 - 246  1997

    DOI CiNii

  • FPGAを対象とした低消費電力指向配置・概略配線同時処理手法

    電子情報通信学会VLSI設計技術研究会   97;42   191 - 198  1997

  • システム設計仕様の部分的変更を実現する概略配線径路を考慮したFPGA向けレイアウト再構成手法

    電子情報通信学会回路とシステム軽井沢ワークショップ論文集     187 - 192  1997

  • スケッチレイアウトシステムにおけるBGAパッケージ配線手法

    電子情報通信学会VLSI設計技術研究会   VLD96;106  1997

  • 接続コストの最小化を目的とした高速アロケーション手法

    電子情報通信学会VLSI設計技術研究会   VLD96;96  1997

  • A Circuit Partitioning Algorithm with Path Delay Constraints for Multi-FPGA Systems

    電子情報通信学会英文論文誌   E80-A;3  1997

  • A Simultaneous Placement and Global Routing Algorithm with Path Length Constraints for Transport-Processing FPGAs

    Proc. of ASP-DAC'97    1997

  • IEICE Trans. on Information and Systems

       1997

  • A Performance-Oriented Simultaneous Placement and Global Routing Algorithm for Transport-Processing FPGAs

    IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences Fast Scheduling and Allocation Algorithms for Entropy CODEC   E-80A/10   1795 - 1806  1997

  • A Circuit Partioning Algorithm with Path Delay Constraints for Multi-FPGA Systems

    IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences   E-80A/3   494 - 505  1997

  • A Circuit Partitioning Alglrithm with Replication Capability for Multi-FPGA Systems

    IEICE Trans,on Fundementals of Eledtronics,Communications and Computer Sciences   E78-A/13   1118 - 1123  1997

  • A Simultaneous Technology Mapping,Placement,and Global Routing Algorithm for FDGAs with Path Delay Constraints

    IEICE Trans,on Fundementals of Eledtronics,Communications and Computer Sciences   E79-A/3   321 - 329  1996

  • Dharmaアーキテクチャに基づくFPGAチップの試作

    マイクロエレクロトニクス研究開発機構第15回研究交流会    1996

  • Simultaneous Placement and Global Routing for Transport-Processing FPGA Layout

    電子情報通信学会英文論文誌    1996

  • Scheduling and Allocation Algorithm for Entropy CODEC

    Proc. of SASIMI'96    1996

  • A Performance-Oriented Circuit Partitioning Algorithm with Logic-Block Replication for Multi-FPGA Systems

    Proc. of APCCAS'96    1996

  • 入力パタン並列故障シミュレーションの高速化手法

    電子情報通信学会VLSI設計技術研究会   VLD96;63  1996

  • パス長制約を考慮した通信処理用FPGA向け配置・概略配線同時処理手法

    電子情報通信学会VLSI設計技術研究会   VLD96;56  1996

  • スケッチレイアウトシステムにおける配線可能性検証手法

    回路実装学会誌   11;6  1996

    DOI

  • 柔軟性の高いレイアウトシステムのためのデータ表現方式

    回路実装学会誌   11;6  1996

    DOI

  • 高位合成システムを用いた画像符号化アルゴリズムのハードウェア合成手法

    情報処理学会DAシンポジウム'96論文集    1996

  • データパス設計を対象とした高位合成システム

    情報処理学会DAシンポジウム'96論文集    1996

  • 通信処理用FPGAを対象とした配置・概略配線同時処理手法

    情報処理学会設計自動化研究会   DA96;51  1996

  • プリント配線板を対象とした二層均等化スペーシング手法

    情報処理学会設計自動化研究会   DA96;51  1996

  • パス遅延制約を考慮したマルチFPGGA用回路分割手法

    電子情報通信学会回路とシステム軽井沢ワークショップ論文集    1996

  • イタレーション間データ依存制約を考慮したパイプライン化DSPスケジューリング手法

    電子情報通信学会VLSI設計技術研究会   95-561  1996

  • 条件分岐構造を持つコントロールデータフローグラフの時間制約スケジューリング手法

    電子情報通信学会VLSI設計技術研究会   95-561  1996

  • A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints

    電子情報通信学会英文論文誌   E79-A;3  1996

  • エントロピーCODECの高位合成手法

    情報処理学会設計自動化研究会   96-16  1996

  • A Simultaneous Technology Mapping,Placement,and Global Routing Algorithm for FDGAs with Path Delay Constraints

    IEICE Trans,on Fundementals of Eledtronics,Communications and Computer Sciences   E79-A/3   321 - 329  1996

  • A Circuit Partitioning Alglrithm with Replication Capability for Multi-FPGA Systems

    IEICE Trans,on Fundementals of Eledtronics,Communications and Computer Sciences   E78-A/12   1765 - 1776  1995

  • CAM-Based parallel Fault Simulation Algorithm with Minimal Storage Size

    IEICE Trans,on Fundementals of Eledtronics,Communications and Computer Sciences   E78-A/12   1755 - 1764  1995

  • A CAM-Based Parallel Fault Simulation Algorithm with Minimal Storage Size

    電子情報通信学会英文論文誌   E78-A;12  1995

  • A Circuit Partitioning Algorithm with Replication Capability for Multi-FPGA Systems

    電子情報通信学会英文論文誌   E78-A;12  1995

  • パイプライン化DSPのデータパス・スケジューリング手法－動作記述からSFL記述の自動合成

    第7回パルテノン研究会    1995

  • リソースアロケーションを考慮したデータパス・スケジューリング手法

    電子情報通信学会VLSI設計技術研究会   VLD95-97  1995

  • 動作記述からのデータフローグラフ生成手法

    電子情報通信学会VLSI設計技術研究会   VLD95-96  1995

  • Maple-opt: A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Performance Optimization

    Proc. ASP-DAC'95    1995

  • A CAM Based Parallel Fault Simulation Algorithm with Minimal Storage Size

    Proc. of SASIMI'95    1995

  • I/Oピン数最小化を目的とした回路分割手法

    第3回FPGA/PLD Design Conference    1995

  • マルチFPGAを対象とした階層的回路分割手法

    電子情報通信学会回路とシステム研究会   VLD95-40  1995

  • Maple-opt: パス遅延制約を考慮したFPGA用テクノロジーマッピング・配置・概略配線同時処理手法

    電子情報通信学会軽井沢ワークショップ論文集    1995

  • A Circuit Partitioning Alglrithm with Replication Capability for Multi-FPGA Systems

    IEICE Trans,on Fundementals of Eledtronics,Communications and Computer Sciences   E78-A/12   1765 - 1776  1995

  • CAM-Based parallel Fault Simulation Algorithm with Minimal Storage Size

    IEICE Trans,on Fundementals of Eledtronics,Communications and Computer Sciences   E78-A/12   1755 - 1764  1995

  • Maple : A Simultaneous Technology Mapping, Placement and Global Routing Algorithm for Field-Programmable Gate Arrays.

      E77-A/12,  1994

  • Experimental Appraisal of Liner and Quadratic Objective Functions Effec on Force Directed Method for Analog Placement

      E-77A/4,  1994

  • ロングラインに対応した階層的FPGA配線手法

    情報処理学会論文誌   35/12,  1994

  • パス長制約を考慮したFPGA配置概略配線同時処理手法

    情報処理学会論文誌   35/5,  1994

  • Maple : A Simultaneous Technology Mapping, Placement and Global Routing Algorithm for Field-Programmable Gate Arrays.

      E77-A/12,  1994

  • Experimental Appraisal of Liner and Quadratic Objective Functions Effec on Force Directed Method for Analog Placement

      E-77A/4,  1994

  • PLACEMENT, ROUTING, AND COMPACTION ALGORITHMS FOR ANALOG CIRCUITS

    MAHMOUD, II, T AWASHIMA, K ASAKURA, T OHTSUKI

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E76A ( 6 ) 894 - 903  1993.06

    　View Summary

    The performance of analog circuits is strongly influenced by their layout. Performance specifications are usually translated into physical constraints such as symmetry, common orientation, and distance constraints among certain components. Automatic digital layout tools can be adopted and modified to deal with the imposed performance constraints on the analog layout. The selection and modifications of algorithms to handle the analog constraints became the area of research in analog layout systems. The existing systems are characterized by the use of stochastic optimization techniques based placement, grid based or channel routers, and lack of compaction. In this paper, algorithms for analog circuit placement, routing, and compaction are presented. The proposed algorithms consider the analog oriented constraints, which are important from an analog layout point of view, and reduce the computation cost. The placement algorithm is based on a force directed method and consists of two main phases, each of which includes a tuning procedure. In the first phase, we solve a set of simultaneous linear equations, based upon the attractive forces. These attractive forces represent the interconnection topology of given blocks and some specified constraints. Symmetry constraint is considered throughout the tuning procedure. In the second phase, block overlap resulting from the first phase is resolved iteratively, where each iteration is followed by the symmetry tuning procedure. Routing is performed using a line expansion based gridless router. Routing constraints are taken into account and several routing priorities are imposed on the nets. The compactor part employs a constraint graph based algorithm while considering the analog symmetry constraints. The algorithms are implemented and integrated within an analog layout design system. An experimental result for an OP AMP provided by MCNC benchmark is shown to demonstrate the performance of the algorithms.

  • OPTIMAL CONSTRAINT GRAPH GENERATION ALGORITHM FOR LAYOUT COMPACTION USING ENHANCED PLANE-SWEEP METHOD

    T AWASHIMA, M SATO, T OHTSUKI

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E76A ( 4 ) 507 - 512  1993.04

    　View Summary

    This paper presents an optimal constraint graph generation algorithm for graph-based one-dimensional layout compaction. The first published algorithm for this problem was the shadow-propagation algorithm. However, without sophisticated implementation of a shadow-front, complexity of the algorithm could fall into 0(n2), where n is the number of layout objects. Although our algorithm, called the enhanced plane-sweep based graph generation algorithm, is an extension of the shadow-propagation algorithm, such a drawback is resolved by introducing an enhanced plane-sweep technique. The algorithm maintains multiple shadow-fronts simultaneously by storing them in a work-list called previous-boundary. Since a balanced search tree is selected for implementation of the work-list, total complexity of the algorithm is 0(n log n) which is optimal. Experimental results show that the enhanced plane-sweep based graph generation algorithm runs in almost linear time with respect to the number of layout objects and is faster than the perpendicular plane-sweep algorithm which is also optimal in terms of time complexity.

  • FPGAを対象とした階層的概略詳細配線手法

    電子情報通信学会論文誌A   J76-A/9   1312 - 1321  1993

  • ジョグ挿入を伴ったチップコンパクション手法

    電子情報通信学会論文誌A   J76-A/7   968 - 978  1993

  • 線分展開法を拡張した多層グリッドレス配線手法

    電子情報通信学会論文誌A   J76-A/3   410 - 420  1993

  • 改良線分探索法の連想プロセッサを用いた-実装手法

    電子情報通信学会論文誌A   J75-A/12   1837 - 1848  1992

  • A VLSI GEOMETRICAL DESIGN RULE VERIFICATION ACCELERATED BY CAM-BASED HARDWARE ENGINE

    T TAKIZAWA, K KUBOTA, M SATO, T OHTSUKI

    IEICE TRANSACTIONS ON COMMUNICATIONS ELECTRONICS INFORMATION AND SYSTEMS   74 ( 10 ) 3072 - 3077  1991.10

    　View Summary

    VLSI technology has matured to the extent that hundreds of thousands or even millions of transistors can be integrated in a single chip. Layout data for VLSIs consist of around ten mask layers, and the total number of polygons on the layers is about ten times larger than the number of circuit elements. In order to deal with such a large number of polygons, algorithms for mask pattern processing are usually based on the underlying assumption that the whole data is accommodated in the secondary storage and that only those patterns within a few consecutive thin slits of the plane can be processed in the main memory (work list). This is called the work-list method. A linear time geometrical design rule verification algorithm is presented in this paper. This algorithm is based on the work-list method. Content Addressable Memory (CAM) is introduced to implement the work list, so as to make the algorithm run in linear time with linear memory space. Data in RAM can be accessed only by its address, whereas data in CAM is accessed not only by address but also by a content which matches a given referential data. This function is called equivalence search. An equivalence search is executed in constant time independent of the amount of data. The advantages of CAM for our algorithm are summarized as follows. (1) It provides the flexibility to deal with a variety of geometrical search problems for VLSI design. ( 2 ) Each geometrical search is done in constant time. ( 3 ) Complicated coding for sophisticated data structures depending on problems is not necessary, unlike software implementation.

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