2024/05/24 更新

写真a

イノウエ ヤスアキ
井上 靖秋
所属
理工学術院
職名
名誉教授
学位
博士(工学) ( 早稲田大学 )

経歴

  • 2009年
    -
     

    上海交通大学客員教授

  • 2009年
    -
     

    Visiting Professor, Shanghai JIo Tong University

  • 2005年
    -
     

    広島大学客員教授

  • 2005年
    -
     

    Visiting Professor, Hiroshima University

  • 2003年
    -
    2004年

    大分大学講師

  • 2003年
    -
    2004年

    Lecturer, Oita university

  • 2003年
    -
     

    - 早稲田大学大学院 教授

  • 2003年
    -
     

    - Professor, Waseda University

  • 2000年
    -
    2003年

    東亜大学 教授

  • 2000年
    -
    2003年

    Professor, East Asia University

  • 2002年
    -
     

    - 福岡県システムLSIカレッジ講師

  • 1964年
    -
    2000年

    三洋電機㈱

  • 1964年
    -
    2000年

    Sanyo Electric Co. Ltd.

▼全件表示

委員歴

  • 2010年
    -
    2011年

    IEEE  回路とシステム福岡支部長

  • 2010年
    -
    2011年

    IEEE  CAS Fukuoka Chapter Chair

  • 1997年
    -
    1999年

    IEEE  回路とシステム論文誌Ⅱ編集委員

  • 1997年
    -
    1999年

    IEEE  Transactions on Circuits and Systems II

  • 1996年
    -
     

    電子情報通信学会  非線形問題研究会専門委員

所属学協会

  •  
     
     

    日本シミュレーション学会

  •  
     
     

    電気学会

  •  
     
     

    情報処理学会

  •  
     
     

    電子情報通信学会

  •  
     
     

    IEEE

  •  
     
     

    IEEE

  •  
     
     

    JSST

  •  
     
     

    IEEJ

  •  
     
     

    IPSJ

  •  
     
     

    IEICE

  •  
     
     

    IEEE

▼全件表示

研究分野

  • 通信工学 / 電子デバイス、電子機器

研究キーワード

  • 回路シミュレーション

  • 回路検証

  • LSI設計CAD

  • アナログ・デジタル混載LSI

  • 非線形理論・回路

  • 電子デバイス・集積回路

  • 集積回路

  • 非線形回路

  • 電子回路

  • Circuit Simulation

  • Circuit Verification

  • EDA

  • Analog Circuit

  • IC

  • Nonlinear Circuit

▼全件表示

受賞

  • 船井情報科学振興賞

    2004年  

  • Funai Information Technology Promotion Award

    2004年  

  • 情報処理学会業績賞

    2003年  

  • Achievement Award from the Information Processing Society Japan

    2003年  

  • 電気通信普及財団 テレコムシステム技術賞

    2002年  

  • TELECOM System Technology Award from the Telecommunications Advancement Foundations

    2002年  

  • 群馬県知事表彰(機械金属工業技術者)

    1999年  

  • 科学技術庁長官賞(科学技術功労者)

    1999年  

  • Engineer Award from the Gunma Prefecture

    1999年  

  • Distinguished Service Award from the Science and Technology Agency, the Japanese Government

    1999年  

  • 日本科学技術連盟 石川賞

    1988年  

  • Ishikawa Award from the Union of Japanese Scientists and Engineers

    1988年  

▼全件表示

 

共同研究・競争的資金等の研究課題

  • 超低電力・高速アナログLSI

    共同研究

    研究期間:

    2004年
    -
    2011年
     

  • Ultra low-power / high-speed analog LSIs

    Cooperative Research

    研究期間:

    2004年
    -
    2011年
     

  • ユビキタスネットワーク用機能融合システムLSIの開発

    共同研究

    研究期間:

    2002年
    -
    2006年
     

  • シグナルインテグリティ問題

    研究期間:

    2004年
    -
     
     

  • アナログ・デジタル混載LSI設計CAD開発

    研究期間:

    2004年
    -
     
     

  • 高速・超低電力アナログLSI開発

    研究期間:

    2004年
    -
     
     

  • Signal integrity issues

    研究期間:

    2004年
    -
     
     

  • Mixed Analog and Digital CAD

    研究期間:

    2004年
    -
     
     

  • High-speed / ultra low-power analog LSIs

    研究期間:

    2004年
    -
     
     

  • アナログ・デジタル混載LSI設計CADシステム開発

    共同研究

    研究期間:

    2002年
    -
     
     

  • ユビキタスセンサネットワーク用システムLSI

    研究期間:

    2002年
    -
     
     

  • Mixed signal LSI CAD systems

    Cooperative Research

    研究期間:

    2002年
    -
     
     

  • System LSIs for ubiquitous sensor network nodes

    研究期間:

    2002年
    -
     
     

  • 先端的回路シミュレーション技法

    共同研究

    研究期間:

    2000年
    -
     
     

  • 非線形回路とシステムの数値解析

    研究期間:

    2000年
    -
     
     

  • Advanced circuit simulation technologies

    Cooperative Research

    研究期間:

    2000年
    -
     
     

  • Numerical analysis of nonlinear circuits and systems

    研究期間:

    2000年
    -
     
     

▼全件表示

Misc

  • An Effective Model of the Overshooting Effect for Multiple-Input Gates in Nanometer Technologies

    Li Ding, Zhangcai Huang, Atsushi Kurokawa, Jing Wang, Yasuaki Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E97A ( 5 ) 1059 - 1074  2014年05月

     概要を見る

    With the scaling of CMOS technology into the nanometer regime, the overshooting effect is more and more obvious and has a significant influence to gate delay and power consumption. Recently, researchers have already proposed the overshooting effect models for an inverter. However, the accurate overshooting effect model for multiple-input gates is seldom presented and the existing technology to reduce a multiple-input gate to an inverter is not useful when modeling the overshooting effect for multiple-input gates. Therefore, modeling the overshooting effect for multiple-input gates is proposed in this paper. Firstly, a formula-based model is presented for the overshooting time of 2-input NOR gate. Then, more complicated methods are given to calculate the overshooting time of 3-input NOR gate and other multiple-input gates. The proposed model is verified to have a good agreement, within 3.4% error margin, compared with SPICE simulation results using CMOS 32 nm PTM model.

    DOI

  • An Effective Model of the Overshooting Effect for Multiple-Input Gates in Nanometer Technologies

    Li Ding, Zhangcai Huang, Atsushi Kurokawa, Jing Wang, Yasuaki Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E97A ( 5 ) 1059 - 1074  2014年05月

     概要を見る

    With the scaling of CMOS technology into the nanometer regime, the overshooting effect is more and more obvious and has a significant influence to gate delay and power consumption. Recently, researchers have already proposed the overshooting effect models for an inverter. However, the accurate overshooting effect model for multiple-input gates is seldom presented and the existing technology to reduce a multiple-input gate to an inverter is not useful when modeling the overshooting effect for multiple-input gates. Therefore, modeling the overshooting effect for multiple-input gates is proposed in this paper. Firstly, a formula-based model is presented for the overshooting time of 2-input NOR gate. Then, more complicated methods are given to calculate the overshooting time of 3-input NOR gate and other multiple-input gates. The proposed model is verified to have a good agreement, within 3.4% error margin, compared with SPICE simulation results using CMOS 32 nm PTM model.

    DOI

  • A 1-V rail-to-rail bulk-driven op-amp with enhanced transconductance

    Hui Zhu, Qiang Li, Jing Wang, Ting Wang, Yasuaki Inoue

    Proceedings The 29th International Technical Conference on Circuits/Systems, Computer and Communications (ITC-CSCC2014)     256 - 259  2014年

  • A sub-1-V supply-insensitive bandgap reference circuit without resistors

    Jing Wang, Qiang Li, Li Ding, Hui Zhu, Ting Wang, Yasuaki Inoue

    Proceedings The 29th International Technical Conference on Circuits/Systems, Computer and Communications (ITC-CSCC2014)     260 - 263  2014年

  • An almost 3VDD rail-to-rail op-amp with constant Gm

    Ting Wang, Yingqian Dai, Qiang Li, Jing Wang, Hui Zhu, Yasuaki Inoue

    Proceedings The 29th International Technical Conference on Circuits/Systems, Computer and Communications (ITC-CSCC2014)     281 - 284  2014年

  • A 1-V rail-to-rail bulk-driven op-amp with enhanced transconductance

    Hui Zhu, Qiang Li, Jing Wang, Ting Wang, Yasuaki Inoue

    Proceedings The 29th International Technical Conference on Circuits/Systems, Computer and Communications (ITC-CSCC2014)     256 - 259  2014年

  • A sub-1-V supply-insensitive bandgap reference circuit without resistors

    Jing Wang, Qiang Li, Li Ding, Hui Zhu, Ting Wang, Yasuaki Inoue

    Proceedings The 29th International Technical Conference on Circuits/Systems, Computer and Communications (ITC-CSCC2014)     260 - 263  2014年

  • An almost 3VDD rail-to-rail op-amp with constant Gm

    Ting Wang, Yingqian Dai, Qiang Li, Jing Wang, Hui Zhu, Yasuaki Inoue

    Proceedings The 29th International Technical Conference on Circuits/Systems, Computer and Communications (ITC-CSCC2014)     281 - 284  2014年

  • An Effective and Globally Convergent Newton Fixed-Point Homotopy Method for MOS Transistor Circuits

    Dan Niu, Xiao Wu, Zhou Jin, Yasuaki Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E96A ( 9 ) 1848 - 1856  2013年09月

     概要を見る

    Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. However, the previous studies are mainly focused on the bipolar transistor circuits. Also the efficiencies of the previous homotopy methods for MOS transistor circuits are not satisfactory. Therefore, finding a more efficient homotopy method for MOS transistor circuits becomes necessary and important. This paper proposes a Newton fixed-point homotopy method for MOS transistor circuits and proposes an embedding algorithm in the implementation as well. Moreover, the global convergence theorems of the proposed Newton fixed-point homotopy method for MOS transistor circuits are also proved. Numerical examples show that the efficiencies for finding DC operating points of MOS transistor circuits by the proposed MOS Newton fixed-point homotopy method with the two embedding types can be largely enhanced (can larger than 50%) comparing with the conventional MOS homotopy methods, especially for some large-scale MOS transistor circuits which can not be easily solved by the SPICE3 and HSPICE simulators.

    DOI

  • An Effective and Globally Convergent Newton Fixed-Point Homotopy Method for MOS Transistor Circuits

    Dan Niu, Xiao Wu, Zhou Jin, Yasuaki Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E96A ( 9 ) 1848 - 1856  2013年09月

     概要を見る

    Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. However, the previous studies are mainly focused on the bipolar transistor circuits. Also the efficiencies of the previous homotopy methods for MOS transistor circuits are not satisfactory. Therefore, finding a more efficient homotopy method for MOS transistor circuits becomes necessary and important. This paper proposes a Newton fixed-point homotopy method for MOS transistor circuits and proposes an embedding algorithm in the implementation as well. Moreover, the global convergence theorems of the proposed Newton fixed-point homotopy method for MOS transistor circuits are also proved. Numerical examples show that the efficiencies for finding DC operating points of MOS transistor circuits by the proposed MOS Newton fixed-point homotopy method with the two embedding types can be largely enhanced (can larger than 50%) comparing with the conventional MOS homotopy methods, especially for some large-scale MOS transistor circuits which can not be easily solved by the SPICE3 and HSPICE simulators.

    DOI

  • A simple and practical statistical device model for analog LSI designs

    Jing Wang, Li Ding, Yasuaki Inoue

    2013 International Conference on Communications, Circuits and Systems, ICCCAS 2013   1   408 - 412  2013年

     概要を見る

    With the scaling of CMOS devices toward their ultimate dimensions, device performance variability induced by process variation has become a critical issue in analog LS I designs. Statistical device model library building based on statistical device model considering the process variation accurately is useful to predict the performance of analog LS I designs. However, conventional statistical device models are either complicated or not accurate enough. Therefore, a simple and practical statistical device model for analog LS I designs is proposed in this paper. Simultaneously, a simple method to extract model parameters is also proposed. Statistical analysis results of 0.65um CMOS Op-Amp based on the proposed model using Monte Carlo simulation have a good agreement with the chip measurement results. © 2013 IEEE.

    DOI

  • An effective implementation and embedding algorithm of PTA method for finding DC operating points

    Zhou Jin, Xiao Wu, Yasuaki Inoue

    2013 International Conference on Communications, Circuits and Systems, ICCCAS 2013   1   417 - 420  2013年

     概要を見る

    Recently, the compound element pseudo transient analysis method, CEPTA, is regarded as an efficient practical method to find DC operating points of nonlinear circuits when the Newton-Raphson method fails. In this paper, an effective SPICE3 implementation algorithm for the CEPTA method is proposed. It can significantly improve simulation efficiency with smaller limitations during simulation. Besides, the influence of different pseudo-elements' embedding positions on the simulation efficiency is also discussed and presented with numerical examples. Several numerical examples demonstrate the improvement of simulation efficiency and convergence performance. © 2013 IEEE.

    DOI

  • Numerical integration algorithms with artificial damping for the PTA method applied to DC analysis of nonlinear circuits

    Xiao Wu, Zhou Jin, Yasuaki Inoue

    2013 International Conference on Communications, Circuits and Systems, ICCCAS 2013   1   421 - 424  2013年

     概要を見る

    In this paper, new numerical integration algorithms with artificial damping effect are proposed which can be applied to the constant, pure PTA method to find DC operating points of nonlinear circuits when the Newton-Raphson method fails. This method can effectively avoid the oscillation and the 'time step too small' problems compared with conventional PTA algorithms. The mathematical description for this method is presented. The application of the proposed method is illustrated by solving practical CMOS nonlinear circuits. © 2013 IEEE.

    DOI

  • An analytical model of the overshooting effect for multiple-input gates in nanometer technologies

    Li Ding, Jing Wang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

    Proceedings - IEEE International Symposium on Circuits and Systems     1712 - 1715  2013年

     概要を見る

    The overshooting effect, which is induced by the input-to-output coupling capacitance, has an significant effect on CMOS gate delay with the scaling of CMOS technology. In this paper, an effective analytical model is proposed to calculate the overshooting time of multiple-input gates. The proposed model is verified having a good agreement with SPICE simulation results. © 2013 IEEE.

    DOI

  • Optimum capacitance ratio for Cockcroft-Walton charge pump

    Yawen Yang, Qiang Li, Yasuaki Inoue

    Proceedings The 28th International Technical Conference on Circuits/Systems, Computer and Communications (ITC-CSCC2013)     208 - 211  2013年

  • An effective ramping PTA method for the DC analysis of nonlinear circuits

    Zhou JIN, Xiao WU, Xiaoli GUAN, Dan NIU, Yasuaki INOUE

    Proceedings The 28th International Technical Conference on Circuits/Systems, Computer and Communications (ITC-CSCC2013)     317 - 320  2013年

  • An effective switching algorithm for the damped pseudo-transient analysis

    Xiao WU, Zhou JIN, Xiuming LIAN, Dan NIU, Yasuaki INOUE

    Proceedings The 28th International Technical Conference on Circuits/Systems, Computer and Communications (ITC-CSCC2013)     922 - 925  2013年

  • A wide input amplitude range, highly efficient rectifier for low power energy harvesting systems

    Qian Li, Jing Wang, Dan Niu, Yasuaki Inoue

    Proceedings 2013 The International Conference on Electrical Engineering (ICEE2013)     199 - 203  2013年

  • An effective method to calculate the overshooting time of multi-input gates

    Yu LI, Li DING, Jin WANG, Yasuaki INOUE

    第21回 電子情報通信学会九州支部学生会講演会論文集 - The 21th IEICE Kyushu Section Gakusekaikoenkai -     A-9  2013年

  • A low temperature coefficient low-voltage CMOS voltage reference

    Wei ZHOU, Zhangcai HUANG, Jing WANG, Qiang LI, Yasuaki INOUE

    第21回 電子情報通信学会九州支部学生会講演会論文集 - The 21th IEICE Kyushu Section Gakusekaikoenkai -     C-23  2013年

  • An almost 3VDD rail-to-rail output amplifier using VDD CMOSFETs

    Yingqian Dai, Qiang Li, Yasuaki Inoue

    第21回 電子情報通信学会九州支部学生会講演会論文集 - The 21th IEICE Kyushu Section Gakusekaikoenkai -     C-29  2013年

  • A wide input amplitude range, highly efficient rectifier for energy harvesting systems

    Qiang Li, Dan Niu, Yasuaki Inoue

    Proceedings 2013 International Conference on Analog VLSI Circuits (AVIC2013)     31 - 35  2013年

  • Effective implementation and embedding algorithms of CEPTA method for finding DC operating points

    Zhou Jin, Xiao Wu, Dan Niu, Yasuaki Inoue

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E96-A ( 12 ) 2524 - 2532  2013年

     概要を見る

    Recently, the compound element pseudo transient analysis, CEPTA, method is regarded as an efficient practical method to find DC operating points of nonlinear circuits when the Newton-Raphson method fails. In the previous CEPTA method, an effective SPICE3 implementation algorithm was proposed without expanding the Jacobian matrix. However the limitation of step size was not well considered. Thus, the non-convergence problem occurs and the simulation efficiency is still a big challenge for current LSI nonlinear cicuits, especially for some practical large-scale circuits. Therefore, in this paper, we propose a new SPICE3 implementation algorithm and an embedding algorithm, which is where to insert the pseudo capacitors, for the CEPTA method. The proposed implementation algorithm has no limitation for step size and can significantly improve simulation efficiency. Considering the existence of various types of circuits, we extend some possible embedding positions. Numerical examples demonstrate the improvement of simulation efficiency and convergence performance.© 2013 The Institute of Electronics, Information and Communication Engineers.

    DOI

  • A simple and practical statistical device model for analog LSI designs

    Jing Wang, Li Ding, Yasuaki Inoue

    2013 International Conference on Communications, Circuits and Systems, ICCCAS 2013   1   408 - 412  2013年

     概要を見る

    With the scaling of CMOS devices toward their ultimate dimensions, device performance variability induced by process variation has become a critical issue in analog LS I designs. Statistical device model library building based on statistical device model considering the process variation accurately is useful to predict the performance of analog LS I designs. However, conventional statistical device models are either complicated or not accurate enough. Therefore, a simple and practical statistical device model for analog LS I designs is proposed in this paper. Simultaneously, a simple method to extract model parameters is also proposed. Statistical analysis results of 0.65um CMOS Op-Amp based on the proposed model using Monte Carlo simulation have a good agreement with the chip measurement results. © 2013 IEEE.

    DOI

  • An effective implementation and embedding algorithm of PTA method for finding DC operating points

    Zhou Jin, Xiao Wu, Yasuaki Inoue

    2013 International Conference on Communications, Circuits and Systems, ICCCAS 2013   1   417 - 420  2013年

     概要を見る

    Recently, the compound element pseudo transient analysis method, CEPTA, is regarded as an efficient practical method to find DC operating points of nonlinear circuits when the Newton-Raphson method fails. In this paper, an effective SPICE3 implementation algorithm for the CEPTA method is proposed. It can significantly improve simulation efficiency with smaller limitations during simulation. Besides, the influence of different pseudo-elements' embedding positions on the simulation efficiency is also discussed and presented with numerical examples. Several numerical examples demonstrate the improvement of simulation efficiency and convergence performance. © 2013 IEEE.

    DOI

  • Numerical integration algorithms with artificial damping for the PTA method applied to DC analysis of nonlinear circuits

    Xiao Wu, Zhou Jin, Yasuaki Inoue

    2013 International Conference on Communications, Circuits and Systems, ICCCAS 2013   1   421 - 424  2013年

     概要を見る

    In this paper, new numerical integration algorithms with artificial damping effect are proposed which can be applied to the constant, pure PTA method to find DC operating points of nonlinear circuits when the Newton-Raphson method fails. This method can effectively avoid the oscillation and the 'time step too small' problems compared with conventional PTA algorithms. The mathematical description for this method is presented. The application of the proposed method is illustrated by solving practical CMOS nonlinear circuits. © 2013 IEEE.

    DOI

  • An analytical model of the overshooting effect for multiple-input gates in nanometer technologies

    Li Ding, Jing Wang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

    Proceedings - IEEE International Symposium on Circuits and Systems     1712 - 1715  2013年

     概要を見る

    The overshooting effect, which is induced by the input-to-output coupling capacitance, has an significant effect on CMOS gate delay with the scaling of CMOS technology. In this paper, an effective analytical model is proposed to calculate the overshooting time of multiple-input gates. The proposed model is verified having a good agreement with SPICE simulation results. © 2013 IEEE.

    DOI

  • Optimum capacitance ratio for Cockcroft-Walton charge pump

    Yawen Yang, Qiang Li, Yasuaki Inoue

    Proceedings The 28th International Technical Conference on Circuits/Systems, Computer and Communications (ITC-CSCC2013)     208 - 211  2013年

  • An effective ramping PTA method for the DC analysis of nonlinear circuits

    Zhou JIN, Xiao WU, Xiaoli GUAN, Dan NIU, Yasuaki INOUE

    Proceedings The 28th International Technical Conference on Circuits/Systems, Computer and Communications (ITC-CSCC2013)     317 - 320  2013年

  • An effective switching algorithm for the damped pseudo-transient analysis

    Xiao WU, Zhou JIN, Xiuming LIAN, Dan NIU, Yasuaki INOUE

    Proceedings The 28th International Technical Conference on Circuits/Systems, Computer and Communications (ITC-CSCC2013)     922 - 925  2013年

  • A wide input amplitude range, highly efficient rectifier for low power energy harvesting systems

    Qian Li, Jing Wang, Dan Niu, Yasuaki Inoue

    Proceedings 2013 The International Conference on Electrical Engineering (ICEE2013)     199 - 203  2013年

  • An effective method to calculate the overshooting time of multi-input gates

    Yu LI, Li DING, Jin WANG, Yasuaki INOUE

    第21回 電子情報通信学会九州支部学生会講演会論文集 - The 21th IEICE Kyushu Section Gakusekaikoenkai -     A-9  2013年

  • A low temperature coefficient low-voltage CMOS voltage reference

    Wei ZHOU, Zhangcai HUANG, Jing WANG, Qiang LI, Yasuaki INOUE

    第21回 電子情報通信学会九州支部学生会講演会論文集 - The 21th IEICE Kyushu Section Gakusekaikoenkai -     C-23  2013年

  • An almost 3VDD rail-to-rail output amplifier using VDD CMOSFETs

    Yingqian Dai, Qiang Li, Yasuaki Inoue

    第21回 電子情報通信学会九州支部学生会講演会論文集 - The 21th IEICE Kyushu Section Gakusekaikoenkai -     C-29  2013年

  • A wide input amplitude range, highly efficient rectifier for energy harvesting systems

    Qiang Li, Dan Niu, Yasuaki Inoue

    Proceedings 2013 International Conference on Analog VLSI Circuits (AVIC2013)     31 - 35  2013年

  • Effective implementation and embedding algorithms of CEPTA method for finding DC operating points

    Zhou Jin, Xiao Wu, Dan Niu, Yasuaki Inoue

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E96-A ( 12 ) 2524 - 2532  2013年

     概要を見る

    Recently, the compound element pseudo transient analysis, CEPTA, method is regarded as an efficient practical method to find DC operating points of nonlinear circuits when the Newton-Raphson method fails. In the previous CEPTA method, an effective SPICE3 implementation algorithm was proposed without expanding the Jacobian matrix. However the limitation of step size was not well considered. Thus, the non-convergence problem occurs and the simulation efficiency is still a big challenge for current LSI nonlinear cicuits, especially for some practical large-scale circuits. Therefore, in this paper, we propose a new SPICE3 implementation algorithm and an embedding algorithm, which is where to insert the pseudo capacitors, for the CEPTA method. The proposed implementation algorithm has no limitation for step size and can significantly improve simulation efficiency. Considering the existence of various types of circuits, we extend some possible embedding positions. Numerical examples demonstrate the improvement of simulation efficiency and convergence performance.© 2013 The Institute of Electronics, Information and Communication Engineers.

    DOI

  • A Globally Convergent Nonlinear Homotopy Method for MOS Transistor Circuits

    Dan Niu, Kazutoshi Sako, Guangming Hu, Yasuaki Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E95A ( 12 ) 2251 - 2260  2012年12月

     概要を見る

    Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. However, most previous studies are mainly focused on the bipolar transistor circuits and no paper presents the global convergence theorems of homotopy methods for MOS transistor circuits. Moreover, due to the improvements and advantages of MOS transistor technologies, extending the homotopy methods to MOS transistor circuits becomes more and more necessary and important. This paper proposes two nonlinear homotopy methods for MOS transistor circuits and proves the global convergence theorems for the proposed MOS nonlinear homotopy method II. Numerical examples show that both of the two proposed homotopy methods for MOS transistor circuits are more effective for finding DC operating points than the conventional MOS homotopy method and they are also capable of finding DC operating points for large-scale circuits.

    DOI

  • A Globally Convergent Nonlinear Homotopy Method for MOS Transistor Circuits

    Dan Niu, Kazutoshi Sako, Guangming Hu, Yasuaki Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E95A ( 12 ) 2251 - 2260  2012年12月

     概要を見る

    Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. However, most previous studies are mainly focused on the bipolar transistor circuits and no paper presents the global convergence theorems of homotopy methods for MOS transistor circuits. Moreover, due to the improvements and advantages of MOS transistor technologies, extending the homotopy methods to MOS transistor circuits becomes more and more necessary and important. This paper proposes two nonlinear homotopy methods for MOS transistor circuits and proves the global convergence theorems for the proposed MOS nonlinear homotopy method II. Numerical examples show that both of the two proposed homotopy methods for MOS transistor circuits are more effective for finding DC operating points than the conventional MOS homotopy method and they are also capable of finding DC operating points for large-scale circuits.

    DOI

  • MODELING THE OVERSHOOTING EFFECT OF MULTI-INPUT GATE IN NANOMETER TECHNOLOGIES

    Li Ding, Zhangcai Huang, Minglu Jiang, Atsushi Kurokawa, Yasuaki Inoue

    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS   21 ( 6 ) 1240012 - 13  2012年10月

     概要を見る

    With the advent of nanometer age in digital circuits, the overshooting time becomes an important component of gate delay for CMOS logic gates. However, there has been little attention paid to the research of the overshooting effect for multi-input gate in nanometer technologies until now. Therefore, in this paper, an effective model considering the overshooting effect of multi-input gate is presented. The experimental results using 32-nm PTM model reflect that the proposed model is accurate within 3.6% error compared with SPICE simulation results.

    DOI

  • MODELING THE OVERSHOOTING EFFECT OF MULTI-INPUT GATE IN NANOMETER TECHNOLOGIES

    Li Ding, Zhangcai Huang, Minglu Jiang, Atsushi Kurokawa, Yasuaki Inoue

    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS   21 ( 6 ) 1240012 - 13  2012年10月

     概要を見る

    With the advent of nanometer age in digital circuits, the overshooting time becomes an important component of gate delay for CMOS logic gates. However, there has been little attention paid to the research of the overshooting effect for multi-input gate in nanometer technologies until now. Therefore, in this paper, an effective model considering the overshooting effect of multi-input gate is presented. The experimental results using 32-nm PTM model reflect that the proposed model is accurate within 3.6% error compared with SPICE simulation results.

    DOI

  • A Retargeting Methodology of Nano-watt CMOS Reference Circuit based on Advanced Compact MOSFET Model

    Gong Chen, Bo Yang, Shigetoshi Nakatake, Zhangcai Huang, Yasuaki Inoue

    2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012)     938 - 941  2012年

     概要を見る

    In retargeting of a nano-watt CMOS reference circuit, we adopt an advanced compact MOSFET model to describe the drain current consistently in strong and weak inversion levels. Based on this model, we describe all bias conditions in terms of ratios of the channel widths and lengths. Taking the effect of very long channels into account, we formulate the threshold voltage as a function of the drain-source voltage. Furthermore, we introduce a tuning parameter with the empirical range and fix all transistor sizes sweeping this parameter as well as applying a simulation. In case studies, we retargeted a circuit from the 180nm/1.8V process to the 90nm/1.2V, 2.5V, 3.3V processes. Besides, we fabricated the circuit in the 90nm/1.2V process, and confirmed the good measurement results such as less than 12.8%/V supply voltage variation and only 1.1nW power consumption.

    DOI

  • A sub-0.3V highly efficient CMOS rectifier for energy harvesting applications

    Dan Niu, Zhangcai Huang, Minglu Jiang, Yasuaki Inoue

    Nonlinear Theory and Its Applications, IEICE   3 ( 3 ) 405 - 416  2012年

     概要を見る

    This paper presents a sub-0.3V CMOS full-wave rectifier for energy harvesting devices. By adopting a body-input comparator with simple bias circuit, combining with body bias technique, the lowest input voltage amplitude can be reduced to 0.28V when using a standard CMOS 0.18µm process. Moreover, the voltage drop of negative voltage converter can be reduced to enhance the output voltage efficiency by adopting the proposed body bias technique. In combination with minimum reverse current and simple bias circuit in the proposed comparator, the proposed active rectifier can achieve the peak voltage conversion efficiency of over 96% and the maximum power efficiency of approximately 94%.

    DOI CiNii

  • An Effective and Globally Convergent Newton Fixed-Point Homotopy Method for MOS Transistor Circuits

    Dan NIU, Ziming ZHAO, Yasuaki INOUE

    電子情報通信学会技術研究報告NLP2012-53   112 ( 117 ) 85 - 90  2012年

     概要を見る

    非線形回路の直流動作点を求めることは重要かつ困難な問題である。SPICE系の回路シミュレータに採用されているNewton-Raphson(NR)法はしばしば解に収束しない。このような問題に対して、ホモトピー法がさまざまな観点から研究されてきた。しかしながら、従来のほとんどの研究は、主としてバイポーラ・トランジスタ回路に対するもので、MOSトランジスタ回路にそのまま適用しても効率は必ずしもよくない。したがって、MOSトランジスタ回路のためのより効率的なホモトピー法を研究することが重要になる。本稿はニュートン不動点ホモトピー法をMOSトランジスタ回路に対して拡張する。数値例では、拡張されたニュートン不動点ホモトピー法が従来のMOSホモトピー法およびMOS非線形ホモトピー法より、特に大規模MOSトランジスタ回路において、有効なことを示す。本稿では更に、MOSトランジスタ回路のための拡張されたニュートン不動点ホモトピー法の大域収束性も証明している。

    CiNii

  • 直流動作点求解のための複合擬似素子擬似過渡解析法の効果的な実装手法と埋め込み手法

    金洲,呉梟,牛丹, 井上靖秋

    電気学会研究会資料 電子回路研究会   ECT-12-077   87 - 91  2012年

  • A Globally Convergent and Highly Ffficient Homotopy Method for MOS Transistor Circuits

    Dan Niu, Zhou Jin, Xiao Wu, Yasuaki Inoue

    2012 7TH INTERNATIONAL CONFERENCE ON COMPUTING AND CONVERGENCE TECHNOLOGY (ICCCT2012)     1349 - 1352  2012年

     概要を見る

    Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. to overcome this convergence problem, homotopy methods have been studied from various viewpoints. However, most previous studies are mainly focused on the bipolar transistor circuits. Also the efficiencies of the previous homotopy methods for MOS transistor circuits are not satisfactory. Therefore, finding a more efficient homotopy method for MOS transistor circuits becomes necessary and important. This paper proposes the Newton Fixed-Point homotopy method for MOS transistor circuits and also proposes the embedding algorithm in the implementation. Numerical examples show that the proposed MOS Newton Fixed-Point homotopy methods with two embedding types are more effective for finding DC operating points of MOS transistor circuits than the conventional MOS homotopy methods. Moreover, the global convergence of the proposed Newton Fixed-Point homotopy method for MOS transistor circuits has also been proved.

  • A Retargeting Methodology of Nano-watt CMOS Reference Circuit based on Advanced Compact MOSFET Model

    Gong Chen, Bo Yang, Shigetoshi Nakatake, Zhangcai Huang, Yasuaki Inoue

    2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012)     938 - 941  2012年

     概要を見る

    In retargeting of a nano-watt CMOS reference circuit, we adopt an advanced compact MOSFET model to describe the drain current consistently in strong and weak inversion levels. Based on this model, we describe all bias conditions in terms of ratios of the channel widths and lengths. Taking the effect of very long channels into account, we formulate the threshold voltage as a function of the drain-source voltage. Furthermore, we introduce a tuning parameter with the empirical range and fix all transistor sizes sweeping this parameter as well as applying a simulation. In case studies, we retargeted a circuit from the 180nm/1.8V process to the 90nm/1.2V, 2.5V, 3.3V processes. Besides, we fabricated the circuit in the 90nm/1.2V process, and confirmed the good measurement results such as less than 12.8%/V supply voltage variation and only 1.1nW power consumption.

    DOI

  • A sub-0.3V highly efficient CMOS rectifier for energy harvesting applications

    Niu Dan, Huang Zhangcai, Jiang Minglu, Inoue Yasuaki

    Nonlinear Theory and Its Applications, IEICE   3 ( 3 ) 405 - 416  2012年

     概要を見る

    This paper presents a sub-0.3V CMOS full-wave rectifier for energy harvesting devices. By adopting a body-input comparator with simple bias circuit, combining with body bias technique, the lowest input voltage amplitude can be reduced to 0.28V when using a standard CMOS 0.18µm process. Moreover, the voltage drop of negative voltage converter can be reduced to enhance the output voltage efficiency by adopting the proposed body bias technique. In combination with minimum reverse current and simple bias circuit in the proposed comparator, the proposed active rectifier can achieve the peak voltage conversion efficiency of over 96% and the maximum power efficiency of approximately 94%.

    DOI CiNii

  • MOSトランジスタ回路に対する効果的な大域的収束性をもつニュートン不動点ホモトピー法

    牛 丹, 趙 子銘, 井上 靖秋

    電子情報通信学会技術研究報告. NLP, 非線形問題   112 ( 117 ) 85 - 90  2012年

     概要を見る

    非線形回路の直流動作点を求めることは重要かつ困難な問題である。SPICE系の回路シミュレータに採用されているNewton-Raphson(NR)法はしばしば解に収束しない。このような問題に対して、ホモトピー法がさまざまな観点から研究されてきた。しかしながら、従来のほとんどの研究は、主としてバイポーラ・トランジスタ回路に対するもので、MOSトランジスタ回路にそのまま適用しても効率は必ずしもよくない。したがって、MOSトランジスタ回路のためのより効率的なホモトピー法を研究することが重要になる。本稿はニュートン不動点ホモトピー法をMOSトランジスタ回路に対して拡張する。数値例では、拡張されたニュートン不動点ホモトピー法が従来のMOSホモトピー法およびMOS非線形ホモトピー法より、特に大規模MOSトランジスタ回路において、有効なことを示す。本稿では更に、MOSトランジスタ回路のための拡張されたニュートン不動点ホモトピー法の大域収束性も証明している。

    CiNii

  • 直流動作点求解のための複合擬似素子擬似過渡解析法の効果的な実装手法と埋め込み手法

    金洲,呉梟,牛丹, 井上靖秋

    電気学会研究会資料 電子回路研究会   ECT-12-077   87 - 91  2012年

  • A Globally Convergent and Highly Ffficient Homotopy Method for MOS Transistor Circuits

    Dan Niu, Zhou Jin, Xiao Wu, Yasuaki Inoue

    2012 7TH INTERNATIONAL CONFERENCE ON COMPUTING AND CONVERGENCE TECHNOLOGY (ICCCT2012)     1349 - 1352  2012年

     概要を見る

    Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. to overcome this convergence problem, homotopy methods have been studied from various viewpoints. However, most previous studies are mainly focused on the bipolar transistor circuits. Also the efficiencies of the previous homotopy methods for MOS transistor circuits are not satisfactory. Therefore, finding a more efficient homotopy method for MOS transistor circuits becomes necessary and important. This paper proposes the Newton Fixed-Point homotopy method for MOS transistor circuits and also proposes the embedding algorithm in the implementation. Numerical examples show that the proposed MOS Newton Fixed-Point homotopy methods with two embedding types are more effective for finding DC operating points of MOS transistor circuits than the conventional MOS homotopy methods. Moreover, the global convergence of the proposed Newton Fixed-Point homotopy method for MOS transistor circuits has also been proved.

  • A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect

    Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Qiang Li, Bin Lin, Yasuaki Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E94A ( 5 ) 1201 - 1209  2011年05月

     概要を見る

    Gate delay evaluation is always a vital concern for high-performance digital VLSI designs. As the feature size of VLSIs decreases to the nano-meter region, the work to obtain an accurate gate delay value becomes more difficult and time consuming than ever. The conventional methods usually use iterative algorithms to ensure the accuracy of the effective capacitance C-eff, which is usually used to compute the gate delay with interconnect loads and to capture the output signal shape of the real gate response. Accordingly, the efficiency is sacrificed. In this paper, an accurate and efficient approach is proposed for gate delay estimation. With the linear relationship of gate output time points and C-eff, a polynomial approximation is used to make the nonlinear effective capacitance equation be solved without iterative method. Compared to the conventional methods, the proposed method improves the efficiency of gate delay calculation. Meanwhile, experimental results show that the proposed method is in good agreement with SPICE results and the average error is 2.8%.

    DOI CiNii

  • A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect

    Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Qiang Li, Bin Lin, Yasuaki Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E94A ( 5 ) 1201 - 1209  2011年05月

     概要を見る

    Gate delay evaluation is always a vital concern for high-performance digital VLSI designs. As the feature size of VLSIs decreases to the nano-meter region, the work to obtain an accurate gate delay value becomes more difficult and time consuming than ever. The conventional methods usually use iterative algorithms to ensure the accuracy of the effective capacitance C-eff, which is usually used to compute the gate delay with interconnect loads and to capture the output signal shape of the real gate response. Accordingly, the efficiency is sacrificed. In this paper, an accurate and efficient approach is proposed for gate delay estimation. With the linear relationship of gate output time points and C-eff, a polynomial approximation is used to make the nonlinear effective capacitance equation be solved without iterative method. Compared to the conventional methods, the proposed method improves the efficiency of gate delay calculation. Meanwhile, experimental results show that the proposed method is in good agreement with SPICE results and the average error is 2.8%.

    DOI CiNii

  • Theorems on the global convergence of the nonlinear homotopy method for MOS circuits

    Dan Niu, Guangming Hu, Yasuaki Inoue

    Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics     41 - 44  2011年

     概要を見る

    Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. However most previous studies are mainly focused on the bipolar transistor circuits and no paper presents the global convergence of the homotopy method for MOS circuits. This paper extends the nonlinear homotopy method to MOS transistor circuits and presents the global convergence theorems of the homotopy method for MOS circuits. © 2011 IEEE.

    DOI

  • An Almost 2VDD Rail-to-Rail Input and Output Operational Amplifier Using VDD CMOSFETs

    Yasuaki Inoue, Changquan Jin, Zhao Chen, Zhangcai Huang

    Proceedings IEEJ 2011 International Analog VLSI Workshop, Bali, Indonesia     5 - 8  2011年

  • Theorems on the global convergence of the nonlinear homotopy method for MOS circuits

    Dan Niu, Guangming Hu, Yasuaki Inoue

    Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics     41 - 44  2011年

     概要を見る

    Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. However most previous studies are mainly focused on the bipolar transistor circuits and no paper presents the global convergence of the homotopy method for MOS circuits. This paper extends the nonlinear homotopy method to MOS transistor circuits and presents the global convergence theorems of the homotopy method for MOS circuits. © 2011 IEEE.

    DOI

  • An Almost 2VDD Rail-to-Rail Input and Output Operational Amplifier Using VDD CMOSFETs

    Yasuaki Inoue, Changquan Jin, Zhao Chen, Zhangcai Huang

    Proceedings IEEJ 2011 International Analog VLSI Workshop, Bali, Indonesia     5 - 8  2011年

  • A Sub-100nA Power Management System for Wireless Structure Health Monitoring Applications

    Zhangcai Huang, Yasuaki Inoue

    2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)     2897 - 2900  2011年

     概要を見る

    Recently, the power management becomes significantly important for the ultra power wireless sensor node powered by energy harvesting devices. In this paper, a power management system from battery to wireless sensor node is proposed for wireless structure health monitoring applications. By using the proposed circuits, the power supply of a sensor network node is switched on only when some event is detected to reduce its average power consumption. In the proposed circuit, the nanopower reference is utilized to bias control circuits. Therefore, the proposed management system has an extremely low power consumption of less than 100nA standby current. The proposed circuits are implemented with a 1.2 mu m CMOS process. Experimental results demonstrate the low power feature of the proposed power management system.

    DOI

  • A Sub-0.3V CMOS Rectifier for Energy Harvesting Applications

    Dan Niu, Zhangcai Huang, Minglu Jiang, Yasuaki Inoue

    Proceedings 54th IEEE International Midwest Symposium on Circuits and Systems (IEEE MWSCAS 2011), Seoul, Korea     Ta2B  2011年

    DOI

  • Modeling the Overshooting Effect of Multi-input Gate in Nanometer Technologies

    Li Ding, Zhangcai Huang, Minglu Jiang, Atsushi Kurokawa, Yasuaki Inoue

    Proceedings 54th IEEE International Midwest Symposium on Circuits and Systems (IEEE MWSCAS 2011), Seoul, Korea     Wa1E  2011年

    DOI

  • A Sub-100nA Power Management System for Wireless Structure Health Monitoring Applications

    Zhangcai Huang, Yasuaki Inoue

    2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)     2897 - 2900  2011年

     概要を見る

    Recently, the power management becomes significantly important for the ultra power wireless sensor node powered by energy harvesting devices. In this paper, a power management system from battery to wireless sensor node is proposed for wireless structure health monitoring applications. By using the proposed circuits, the power supply of a sensor network node is switched on only when some event is detected to reduce its average power consumption. In the proposed circuit, the nanopower reference is utilized to bias control circuits. Therefore, the proposed management system has an extremely low power consumption of less than 100nA standby current. The proposed circuits are implemented with a 1.2 mu m CMOS process. Experimental results demonstrate the low power feature of the proposed power management system.

    DOI

  • A Sub-0.3V CMOS Rectifier for Energy Harvesting Applications

    Dan Niu, Zhangcai Huang, Minglu Jiang, Yasuaki Inoue

    Proceedings 54th IEEE International Midwest Symposium on Circuits and Systems (IEEE MWSCAS 2011), Seoul, Korea     Ta2B  2011年

    DOI

  • Modeling the Overshooting Effect of Multi-input Gate in Nanometer Technologies

    Li Ding, Zhangcai Huang, Minglu Jiang, Atsushi Kurokawa, Yasuaki Inoue

    Proceedings 54th IEEE International Midwest Symposium on Circuits and Systems (IEEE MWSCAS 2011), Seoul, Korea     Wa1E  2011年

    DOI

  • Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies

    Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimoto, Takashi Sato, Minglu Jiang, Yasuaki Inoue

    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS   29 ( 2 ) 250 - 260  2010年02月

     概要を見る

    With the scaling of complementary metal-oxidesemiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacitance has more significant influence on CMOS gate analysis, especially on CMOS gate static timing analysis. In this paper, the overshooting effect is modeled for CMOS inverter delay analysis in nanometer technologies. The results produced by the proposed model are close to simulation program with integrated circuit emphasis (SPICE). Moreover, the influence of the overshooting effect on CMOS inverter analysis is discussed. An analytical model is presented to calculate the CMOS inverter delay time based on the proposed overshooting effect model, which is verified to be in good agreement with SPICE results. Furthermore, the proposed model is used to improve the accuracy of the switch-resistor model for approximating the inverter output waveform.

    DOI CiNii

  • Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies

    Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimoto, Takashi Sato, Minglu Jiang, Yasuaki Inoue

    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS   29 ( 2 ) 250 - 260  2010年02月

     概要を見る

    With the scaling of complementary metal-oxidesemiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacitance has more significant influence on CMOS gate analysis, especially on CMOS gate static timing analysis. In this paper, the overshooting effect is modeled for CMOS inverter delay analysis in nanometer technologies. The results produced by the proposed model are close to simulation program with integrated circuit emphasis (SPICE). Moreover, the influence of the overshooting effect on CMOS inverter analysis is discussed. An analytical model is presented to calculate the CMOS inverter delay time based on the proposed overshooting effect model, which is verified to be in good agreement with SPICE results. Furthermore, the proposed model is used to improve the accuracy of the switch-resistor model for approximating the inverter output waveform.

    DOI CiNii

  • A Bulk-Current Model for Advanced MOSFET Technologies Without Binning: Substrate Current and Fowler-Nordheim Current

    Ryosuke Inagaki, Norio Sadachika, Dondee Navarro, Mitiko Miura-Mattausch, Yasuaki Inoue

    IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING   5 ( 1 ) 96 - 104  2010年01月

     概要を見る

    A bulk-current model for advanced metal oxide semiconductor field effect transistors (MOSFETs) is proposed and implemented. The model consists of,in impact ionization mechanism, the drain to bulk current and a tunneling mechanism, the gate to bulk Current. and requires totally 21 model parameters covering all bias conditions. The simulated results With the parameter values reproduce measurements for any device size without binning. Validity of the model has been tested With Circuits, which are sensitive to the change of the stored charge due to impact ionization current and tunneling current. (C) 2010 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

    DOI CiNii

  • An Efficient Charge Pump Based on Cockcroft-Walton Structure

    Renyuan Zhang, Qiang Li, Zhangcai Huang, Minglv Jiang, Yasuaki Inoue

    電子情報通信学会第23回 回路とシステム軽井沢ワークショップ論文集     316 - 321  2010年

  • An Automatic Design Method for MOS Analog Circuits using Reduction of Independent Design Variables Based on Topological Constraints

    古川且洋, 井上靖秋, 北城三郎

    電子情報通信学会第22回 回路とシステム軽井沢ワークショップ論文集     315 - 320  2010年

  • A Low Voltage CMOS Rectifier for Low Power Battery-less Devices

    Qiang Li, Zhangcai Huang, Minglv Jiang, Renyuan Zhang, Yasuaki Inoue

    電子情報通信学会第23回 回路とシステム軽井沢ワークショップ論文集     306 - 311  2010年

  • Explicit Effective Capacitance Model for CMOS Gate with Interconnect Load

    Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

    電子情報通信学会第23回 回路とシステム軽井沢ワークショップ論文集     257 - 260  2010年

  • A Low Voltage CMOS Rectifier for Wirelessly Powered Devices

    Qiang Li, Renyuan Zhang, Zhangcai Huang, Yasuaki Inoue

    2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS     873 - 876  2010年

     概要を見る

    This paper presents a low voltage CMOS full-wave rectifier for wirelessly powered devices. By using a simple comparator-controlled switch, the lowest input voltage amplitude can be reduced to 0.7V when using a standard CMOS 0.18 mu m process. With only one comparator, the proposed design dramatically reduces the production cost. In combination with unbalanced transistor scale, the proposed rectifier can achieve a maximum peak voltage conversion efficiency of more than 93% and power efficiency near to 87%.

    DOI

  • A CMOS sub-1-V nanopower current and voltage reference with leakage compensation

    Zhangcai Huang, Qin Luo, Yasuaki Inoue

    ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems     4069 - 4072  2010年

     概要を見る

    In this paper, a CMOS sub-1-V nanopower reference is proposed, which is implemented without resistors and with only standard CMOS transistors. The proposed circuit has the most attractive merit that it can afford reference current and reference voltage simultaneously. Moreover, the leakage compensation technique is utilized, and thus it has very low temperature coefficient for a wide temperature range. The proposed circuit is verified by SPICE simulation with CMOS 0.18um process. The temperature coefficient of the reference voltage and reference current are 0.0037%/°C and 0.0091%/°C, respectively. Also, the power supply voltage can be as low as 0.85V and its power consumption is only 5.1nW. ©2010 IEEE.

    DOI

  • A non-iterative effective capacitance model for CMOS gate delay computing

    Minglu Jiang, Qiang Li, Zhangcai Huang, Yasuaki Inoue

    2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings     896 - 900  2010年

     概要を見る

    In Static Timing Analysis, the conventional methods usually use an iterative method to ensure the accuracy of the effective capacitance G ef f which is usually used to compute the delay of gate with interconnect load and to capture the output signal shape of the real gate response. In this paper, a polynomial approximation method is used to make the nonlinear Gef f equation be solved without iterative method. Compared to the conventional methods, the proposed method has the merit of improving the efficiency for Gef f calculation. Meanwhile, experimental results show that the proposed method is in agreement with the Spice simulation. © 2010 IEEE.

    DOI

  • A low voltage CMOS rectifier for low power battery-less devices

    Qiang Li, Zhangcai Huang, Renyuan Zhang, Minglv Jiang, Bin Lin, Yasuaki Inoue

    Nonlinear Theory and Its Applications, IEICE   1 ( 1 ) 186 - 195  2010年

     概要を見る

    This paper presents a low voltage CMOS full-wave rectifier for transcutaneous power transmission in low power battery-less devices such as biomedical implants. By using a simple comparator-controlled switch which needs a small supply voltage, the lowest input voltage amplitude can be reduced to 0.7V with a standard CMOS 0.18µm process. With only one comparator, the proposed design dramatically reduces the power loss and the production cost. In combination with current offset which minimize the reverse current of the rectifier under different input amplitudes, the proposed rectifier can achieve a maximum peak voltage conversion efficiency of more than 93% and a power efficiency of approximately 87%.

    DOI CiNii

  • A Bulk-Current Model for Advanced MOSFET Technologies Without Binning: Substrate Current and Fowler-Nordheim Current

    Ryosuke Inagaki, Norio Sadachika, Dondee Navarro, Mitiko Miura-Mattausch, Yasuaki Inoue

    IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING   5 ( 1 ) 96 - 104  2010年01月

     概要を見る

    A bulk-current model for advanced metal oxide semiconductor field effect transistors (MOSFETs) is proposed and implemented. The model consists of,in impact ionization mechanism, the drain to bulk current and a tunneling mechanism, the gate to bulk Current. and requires totally 21 model parameters covering all bias conditions. The simulated results With the parameter values reproduce measurements for any device size without binning. Validity of the model has been tested With Circuits, which are sensitive to the change of the stored charge due to impact ionization current and tunneling current. (C) 2010 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

    DOI CiNii

  • An Efficient Charge Pump Based on Cockcroft-Walton Structure

    Renyuan Zhang, Qiang Li, Zhangcai Huang, Minglv Jiang, Yasuaki Inoue

    電子情報通信学会第23回 回路とシステム軽井沢ワークショップ論文集     316 - 321  2010年

  • An Automatic Design Method for MOS Analog Circuits using Reduction of Independent Design Variables Based on Topological Constraints

    古川且洋, 井上靖秋, 北城三郎

    電子情報通信学会第22回 回路とシステム軽井沢ワークショップ論文集     315 - 320  2010年

  • A Low Voltage CMOS Rectifier for Low Power Battery-less Devices

    Qiang Li, Zhangcai Huang, Minglv Jiang, Renyuan Zhang, Yasuaki Inoue

    電子情報通信学会第23回 回路とシステム軽井沢ワークショップ論文集     306 - 311  2010年

  • Explicit Effective Capacitance Model for CMOS Gate with Interconnect Load

    Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

    電子情報通信学会第23回 回路とシステム軽井沢ワークショップ論文集     257 - 260  2010年

  • A Low Voltage CMOS Rectifier for Wirelessly Powered Devices

    Qiang Li, Renyuan Zhang, Zhangcai Huang, Yasuaki Inoue

    2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS     873 - 876  2010年

     概要を見る

    This paper presents a low voltage CMOS full-wave rectifier for wirelessly powered devices. By using a simple comparator-controlled switch, the lowest input voltage amplitude can be reduced to 0.7V when using a standard CMOS 0.18 mu m process. With only one comparator, the proposed design dramatically reduces the production cost. In combination with unbalanced transistor scale, the proposed rectifier can achieve a maximum peak voltage conversion efficiency of more than 93% and power efficiency near to 87%.

    DOI

  • A CMOS sub-1-V nanopower current and voltage reference with leakage compensation

    Zhangcai Huang, Qin Luo, Yasuaki Inoue

    ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems     4069 - 4072  2010年

     概要を見る

    In this paper, a CMOS sub-1-V nanopower reference is proposed, which is implemented without resistors and with only standard CMOS transistors. The proposed circuit has the most attractive merit that it can afford reference current and reference voltage simultaneously. Moreover, the leakage compensation technique is utilized, and thus it has very low temperature coefficient for a wide temperature range. The proposed circuit is verified by SPICE simulation with CMOS 0.18um process. The temperature coefficient of the reference voltage and reference current are 0.0037%/°C and 0.0091%/°C, respectively. Also, the power supply voltage can be as low as 0.85V and its power consumption is only 5.1nW. ©2010 IEEE.

    DOI

  • A non-iterative effective capacitance model for CMOS gate delay computing

    Minglu Jiang, Qiang Li, Zhangcai Huang, Yasuaki Inoue

    2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings     896 - 900  2010年

     概要を見る

    In Static Timing Analysis, the conventional methods usually use an iterative method to ensure the accuracy of the effective capacitance G ef f which is usually used to compute the delay of gate with interconnect load and to capture the output signal shape of the real gate response. In this paper, a polynomial approximation method is used to make the nonlinear Gef f equation be solved without iterative method. Compared to the conventional methods, the proposed method has the merit of improving the efficiency for Gef f calculation. Meanwhile, experimental results show that the proposed method is in agreement with the Spice simulation. © 2010 IEEE.

    DOI

  • A low voltage CMOS rectifier for low power battery-less devices

    Li Qiang, Huang Zhangcai, Zhang Renyuan, Jiang Minglv, Lin Bin, Inoue Yasuaki

    Nonlinear Theory and Its Applications, IEICE   1 ( 1 ) 186 - 195  2010年

     概要を見る

    This paper presents a low voltage CMOS full-wave rectifier for transcutaneous power transmission in low power battery-less devices such as biomedical implants. By using a simple comparator-controlled switch which needs a small supply voltage, the lowest input voltage amplitude can be reduced to 0.7V with a standard CMOS 0.18µm process. With only one comparator, the proposed design dramatically reduces the power loss and the production cost. In combination with current offset which minimize the reverse current of the rectifier under different input amplitudes, the proposed rectifier can achieve a maximum peak voltage conversion efficiency of more than 93% and a power efficiency of approximately 87%.

    DOI CiNii

  • Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model

    Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Shuai Fang, Yasuaki Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E92A ( 10 ) 2531 - 2539  2009年10月

     概要を見る

    In deep submicron designs, predicting gate delays with interconnect load is a noteworthy work for Static Timing Analysis (STA). The effective capacitance C-eff concept and the Thevenin model that replaces the gate with a linear resistor and a voltage source are usually used to calculate the delay of gate with interconnect load. In conventional methods, it is not considered that the charges transferred into interconnect load and C-eff in the Thevenin model rue not equal. The charge difference between interconnect load and C-eff has the large influence to the accuracy of computing C-eff. In this paper, an advanced effective capacitance model is proposed to consider the above problem in the Thevenin model, where the influence of the charge difference is modeled as one part of the effective capacitance to compute the gate delay. Experimental results show a significant improvement in accuracy when the charge difference between interconnect load and C-eff is considered.

    DOI CiNii

  • Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model

    Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Shuai Fang, Yasuaki Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E92A ( 10 ) 2531 - 2539  2009年10月

     概要を見る

    In deep submicron designs, predicting gate delays with interconnect load is a noteworthy work for Static Timing Analysis (STA). The effective capacitance C-eff concept and the Thevenin model that replaces the gate with a linear resistor and a voltage source are usually used to calculate the delay of gate with interconnect load. In conventional methods, it is not considered that the charges transferred into interconnect load and C-eff in the Thevenin model rue not equal. The charge difference between interconnect load and C-eff has the large influence to the accuracy of computing C-eff. In this paper, an advanced effective capacitance model is proposed to consider the above problem in the Thevenin model, where the influence of the charge difference is modeled as one part of the effective capacitance to compute the gate delay. Experimental results show a significant improvement in accuracy when the charge difference between interconnect load and C-eff is considered.

    DOI CiNii

  • A PN Junction-Current Model for Advanced MOSFET Technologies

    Ryosuke Inagaki, Norio Sadachika, Mitiko Miura-Mattausch, Yasuaki Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E92A ( 4 ) 983 - 989  2009年04月

     概要を見る

    A PN junction current model for advanced MOSFETs is proposed and implemented into HiSIM2, a complete surface-potential-based MOSFET model. The model includes forward diode currents and reverse diode currents, and requires a total of 13 model parameters covering all bias conditions. Model simulation results reproduce measurements for different device geometries over a wide range of bias and temperature values.

    DOI CiNii

  • A PN Junction-Current Model for Advanced MOSFET Technologies

    Ryosuke Inagaki, Norio Sadachika, Mitiko Miura-Mattausch, Yasuaki Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E92A ( 4 ) 983 - 989  2009年04月

     概要を見る

    A PN junction current model for advanced MOSFETs is proposed and implemented into HiSIM2, a complete surface-potential-based MOSFET model. The model includes forward diode currents and reverse diode currents, and requires a total of 13 model parameters covering all bias conditions. Model simulation results reproduce measurements for different device geometries over a wide range of bias and temperature values.

    DOI CiNii

  • A GIDL-current model for advanced MOSFET technologies without binning

    Ryosuke Inagaki, Norio Sadachika, Dondee Navarro, Mitiko Miura-Mattausch, Yasuaki Inoue

    IPSJ Transactions on System LSI Design Methodology   2   93 - 102  2009年

     概要を見る

    A GIDL (Gate Induced Drain Leakage) current model for advanced MOS-FETs is proposed and implemented into HiSIM2, complete surface potential based MOSFET model. The model considers two tunneling mechanisms, the band-to-band tunneling and the trap assisted tunneling. Totally 7 model parameters are introduced. Simulation results of NFETs and PFETs reproduce measurements for any device size without binning of model parameters. The influence of the GIDL current is investigated with circuits, which are sensitive to the change of the stored charge due to the GIDL current. © 2009 Information Processing Society of Japan.

    DOI CiNii

  • ランダム曲面の性質と新しい曲面モデルの提案

    大川眞一, 増田弘生, 井上靖秋

    電子情報通信学会論文誌C   92-C ( 3 ) 85 - 93  2009年

  • ランダム曲面による空間相関の表現

    大川眞一, 青木正和, 増田弘生, 井上靖秋

    電子情報通信学会論文誌C   92-C ( 3 ) 75 - 84  2009年

  • A 5.26-nW 0.8-V CMOS Current and Voltage Reference Circuit Without Resistors

    Zhangcai Huang, Yubo Guo, Yasuaki Inoue

    電子情報通信学会第22回 回路とシステム軽井沢ワークショップ論文集     310 - 314  2009年

  • A Low Breakdown-voltage Charge Pump based on Cockcroft-Walton Structure

    Renyuan Zhang, Zhangcai Huang, Yasuaki Inoue

    2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS     328 - 331  2009年

     概要を見る

    A Cockcroft-Walton type charge pump circuit is proposed in this paper. Compared with Dickson type, each transistor and capacitor in the proposed circuit just stand against the voltage less than one Vdd, so that a low break-down voltage process can be applied to this kind of charge pump to reduce the chip area cost and break-down risk. By using the proposed structure, the performances of voltage boosting efficiency and power efficiency can reach 98.9% and 87%.

    DOI

  • A GIDL-current model for advanced MOSFET technologies without binning

    Ryosuke Inagaki, Norio Sadachika, Dondee Navarro, Mitiko Miura-Mattausch, Yasuaki Inoue

    IPSJ Transactions on System LSI Design Methodology   2   93 - 102  2009年

     概要を見る

    A GIDL (Gate Induced Drain Leakage) current model for advanced MOS-FETs is proposed and implemented into HiSIM2, complete surface potential based MOSFET model. The model considers two tunneling mechanisms, the band-to-band tunneling and the trap assisted tunneling. Totally 7 model parameters are introduced. Simulation results of NFETs and PFETs reproduce measurements for any device size without binning of model parameters. The influence of the GIDL current is investigated with circuits, which are sensitive to the change of the stored charge due to the GIDL current. © 2009 Information Processing Society of Japan.

    DOI CiNii

  • A 5.26-nW 0.8-V CMOS Current and Voltage Reference Circuit Without Resistors

    Zhangcai Huang, Yubo Guo, Yasuaki Inoue

    電子情報通信学会第22回 回路とシステム軽井沢ワークショップ論文集     310 - 314  2009年

  • A Low Breakdown-voltage Charge Pump based on Cockcroft-Walton Structure

    Renyuan Zhang, Zhangcai Huang, Yasuaki Inoue

    2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS     328 - 331  2009年

     概要を見る

    A Cockcroft-Walton type charge pump circuit is proposed in this paper. Compared with Dickson type, each transistor and capacitor in the proposed circuit just stand against the voltage less than one Vdd, so that a low break-down voltage process can be applied to this kind of charge pump to reduce the chip area cost and break-down risk. By using the proposed structure, the performances of voltage boosting efficiency and power efficiency can reach 98.9% and 87%.

    DOI

  • An Advanced Effective Capacitance Model for Calculating Gate Delay Considering Input Waveform Effect

    Jiang Minglu, Huang Zhangcai, Atsushi Kurokawa, Li Na, Yasuaki Inoue

    CHINESE JOURNAL OF ELECTRONICS   17 ( 4 ) 633 - 639  2008年10月

     概要を見る

    In deep submicron designs, predicting gate delay time is a noteworthy work for Static Timing Analysis. The effective capacitance C-eff concept is usually used to calculate the gate delay with interconnect loads. Conventionally, the input-signal to the gate is always assumed as a ramp waveform. However, the input signal is also the output of CMOS gates with interconnect loads and not the ramp waveform. Thus the simple assumption as a ramp signal results in significant influence on the delay calculation. In this paper, an advanced effective capacitance model is proposed to consider both the input waveform effect and the interconnect loads, where the nonlinear influence of input waveform is modeled as one part of the effective capacitance for calculating the gate delay. Experimental results show a significant improvement in accuracy when the input waveform effect is considered.

  • An Advanced Effective Capacitance Model for Calculating Gate Delay Considering Input Waveform Effect

    Jiang Minglu, Huang Zhangcai, Atsushi Kurokawa, Li Na, Yasuaki Inoue

    CHINESE JOURNAL OF ELECTRONICS   17 ( 4 ) 633 - 639  2008年10月

     概要を見る

    In deep submicron designs, predicting gate delay time is a noteworthy work for Static Timing Analysis. The effective capacitance C-eff concept is usually used to calculate the gate delay with interconnect loads. Conventionally, the input-signal to the gate is always assumed as a ramp waveform. However, the input signal is also the output of CMOS gates with interconnect loads and not the ramp waveform. Thus the simple assumption as a ramp signal results in significant influence on the delay calculation. In this paper, an advanced effective capacitance model is proposed to consider both the input waveform effect and the interconnect loads, where the nonlinear influence of input waveform is modeled as one part of the effective capacitance for calculating the gate delay. Experimental results show a significant improvement in accuracy when the input waveform effect is considered.

  • A 12-bit 3.7-MSample/s pipelined A/D Converter based on the novel capacitor mismatch calibration technique

    Shuaiqi Wang, Fule Li, Yasuaki Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 9 ) 2465 - 2474  2008年09月

     概要を見る

    This paper proposes a 12-bit 3.7-MS/s pipelined A/D Converter based on the novel capacitor mismatch calibration technique. The conventional stage is improved to an algorithmic circuit involving charge summing, capacitors' exchange and charge redistribution, simply through introducing some extra switches into the analog circuit. This proposed ADC obtains the linearity beyond the accuracy of the capacitor match and verifies the validity of reducing the nonlinear error from the capacitor mismatch to the second order without additional power dissipation through the novel capacitor mismatch calibration technique. It is processed in 0.5 mu m CMOS technology. The transistor-level simulation results show that 72.6 dB SNDR, 78.5 dB SFDR are obtained for a 2 V V-pp 159.144 kHz sine input sampled at 3.7 MS/s. The whole power dissipation of this ADC is 33.4 mW at the power supply of 5 V.

    DOI CiNii

  • A 12-bit 3.7-MSample/s pipelined A/D Converter based on the novel capacitor mismatch calibration technique

    Shuaiqi Wang, Fule Li, Yasuaki Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 9 ) 2465 - 2474  2008年09月

     概要を見る

    This paper proposes a 12-bit 3.7-MS/s pipelined A/D Converter based on the novel capacitor mismatch calibration technique. The conventional stage is improved to an algorithmic circuit involving charge summing, capacitors' exchange and charge redistribution, simply through introducing some extra switches into the analog circuit. This proposed ADC obtains the linearity beyond the accuracy of the capacitor match and verifies the validity of reducing the nonlinear error from the capacitor mismatch to the second order without additional power dissipation through the novel capacitor mismatch calibration technique. It is processed in 0.5 mu m CMOS technology. The transistor-level simulation results show that 72.6 dB SNDR, 78.5 dB SFDR are obtained for a 2 V V-pp 159.144 kHz sine input sampled at 3.7 MS/s. The whole power dissipation of this ADC is 33.4 mW at the power supply of 5 V.

    DOI CiNii

  • A novel expression of spatial correlation by a random curved surface model and its application to LSI design

    Shin-ichi Ohkawa, Hiroo Masuda, Yasuaki Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 4 ) 1062 - 1070  2008年04月

     概要を見る

    We have proposed a random curved surface model as a new mathematical concept which enables the expression of spatial correlation. The model gives us an appropriate methodology to deal with the systematic components of device variation in an LSI chip. The key idea of the model is the fitting of a polynomial to an array of Gaussian random numbers. The curved surface is expressed by a new extension from the Legendre polynomials to form two-dimensional formulas. The formulas were proven to be suitable to express the spatial correlation with reasonable computational complexity. In this paper, we show that this approach is useful in analyzing characteristics of device variation of actual chips by using experimental data.

    DOI CiNii

  • A novel expression of spatial correlation by a random curved surface model and its application to LSI design

    Shin-ichi Ohkawa, Hiroo Masuda, Yasuaki Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 4 ) 1062 - 1070  2008年04月

     概要を見る

    We have proposed a random curved surface model as a new mathematical concept which enables the expression of spatial correlation. The model gives us an appropriate methodology to deal with the systematic components of device variation in an LSI chip. The key idea of the model is the fitting of a polynomial to an array of Gaussian random numbers. The curved surface is expressed by a new extension from the Legendre polynomials to form two-dimensional formulas. The formulas were proven to be suitable to express the spatial correlation with reasonable computational complexity. In this paper, we show that this approach is useful in analyzing characteristics of device variation of actual chips by using experimental data.

    DOI CiNii

  • A gate-current model for advanced MOSFET technologies implemented into HiSIM2

    Ryosuke Inagaki, Norio Sadachika, Dondee Navarro, Mitiko Miura-Mattausch, Yasuaki Inoue

    IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING   3 ( 1 ) 64 - 71  2008年01月

     概要を見る

    A gate leakage current model for advanced MOSFETs; has been developed and implemented into the Hiroshima-university STARC IGFET Model (HiSIM), the first complete surface-potential-based model. The model consists of four tunneling mechanisms, the gate to channel/bulk/source/drain, and requires totally 15 model parameters covering all bias conditions. Simulation results reproduce measurement for any device size and temperature without binning. Validity of the model has been tested with circuits that are sensitive to the change of stored charge due to tunneling current. (C) 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

    DOI CiNii

  • A 45nm stable SRAM structure for ultra low leakage power

    Sui Huang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

    電子情報通信学会第21回 回路とシステム軽井沢ワークショップ論文集     635 - 640  2008年

  • An advanced effective capacitance model considering input waveform effect

    Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

    電子情報通信学会第21回 回路とシステム軽井沢ワークショップ論文集     433 - 438  2008年

  • Four-phase all PMOS charge pump without body effects in standard CMOS technology

    Na Li, Zhangcai Huang, Minglu Jiang, Yasuaki Inoue

    電子情報通信学会第21回 回路とシステム軽井沢ワークショップ論文集     409 - 414  2008年

  • ランダム曲面モデルによる空間相関に関する考察

    大川 眞一, 増田 弘生, 井上 靖秋

    電子情報通信学会第21回 回路とシステム軽井沢ワークショップ論文集     305 - 310  2008年

  • An Algorithmic Stage Based on the Novel Capacitor Mismatch Calibration Technique

    Shuaiqi Wang, Fule Li, Yasuaki Inoue

    電子情報通信学会第21回 回路とシステム軽井沢ワークショップ論文集     87 - 90  2008年

  • Stability Analysis and Design for Amplifier-Based CMOS Analog Signal Processing Cells

    Zhangcai Huang, Yasuaki Inoue, Fayan Wang, Xuetao Sun

    2008 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1 AND 2     1238 - 1243  2008年

     概要を見る

    In this paper the stability analysis and design are presented for amplifier-based CMOS analog signal and information prooessing cells. By analyzing the influence of dominant pole of feedback path on the frequency response of feedback circuits, several design criteria are proposed to keep amplifier-based CMOS analog processing cells stable such as divider and square root. Moreover, several methods to avoid oscillation are discussed for amplifier-based CMOS analog signal and information processing cells. To verify the proposed design, test circuits are fabricated using CMOS 0.6 um process and experimental results show that the proposed analysis and design can be used to improve the stability of amplifier-based CMOS analog and information processing cells significantly.

    DOI

  • An Advanced Model for Calculating the Effective Capacitance Considering Input Waveform Effect

    Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

    2008 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1 AND 2     1221 - 1225  2008年

     概要を見る

    In deep submicron designs, predicting gate delays is a noteworthy work for Static Timing Analysis (STA). The effective capacitance C-eff concept is usually used to calculate the gate delay of interconnect load. Conventionally, the input-signal is assumed as ramp waveform. However, the input waveform is also the output of CMOS gates with interconnect wires. Thus the simple assumption as a ramp signal results in significant influence on the delay calculating. In this paper, an advanced effective capacitance model is proposed to consider both the input waveform effect and interconnect wire load, where the nonlinear influence of input waveform is modeled as one part of effective capacitance of capacitive load to compute the gate delay. Experimental results show a significant improvement in accuracy when the input waveform effect is considered.

    DOI

  • High Efficiency Four-phase All PMOS Charge Pump without Body Effects

    Na Li, Zhangcai Huang, Minglu Jiang, Yasuaki Inoue

    2008 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1 AND 2     1216 - 1220  2008年

     概要を見る

    In this paper, a four-phase all PMOS charge pump based on the voltage doubler structure is proposed. The proposed charge pump is designed in 1.8V 0.18 mu m standard CMOS process with high voltage boosting efficiency and little output tipple. Moreover, it solves the voltage overstress problem which exists in the conventional charge pump and eliminates the body effect as well by means of adding two auxiliary substrate switching PMOS transistors. The simulation results show that the proposed charge pump circuits have an improvement about 93.2% compared with the original two-phase Dickson charge pump and an improvement about 28.2% compared with the negative four-phase Dickson charge pump when the supply voltage is 1.8V. Moreover it can even work as long as the supply power voltage is larger than the threshold voltage, which makes it quite suitable to be utilized in low supply voltage applications.

    DOI

  • A Novel SRAM Structure for Leakage Power Suppression in 45nm Technology

    Sui Huang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

    2008 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1 AND 2     1203 - 1207  2008年

     概要を見る

    Due to aggressively scaling down the size of MOS transistor, leakage power dissipation becomes the key issue that is always concerned in SRAM design. In this paper, a novel structure named Dynamic Standby Mode SRAM is proposed, which is based on the theory that both raising negative supply voltage, Vss, and reducing the difference between Vdd and Vss to its limit could cut down leakage current substantially. Furthermore, the impact of performance and the cost of additional area are also carefully considered. The simulation results based on a 45nm technology model of BPTM (Berkeley Predictive Technology Method) show that 55.8% and 80.2% leakage power is saved compared to DRV method and Gated-Vdd SRAM, respectively [1] [2]. Meanwhile, the stability of SRAM is guaranteed by choosing an appropriate value of Vss.

    DOI

  • A gate-current model for advanced MOSFET technologies implemented into HiSIM2

    Ryosuke Inagaki, Norio Sadachika, Dondee Navarro, Mitiko Miura-Mattausch, Yasuaki Inoue

    IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING   3 ( 1 ) 64 - 71  2008年01月

     概要を見る

    A gate leakage current model for advanced MOSFETs; has been developed and implemented into the Hiroshima-university STARC IGFET Model (HiSIM), the first complete surface-potential-based model. The model consists of four tunneling mechanisms, the gate to channel/bulk/source/drain, and requires totally 15 model parameters covering all bias conditions. Simulation results reproduce measurement for any device size and temperature without binning. Validity of the model has been tested with circuits that are sensitive to the change of stored charge due to tunneling current. (C) 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

    DOI CiNii

  • A 45nm stable SRAM structure for ultra low leakage power

    Sui Huang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

    電子情報通信学会第21回 回路とシステム軽井沢ワークショップ論文集     635 - 640  2008年

  • An advanced effective capacitance model considering input waveform effect

    Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

    電子情報通信学会第21回 回路とシステム軽井沢ワークショップ論文集     433 - 438  2008年

  • Four-phase all PMOS charge pump without body effects in standard CMOS technology

    Na Li, Zhangcai Huang, Minglu Jiang, Yasuaki Inoue

    電子情報通信学会第21回 回路とシステム軽井沢ワークショップ論文集     409 - 414  2008年

  • An Algorithmic Stage Based on the Novel Capacitor Mismatch Calibration Technique

    Shuaiqi Wang, Fule Li, Yasuaki Inoue

    電子情報通信学会第21回 回路とシステム軽井沢ワークショップ論文集     87 - 90  2008年

  • Stability Analysis and Design for Amplifier-Based CMOS Analog Signal Processing Cells

    Zhangcai Huang, Yasuaki Inoue, Fayan Wang, Xuetao Sun

    2008 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1 AND 2     1238 - 1243  2008年

     概要を見る

    In this paper the stability analysis and design are presented for amplifier-based CMOS analog signal and information prooessing cells. By analyzing the influence of dominant pole of feedback path on the frequency response of feedback circuits, several design criteria are proposed to keep amplifier-based CMOS analog processing cells stable such as divider and square root. Moreover, several methods to avoid oscillation are discussed for amplifier-based CMOS analog signal and information processing cells. To verify the proposed design, test circuits are fabricated using CMOS 0.6 um process and experimental results show that the proposed analysis and design can be used to improve the stability of amplifier-based CMOS analog and information processing cells significantly.

    DOI

  • An Advanced Model for Calculating the Effective Capacitance Considering Input Waveform Effect

    Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

    Proceedings 2008 International Conference on Communications, Circuits and Systems (ICCCAS), Xiamen, China     1221 - 1225  2008年

    DOI

  • High Efficiency Four-phase All PMOS Charge Pump without Body Effects

    Na Li, Zhangcai Huang, Minglu Jiang, Yasuaki Inoue

    2008 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1 AND 2     1216 - 1220  2008年

     概要を見る

    In this paper, a four-phase all PMOS charge pump based on the voltage doubler structure is proposed. The proposed charge pump is designed in 1.8V 0.18 mu m standard CMOS process with high voltage boosting efficiency and little output tipple. Moreover, it solves the voltage overstress problem which exists in the conventional charge pump and eliminates the body effect as well by means of adding two auxiliary substrate switching PMOS transistors. The simulation results show that the proposed charge pump circuits have an improvement about 93.2% compared with the original two-phase Dickson charge pump and an improvement about 28.2% compared with the negative four-phase Dickson charge pump when the supply voltage is 1.8V. Moreover it can even work as long as the supply power voltage is larger than the threshold voltage, which makes it quite suitable to be utilized in low supply voltage applications.

    DOI

  • A Novel SRAM Structure for Leakage Power Suppression in 45nm Technology

    Sui Huang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

    2008 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1 AND 2     1203 - 1207  2008年

     概要を見る

    Due to aggressively scaling down the size of MOS transistor, leakage power dissipation becomes the key issue that is always concerned in SRAM design. In this paper, a novel structure named Dynamic Standby Mode SRAM is proposed, which is based on the theory that both raising negative supply voltage, Vss, and reducing the difference between Vdd and Vss to its limit could cut down leakage current substantially. Furthermore, the impact of performance and the cost of additional area are also carefully considered. The simulation results based on a 45nm technology model of BPTM (Berkeley Predictive Technology Method) show that 55.8% and 80.2% leakage power is saved compared to DRV method and Gated-Vdd SRAM, respectively [1] [2]. Meanwhile, the stability of SRAM is guaranteed by choosing an appropriate value of Vss.

    DOI

  • An energy management circuit for self-powered ubiquitous sensor modules using vibiration-based energy

    Jun Pan, Yasuaki Inoue, Zheng Liang

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E90A ( 10 ) 2116 - 2123  2007年10月

     概要を見る

    An energy management circuit is proposed for self-powered ubiquitous sensor modules using vibration-based energy. With the proposed circuit, the sensor modules work with low duty cycle operation. Moreover, a two-tank circuit as a part of the energy management circuit is utilized to solve the problem that the average power density of ambient energy always varies with time while the power consumption of the sensor modules is constant and larger than it. In addition, the long start-up time problem is also avoided with the timing control of the proposed energy management circuit. The CMOS implementation and silicon verification results of the proposed circuit are also presented. Its validity is further confirmed with a vibration-based energy generation. The sensor module is used to supervise the vibration of machines and transfer the vibration signal discontinuously. A piezoelectric element acts as the vibration-to-electricity converter to realize battery-free operation.

    DOI CiNii

  • An effective SPICE3 implementation of the compound element pseudo-transient algorithm

    Hong Yu, Yasuaki Inoue, Kazutoshi Sako, Xiaochuan Hu, Zhangcai Huang

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E90A ( 10 ) 2124 - 2131  2007年10月

     概要を見る

    The compound element pseudo-transient analysis (PTA) algorithm is an effective practical method for finding the DC operating point when the Newton-Raphson method fails. It is able to effectively prevent from the oscillation problems compared with conventional PTA algorithms. In this paper, an effective SPICE3 implementation method for the compound element PTA algorithm is proposed. It has the characteristic of not expanding the Jacobian matrix and not changing the Jacobian matrix structure when the pseudo-transient numerical simulation is being done. Thus a high simulation efficiency is guaranteed. The ability of the proposed SPICE3 implementation to avoid the oscillation problems and the simulation efficiency are demonstrated by examples.

    DOI CiNii

  • An energy management circuit for self-powered ubiquitous sensor modules using vibiration-based energy

    Jun Pan, Yasuaki Inoue, Zheng Liang

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E90A ( 10 ) 2116 - 2123  2007年10月

     概要を見る

    An energy management circuit is proposed for self-powered ubiquitous sensor modules using vibration-based energy. With the proposed circuit, the sensor modules work with low duty cycle operation. Moreover, a two-tank circuit as a part of the energy management circuit is utilized to solve the problem that the average power density of ambient energy always varies with time while the power consumption of the sensor modules is constant and larger than it. In addition, the long start-up time problem is also avoided with the timing control of the proposed energy management circuit. The CMOS implementation and silicon verification results of the proposed circuit are also presented. Its validity is further confirmed with a vibration-based energy generation. The sensor module is used to supervise the vibration of machines and transfer the vibration signal discontinuously. A piezoelectric element acts as the vibration-to-electricity converter to realize battery-free operation.

    DOI CiNii

  • An effective SPICE3 implementation of the compound element pseudo-transient algorithm

    Hong Yu, Yasuaki Inoue, Kazutoshi Sako, Xiaochuan Hu, Zhangcai Huang

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E90A ( 10 ) 2124 - 2131  2007年10月

     概要を見る

    The compound element pseudo-transient analysis (PTA) algorithm is an effective practical method for finding the DC operating point when the Newton-Raphson method fails. It is able to effectively prevent from the oscillation problems compared with conventional PTA algorithms. In this paper, an effective SPICE3 implementation method for the compound element PTA algorithm is proposed. It has the characteristic of not expanding the Jacobian matrix and not changing the Jacobian matrix structure when the pseudo-transient numerical simulation is being done. Thus a high simulation efficiency is guaranteed. The ability of the proposed SPICE3 implementation to avoid the oscillation problems and the simulation efficiency are demonstrated by examples.

    DOI CiNii

  • A low-power sub-1-V low-voltage reference using body effect

    Jun Pan, Yasuaki Inoue, Zheng Liang, Zhangcai Huang, Weilun Huang

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E90A ( 4 ) 748 - 755  2007年04月

     概要を見る

    A low-power sub-1-V self-biased low-voltage reference is proposed for micropower electronic applications based on body effect. The proposed reference has a very low temperature dependence by using a MOSFET with body effect compared with other reported low-power references. An HSPICE simulation shows that the reference voltage and the total power dissipation are 181 mV and 1.1 mu W, respectively. The temperature coefficient of the reference voltage is 33 ppm/degrees C at temperatures from -40 to 100 degrees C. The supply voltage can be as low as 0.95 V in a standard CMOS 0.35 mu m technology with threshold voltages of about 0.5 V and -0.65 V for n-channel and p-channel MOSFETs, respectively. Furthermore, the supply voltage dependence is -0.36 mV/V (Vdd = 0.95-3.3 V).

    DOI CiNii

  • Behavioral circuit macromodeling and analog LSI implementation for automobile engine intake system

    Zhangcai Huang, Yasuaki Inoue, Hong Yu, Jun Pan, Yun Yang, Quan Zhang, Shuai Fang

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E90A ( 4 ) 732 - 740  2007年04月

     概要を見る

    Accurate estimating or measuring the intake manifold absolute pressure plays an important role in automobile engine control. In order to achieve the real-time estimation of the absolute pressure, the high accuracy and high speed processing ability are required for automobile engine control systems. Therefore, in this paper, an analog method is discussed and a fully integrated analog circuit is proposed to simulate automobile intake systems. Furthermore, a novel behavioral macromodeling is proposed for the analog circuit design. With the analog circuit, the intake manifold absolute pressure, which plays an important role for the effective automobile engine control, can be accurately estimated or measured in real time.

    DOI CiNii

  • A low-power sub-1-V low-voltage reference using body effect

    Jun Pan, Yasuaki Inoue, Zheng Liang, Zhangcai Huang, Weilun Huang

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E90A ( 4 ) 748 - 755  2007年04月

     概要を見る

    A low-power sub-1-V self-biased low-voltage reference is proposed for micropower electronic applications based on body effect. The proposed reference has a very low temperature dependence by using a MOSFET with body effect compared with other reported low-power references. An HSPICE simulation shows that the reference voltage and the total power dissipation are 181 mV and 1.1 mu W, respectively. The temperature coefficient of the reference voltage is 33 ppm/degrees C at temperatures from -40 to 100 degrees C. The supply voltage can be as low as 0.95 V in a standard CMOS 0.35 mu m technology with threshold voltages of about 0.5 V and -0.65 V for n-channel and p-channel MOSFETs, respectively. Furthermore, the supply voltage dependence is -0.36 mV/V (Vdd = 0.95-3.3 V).

    DOI CiNii

  • Behavioral circuit macromodeling and analog LSI implementation for automobile engine intake system

    Zhangcai Huang, Yasuaki Inoue, Hong Yu, Jun Pan, Yun Yang, Quan Zhang, Shuai Fang

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E90A ( 4 ) 732 - 740  2007年04月

     概要を見る

    Accurate estimating or measuring the intake manifold absolute pressure plays an important role in automobile engine control. In order to achieve the real-time estimation of the absolute pressure, the high accuracy and high speed processing ability are required for automobile engine control systems. Therefore, in this paper, an analog method is discussed and a fully integrated analog circuit is proposed to simulate automobile intake systems. Furthermore, a novel behavioral macromodeling is proposed for the analog circuit design. With the analog circuit, the intake manifold absolute pressure, which plays an important role for the effective automobile engine control, can be accurately estimated or measured in real time.

    DOI CiNii

  • A substrate-current model for advanced MOSFET technologies implemented into HiSIM2

    R. Inagaki, N. Sadachika, K. Konno, D. Navarro, Q. Ngo, C. Y. Yang, M. Miura-Mattausch, Y. Inoue

    Proceedings The 4th International Workshop on Compact Modeling, Yokohama, Japan     89 - 92  2007年

  • Modeling the overshooting effect for CMOS inverter in nanometer technologies

    Zhangcai Huang, Hong Yu, Atsushi Kurokawa, Yasuaki Inoue

    Proceedings 12th Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan     565 - 570  2007年

    DOI

  • A high efficiency all PMOS charge pump circuit without overstress in low-voltage CMOS process

    Jun Pan, Yasuaki Inoue

    電子情報通信学会第20回 回路とシステム軽井沢ワークショップ論文集     541 - 546  2007年

  • An ultra low-power high-speed rail-to-rail buffer amplifier for LCD source drivers

    Zheng Liang, Wei-Lun Huang, Jun Pan, Yasuaki Inoue

    電子情報通信学会第20回 回路とシステム軽井沢ワークショップ論文集     529 - 533  2007年

  • Stability analysis of nonlinear feedback circuits

    Zhangcai Huang, Fayan Wang, Shuai Fang, Xuetao Sun, Yasuaki Inoue

    電子情報通信学会第20回 回路とシステム軽井沢ワークショップ論文集     105 - 110  2007年

  • A fast lock phase-locked loop with a continuous-time phase frequency detector

    Jun Pan, Yasuaki Inoue

    電子情報通信学会第20回 回路とシステム軽井沢ワークショップ論文集     99 - 103  2007年

  • 先端MOSFET技術におけるHiSIM2基板電流モデル

    稲垣亮介, 貞近倫夫, Dondee Navvaro, Q. Ngo, C.Y. Yang, 三浦道子, 井上靖秋

    電子情報通信学会第20回 回路とシステム軽井沢ワークショップ論文集     1 - 6  2007年

  • Modeling the impact of input-to-output coupling capacitance on power dissipation

    Zhangcai Huang, Na Li, Sui Huang, Yasuaki Inoue

    Proceedings 2007 International Conference on Communications, Circuits and Systems (ICCCAS), Fukuoka, Japan     1154 - 1157  2007年

  • An effective implementation of the nonlinear homotopy method for MOS transistor circuits based on SPICE3

    Hong Yu, Yasuaki Inoue, Kazutoshi Sako, Guangming Hu

    Proceedings 2007 International Conference on Communications, Circuits and Systems (ICCCAS), Fukuoka, Japan     1086 - 1089  2007年

  • A GIDL-current model for advanced MOSFET technologies implemented into HiSIM2

    Ryosuke Inagaki, Mitiko Miura Mattusch, Yasuaki Inoue

    Proceedings 2007 International Conference on Communications, Circuits and Systems (ICCCAS), Fukuoka, Japan     1057 - 1061  2007年

  • Stability analysis of feedback circuits in analog multiplier designs

    Fayan Wang, Zhangcai Huang, Na Li, Xuetao Sun, Yasuaki Inoue

    Proceedings 2007 International Conference on Communications, Circuits and Systems (ICCCAS), Fukuoka, Japan     1033 - 1036  2007年

  • An ultra low-power high-speed rail-to-rail buffer amplifier for LCD source drivers

    PAN Jun, LIANG Zheng, HUANG Wei-Lun, INOUE Yasuaki

    Proceedings International Symposium on Nonlinear Theory and its Applications (NOLTA’07), Vancouver, Canada     3 - 6  2007年

  • A 12-bit 3.7-Msample/s pipelined A/D converter based on the novel capacitor mismatch calibration technique

    Shuaiqi Wang, Fule Li, Yasuaki Inoue

    Proceedings The 14th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2007), Sapporo, Japan     97 - 103  2007年

  • A High-Speed CMOS Blue-Laser Diode Driver for Multi-speed HD-DVD System

    Shuaiqi Wang, Yasuaki Inoue

    Far East Journal of Electronics and Communications   1 ( 2 ) 167 - 187  2007年

  • A substrate-current model for advanced MOSFET technologies implemented into HiSIM2

    R. Inagaki, N. Sadachika, K. Konno, D. Navarro, Q. Ngo, C. Y. Yang, M. Miura-Mattausch, Y. Inoue

    Proceedings The 4th International Workshop on Compact Modeling, Yokohama, Japan     89 - 92  2007年

  • Modeling the overshooting effect for CMOS inverter in nanometer technologies

    Zhangcai Huang, Hong Yu, Atsushi Kurokawa, Yasuaki Inoue

    Proceedings 12th Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan     565 - 570  2007年

    DOI

  • A high efficiency all PMOS charge pump circuit without overstress in low-voltage CMOS process

    Jun Pan, Yasuaki Inoue

    電子情報通信学会第20回 回路とシステム軽井沢ワークショップ論文集     541 - 546  2007年

  • An ultra low-power high-speed rail-to-rail buffer amplifier for LCD source drivers

    Zheng Liang, Wei-Lun Huang, Jun Pan, Yasuaki Inoue

    電子情報通信学会第20回 回路とシステム軽井沢ワークショップ論文集     529 - 533  2007年

  • Stability analysis of nonlinear feedback circuits

    Zhangcai Huang, Fayan Wang, Shuai Fang, Xuetao Sun, Yasuaki Inoue

    電子情報通信学会第20回 回路とシステム軽井沢ワークショップ論文集     105 - 110  2007年

  • A fast lock phase-locked loop with a continuous-time phase frequency detector

    Jun Pan, Yasuaki Inoue

    電子情報通信学会第20回 回路とシステム軽井沢ワークショップ論文集     99 - 103  2007年

  • Modeling the impact of input-to-output coupling capacitance on power dissipation

    Zhangcai Huang, Na Li, Sui Huang, Yasuaki Inoue

    Proceedings 2007 International Conference on Communications, Circuits and Systems (ICCCAS), Fukuoka, Japan     1154 - 1157  2007年

  • An effective implementation of the nonlinear homotopy method for MOS transistor circuits based on SPICE3

    Hong Yu, Yasuaki Inoue, Kazutoshi Sako, Guangming Hu

    Proceedings 2007 International Conference on Communications, Circuits and Systems (ICCCAS), Fukuoka, Japan     1086 - 1089  2007年

  • A GIDL-current model for advanced MOSFET technologies implemented into HiSIM2

    Ryosuke Inagaki, Mitiko Miura Mattusch, Yasuaki Inoue

    Proceedings 2007 International Conference on Communications, Circuits and Systems (ICCCAS), Fukuoka, Japan     1057 - 1061  2007年

  • Stability analysis of feedback circuits in analog multiplier designs

    Fayan Wang, Zhangcai Huang, Na Li, Xuetao Sun, Yasuaki Inoue

    Proceedings 2007 International Conference on Communications, Circuits and Systems (ICCCAS), Fukuoka, Japan     1033 - 1036  2007年

  • An ultra low-power high-speed rail-to-rail buffer amplifier for LCD source drivers

    PAN Jun, LIANG Zheng, HUANG Wei-Lun, INOUE Yasuaki

    Proceedings International Symposium on Nonlinear Theory and its Applications (NOLTA’07), Vancouver, Canada     3 - 6  2007年

  • A 12-bit 3.7-Msample/s pipelined A/D converter based on the novel capacitor mismatch calibration technique

    Shuaiqi Wang, Fule Li, Yasuaki Inoue

    Proceedings The 14th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2007), Sapporo, Japan     97 - 103  2007年

  • A High-Speed CMOS Blue-Laser Diode Driver for Multi-speed HD-DVD System

    Shuaiqi Wang, Yasuaki Inoue

    Far East Journal of Electronics and Communications   1 ( 2 ) 167 - 187  2007年

  • Determination of interconnect structural parameters for best- and worst-case delays

    A Kurokawa, H Masuda, J Fujui, T Inoshita, A Kasebe, Z Huang, Y Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E89A ( 4 ) 856 - 864  2006年04月

     概要を見る

    In general, a corner model with best- and worst-case delay conditions is used in static timing analysis (STA). The best- and worst-case delays of a stage are defined as the fastest and slowest delays from a cell input to the next cell input. In this paper, we present a methodology for determining the parameters that yield the best- and worst-case delays when interconnect structural parameters have the minimum and maximum values with process variations. We also present analysis results of our circuit model using the methodology. The min and max conditions for the time constant are found to be (+Delta w, +Delta t, +Delta h) & (-Delta w, -Delta t, -Delta h), respectively. Here, +Delta or -Delta means the max or min corner value of each parameter variation, where w is the width, t is the interconnect thickness, and h is the height. Best and worst conditions for delay time are as follows: 1) given a circuit with an optimum driver, dense interconnects, and small branch capacitance, the best and worst conditions are respectively (-Delta w. +Delta t, +Delta h) & (+Delta w, +Delta t, -Delta h), 2) given driver and/or via resistances that are higher than the interconnect resistance, dense interconnects, and small branch capacitance, they are (-Delta w, -Delta t, +Delta h) & (+Delta w, +Delta t, -Delta h), and 3) for other conditions, they are (+Delta w, +Delta t. +Delta h) & (-Delta w, -Delta t, -Delta h). Moreover, if there must be only one condition each for the best- and worst-case delays, they are (+Delta w, +Delta t, +Delta h) & (-Delta w, -Delta t, -Delta h).

    DOI CiNii

  • Formula-based method for capacitance extraction of interconnects with dummy fills

    A Kurokawata, A Kasebe, T Kanamoto, Y Yang, Z Huang, Y Inoue, H Masuda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E89A ( 4 ) 847 - 855  2006年04月

     概要を見る

    In advanced ASIC/SoC physical designs, interconnect parasitic extraction is one of the important factors to determine the accuracy of timing analysis. We present a formula-based method to efficiently extract interconnect capacitances of interconnects with dummy fills for VLSI designs. The whole flow is as follows: 1) in each process, obtain capacitances per unit length using a 3-D field solver and then create formulas, and 2) in the actual design phase, execute a well-known 2.5-D capacitance extraction. Our results indicated that accuracies of the proposed formulas were almost within 3% error. The proposed formula-based method can extract interconnect capacitances with high accuracy for VLSI circuits. Moreover, we present formulas to evaluate the effect of dummy fills on interconnect capacitances. These can be useful for determining design guidelines, such as metal density before the actual design, and for analyzing the effect of each structural parameter during the design phase.

    DOI CiNii

  • Modeling the influence of input-to-output coupling capacitance on CMOS inverter delay

    Z Huang, A Kurokawa, Y Yang, H Yu, Y Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E89A ( 4 ) 840 - 846  2006年04月

     概要を見る

    The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of the input-to-output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.

    DOI CiNii

  • Determination of interconnect structural parameters for best- and worst-case delays

    A Kurokawa, H Masuda, J Fujui, T Inoshita, A Kasebe, Z Huang, Y Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E89A ( 4 ) 856 - 864  2006年04月

     概要を見る

    In general, a corner model with best- and worst-case delay conditions is used in static timing analysis (STA). The best- and worst-case delays of a stage are defined as the fastest and slowest delays from a cell input to the next cell input. In this paper, we present a methodology for determining the parameters that yield the best- and worst-case delays when interconnect structural parameters have the minimum and maximum values with process variations. We also present analysis results of our circuit model using the methodology. The min and max conditions for the time constant are found to be (+Delta w, +Delta t, +Delta h) & (-Delta w, -Delta t, -Delta h), respectively. Here, +Delta or -Delta means the max or min corner value of each parameter variation, where w is the width, t is the interconnect thickness, and h is the height. Best and worst conditions for delay time are as follows: 1) given a circuit with an optimum driver, dense interconnects, and small branch capacitance, the best and worst conditions are respectively (-Delta w. +Delta t, +Delta h) & (+Delta w, +Delta t, -Delta h), 2) given driver and/or via resistances that are higher than the interconnect resistance, dense interconnects, and small branch capacitance, they are (-Delta w, -Delta t, +Delta h) & (+Delta w, +Delta t, -Delta h), and 3) for other conditions, they are (+Delta w, +Delta t. +Delta h) & (-Delta w, -Delta t, -Delta h). Moreover, if there must be only one condition each for the best- and worst-case delays, they are (+Delta w, +Delta t, +Delta h) & (-Delta w, -Delta t, -Delta h).

    DOI CiNii

  • Formula-based method for capacitance extraction of interconnects with dummy fills

    A Kurokawata, A Kasebe, T Kanamoto, Y Yang, Z Huang, Y Inoue, H Masuda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E89A ( 4 ) 847 - 855  2006年04月

     概要を見る

    In advanced ASIC/SoC physical designs, interconnect parasitic extraction is one of the important factors to determine the accuracy of timing analysis. We present a formula-based method to efficiently extract interconnect capacitances of interconnects with dummy fills for VLSI designs. The whole flow is as follows: 1) in each process, obtain capacitances per unit length using a 3-D field solver and then create formulas, and 2) in the actual design phase, execute a well-known 2.5-D capacitance extraction. Our results indicated that accuracies of the proposed formulas were almost within 3% error. The proposed formula-based method can extract interconnect capacitances with high accuracy for VLSI circuits. Moreover, we present formulas to evaluate the effect of dummy fills on interconnect capacitances. These can be useful for determining design guidelines, such as metal density before the actual design, and for analyzing the effect of each structural parameter during the design phase.

    DOI CiNii

  • Modeling the influence of input-to-output coupling capacitance on CMOS inverter delay

    Z Huang, A Kurokawa, Y Yang, H Yu, Y Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E89A ( 4 ) 840 - 846  2006年04月

     概要を見る

    The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of the input-to-output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.

    DOI CiNii

  • A highly linear and wide dynamic range four-quadrant CMOS analog multiplier using active feedback

    Zhangcai Huang, Yasuaki Inoue, Quan Zhang, Hong Yu

    電子情報通信学会第19回 回路とシステム軽井沢ワークショップ論文集     441 - 445  2006年

  • A sub-1-V low-voltage low-power reference with a back-gate connection MOSFET

    Jun Pan, Yasuaki Inoue

    電子情報通信学会第19回 回路とシステム軽井沢ワークショップ論文集     411 - 416  2006年

  • An effective large current and high gain laser diode driver circuit design

    Yun Yang, Jia Guo, Yasuaki Inoue

    電子情報通信学会第19回 回路とシステム軽井沢ワークショップ論文集     383 - 386  2006年

  • A study for the frequency analysis of CMOS multiplier

    Quan Zhang, Zhangcai Huang, Yasuaki Inoue

    電子情報通信学会第19回 回路とシステム軽井沢ワークショップ論文集     87 - 91  2006年

  • A 15-bit 10-Msample/s pipelined A/D converter based on incomplete settling principle

    Shuaiqi Wang, Fule Li, Yasuaki Inoue

    電子情報通信学会第19回 回路とシステム軽井沢ワークショップ論文集     81 - 86  2006年

  • Behavioral circuit macromodeling of analog LSI implementation for automobile intake system

    Zhangcai Huang, Yasuaki Inoue, Quan Zhang, Shuai Fang, Yuehu Zhou

    電子情報通信学会第19回 回路とシステム軽井沢ワークショップ論文集     35 - 38  2006年

  • A pseudo-transient method using compound elements for finding DC operating points

    Hong Yu, Yasuaki Inoue, Yuki Matsuya, Zhangcai Huang

    電子情報通信学会第19回 回路とシステム軽井沢ワークショップ論文集     23 - 28  2006年

  • Calculating the effective capacitance for interconnect loads based on Thevenin model

    Shuai Fang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

    電子情報通信学会第19回 回路とシステム軽井沢ワークショップ論文集     1 - 4  2006年

  • Behavioral macromodeling of analog LSI implementation for automobile intake system

    Zhangcai Huang, Yasuaki Inoue, Quan Zhang, Yuehu Zhou, Long Xie, Harutoshi Ogai

    Proceedings 2006 IEEE International Symposium on Circuits and Systems (ISCAS), Iland of Kos, Greece     4659 - 4662  2006年

  • An effective pseudo-transient algorithm for finding DC operating points of nonlinear circuits

    Hong Yu, Yasuaki Inoue, Yuki Matsuya, Zhangcai Huang

    Proceedings 2006 IEEE International Symposium on Circuits and Systems (ISCAS), Iland of Kos, Greece     1772 - 1775  2006年

  • Calculating the effective capacitance for interconnect loads based on Thevenin model

    Shuai Fang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

    2006 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1-4     2474 - 2477  2006年

     概要を見る

    Interconnect wires give large influences on circuit delay in very deep submicron designs. The venin model and effective capacitance C-eff concept are usually used to calculate the delay of gate with interconnect loads. In the researches before, the condition that the charges transferred to C-eff and RC - pi are not equal was not considered. With the progress of IC process technology, its influence on Static Timing Analysis becomes larger. In this paper, we consider this condition, and propose an new algorithm for calculating the effective capacitance based on The venin model. Experimental results show that it is in agreement with the Spice simulation.

    DOI

  • A large current and high speed laser diode driver using switch position modification

    Yun Yang, Jia Guo, Yasuaki Inoue, Hong Yu

    2006 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1-4     2319 - 2323  2006年

     概要を見る

    This paper describes how to realize the high speed laser diode driver (LDD) circuit with high performance signal and large output current to drive the laser diode device. Based on the introduced idea of "Switch Position Modification (SPM)", two types of LDD circuit architectures, including "Combination Switch Mode (CSM)" and "Source Follower Mode (SFM)", have been proposed to satisfy the output signal requirements. Under the corresponding design specification, the CSM architecture was selected to realize the effective LDD circuit design. Moreover, the signal integrity problems, such as overshoot, undershoot and slew-rate, have also been improved in the new CSM architecture. In addition, appropriate transistor size selection and circuit combination can further amend the signal waveform. The LDD circuit was realized in a 0.6-mu m CMOS technology. And the output current can reach several hundred milliampere with good signal integrity in the experimental simulation results. Thus the introduced "Switch Position Modification" idea and the proposed "Combination Switch Mode" architecture assure the high performance LDD circuit realization and signal output.

    DOI

  • A sub-1-V low-voltage low-power voltage referencewith a back-gate connection MOSFET

    Jun Pan, Yasuaki Inoue

    2006 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1-4     2314 - 2318  2006年

     概要を見る

    A sub-1-V self-biased low-voltage low-power voltage reference is presented for micropower electronic applications. And the proposed circuit has very low temperature dependence by using a back-gate connection MOSFET. An Hspice simulation shows that the reference voltage and total power dissipation are 181 mV and 1.1 mu W, respectively. The temperature coefficient of the reference voltage is 33 ppm/degrees C within a temperature range from -40 to 100 degrees C. The supply voltage dependence is -0.36 mV/V (Vdd=0.95 similar to 3.3 V). Supply voltage can be as low as 0.95 V in a standard CMOS 0.35 mu m technology with threshold voltages of about 0.5 V and -0.65 V for n-channel and p-channel MOSFETs, respectively.

    DOI

  • A 15-bit 10-Msample/s pipelined A/D converter based on incomplete settling principle

    Shuaiqi Wang, Fule Li, Yasuaki Inoue

    2006 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1-4     2176 - 2180  2006年

     概要を見る

    This paper proposes a 15-bit 10-MS/s pipelined ADC. To implement the incomplete settling principle, the traditional complete settling stage is improved to the incomplete settling structure through dividing the sampling clock of the traditional stage into two parts for discharging the sampling and feedback capacitors and completing the sampling, respectively. It verifies the correction and validity of optimizing ADCs' conversion speed without increasing power consumption through the incomplete settling. It is processed in 0.18 mu m 1P6M CMOS mixed-mode technology. Simulation results show that 82dB SNDR and 87dB SFDR are obtained at the sampling rate of 10MHz with the input sine frequency of 100KHz and the whole static power dissipation is 21.94mW.

    DOI

  • A high-speed CMOS blue-laser diode driver for multi-speed HD-DVD system

    Shuaiqi Wang, Yasuaki Inoue

    Proceedings 2006 IEEJ International Analog VLSI Workshop, Hangzhou, China     6 pages  2006年

  • A low-power high-speed rail-to-rail class-B buffer amplifier for LCD column driver

    Zheng Liang, Jun Pan, Wei-Lun Huang, Yasuaki Inoue

    Proceedings 2006 IEEJ International Analog VLSI Workshop, Hangzhou, China     6 pages  2006年

  • Analog LSI implementation for dynamic systems in automobile intake manifold

    Zhangcai Huang, Yasuaki Inoue

    Proceedings 2006 IEEJ International Analog VLSI Workshop, Hangzhou, China     6 pages  2006年

  • A globally convergent method for finding DC solutions of MOS transistor circuits

    Kazutoshi Sako, Hong Yu, Yasuaki Inoue

    Proceedings 2006 IEEJ International Analog VLSI Workshop, Hangzhou, China     6 pages  2006年

  • An effective implementation of the compound element pseudo-transient algorithm on SPICE3

    Hong Yu, Yasuaki Inoue, Xiaochuan Hu, Kazutoshi Sako, Yun Yang

    Proceedings 2006 IEEJ International Analog VLSI Workshop, Hangzhou, China     6 pages  2006年

  • A gate-current model for advanced MOSFET technologies implemented into HiSIM2

    R. Inagaki, N. Sadachika, K. Konno, D. Navarro, Q. Ngo, C.Y. Yang, M. Miura-Mattausch, Y. Inoue

    Proceedings 2006 IEEJ International Analog VLSI Workshop, Hangzhou, China     6 pages  2006年

  • A wide dynamic range four-quadrant CMOS analog multiplier using active feedback

    Zhangcai Huang, Yasuaki Inoue, Hong Yu, Quan Zhang

    Proceedings 2006 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Singapore     709 - 712  2006年

    DOI

  • A highly linear and wide dynamic range four-quadrant CMOS analog multiplier using active feedback

    Zhangcai Huang, Yasuaki Inoue, Quan Zhang, Hong Yu

    電子情報通信学会第19回 回路とシステム軽井沢ワークショップ論文集     441 - 445  2006年

  • A sub-1-V low-voltage low-power reference with a back-gate connection MOSFET

    Jun Pan, Yasuaki Inoue

    電子情報通信学会第19回 回路とシステム軽井沢ワークショップ論文集     411 - 416  2006年

  • An effective large current and high gain laser diode driver circuit design

    Yun Yang, Jia Guo, Yasuaki Inoue

    電子情報通信学会第19回 回路とシステム軽井沢ワークショップ論文集     383 - 386  2006年

  • A study for the frequency analysis of CMOS multiplier

    Quan Zhang, Zhangcai Huang, Yasuaki Inoue

    電子情報通信学会第19回 回路とシステム軽井沢ワークショップ論文集     87 - 91  2006年

  • A 15-bit 10-Msample/s pipelined A/D converter based on incomplete settling principle

    Shuaiqi Wang, Fule Li, Yasuaki Inoue

    電子情報通信学会第19回 回路とシステム軽井沢ワークショップ論文集     81 - 86  2006年

  • Behavioral circuit macromodeling of analog LSI implementation for automobile intake system

    Zhangcai Huang, Yasuaki Inoue, Quan Zhang, Shuai Fang, Yuehu Zhou

    電子情報通信学会第19回 回路とシステム軽井沢ワークショップ論文集     35 - 38  2006年

  • A pseudo-transient method using compound elements for finding DC operating points

    Hong Yu, Yasuaki Inoue, Yuki Matsuya, Zhangcai Huang

    電子情報通信学会第19回 回路とシステム軽井沢ワークショップ論文集     23 - 28  2006年

  • Calculating the effective capacitance for interconnect loads based on Thevenin model

    Shuai Fang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

    電子情報通信学会第19回 回路とシステム軽井沢ワークショップ論文集     1 - 4  2006年

  • Behavioral macromodeling of analog LSI implementation for automobile intake system

    Zhangcai Huang, Yasuaki Inoue, Quan Zhang, Yuehu Zhou, Long Xie, Harutoshi Ogai

    Proceedings 2006 IEEE International Symposium on Circuits and Systems (ISCAS), Iland of Kos, Greece     4659 - 4662  2006年

  • An effective pseudo-transient algorithm for finding DC operating points of nonlinear circuits

    Hong Yu, Yasuaki Inoue, Yuki Matsuya, Zhangcai Huang

    Proceedings 2006 IEEE International Symposium on Circuits and Systems (ISCAS), Iland of Kos, Greece     1772 - 1775  2006年

  • Calculating the effective capacitance for interconnect loads based on thevenin model

    Shuai Fang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

    2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings   4   2474 - 2477  2006年

     概要を見る

    Interconnect wires give large influences on circuit delay in very deep submicron designs. Thevenin model and effective capacitance Ceff concept are usually used to calculate the delay of gate with interconnect loads. In the researches before, the condition that the charges transferred to C eff and RC -π are not equal was not considered. With the progress of IC process technology, its influence on Static Timing Analysis becomes larger. In this paper, we consider this condition, and propose an new algorithm for calculating the effective capacitance based on Thevenin model. Experimental results show that it is in agreement with the Spice simulation. © 2006 IEEE.

    DOI

  • A large current and high speed laser diode driver using switch position modification

    Yun Yang, Jia Guo, Yasuaki Inoue, Hong Yu

    2006 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1-4     2319 - 2323  2006年

     概要を見る

    This paper describes how to realize the high speed laser diode driver (LDD) circuit with high performance signal and large output current to drive the laser diode device. Based on the introduced idea of "Switch Position Modification (SPM)", two types of LDD circuit architectures, including "Combination Switch Mode (CSM)" and "Source Follower Mode (SFM)", have been proposed to satisfy the output signal requirements. Under the corresponding design specification, the CSM architecture was selected to realize the effective LDD circuit design. Moreover, the signal integrity problems, such as overshoot, undershoot and slew-rate, have also been improved in the new CSM architecture. In addition, appropriate transistor size selection and circuit combination can further amend the signal waveform. The LDD circuit was realized in a 0.6-mu m CMOS technology. And the output current can reach several hundred milliampere with good signal integrity in the experimental simulation results. Thus the introduced "Switch Position Modification" idea and the proposed "Combination Switch Mode" architecture assure the high performance LDD circuit realization and signal output.

    DOI

  • A sub-1-V low-voltage low-power voltage referencewith a back-gate connection MOSFET

    Jun Pan, Yasuaki Inoue

    2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings   4   2314 - 2318  2006年

     概要を見る

    A sub-1-V self-biased low-voltage low-power voltage reference is presented for micropower electronic applications. And the proposed circuit has very low temperature dependence by using a back-gate connection MOSFET. An Hspice simulation shows that the reference voltage and total power dissipation are 181 mV and 1.1 μW, respectively. The temperature coefficient of the reference voltage is 33 ppm/°C within a temperature range from -40 to 100°C. The supply voltage dependence is -0.36 m V/V (Vdd=0.95-3.3 V). Supply voltage can be as low as 0.95 V in a standard CMOS 0.35 °m technology with threshold voltages of about 0.5 V and -0.65 V for n-channel and p-channel MOSFETs, respectively. © 2006 IEEE.

    DOI

  • A 15-bit 10-msample/s pipelined A/D converter based on incomplete settling principle

    Shuaiqi Wang, Fule Li, Yasuaki Inoue

    2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings   4   2176 - 2180  2006年

     概要を見る

    This paper proposes a 15-bit 10-MS/s pipelined ADC. To implement the incomplete settling principle, the traditional complete settling stage is improved to the incomplete settling structure through dividing the sampling clock of the traditional stage into two parts for discharging the sampling and feedback capacitors and completing the sampling, respectively. It verifies the correction and validity of optimizing ADCs' conversion speed without increasing power consumption through the incomplete settling. It is processed in 0.18μm 1P6M CMOS mixed-mode technology. Simulation results show that 82dB SNDR and 87dB SFDR are obtained at the sampling rate of 10MHz with the input sine frequency of 100KHz and the whole static power dissipation is 21.94mW. © 2006 IEEE.

    DOI

  • A high-speed CMOS blue-laser diode driver for multi-speed HD-DVD system

    Shuaiqi Wang, Yasuaki Inoue

    Proceedings 2006 IEEJ International Analog VLSI Workshop, Hangzhou, China     6 pages  2006年

  • A low-power high-speed rail-to-rail class-B buffer amplifier for LCD column driver

    Zheng Liang, Jun Pan, Wei-Lun Huang, Yasuaki Inoue

    Proceedings 2006 IEEJ International Analog VLSI Workshop, Hangzhou, China     6 pages  2006年

  • Analog LSI implementation for dynamic systems in automobile intake manifold

    Zhangcai Huang, Yasuaki Inoue

    Proceedings 2006 IEEJ International Analog VLSI Workshop, Hangzhou, China     6 pages  2006年

  • A globally convergent method for finding DC solutions of MOS transistor circuits

    Kazutoshi Sako, Hong Yu, Yasuaki Inoue

    Proceedings 2006 IEEJ International Analog VLSI Workshop, Hangzhou, China     6 pages  2006年

  • An effective implementation of the compound element pseudo-transient algorithm on SPICE3

    Hong Yu, Yasuaki Inoue, Xiaochuan Hu, Kazutoshi Sako, Yun Yang

    Proceedings 2006 IEEJ International Analog VLSI Workshop, Hangzhou, China     6 pages  2006年

  • A gate-current model for advanced MOSFET technologies implemented into HiSIM2

    R. Inagaki, N. Sadachika, K. Konno, D. Navarro, Q. Ngo, C.Y. Yang, M. Miura-Mattausch, Y. Inoue

    Proceedings 2006 IEEJ International Analog VLSI Workshop, Hangzhou, China     6 pages  2006年

  • A wide dynamic range four-quadrant CMOS analog multiplier using active feedback

    Zhangcai Huang, Yasuaki Inoue, Hong Yu, Quan Zhang

    Proceedings 2006 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Singapore     709 - 712  2006年

    DOI

  • Efficient dummy filling methods to reduce interconnect capacitance and number of dummy metal fills

    A Kurokawa, T Kanamoto, T Ibe, A Kasebe, WF Chang, T Kage, Y Inoue, H Masuda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E88A ( 12 ) 3471 - 3478  2005年12月

     概要を見る

    Floating dummy metal fills inserted for planarization of multi-dielectric layers have created serious problems because of increased interconnect capacitance and the enormous number of fills. We present new dummy filling methods to reduce the interconnect capacitance and the number of dummy metal fills needed. These techniques include three ways of filling: 1) improved floating square fills, 2) floating parallel lines, and 3) floating perpendicular lines (with spacing between dummy metal fills above and below signal lines). We also present efficient formulas for estimating the appropriate spacing and number of fills. In our experiments, the capacitance increase using the conventional regular square method was 13.1%. while that using the methods of improved square fills, extended parallel lines, and perpendicular lines were 2.7%, 2.4%, and 1.0%, respectively. Moreover, the number of necessary dummy metal fills can be reduced by two orders of magnitude through use of the parallel line method.

    DOI CiNii

  • Second-order polynomial expressions for on-chip interconnect capacitance

    A Kurokawa, M Hashimoto, A Kasebe, ZC Huang, Y Yang, Y Inoue, R Inagaki, H Masuda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E88A ( 12 ) 3453 - 3462  2005年12月

     概要を見る

    Simple closed-form expressions for efficiently calculating on-chip interconnect capacitances are presented. The formulas are expressed with second-order polynomial functions which do not include exponential functions. The runtime of the proposed formulas is about 2-10 times faster than those of existing formulas. The root mean square (RMS) errors of the proposed formulas are within 1.5%, 1.3%, 3.1%, and 4.6% of the results obtained by a field solver for structures with one line above a ground plane, one line between ground planes, three lines above a ground plane, and three lines between ground planes, respectively. The proposed formulas are also superior in accuracy to existing formulas.

    DOI CiNii

  • Modeling the effective capacitance of interconnect loads for predicting CMOS gate slew

    ZC Huang, A Kurokawa, J Pan, Y Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E88A ( 12 ) 3367 - 3374  2005年12月

     概要を見る

    In deep submicron designs, predicting gate stews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance C-eff concept is usually used to calculate the gate delay of interconnect loads. Many C-eff algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a C-eff algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating the C-eff of interconnect load for gate slew. We firstly establish a new expression for C-eff in 0.8Vdd point. Then the Integration Approximation method is used to calculate the value of C-eff in 0.8Vdd point. In this method, the integration of a complicated nonlinear gate output is approximated with that of a piecewise linear waveform. Based on the value of C-eff in 0.8Vdd point, C-eff of interconnect load for gate slew is obtained. The simulation results demonstrate a significant improvement in accuracy.

    DOI CiNii

  • Efficient large scale integration power/ground network optimization based on grid genetic algorithm

    Y Yang, A Kurokawa, Y Inoue, WQ Zhao

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E88A ( 12 ) 3412 - 3420  2005年12月

     概要を見る

    In this paper we propose a novel and efficient method for the optimization of the power/ground (P/G) network in VLSI circuit layouts with reliability constraints. Previous algorithms in the P/G network sizing used the sequence-of-linear-programming (SLP) algorithm to solve the nonlinear optimization problems. However the transformation from nonlinear network to linear subnetwork is not optimal enough. Our new method is inspired by the biological evolution and use the grid-genetic-algorithm (GGA) to solve the optimization problem. Experimental results show that new P/G network sizes are smaller than previous algorithms, as the fittest survival in the nature. Another significant advance is that GGA method can be applied for all P/G network problems because it can get the results directly no matter whether these problems are linear or not. Thus GGA can be adopted in the transient behavior of the P/G network sizing in the future, which recently faces on the obstacles in the solution of the complex nonlinear problems.

    DOI CiNii

  • Efficient dummy filling methods to reduce interconnect capacitance and number of dummy metal fills

    A Kurokawa, T Kanamoto, T Ibe, A Kasebe, WF Chang, T Kage, Y Inoue, H Masuda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E88A ( 12 ) 3471 - 3478  2005年12月

     概要を見る

    Floating dummy metal fills inserted for planarization of multi-dielectric layers have created serious problems because of increased interconnect capacitance and the enormous number of fills. We present new dummy filling methods to reduce the interconnect capacitance and the number of dummy metal fills needed. These techniques include three ways of filling: 1) improved floating square fills, 2) floating parallel lines, and 3) floating perpendicular lines (with spacing between dummy metal fills above and below signal lines). We also present efficient formulas for estimating the appropriate spacing and number of fills. In our experiments, the capacitance increase using the conventional regular square method was 13.1%. while that using the methods of improved square fills, extended parallel lines, and perpendicular lines were 2.7%, 2.4%, and 1.0%, respectively. Moreover, the number of necessary dummy metal fills can be reduced by two orders of magnitude through use of the parallel line method.

    DOI CiNii

  • Second-order polynomial expressions for on-chip interconnect capacitance

    A Kurokawa, M Hashimoto, A Kasebe, ZC Huang, Y Yang, Y Inoue, R Inagaki, H Masuda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E88A ( 12 ) 3453 - 3462  2005年12月

     概要を見る

    Simple closed-form expressions for efficiently calculating on-chip interconnect capacitances are presented. The formulas are expressed with second-order polynomial functions which do not include exponential functions. The runtime of the proposed formulas is about 2-10 times faster than those of existing formulas. The root mean square (RMS) errors of the proposed formulas are within 1.5%, 1.3%, 3.1%, and 4.6% of the results obtained by a field solver for structures with one line above a ground plane, one line between ground planes, three lines above a ground plane, and three lines between ground planes, respectively. The proposed formulas are also superior in accuracy to existing formulas.

    DOI CiNii

  • Modeling the effective capacitance of interconnect loads for predicting CMOS gate slew

    ZC Huang, A Kurokawa, J Pan, Y Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E88A ( 12 ) 3367 - 3374  2005年12月

     概要を見る

    In deep submicron designs, predicting gate stews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance C-eff concept is usually used to calculate the gate delay of interconnect loads. Many C-eff algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a C-eff algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating the C-eff of interconnect load for gate slew. We firstly establish a new expression for C-eff in 0.8Vdd point. Then the Integration Approximation method is used to calculate the value of C-eff in 0.8Vdd point. In this method, the integration of a complicated nonlinear gate output is approximated with that of a piecewise linear waveform. Based on the value of C-eff in 0.8Vdd point, C-eff of interconnect load for gate slew is obtained. The simulation results demonstrate a significant improvement in accuracy.

    DOI CiNii

  • Efficient large scale integration power/ground network optimization based on grid genetic algorithm

    Y Yang, A Kurokawa, Y Inoue, WQ Zhao

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E88A ( 12 ) 3412 - 3420  2005年12月

     概要を見る

    In this paper we propose a novel and efficient method for the optimization of the power/ground (P/G) network in VLSI circuit layouts with reliability constraints. Previous algorithms in the P/G network sizing used the sequence-of-linear-programming (SLP) algorithm to solve the nonlinear optimization problems. However the transformation from nonlinear network to linear subnetwork is not optimal enough. Our new method is inspired by the biological evolution and use the grid-genetic-algorithm (GGA) to solve the optimization problem. Experimental results show that new P/G network sizes are smaller than previous algorithms, as the fittest survival in the nature. Another significant advance is that GGA method can be applied for all P/G network problems because it can get the results directly no matter whether these problems are linear or not. Thus GGA can be adopted in the transient behavior of the P/G network sizing in the future, which recently faces on the obstacles in the solution of the complex nonlinear problems.

    DOI CiNii

  • A practical approach for efficiently extracting interconnect capacitances with floating dummy fills

    A Kurokawa, T Kanamoto, A Kasebe, Y Inoue, H Masuda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E88A ( 11 ) 3180 - 3187  2005年11月

     概要を見る

    We present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances for system-on-chip (SoC) designs. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy metal fills on the parasitic capacitance, signal delay, and crosstalk noise. Moreover, we address that interlayer dummy metal fills have more significant influences than intralayer ones in terms of the impact on coupling capacitances. When dummy metal fills are ignored, the error of capacitance extraction can be more than 30%, whereas the error of the proposed method is less than about 10% for many practical geometries. We also demonstrate, by comparison with capacitance results measured for a 90-nm test chip, that the error of the proposed method is less than 8%.

    DOI CiNii

  • A practical approach for efficiently extracting interconnect capacitances with floating dummy fills

    A Kurokawa, T Kanamoto, A Kasebe, Y Inoue, H Masuda

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E88A ( 11 ) 3180 - 3187  2005年11月

     概要を見る

    We present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances for system-on-chip (SoC) designs. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy metal fills on the parasitic capacitance, signal delay, and crosstalk noise. Moreover, we address that interlayer dummy metal fills have more significant influences than intralayer ones in terms of the impact on coupling capacitances. When dummy metal fills are ignored, the error of capacitance extraction can be more than 30%, whereas the error of the proposed method is less than about 10% for many practical geometries. We also demonstrate, by comparison with capacitance results measured for a 90-nm test chip, that the error of the proposed method is less than 8%.

    DOI CiNii

  • A novel model for computing the effective capacitance of CMOS gates with interconnect loads

    ZC Huang, A Kurokawa, Y Inoue, JF Mao

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E88A ( 10 ) 2562 - 2569  2005年10月

     概要を見る

    In deep submicron designs, the interconnect wires play a major role in the timing behavior of logic gates. The effective capacitance C-eff concept is usually used to calculate the delay of gate with interconnect loads. In this paper, we present a new method of Integration Approximation to calculate C-eff. In this new method, the complicated nonlinear gate output is assumed as a piecewise linear (PWL) waveform. A new model is then derived to compute the value of C-eff. The introduction of Integration Approximation results in C-eff being insensitive to output waveform shape. Therefore, the new method can be applied to various output waveforms of CMOS gates with RC-pi loads. Experimental results show a significant improvement in accuracy.

    DOI CiNii

  • An efficient homotopy method for finding DC operating points of nonlinear circuits

    Y Imai, K Yamamura, Y Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E88A ( 10 ) 2554 - 2561  2005年10月

     概要を見る

    Finding DC operating points of nonlinear circuits is an important problem in circuit simulation. The Newton-Raphson method employed in SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. There are several types of homotopy methods, one of which succeeded in solving bipolar analog circuits with more than 20000 elements with the theoretical guarantee of global convergence. In this paper, we propose an improved version of the homotopy method that can find DC operating points of practical nonlinear circuits smoothly and efficiently. Numerical examples show the effectiveness of the proposed method.

    DOI CiNii

  • A novel model for computing the effective capacitance of CMOS gates with interconnect loads

    ZC Huang, A Kurokawa, Y Inoue, JF Mao

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E88A ( 10 ) 2562 - 2569  2005年10月

     概要を見る

    In deep submicron designs, the interconnect wires play a major role in the timing behavior of logic gates. The effective capacitance C-eff concept is usually used to calculate the delay of gate with interconnect loads. In this paper, we present a new method of Integration Approximation to calculate C-eff. In this new method, the complicated nonlinear gate output is assumed as a piecewise linear (PWL) waveform. A new model is then derived to compute the value of C-eff. The introduction of Integration Approximation results in C-eff being insensitive to output waveform shape. Therefore, the new method can be applied to various output waveforms of CMOS gates with RC-pi loads. Experimental results show a significant improvement in accuracy.

    DOI CiNii

  • An efficient homotopy method for finding DC operating points of nonlinear circuits

    Y Imai, K Yamamura, Y Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E88A ( 10 ) 2554 - 2561  2005年10月

     概要を見る

    Finding DC operating points of nonlinear circuits is an important problem in circuit simulation. The Newton-Raphson method employed in SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. There are several types of homotopy methods, one of which succeeded in solving bipolar analog circuits with more than 20000 elements with the theoretical guarantee of global convergence. In this paper, we propose an improved version of the homotopy method that can find DC operating points of practical nonlinear circuits smoothly and efficiently. Numerical examples show the effectiveness of the proposed method.

    DOI CiNii

  • A homotopy method using a nonlinear auxiliary function for solving transistor circuits

    Y Inoue, Y Imai, K Yamamura

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS   E88D ( 7 ) 1401 - 1408  2005年07月

     概要を見る

    Finding DC operating points of transistor circuits is a very important and difficult task. The Newton-Raphson method employed in SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. For efficiency of homotopy methods, it is important to construct an appropriate homotopy function. In conventional homotopy methods, linear auxiliary functions have been commonly used. In this paper, a homotopy method for solving transistor circuits using a nonlinear auxiliary function is proposed. The proposed method utilizes the nonlinear function closely related to circuit equations to be solved, so that it efficiently finds DC operating points of practical transistor circuits. Numerical examples show that the proposed method is several times more efficient than conventional three homotopy methods.

    DOI

  • A homotopy method using a nonlinear auxiliary function for solving transistor circuits

    Y Inoue, Y Imai, K Yamamura

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS   E88D ( 7 ) 1401 - 1408  2005年07月

     概要を見る

    Finding DC operating points of transistor circuits is a very important and difficult task. The Newton-Raphson method employed in SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. For efficiency of homotopy methods, it is important to construct an appropriate homotopy function. In conventional homotopy methods, linear auxiliary functions have been commonly used. In this paper, a homotopy method for solving transistor circuits using a nonlinear auxiliary function is proposed. The proposed method utilizes the nonlinear function closely related to circuit equations to be solved, so that it efficiently finds DC operating points of practical transistor circuits. Numerical examples show that the proposed method is several times more efficient than conventional three homotopy methods.

    DOI

  • Path following circuits - SPICE-oriented numerical methods where formulas are described by circuits

    K Yamamura, W Kuroki, H Okuma, Y Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E88A ( 4 ) 825 - 831  2005年04月

     概要を見る

    Path following circuits (PFC's) are circuits for solving nonlinear problems on the circuit simulator SPICE. In the method of PFC's, formulas of numerical methods are described by circuits, which are solved by SPICE. Using PFC's, numerical analysis without programming is possible, and various techniques implemented in SPICE will make the numerical analysis very efficient. In this paper, we apply the PFC's of the homotopy method to various nonlinear problems (excluding circuit analysis) where the homotopy method is proven to be globally convergent; namely, we apply the method to fixed-point problems, linear programming problems, and nonlinear programming problems. This approach may give a new possibility to the fields of applied mathematics and operations research. Moreover, this approach makes SPICE applicable to a broader class of scientific problems.

    DOI CiNii

  • Path following circuits - SPICE-oriented numerical methods where formulas are described by circuits

    K Yamamura, W Kuroki, H Okuma, Y Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E88A ( 4 ) 825 - 831  2005年04月

     概要を見る

    Path following circuits (PFC's) are circuits for solving nonlinear problems on the circuit simulator SPICE. In the method of PFC's, formulas of numerical methods are described by circuits, which are solved by SPICE. Using PFC's, numerical analysis without programming is possible, and various techniques implemented in SPICE will make the numerical analysis very efficient. In this paper, we apply the PFC's of the homotopy method to various nonlinear problems (excluding circuit analysis) where the homotopy method is proven to be globally convergent; namely, we apply the method to fixed-point problems, linear programming problems, and nonlinear programming problems. This approach may give a new possibility to the fields of applied mathematics and operations research. Moreover, this approach makes SPICE applicable to a broader class of scientific problems.

    DOI CiNii

  • Dummy filling methods for reducing interconnect capacitance and number of fills

    A Kurokawa, T Kanamoto, T Ibe, A Kasebe, CW Fong, T Kage, Y Inoue, H Masuda

    6th International Symposium on Quality Electronic Design, Proceedings     586 - 591  2005年

     概要を見る

    In recent system-on-chip (SoC) designs, floating dummy metals inserted for planarization have created serious problems because of increased interconnect capacitance and the enormous amount of fill required. We present new methods to reduce the interconnect capacitance and the amount of dummy metals needed. These techniques include three ways of filling: 1) improved floating square fills, 2) floating parallel lines, and 3) floating perpendicular lines (with spacing between dummy metals above and below signal lines). We also present efficient simple formulas for estimating the appropriate spacing and number of fills. In our experiments, the capacitance increase using the traditional regular square method was 13.1%, while that using the methods of improved square fills, extended parallel lines, and perpendicular lines was 2.5%, 2.4%, and 1.1%, respectively. Moreover, the number of necessary dummy metals can be reduced by two orders of magnitude through use of the parallel line method.

    DOI

  • Capacitance and yield evaluations using a 90-nm process technology based on the dense power-ground interconnect architecture

    A Kurokawa, M Yamamoto, N Ono, T Kage, Y Inoue, H Masuda

    6TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS     153 - 158  2005年

     概要を見る

    In the VLSI design of sub-100-nm technologies, most engineers in the process, chip-design, and EDA areas are acutely aware of a tough "Red Brick Wall" emerging because of process variability and physical integrity issues. Process variability is not only a fabrication problem, but also a serious design issue. Similarly, physical integrity problems are not only design and EDA issues, but also process-related architecture problems.
    In this paper, we investigate the practicality of a dense power-ground interconnect architecture [1,2] developed to ensure physical design integrity. The interconnect architecture basically consists of adjoining power and ground lines. We describe the design methodologies and a simple method for calculating the decoupling capacitance (decap) values, and report both calculated and measured decap values for the architecture. We also report measurement results regarding the signal line capacitance and the interconnect defect-type yield of a 90-nm process technology.

    DOI

  • An Efficient Homotopy Method for Finding DC Operating Points of Nonlinear Circuits

    Kiyotaka Yamamura, Yu Imai, Yasuaki Inoue

    電子情報通信学会第18回 回路とシステム(軽井沢)ワークショップ論文集     55 - 60  2005年

  • The efficient grid genetic algorithm used in VLSI static power/ground network optimization

    Yun Yang, Atsushi Kurokawa, Yasuaki Inoue

    電子情報通信学会第18回 回路とシステム(軽井沢)ワークショップ論文集     37 - 42  2005年

  • 遅延ベスト/ワーストとなる配線構造パラメータの決定

    黒川敦, 増田弘生, 藤井順子, 井下順功, 加瀬部彰, 黄章財, 井上靖秋

    電子情報通信学会第18回 回路とシステム(軽井沢)ワークショップ論文集     25 - 30  2005年

  • Modeling the influence of input-to-output coupling capacitance on the CMOS inverter delay

    Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

    電子情報通信学会第18回 回路とシステム(軽井沢)ワークショップ論文集     13 - 18  2005年

  • Modeling the effective capacitance of interconnect loads for CMOS gates

    Zhang-cai Huang, Atsushi Kurokawa, Yasuaki Inoue

    電子情報通信学会第18回 回路とシステム(軽井沢)ワークショップ論文集     7 - 12  2005年

  • ダミー・フィルを考慮した解析式ベース配線容量抽出手法

    黒川敦, 加瀬部彰, 金本俊幾, 楊贇, 黄章財, 井上靖秋, 増田弘生

    電子情報通信学会第18回 回路とシステム(軽井沢)ワークショップ論文集     19 - 24  2005年

  • An efficient homotopy method for finding DC operating points of transistor circuits

    Yu Imai, Kiyotaka Yamamura, Yasuaki Inoue

    Proceedings 2005 IEEE International Symposium on Circuits and Systems (ISCAS), Kobe, Japan     4911 - 4944  2005年

    DOI

  • Path following circuits

    Kiyotaka Yamamura, Wataru Kuroki, Yasuaki Inoue

    Proceedings - IEEE International Symposium on Circuits and Systems     3761 - 3764  2005年

     概要を見る

    In this paper, it is shown that various scientific problems such as fixed-point problems, linear programming problems, and nonlinear programming problems can be solved by using the circuit simulator SPICE. The basic idea of the proposed method is that formulas of the homotopy method are described by circuits, and then they are solved by SPICE. Since SPICE is an excellent software that includes various excellent techniques, this approach will make the numerical analysis very efficient, especially for stiff problems. Moreover, for SPICE users, the proposed method will be useful because they can easily solve a broad class of problems by the homotopy method realized on SPICE without programming, although they do not know the homotopy method well. © 2005 IEEE.

    DOI

  • Effective capacitance for gate delay with RC loads

    Zhang-Cai Huang, Atsushi Kurokawa, Yasuaki Inoue

    Proceedings - IEEE International Symposium on Circuits and Systems     2795 - 2798  2005年

     概要を見る

    In deep submicron designs, the resistance of interconnect is playing dominant role on the timing behavior of logic gates. The concept of effective capacitance Ceff is usually used to calculate the gate delay for interconnect loads. In this paper, a new method to derive the expression C eff is presented, and the accuracy of the expression is discussed. In our approach, the output waveform is assumed as linear. Thus, the expression of effective capacitance is simple and efficient. Moreover, the result of effective capacitance is insensitive to output wave shape because C eff is determined by the curve area. Therefore, it is appropriate for various output waveform of CMOS gate with RC loads. Experimental results show it is in agreement with the Spice simulation. © 2005 IEEE.

    DOI

  • High-performance systolic arrays for band matrix multiplication

    Y Yang, WQ Zhao, Y Inoue

    2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS     1130 - 1133  2005年

     概要を見る

    Band matrix multiplication is widely used in DSP systems. However traditional Kung-Leiserson systolic array for band matrix multiplication cannot be realized with high cell-efficiency. In this paper, three high-performance band matrix multiplication systolic arrays (BMMSA) are presented based on the ideas of "Matrix Compression" and "Super Pipelined". These new systolic arrays are realized by compressing the data matrix skillfully and adjusting the operation sequence carefully. The results show that the best systolic array for band matrix multiplication uses almost 100% processing elements(PE) in each step. Also, these modifications increase the operation speed and at best spend only 1/3 processing time to complete the multiplication operation.

    DOI

  • Modeling the overshooting effect in the submicron CMOS inverters

    Z Huang, A Kurokawa, Y Inoue

    2005 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS     1191 - 1195  2005年

     概要を見る

    The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of input-to output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.

  • A self-powered sensor module using vibration-based energy generation for ubiquitous systems

    J Pan, B Xue, Y Inoue

    2005 6th International Conference on ASIC Proceedings, Books 1 and 2     443 - 446  2005年

     概要を見る

    A new architecture for ubiquitous sensor modules using vibration-based energy generation is proposed and the CMOS implementation of the proposed architecture is presented. The sensor module only scavenges vibration-based energy as energy source by using piezoelectric element to realize no batteries operation. The sensor module is used to supervise the vibration of machines and transfer the vibration signal discontinuously. Based on the proposed new architecture, the sensor module can sense signal and scavenge energy from the same piece of piezoelectric element and can avoid the long time start-up time. The sensor module also realizes short range (about ten meters) wireless transmission.

  • A new high-speed low-voltage charge pump for PLL applications

    Hong YU, Yasuaki INOUE, Yan HAN

    Proceedings 2005 6th International Conference on ASIC (ASICON), Shanghai, China     435 - 438  2005年

  • Dummy filling methods for reducing interconnect capacitance and number of fills

    A Kurokawa, T Kanamoto, T Ibe, A Kasebe, CW Fong, T Kage, Y Inoue, H Masuda

    6th International Symposium on Quality Electronic Design, Proceedings     586 - 591  2005年

     概要を見る

    In recent system-on-chip (SoC) designs, floating dummy metals inserted for planarization have created serious problems because of increased interconnect capacitance and the enormous amount of fill required. We present new methods to reduce the interconnect capacitance and the amount of dummy metals needed. These techniques include three ways of filling: 1) improved floating square fills, 2) floating parallel lines, and 3) floating perpendicular lines (with spacing between dummy metals above and below signal lines). We also present efficient simple formulas for estimating the appropriate spacing and number of fills. In our experiments, the capacitance increase using the traditional regular square method was 13.1%, while that using the methods of improved square fills, extended parallel lines, and perpendicular lines was 2.5%, 2.4%, and 1.1%, respectively. Moreover, the number of necessary dummy metals can be reduced by two orders of magnitude through use of the parallel line method.

    DOI

  • Capacitance and yield evaluations using a 90-nm process technology based on the dense power-ground interconnect architecture

    A Kurokawa, M Yamamoto, N Ono, T Kage, Y Inoue, H Masuda

    6TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS     153 - 158  2005年

     概要を見る

    In the VLSI design of sub-100-nm technologies, most engineers in the process, chip-design, and EDA areas are acutely aware of a tough "Red Brick Wall" emerging because of process variability and physical integrity issues. Process variability is not only a fabrication problem, but also a serious design issue. Similarly, physical integrity problems are not only design and EDA issues, but also process-related architecture problems.
    In this paper, we investigate the practicality of a dense power-ground interconnect architecture [1,2] developed to ensure physical design integrity. The interconnect architecture basically consists of adjoining power and ground lines. We describe the design methodologies and a simple method for calculating the decoupling capacitance (decap) values, and report both calculated and measured decap values for the architecture. We also report measurement results regarding the signal line capacitance and the interconnect defect-type yield of a 90-nm process technology.

    DOI

  • An Efficient Homotopy Method for Finding DC Operating Points of Nonlinear Circuits

    Kiyotaka Yamamura, Yu Imai, Yasuaki Inoue

    電子情報通信学会第18回 回路とシステム(軽井沢)ワークショップ論文集     55 - 60  2005年

  • The efficient grid genetic algorithm used in VLSI static power/ground network optimization

    Yun Yang, Atsushi Kurokawa, Yasuaki Inoue

    電子情報通信学会第18回 回路とシステム(軽井沢)ワークショップ論文集     37 - 42  2005年

  • Modeling the influence of input-to-output coupling capacitance on the CMOS inverter delay

    Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

    電子情報通信学会第18回 回路とシステム(軽井沢)ワークショップ論文集     13 - 18  2005年

  • Modeling the effective capacitance of interconnect loads for CMOS gates

    Zhang-cai Huang, Atsushi Kurokawa, Yasuaki Inoue

    電子情報通信学会第18回 回路とシステム(軽井沢)ワークショップ論文集     7 - 12  2005年

  • An efficient homotopy method for finding DC operating points of transistor circuits

    Yu Imai, Kiyotaka Yamamura, Yasuaki Inoue

    Proceedings 2005 IEEE International Symposium on Circuits and Systems (ISCAS), Kobe, Japan     4911 - 4944  2005年

    DOI

  • Path following circuits

    Kiyotaka Yamamura, Wataru Kuroki, Yasuaki Inoue

    Proceedings - IEEE International Symposium on Circuits and Systems     3761 - 3764  2005年

     概要を見る

    In this paper, it is shown that various scientific problems such as fixed-point problems, linear programming problems, and nonlinear programming problems can be solved by using the circuit simulator SPICE. The basic idea of the proposed method is that formulas of the homotopy method are described by circuits, and then they are solved by SPICE. Since SPICE is an excellent software that includes various excellent techniques, this approach will make the numerical analysis very efficient, especially for stiff problems. Moreover, for SPICE users, the proposed method will be useful because they can easily solve a broad class of problems by the homotopy method realized on SPICE without programming, although they do not know the homotopy method well. © 2005 IEEE.

    DOI

  • Effective capacitance for gate delay with RC loads

    Zhang-Cai Huang, Atsushi Kurokawa, Yasuaki Inoue

    Proceedings - IEEE International Symposium on Circuits and Systems     2795 - 2798  2005年

     概要を見る

    In deep submicron designs, the resistance of interconnect is playing dominant role on the timing behavior of logic gates. The concept of effective capacitance Ceff is usually used to calculate the gate delay for interconnect loads. In this paper, a new method to derive the expression C eff is presented, and the accuracy of the expression is discussed. In our approach, the output waveform is assumed as linear. Thus, the expression of effective capacitance is simple and efficient. Moreover, the result of effective capacitance is insensitive to output wave shape because C eff is determined by the curve area. Therefore, it is appropriate for various output waveform of CMOS gate with RC loads. Experimental results show it is in agreement with the Spice simulation. © 2005 IEEE.

    DOI

  • High-performance systolic arrays for band matrix multiplication

    Y Yang, WQ Zhao, Y Inoue

    2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS     1130 - 1133  2005年

     概要を見る

    Band matrix multiplication is widely used in DSP systems. However traditional Kung-Leiserson systolic array for band matrix multiplication cannot be realized with high cell-efficiency. In this paper, three high-performance band matrix multiplication systolic arrays (BMMSA) are presented based on the ideas of "Matrix Compression" and "Super Pipelined". These new systolic arrays are realized by compressing the data matrix skillfully and adjusting the operation sequence carefully. The results show that the best systolic array for band matrix multiplication uses almost 100% processing elements(PE) in each step. Also, these modifications increase the operation speed and at best spend only 1/3 processing time to complete the multiplication operation.

    DOI

  • Modeling the overshooting effect in the submicron CMOS inverters

    Z Huang, A Kurokawa, Y Inoue

    2005 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS     1191 - 1195  2005年

     概要を見る

    The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of input-to output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.

  • A self-powered sensor module using vibration-based energy generation for ubiquitous systems

    J Pan, B Xue, Y Inoue

    2005 6th International Conference on ASIC Proceedings, Books 1 and 2     443 - 446  2005年

     概要を見る

    A new architecture for ubiquitous sensor modules using vibration-based energy generation is proposed and the CMOS implementation of the proposed architecture is presented. The sensor module only scavenges vibration-based energy as energy source by using piezoelectric element to realize no batteries operation. The sensor module is used to supervise the vibration of machines and transfer the vibration signal discontinuously. Based on the proposed new architecture, the sensor module can sense signal and scavenge energy from the same piece of piezoelectric element and can avoid the long time start-up time. The sensor module also realizes short range (about ten meters) wireless transmission.

  • A new high-speed low-voltage charge pump for PLL applications

    Hong YU, Yasuaki INOUE, Yan HAN

    Proceedings 2005 6th International Conference on ASIC (ASICON), Shanghai, China     435 - 438  2005年

  • An initial solution algorithm for globally convergent homotopy methods

    Y Inoue, S Kusanobu, K Yamamura, M Ando

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E87A ( 4 ) 780 - 786  2004年04月

     概要を見る

    Finding DC operating points of transistor circuits is an important and difficult task. The Newton-Raphson method adopted in SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. For efficiency of globally convergent homotopy methods, it is important to give an appropriate initial solution as a starting point. However, there are few studies concerning such initial solution algorithms, In this paper, initial solution problems in homotopy methods are discussed, and an effective initial solution algorithm is proposed for globally convergent homotopy methods, which finds DC operating points of transistor circuits efficiently. Numerical examples using practical transistor circuits show the effectiveness of the proposed algorithm.

  • An initial solution algorithm for globally convergent homotopy methods

    Y Inoue, S Kusanobu, K Yamamura, M Ando

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E87A ( 4 ) 780 - 786  2004年04月

     概要を見る

    Finding DC operating points of transistor circuits is an important and difficult task. The Newton-Raphson method adopted in SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. For efficiency of globally convergent homotopy methods, it is important to give an appropriate initial solution as a starting point. However, there are few studies concerning such initial solution algorithms, In this paper, initial solution problems in homotopy methods are discussed, and an effective initial solution algorithm is proposed for globally convergent homotopy methods, which finds DC operating points of transistor circuits efficiently. Numerical examples using practical transistor circuits show the effectiveness of the proposed algorithm.

  • A homotopy method using nonlinear auxiliary function

    Yasuaki Inoue, Yu Imai, Makoto Ando, Kiyotaka Yamamura

    電子情報通信学会第17回 回路とシステム(軽井沢)ワークショップ論文集     615 - 620  2004年

  • パス追跡回路 ― 式を回路で記述するSPICE指向型数値解析法 ―

    黒木渉, 大熊秀明, 山村清隆, 井上靖秋

    電子情報通信学会第17回 回路とシステム(軽井沢)ワークショップ論文集     351 - 356  2004年

  • 物理設計完全性のための新配線アーキテクチャ

    黒川敦, 小野信任, 鹿毛哲郎, 井上靖秋, 増田広生

    情報処理学会論文誌   45 ( 5 ) 1251 - 1260  2004年

  • A nonlinear homotopy method for solving transistor circuits

    Yasuaki Inoue, Yu Imai, Makoto Ando, Kiyotaka Yamamura

    Proceedings 2004 International Conference on Communications, Circuits and Systems (ICCCAS 2004), Chengdu, China     1354-1357B  2004年

  • An efficient homotopy method for solving transistor circuits

    Yasuaki Inoue, Yu Imai, Makoto Ando, Kiyotaka Yamamura

    Proceedings 2004 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2004), Hiroshima, Japan     II  2004年

  • Efficient capacitance extraction method for interconnects with dummy fills

    A Kurokawa, T Kanamoto, A Kasebe, Y Inoue, H Masuda

    PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE     485 - 488  2004年

     概要を見る

    The accuracy of parasitic extraction has become increasingly important for system-on-chip (SoC) designs. In this paper, we present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by the chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy metal fills on the parasitic capacitance, signal delay, and crosstalk noise. Moreover, we address that the existence of the interlayer dummy metal fills has more significant influences than the intralayer dummies in terms of the impact on coupling capacitances. When dummy metal fills are ignored, the error of capacitance extraction can be more than 30%, whereas the error of the proposed method is less than about 10% for many practical geometries. We also demonstrate, by comparison with capacitance results measured for a 90-nm test chip, that the error of the proposed method is less than 8%.

  • An algorithm for the “effective capacitance” of CMOS gate with interconnect load

    Zhang-cai Huang, Atsushi Kurokawa, Yasuaki Inoue, Jun-fa Mao

    Proceedings International Symposium on Nonlinear Theory and its Applications (NOLTA’04), Fukuoka, Japan     103 - 106  2004年

  • A homotopy method using nonlinear auxiliary function

    Yasuaki Inoue, Yu Imai, Makoto Ando, Kiyotaka Yamamura

    電子情報通信学会第17回 回路とシステム(軽井沢)ワークショップ論文集     615 - 620  2004年

  • A nonlinear homotopy method for solving transistor circuits

    Yasuaki Inoue, Yu Imai, Makoto Ando, Kiyotaka Yamamura

    Proceedings 2004 International Conference on Communications, Circuits and Systems (ICCCAS 2004), Chengdu, China     1354-1357B  2004年

  • An efficient homotopy method for solving transistor circuits

    Yasuaki Inoue, Yu Imai, Makoto Ando, Kiyotaka Yamamura

    Proceedings 2004 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2004), Hiroshima, Japan     II  2004年

  • Efficient capacitance extraction method for interconnects with dummy fills

    A Kurokawa, T Kanamoto, A Kasebe, Y Inoue, H Masuda

    PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE     485 - 488  2004年

     概要を見る

    The accuracy of parasitic extraction has become increasingly important for system-on-chip (SoC) designs. In this paper, we present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by the chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy metal fills on the parasitic capacitance, signal delay, and crosstalk noise. Moreover, we address that the existence of the interlayer dummy metal fills has more significant influences than the intralayer dummies in terms of the impact on coupling capacitances. When dummy metal fills are ignored, the error of capacitance extraction can be more than 30%, whereas the error of the proposed method is less than about 10% for many practical geometries. We also demonstrate, by comparison with capacitance results measured for a 90-nm test chip, that the error of the proposed method is less than 8%.

  • An algorithm for the “effective capacitance” of CMOS gate with interconnect load

    Zhang-cai Huang, Atsushi Kurokawa, Yasuaki Inoue, Jun-fa Mao

    Proceedings International Symposium on Nonlinear Theory and its Applications (NOLTA’04), Fukuoka, Japan     103 - 106  2004年

  • Theorems on the unique initial solution for globally convergent homotopy methods

    Y Inoue, S Kusanobu

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E86A ( 9 ) 2184 - 2191  2003年09月

     概要を見る

    Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. For the global convergence of homotopy methods, it is a necessary condition that a given initial solution is the unique solution to the homotopy equation. According to the conventional criterion, such an initial solution, however, is restricted in some very narrow region. In this paper, considering the circuit interpretation of homotopy equations, we prove theorems on the uniqueness of an initial solution for globally convergent homotopy methods. These theorems give new criteria extending the region wherein any desired initial solution satisfies the uniqueness condition.

  • Theorems on the unique initial solution for globally convergent homotopy methods

    Y Inoue, S Kusanobu

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E86A ( 9 ) 2184 - 2191  2003年09月

     概要を見る

    Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. For the global convergence of homotopy methods, it is a necessary condition that a given initial solution is the unique solution to the homotopy equation. According to the conventional criterion, such an initial solution, however, is restricted in some very narrow region. In this paper, considering the circuit interpretation of homotopy equations, we prove theorems on the uniqueness of an initial solution for globally convergent homotopy methods. These theorems give new criteria extending the region wherein any desired initial solution satisfies the uniqueness condition.

  • ニュートン不動点ホモトピーを用い非線形抵抗回路の大域的求解法

    井上靖秋, 山村清隆, 高橋朋弘, 草信佐栄子

    シミュレーション   22 ( 1 ) 43 - 48  2003年

  • An initial solution approach for globally convergent homotopy methods solving transistor circuits

    Yasuaki Inoue, Saeko Kusanobu, Makoto Ando, Kiyotaka Yamamura

    電子情報通信学会第16回 回路とシステム(軽井沢)ワークショップ論文集     47 - 54  2003年

  • An effective initial solution algorithm for globally convergent homotopy methods

    Y Inoue, S Kusanobu, K Yamamura, M Ando

    PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL III   3   196 - 199  2003年

     概要を見る

    In this paper, an effective initial solution algorithm is proposed for globally convergent homotopy methods, which Pnds DC operating points of transistor circuits efPciently. A new criterion on the initial solution necessary for guaranteeing the global convergence is presented for a practical class of transistor circuits. Numerical examples show the effectiveness of the proposed algorithm.

  • An interval algorithm for finding all solutions of nonlinear resistive circuits

    K Yamamura, N Igarashi, YA Inoue

    PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL III   3   192 - 195  2003年

     概要を見る

    An efficient algorithm is proposed for finding all solutions of nonlinear (not piecewise-linear) resistive circuits with mathematical certainty. This algorithm is based on interval analysis, the dual simplex method, and the contraction method. By numerical examples, it is shown that the proposed algorithm could find all solutions of systems of 500 similar to 700 nonlinear circuit equations in acceptable computation time.

  • An initial solution approach for globally convergent homotopy methods solving transistor circuits

    Yasuaki Inoue, Saeko Kusanobu, Makoto Ando, Kiyotaka Yamamura

    電子情報通信学会第16回 回路とシステム(軽井沢)ワークショップ論文集     47 - 54  2003年

  • An effective initial solution algorithm for globally convergent homotopy methods

    Y Inoue, S Kusanobu, K Yamamura, M Ando

    PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL III   3   196 - 199  2003年

     概要を見る

    In this paper, an effective initial solution algorithm is proposed for globally convergent homotopy methods, which Pnds DC operating points of transistor circuits efPciently. A new criterion on the initial solution necessary for guaranteeing the global convergence is presented for a practical class of transistor circuits. Numerical examples show the effectiveness of the proposed algorithm.

  • An interval algorithm for finding all solutions of nonlinear resistive circuits

    Kiyotaka Yamamura, Naoya Igarashi, Yasuaki Inoue

    Proceedings 2003 IEEE International Symposium on Circuits and Systems (ISCAS), Bangkok, Thailand   3   192 - 195  2003年

  • An efficient algorithm for finding multiple DC solutions based on the SPICE-oriented Newton homotopy method

    A Ushida, Y Yamagami, Y Nishio, Kinouchi, I, Y Inoue

    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS   21 ( 3 ) 337 - 348  2002年03月

     概要を見る

    It is a very important, but difficult, task to calculate the multiple dc solutions in circuit simulations. In this paper, we show a very simple SPICE-oriented Newton homotopy method which can efficiently find out the multiple dc solutions. In the paper, we show our solution curve-tracing algorithm based on the arc-length method and the Newton homotopy method. We will also prove an important theorem about how many variables should be chosen to implement our algorithm. It verifies that our simulator can be efficiently applied even if the circuit scales are relatively large. In Section III, we show that our Newton homotopy method is implemented by the transient analysis of SPICE. Thus, we do not need to formulate a troublesome circuit equation or the Jacobian matrix. Finally, applying our method to solve many important benchmark problems, all the solutions for the transistor circuits could be found on each homotopy path. Thus, our simulator can be efficiently applied to calculate the multiple de solutions and perhaps all the solutions.

    DOI CiNii

  • A practical approach for the fixed-point homotopy method using a solution-tracing circuit

    Y Inoue, S Kusanobu, K Yamamura

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E85A ( 1 ) 222 - 233  2002年01月

     概要を見る

    Finding DC operating-points of nonlinear circuits is an important and difficult task. The Newton-Raphson method employed in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. The fixed-point homotopy method is one of the excellent methods. However, from the viewpoint of implementation, it is important to study it further so that the method can be easily and widely used by many circuit designers. This paper presents a practical method to implement the fixed-point homotopy method. A special circuit called the solution-tracing circuit for the fixed-point homotopy method is proposed. By using this circuit, the solution curves of homotopy equations can be traced by performing the SPICE transient analysis. Therefore, no modification to the existing programs is necessary. Moreover, it is proved that the proposed method is globally convergent. Numerical examples show that the proposed technique is effective and can be easily implemented. By the proposed technique, many SPICE users can easily implement the fixed-point homotopy method.

  • Theorems on the uniqueness of an initial solution for homotopy methods

    Yasuaki Inoue, Saeko Kusanobu

    Proceedings International Symposium on Nonlinear Theory and its Applications (NOLTA’02), Xi’an, PRC     343 - 346  2002年

  • Theorems on the uniqueness of an initial solution for homotopy methods

    Yasuaki Inoue, Saeko Kusanobu

    Proceedings International Symposium on Nonlinear Theory and its Applications (NOLTA’02), Xi’an, PRC     343 - 346  2002年

  • Finding all solutions of nonlinear equations using inverses of approximate Jacobian matrices

    K Yamamura, T Kumakura, Y Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E84A ( 11 ) 2950 - 2952  2001年11月

    速報,短報,研究ノート等(学術雑誌)  

     概要を見る

    Recently, an efficient algorithm has been proposed for finding all solutions of systems of nonlinear equations using inverses of approximate Jacobian matrices. In this letter, an effective technique is proposed for improving the computational efficiency of the algorithm with a little bit of computational effort.

  • A practical implementation for the fixed-point homotopy method using the solution-tracing circuit

    Yasuaki Inoue, Saeko Kusanobu

    電子情報通信学会第14回 回路とシステム(軽井沢)ワークショップ論文集     293 - 298  2001年

  • An efficient algorithm for finding multiple DC solutions based on SPICE oriented Newton homotopy method

    A. Ushida, Y. Yamagami, I. Kinouchi, Y. Nishio, Y. Inoue

    Proceedings 2001 IEEE International Symposium on Circuits and Systems (ISCAS), Sydney   V   447 - 450  2001年

  • A solution-tracing circuit for the fixed-point homotopy method

    Yasuaki Inoue, Eigo Kaji, Saeko Kasanobu

    ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings   3   21 - 24  2001年

     概要を見る

    This paper presents a practical implementation approach for the fixed-point homotopy method which determines DC operating-points of nonlinear circuits. We propose a special circuit called the "solution-tracing circuit". By using this circuit, SPICE transient analysis is performed to trace the solution curves of the homotopy equations and to reach the DC operating points of the circuits to be solved. The proposed technique is effective and can be easily implemented. © 2001 IEEE.

    DOI

  • Newton-fixed-point homotopy method for finding DC operating-points of nonlinear circuits

    Yasuaki Inoue, Saeko Kusanobu, Kiyotaka Yamamura, Tomohiro Takahashi

    Proceedings 2001 International Technical Conference on Circuits/Systems, Computer and Communications (ITC-CSCC), Tokushima, Japan   I   370 - 373  2001年

  • ホモトピー連続法を用いた大規模回路解析――「軽井沢」での理論から実用化への道(招待講演)

    井上靖秋

    電子情報通信学会第13回 回路とシステム(軽井沢)ワークショップ論文集     173 - 180  2000年

  • A fixed-point homotopy method for solving modified nodal equations

    K Yamamura, T Sekiguchi, Y Inoue

    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS   46 ( 6 ) 654 - 665  1999年06月

     概要を見る

    Recently, the application of homotopy methods to practical circuit simulation has been remarkably developed, and bipolar analog integrated circuits with more than 10000 elements are now solved efficiently by the homotopy methods, There are several approaches to applying the homotopy methods to large-scale circuit simulation. One of them is combining the publicly available software package of the homotopy methods (such as HOMPACK) with the general-purpose circuit simulators such as SPICE. However, the homotopy method using the fixed-point (FP) homotopy (that is provided as a default in HOMPACK) is not guaranteed to converge for the modified nodal (MN) equations that are used in SPICE. In this paper, we propose a modified algorithm of the homotopy method using the FP homotopy and prove that this algorithm is globally convergent for the MN equations. We also show that the proposed algorithm converges to a stable operating point with high possibility from any initial point.

    DOI CiNii

  • A fixed-point homotopy method for solving modified nodal equations

    K Yamamura, T Sekiguchi, Y Inoue

    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS   46 ( 6 ) 654 - 665  1999年06月

     概要を見る

    Recently, the application of homotopy methods to practical circuit simulation has been remarkably developed, and bipolar analog integrated circuits with more than 10000 elements are now solved efficiently by the homotopy methods, There are several approaches to applying the homotopy methods to large-scale circuit simulation. One of them is combining the publicly available software package of the homotopy methods (such as HOMPACK) with the general-purpose circuit simulators such as SPICE. However, the homotopy method using the fixed-point (FP) homotopy (that is provided as a default in HOMPACK) is not guaranteed to converge for the modified nodal (MN) equations that are used in SPICE. In this paper, we propose a modified algorithm of the homotopy method using the FP homotopy and prove that this algorithm is globally convergent for the MN equations. We also show that the proposed algorithm converges to a stable operating point with high possibility from any initial point.

    DOI CiNii

  • 解曲線追跡のためのステップ幅制御アルゴリズム

    井上靖秋

    電子情報通信学会論文誌(A)   J78-A ( 3 ) 381 - 390  1995年

  • Practical algorithms for DC operating-point analysis of large-scale circuits(Invited)

    Yasuaki Inoue, Kiyotaka Yamamura

    International Symposium on Nonlinear Theory and its Applications (NOLTA), Las Vegas, Nevada     1153 - 1158  1995年

  • Practical algorithms for DC operating-point analysis of large-scale circuits(Invited)

    Yasuaki Inoue, Kiyotaka Yamamura

    International Symposium on Nonlinear Theory and its Applications (NOLTA), Las Vegas, Nevada     1153 - 1158  1995年

  • 大規模回路の直流動作点解析法

    井上靖秋

    電子情報通信学会論文誌(A)   J77-A ( 3 ) 388 - 398  1994年

  • A practical algorithm for DC operating-point analysis of large scale circuits(English translation of IEICE Trans., vol.J77-A, no.3, pp.388-398, March 1994.)

    Yasuaki Inoue

    Electronics and Communications in Japan, part3   77 ( 10 ) 49 - 62  1994年

  • A practical algorithm for DC operating-point analysis of large scale circuits(English translation of IEICE Trans., vol.J77-A, no.3, pp.388-398, March 1994.)

    Yasuaki Inoue

    Electronics and Communications in Japan, part3   77 ( 10 ) 49 - 62  1994年

  • DC analysis of nonlinear circuits using solution-tracing circuits(English translation of IEICE Trans, vol.J74-A, no.11, pp.1647-1655, Nov. 1991

    Yasuaki Inoue

    Electronics and Communications in Japan, part 3   75 ( 7 ) 52 - 63  1992年

  • 予測子修正子法を用いた解曲線追跡アルゴリズムの幾何学的解釈

    井上靖秋

    電子情報通信学会論文誌(A)   J75-A ( 11 ) 1682 - 1690  1992年

  • DC analysis of nonlinear circuits using solution-tracing circuits(English translation of IEICE Trans, vol.J74-A, no.11, pp.1647-1655, Nov. 1991

    Yasuaki Inoue

    Electronics and Communications in Japan, part 3   75 ( 7 ) 52 - 63  1992年

  • A SUPPORT SYSTEM FOR ANALOG CIRCUIT-DESIGN WITH HIERARCHICAL LIBRARY

    Y INOUE, M KATOH, Y YASUDA, H SATOMI, K NAKAYA

    IEEE TRANSACTIONS ON CONSUMER ELECTRONICS   37 ( 3 ) 635 - 641  1991年08月

     概要を見る

    The ability to design analog LSIs largely depends on the experience and knowledge of skilled engineers, and automating the design of such circuits by using the computer poses a difficult challenge. Thus, to develop analog LSIs in a relatively short period it is impotant to provide a system environment where skilled engineers can fully employ their collective creativity and make proper decisions, and where design information is efficiently shared, while promoting the repeated use of design properties. It is for these reasons that the authors have developed and put to practical use an interactive support system with a hierarchical library to support the design and verification of analog LSIs. This paper describes the system configuration of this support system for analog circuit design, outlines the system functions, and proposes a practical approach to building a hierarchical library suitable for the hierarchical design of analog LSIs. Moreover, this paper presents an application example of the hierarchical design of LSIs to illustrate the effectiveness of this system.

    DOI CiNii

  • A SUPPORT SYSTEM FOR ANALOG CIRCUIT-DESIGN WITH HIERARCHICAL LIBRARY

    Y INOUE, M KATOH, Y YASUDA, H SATOMI, K NAKAYA

    IEEE TRANSACTIONS ON CONSUMER ELECTRONICS   37 ( 3 ) 635 - 641  1991年08月

     概要を見る

    The ability to design analog LSIs largely depends on the experience and knowledge of skilled engineers, and automating the design of such circuits by using the computer poses a difficult challenge. Thus, to develop analog LSIs in a relatively short period it is impotant to provide a system environment where skilled engineers can fully employ their collective creativity and make proper decisions, and where design information is efficiently shared, while promoting the repeated use of design properties. It is for these reasons that the authors have developed and put to practical use an interactive support system with a hierarchical library to support the design and verification of analog LSIs. This paper describes the system configuration of this support system for analog circuit design, outlines the system functions, and proposes a practical approach to building a hierarchical library suitable for the hierarchical design of analog LSIs. Moreover, this paper presents an application example of the hierarchical design of LSIs to illustrate the effectiveness of this system.

    DOI CiNii

  • 連続法に基づく統計解析アルゴリズム

    井上靖秋

    電子情報通信学会論文誌(A)   J74-A ( 1 ) 63 - 71  1991年

  • A support system for analog circuit design with hierarchical library

    Yasuaki Inoue, Masami Katoh, Yuzo Yasuda, Hideo Satomi

    Digest of Technical Papers International Conference on Consumer Electronics, Rosemont, Illinois     114 - 115  1991年

  • DC analysis of non-linear circuits using solution tracing circuits

    Yasuaki Inoue

    Proceedings Seventeenth European Solid State Circuits Conference, Milan, Italy     41 - 44  1991年

    CiNii

  • 解曲線追跡回路を用いた非線形回路の直流解析

    井上靖秋

    電子情報通信学会論文誌(A)   J74-A ( 11 ) 1647 - 1655  1991年

  • A support system for analog circuit design with hierarchical library

    Yasuaki Inoue, Masami Katoh, Yuzo Yasuda, Hideo Satomi

    Digest of Technical Papers International Conference on Consumer Electronics, Rosemont, Illinois     114 - 115  1991年

  • DC analysis of non-linear circuits using solution tracing circuits

    Yasuaki Inoue

    Proceedings Seventeenth European Solid State Circuits Conference, Milan, Italy     41 - 44  1991年

  • アナログ回路設計用統合化CAEシステム

    井上靖秋

    ENGINEERS   483   6 - 14  1988年

▼全件表示

 

特別研究期間制度(学内資金)

  • ミクストシグナルLSI設計技術の研究

    2009年04月
    -
    2010年03月

    中国   上海交通大学

特定課題制度(学内資金)

  • スーパダンピング数値積分法を用いる擬似過渡解析法に関する研究

    2013年  

     概要を見る

    研究の背景と目的 擬似過渡解析法の大域的収束性(重大欠点)に対処する新たな数値積分手法スーパダンピング数値積分法を研究開発し,その有効性を理論と実験の両面から検証する. 回路シミュレーションの非収束の問題は古くから認識されている重要かつ困難な問題であり,これまで様々な観点から多数の研究がなされてきたが,未だ実用的解決に至ってない.全世界で広く実用されている業界標準回路シミュレータ(HSPICE など)もしばしば非収束の現象を起こす.本研究はこの非収束問題に対処する実用的なアルゴリズムの研究・開発に関するものである.具体的には,実用的(実装容易)な擬似過渡解析法の致命欠点を克服する新たな擬似過渡解析法を数値積分手法の立場から研究・開発し,回路シミュレータSPICE3 に実装してその有効性を検証する.研究成果 上述目的を達成するために,(1)数値積分手法の観点からの研究と(2)アルゴリズム実装手法の観点からの昨年度までの研究をさらに発展させる研究を行った.(1)数値積分手法の観点から擬似過渡解析法に適した新数値積分手法について研究した.具体的には,従来手法より大きなダンピング効果をもつ新数値積分手法(スーパダンピング数値積分法)について,理論的検討を加え,アルゴリズムを改良し,これを用いた擬似過渡解析手法を回路シミュレータSPICEに実装し,有効性を検証した.その結果,従来手法と比較して収束性能が格段に向上することを確認した.研究成果を国際会議で発表した.(2)アルゴリズム実装手法の観点から,擬似過渡解析法を回路シミュレータに実装する際のランピング手法について研究した.具体的には,擬似インダクタを用いる代わりに,ギジインダクタを挿入せず回路の電源をランピングさせる効果的な手法を提案し,回路シミュレータSPICEに実装し,有効性を検証した.これらの研究の結果,従来手法より収束性能が格段に向上することを確認した.研究成果を国際会議で発表した.更に,これまでの研究成果について,論文誌に投稿し採録された.

  • 新擬似過渡解析法に基づく大規模集積回路網の大域的求解法に関する研究

    2012年  

     概要を見る

    研究の背景と目的回路シミュレーションの非収束の問題は古くから認識されている重要かつ困難な問題であり,これまで様々な観点から多数の研究がなされてきたが,未だ実用的解決に至ってない.全世界で広く実用されている業界標準回路シミュレータ(HSPICE など)もしばしば非収束の現象を起こす.本研究はこの非収束問題に対処する実用的なアルゴリズムの研究・開発に関するものである.研究代表者のこれまでの一連の関連研究成果を更に発展させて,世界一の実用技術を研究・開発し,回路シミュレータの重要かつ困難な課題を解決することを狙いとしている.具体的には,実用的(実装容易)な擬似過渡解析法の致命欠点を克服する新たな擬似過渡解析法を数値積分手法の立場から研究・開発し,回路シミュレータSPICE3 に実装してその有効性を検証する.研究成果上述目的を達成するために,(1)数値積分手法の観点からの研究と(2)アルゴリズム実装手法の観点からの研究を行った.(1)数値積分手法の観点から擬似過渡解析法に適した新数値積分手法について研究した.具体的には,従来手法より大きなダンピング効果をもつ新数値積分手法を提案し,これを用いた擬似過渡解析手法を回路シミュレータSPICEに実装し,有効性を検証した.その結果,従来手法より収束性能が格段に向上することを確認した.(2)アルゴリズム実装手法の観点から,擬似過渡手法を回路シミュレータに実装する際の実装手法と擬似素子の埋め込み位置について研究した.具体的には,複合擬似素子を用いる擬似過渡解析法において,数値積分公式を複合擬似素子に適用し実装する際に,複数の実装法があることを見出して,新たな実装法を提案し,回路シミュレータSPICEに実装し,有効性を検証した.更に,複合擬似素子を元の回路に埋め込む(挿入する)際の埋め込み位置についても検討し,CMOS回路に適したある埋め込み位置があることを発見した.これらの研究の結果,従来手法より収束性能が格段に向上することを確認した.

  • 擬似過渡解析法に基づく大規模集積回路網の大域的求解法に関する研究

    2007年  

     概要を見る

     1.研究計画の概要本研究では,集積回路の回路シミュレーションにおける非収束問題に対する擬似過渡解析法の致命欠点を克服する新たな手法を実現する第一段階として,そのアルゴリズムの中核となる擬似エレメントの開発と有効性の検証を行う.1.1 擬似過渡解析の擬似エレメントの開発従来の擬似過渡解析法では,擬似エレメントとして純粋なリアクタンス素子が用いられていた.このために,解くべき回路が新たに発振するという致命欠点があった.これを克服する新たな複合擬似エレメントとそれを用いた解法アルゴリズムを開発する. 1.2 擬似エレメント実装手法の開発複合擬似エレメントを用いる手法を回路シミュレータに実装する場合に,新たに変数と方程式の数が増加するという問題が生じる.これを解決するために,変数と方程式の数が解くべき回路と同じサイズで,ヤコビ行列の構造の変更が不要な実装手法を開発する.1.3 数値実験と有効性の検証前述複合擬似エレメントと実装手法を回路シミュレータSPICE3にソースコードレベルで試験的に実装する.更に,実用回路を用いた数値実験により,前述擬似過渡解析法の有効性を検証する. 2.研究成果(1) 複合擬似エレメントの開発: 旧来の擬似エレメントの概念を拡張して,リアクタンス虚数軸直線上からインピーダンス(アドミタンス)平面へと拡張する複合擬似エレメントについて検討し,実用回路に有効なエレメントの組み合わせ,時変特性について最適化を行った.(2)実装手法の開発: 複合擬似エレメント実装の際に生ずる変数と方程式の増大に対処する新たな実装手法を検討し,複合擬似素子の変数を縮退する手法を開発した.変数と方程式の数が解くべき回路方程式と同じサイズで,ヤコビ行列の構造の変更が不要である.(3)数値実験と有効性の検証:SPICE3の内部構造を調査して,前述手法をソースコードレベルでSPICE3に実装した.それを用いて数値実験し,アルゴリズムの制御パラメータの最適化等を行い,提案手法(複合擬似エレメント,実装手法)の有効性を検証した.

  • 擬似過渡解析法に基づく大規模集積回路網の大域的求解法に関する研究

    2006年  

     概要を見る

    1.研究の目的 本研究では,擬似過渡解析法に基づく大規模集積回路網の大域的求解法を開発する.擬似過渡解析法に関する要素技術としては次のような点があげられる.(1)解くべき直流回路に擬似的に挿入する擬似リアクタンスを含む擬似エレメント(2)擬似エレメントの挿入箇所(3)擬似エレメントの時間軸での制御(4)擬似過渡解析のアルゴリズムの制御 本研究では上述要素技術について研究して,今後のユビキタス時代に向けたアナログデジタル混載システムLSI(バイポーラ・CMOS回路)に有効で,より効率的で実現容易な解法と実施手法を開発し,更に,実用回路の解析に適用して,その有効性を検証し,幅広く実施可能な大域的求解法を確立することを目的とする.2.研究成果概要(1)時変素子を用いる擬似過渡解析法アルゴリズムの開発:解くべき回路に擬似的に挿入するリアクタンスに加えて新たに時変抵抗を用いて発振の問題を解決し,擬似過渡解析法を大域的収束性を保証するアルゴリズムへと発展させる手法を開発した.(2)回路シミュレータSPICEへの実装提案手法を回路シミュレータSPICE上に効果的に実装する手法を検討し,擬似過渡解析法回路シミュレータプロトタイプ版を開発した.(3)実用回路で有効性確認プロトタイプ版回路シミュレータを実用回路の解析に適用し,提案手法の有効性を確認した.(4)研究論文発表論文誌1件,国際会議2件,国内会議(査読付)1件,研究会1件,特許出願1件.このほかに,論文誌に1件投稿中.