Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. However, the previous studies are mainly focused on the bipolar transistor circuits. Also the efficiencies of the previous homotopy methods for MOS transistor circuits are not satisfactory. Therefore, finding a more efficient homotopy method for MOS transistor circuits becomes necessary and important. This paper proposes a Newton fixed-point homotopy method for MOS transistor circuits and proposes an embedding algorithm in the implementation as well. Moreover, the global convergence theorems of the proposed Newton fixed-point homotopy method for MOS transistor circuits are also proved. Numerical examples show that the efficiencies for finding DC operating points of MOS transistor circuits by the proposed MOS Newton fixed-point homotopy method with the two embedding types can be largely enhanced (can larger than 50%) comparing with the conventional MOS homotopy methods, especially for some large-scale MOS transistor circuits which can not be easily solved by the SPICE3 and HSPICE simulators.

Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. However, the previous studies are mainly focused on the bipolar transistor circuits. Also the efficiencies of the previous homotopy methods for MOS transistor circuits are not satisfactory. Therefore, finding a more efficient homotopy method for MOS transistor circuits becomes necessary and important. This paper proposes a Newton fixed-point homotopy method for MOS transistor circuits and proposes an embedding algorithm in the implementation as well. Moreover, the global convergence theorems of the proposed Newton fixed-point homotopy method for MOS transistor circuits are also proved. Numerical examples show that the efficiencies for finding DC operating points of MOS transistor circuits by the proposed MOS Newton fixed-point homotopy method with the two embedding types can be largely enhanced (can larger than 50%) comparing with the conventional MOS homotopy methods, especially for some large-scale MOS transistor circuits which can not be easily solved by the SPICE3 and HSPICE simulators.

With the scaling of CMOS devices toward their ultimate dimensions, device performance variability induced by process variation has become a critical issue in analog LS I designs. Statistical device model library building based on statistical device model considering the process variation accurately is useful to predict the performance of analog LS I designs. However, conventional statistical device models are either complicated or not accurate enough. Therefore, a simple and practical statistical device model for analog LS I designs is proposed in this paper. Simultaneously, a simple method to extract model parameters is also proposed. Statistical analysis results of 0.65um CMOS Op-Amp based on the proposed model using Monte Carlo simulation have a good agreement with the chip measurement results. © 2013 IEEE.

Recently, the compound element pseudo transient analysis method, CEPTA, is regarded as an efficient practical method to find DC operating points of nonlinear circuits when the Newton-Raphson method fails. In this paper, an effective SPICE3 implementation algorithm for the CEPTA method is proposed. It can significantly improve simulation efficiency with smaller limitations during simulation. Besides, the influence of different pseudo-elements' embedding positions on the simulation efficiency is also discussed and presented with numerical examples. Several numerical examples demonstrate the improvement of simulation efficiency and convergence performance. © 2013 IEEE.

In this paper, new numerical integration algorithms with artificial damping effect are proposed which can be applied to the constant, pure PTA method to find DC operating points of nonlinear circuits when the Newton-Raphson method fails. This method can effectively avoid the oscillation and the 'time step too small' problems compared with conventional PTA algorithms. The mathematical description for this method is presented. The application of the proposed method is illustrated by solving practical CMOS nonlinear circuits. © 2013 IEEE.

The overshooting effect, which is induced by the input-to-output coupling capacitance, has an significant effect on CMOS gate delay with the scaling of CMOS technology. In this paper, an effective analytical model is proposed to calculate the overshooting time of multiple-input gates. The proposed model is verified having a good agreement with SPICE simulation results. © 2013 IEEE.

Recently, the compound element pseudo transient analysis, CEPTA, method is regarded as an efficient practical method to find DC operating points of nonlinear circuits when the Newton-Raphson method fails. In the previous CEPTA method, an effective SPICE3 implementation algorithm was proposed without expanding the Jacobian matrix. However the limitation of step size was not well considered. Thus, the non-convergence problem occurs and the simulation efficiency is still a big challenge for current LSI nonlinear cicuits, especially for some practical large-scale circuits. Therefore, in this paper, we propose a new SPICE3 implementation algorithm and an embedding algorithm, which is where to insert the pseudo capacitors, for the CEPTA method. The proposed implementation algorithm has no limitation for step size and can significantly improve simulation efficiency. Considering the existence of various types of circuits, we extend some possible embedding positions. Numerical examples demonstrate the improvement of simulation efficiency and convergence performance.© 2013 The Institute of Electronics, Information and Communication Engineers.

With the scaling of CMOS devices toward their ultimate dimensions, device performance variability induced by process variation has become a critical issue in analog LS I designs. Statistical device model library building based on statistical device model considering the process variation accurately is useful to predict the performance of analog LS I designs. However, conventional statistical device models are either complicated or not accurate enough. Therefore, a simple and practical statistical device model for analog LS I designs is proposed in this paper. Simultaneously, a simple method to extract model parameters is also proposed. Statistical analysis results of 0.65um CMOS Op-Amp based on the proposed model using Monte Carlo simulation have a good agreement with the chip measurement results. © 2013 IEEE.

Recently, the compound element pseudo transient analysis method, CEPTA, is regarded as an efficient practical method to find DC operating points of nonlinear circuits when the Newton-Raphson method fails. In this paper, an effective SPICE3 implementation algorithm for the CEPTA method is proposed. It can significantly improve simulation efficiency with smaller limitations during simulation. Besides, the influence of different pseudo-elements' embedding positions on the simulation efficiency is also discussed and presented with numerical examples. Several numerical examples demonstrate the improvement of simulation efficiency and convergence performance. © 2013 IEEE.

In this paper, new numerical integration algorithms with artificial damping effect are proposed which can be applied to the constant, pure PTA method to find DC operating points of nonlinear circuits when the Newton-Raphson method fails. This method can effectively avoid the oscillation and the 'time step too small' problems compared with conventional PTA algorithms. The mathematical description for this method is presented. The application of the proposed method is illustrated by solving practical CMOS nonlinear circuits. © 2013 IEEE.

The overshooting effect, which is induced by the input-to-output coupling capacitance, has an significant effect on CMOS gate delay with the scaling of CMOS technology. In this paper, an effective analytical model is proposed to calculate the overshooting time of multiple-input gates. The proposed model is verified having a good agreement with SPICE simulation results. © 2013 IEEE.

Recently, the compound element pseudo transient analysis, CEPTA, method is regarded as an efficient practical method to find DC operating points of nonlinear circuits when the Newton-Raphson method fails. In the previous CEPTA method, an effective SPICE3 implementation algorithm was proposed without expanding the Jacobian matrix. However the limitation of step size was not well considered. Thus, the non-convergence problem occurs and the simulation efficiency is still a big challenge for current LSI nonlinear cicuits, especially for some practical large-scale circuits. Therefore, in this paper, we propose a new SPICE3 implementation algorithm and an embedding algorithm, which is where to insert the pseudo capacitors, for the CEPTA method. The proposed implementation algorithm has no limitation for step size and can significantly improve simulation efficiency. Considering the existence of various types of circuits, we extend some possible embedding positions. Numerical examples demonstrate the improvement of simulation efficiency and convergence performance.© 2013 The Institute of Electronics, Information and Communication Engineers.

Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. However, most previous studies are mainly focused on the bipolar transistor circuits and no paper presents the global convergence theorems of homotopy methods for MOS transistor circuits. Moreover, due to the improvements and advantages of MOS transistor technologies, extending the homotopy methods to MOS transistor circuits becomes more and more necessary and important. This paper proposes two nonlinear homotopy methods for MOS transistor circuits and proves the global convergence theorems for the proposed MOS nonlinear homotopy method II. Numerical examples show that both of the two proposed homotopy methods for MOS transistor circuits are more effective for finding DC operating points than the conventional MOS homotopy method and they are also capable of finding DC operating points for large-scale circuits.

Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. However, most previous studies are mainly focused on the bipolar transistor circuits and no paper presents the global convergence theorems of homotopy methods for MOS transistor circuits. Moreover, due to the improvements and advantages of MOS transistor technologies, extending the homotopy methods to MOS transistor circuits becomes more and more necessary and important. This paper proposes two nonlinear homotopy methods for MOS transistor circuits and proves the global convergence theorems for the proposed MOS nonlinear homotopy method II. Numerical examples show that both of the two proposed homotopy methods for MOS transistor circuits are more effective for finding DC operating points than the conventional MOS homotopy method and they are also capable of finding DC operating points for large-scale circuits.

With the advent of nanometer age in digital circuits, the overshooting time becomes an important component of gate delay for CMOS logic gates. However, there has been little attention paid to the research of the overshooting effect for multi-input gate in nanometer technologies until now. Therefore, in this paper, an effective model considering the overshooting effect of multi-input gate is presented. The experimental results using 32-nm PTM model reflect that the proposed model is accurate within 3.6% error compared with SPICE simulation results.

With the advent of nanometer age in digital circuits, the overshooting time becomes an important component of gate delay for CMOS logic gates. However, there has been little attention paid to the research of the overshooting effect for multi-input gate in nanometer technologies until now. Therefore, in this paper, an effective model considering the overshooting effect of multi-input gate is presented. The experimental results using 32-nm PTM model reflect that the proposed model is accurate within 3.6% error compared with SPICE simulation results.

In retargeting of a nano-watt CMOS reference circuit, we adopt an advanced compact MOSFET model to describe the drain current consistently in strong and weak inversion levels. Based on this model, we describe all bias conditions in terms of ratios of the channel widths and lengths. Taking the effect of very long channels into account, we formulate the threshold voltage as a function of the drain-source voltage. Furthermore, we introduce a tuning parameter with the empirical range and fix all transistor sizes sweeping this parameter as well as applying a simulation. In case studies, we retargeted a circuit from the 180nm/1.8V process to the 90nm/1.2V, 2.5V, 3.3V processes. Besides, we fabricated the circuit in the 90nm/1.2V process, and confirmed the good measurement results such as less than 12.8%/V supply voltage variation and only 1.1nW power consumption.

This paper presents a sub-0.3V CMOS full-wave rectifier for energy harvesting devices. By adopting a body-input comparator with simple bias circuit, combining with body bias technique, the lowest input voltage amplitude can be reduced to 0.28V when using a standard CMOS 0.18µm process. Moreover, the voltage drop of negative voltage converter can be reduced to enhance the output voltage efficiency by adopting the proposed body bias technique. In combination with minimum reverse current and simple bias circuit in the proposed comparator, the proposed active rectifier can achieve the peak voltage conversion efficiency of over 96% and the maximum power efficiency of approximately 94%.

Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. However, most previous studies are mainly focused on the bipolar transistor circuits. Also the efficiencies of the previous homotopy methods for MOS transistor circuits are not satisfactory. Therefore, finding a more efficient homotopy method for MOS transistor circuits becomes necessary and important. This paper extends the Newton Fixed-Point homotopy method to MOS transistor circuits. Numerical examples show that the extended Newton Fixed-Point homotopy method is more effective for finding DC operating points of MOS transistor circuits than the conventional MOS homotopy method and the MOS nonlinear homotopy methods, especially for the large-scale MOS transistor circuits. Moreover, the global convergence of the extended Newton Fixed-Point homotopy method for MOS transistor circuits has also been proved.

Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. to overcome this convergence problem, homotopy methods have been studied from various viewpoints. However, most previous studies are mainly focused on the bipolar transistor circuits. Also the efficiencies of the previous homotopy methods for MOS transistor circuits are not satisfactory. Therefore, finding a more efficient homotopy method for MOS transistor circuits becomes necessary and important. This paper proposes the Newton Fixed-Point homotopy method for MOS transistor circuits and also proposes the embedding algorithm in the implementation. Numerical examples show that the proposed MOS Newton Fixed-Point homotopy methods with two embedding types are more effective for finding DC operating points of MOS transistor circuits than the conventional MOS homotopy methods. Moreover, the global convergence of the proposed Newton Fixed-Point homotopy method for MOS transistor circuits has also been proved.

In retargeting of a nano-watt CMOS reference circuit, we adopt an advanced compact MOSFET model to describe the drain current consistently in strong and weak inversion levels. Based on this model, we describe all bias conditions in terms of ratios of the channel widths and lengths. Taking the effect of very long channels into account, we formulate the threshold voltage as a function of the drain-source voltage. Furthermore, we introduce a tuning parameter with the empirical range and fix all transistor sizes sweeping this parameter as well as applying a simulation. In case studies, we retargeted a circuit from the 180nm/1.8V process to the 90nm/1.2V, 2.5V, 3.3V processes. Besides, we fabricated the circuit in the 90nm/1.2V process, and confirmed the good measurement results such as less than 12.8%/V supply voltage variation and only 1.1nW power consumption.

This paper presents a sub-0.3V CMOS full-wave rectifier for energy harvesting devices. By adopting a body-input comparator with simple bias circuit, combining with body bias technique, the lowest input voltage amplitude can be reduced to 0.28V when using a standard CMOS 0.18µm process. Moreover, the voltage drop of negative voltage converter can be reduced to enhance the output voltage efficiency by adopting the proposed body bias technique. In combination with minimum reverse current and simple bias circuit in the proposed comparator, the proposed active rectifier can achieve the peak voltage conversion efficiency of over 96% and the maximum power efficiency of approximately 94%.

Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. However, most previous studies are mainly focused on the bipolar transistor circuits. Also the efficiencies of the previous homotopy methods for MOS transistor circuits are not satisfactory. Therefore, finding a more efficient homotopy method for MOS transistor circuits becomes necessary and important. This paper extends the Newton Fixed-Point homotopy method to MOS transistor circuits. Numerical examples show that the extended Newton Fixed-Point homotopy method is more effective for finding DC operating points of MOS transistor circuits than the conventional MOS homotopy method and the MOS nonlinear homotopy methods, especially for the large-scale MOS transistor circuits. Moreover, the global convergence of the extended Newton Fixed-Point homotopy method for MOS transistor circuits has also been proved.

Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. to overcome this convergence problem, homotopy methods have been studied from various viewpoints. However, most previous studies are mainly focused on the bipolar transistor circuits. Also the efficiencies of the previous homotopy methods for MOS transistor circuits are not satisfactory. Therefore, finding a more efficient homotopy method for MOS transistor circuits becomes necessary and important. This paper proposes the Newton Fixed-Point homotopy method for MOS transistor circuits and also proposes the embedding algorithm in the implementation. Numerical examples show that the proposed MOS Newton Fixed-Point homotopy methods with two embedding types are more effective for finding DC operating points of MOS transistor circuits than the conventional MOS homotopy methods. Moreover, the global convergence of the proposed Newton Fixed-Point homotopy method for MOS transistor circuits has also been proved.

Gate delay evaluation is always a vital concern for high-performance digital VLSI designs. As the feature size of VLSIs decreases to the nano-meter region, the work to obtain an accurate gate delay value becomes more difficult and time consuming than ever. The conventional methods usually use iterative algorithms to ensure the accuracy of the effective capacitance C-eff, which is usually used to compute the gate delay with interconnect loads and to capture the output signal shape of the real gate response. Accordingly, the efficiency is sacrificed. In this paper, an accurate and efficient approach is proposed for gate delay estimation. With the linear relationship of gate output time points and C-eff, a polynomial approximation is used to make the nonlinear effective capacitance equation be solved without iterative method. Compared to the conventional methods, the proposed method improves the efficiency of gate delay calculation. Meanwhile, experimental results show that the proposed method is in good agreement with SPICE results and the average error is 2.8%.

Gate delay evaluation is always a vital concern for high-performance digital VLSI designs. As the feature size of VLSIs decreases to the nano-meter region, the work to obtain an accurate gate delay value becomes more difficult and time consuming than ever. The conventional methods usually use iterative algorithms to ensure the accuracy of the effective capacitance C-eff, which is usually used to compute the gate delay with interconnect loads and to capture the output signal shape of the real gate response. Accordingly, the efficiency is sacrificed. In this paper, an accurate and efficient approach is proposed for gate delay estimation. With the linear relationship of gate output time points and C-eff, a polynomial approximation is used to make the nonlinear effective capacitance equation be solved without iterative method. Compared to the conventional methods, the proposed method improves the efficiency of gate delay calculation. Meanwhile, experimental results show that the proposed method is in good agreement with SPICE results and the average error is 2.8%.

Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. However most previous studies are mainly focused on the bipolar transistor circuits and no paper presents the global convergence of the homotopy method for MOS circuits. This paper extends the nonlinear homotopy method to MOS transistor circuits and presents the global convergence theorems of the homotopy method for MOS circuits. © 2011 IEEE.

Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. However most previous studies are mainly focused on the bipolar transistor circuits and no paper presents the global convergence of the homotopy method for MOS circuits. This paper extends the nonlinear homotopy method to MOS transistor circuits and presents the global convergence theorems of the homotopy method for MOS circuits. © 2011 IEEE.

Recently, the power management becomes significantly important for the ultra power wireless sensor node powered by energy harvesting devices. In this paper, a power management system from battery to wireless sensor node is proposed for wireless structure health monitoring applications. By using the proposed circuits, the power supply of a sensor network node is switched on only when some event is detected to reduce its average power consumption. In the proposed circuit, the nanopower reference is utilized to bias control circuits. Therefore, the proposed management system has an extremely low power consumption of less than 100nA standby current. The proposed circuits are implemented with a 1.2 mu m CMOS process. Experimental results demonstrate the low power feature of the proposed power management system.

Recently, the power management becomes significantly important for the ultra power wireless sensor node powered by energy harvesting devices. In this paper, a power management system from battery to wireless sensor node is proposed for wireless structure health monitoring applications. By using the proposed circuits, the power supply of a sensor network node is switched on only when some event is detected to reduce its average power consumption. In the proposed circuit, the nanopower reference is utilized to bias control circuits. Therefore, the proposed management system has an extremely low power consumption of less than 100nA standby current. The proposed circuits are implemented with a 1.2 mu m CMOS process. Experimental results demonstrate the low power feature of the proposed power management system.

With the scaling of complementary metal-oxidesemiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacitance has more significant influence on CMOS gate analysis, especially on CMOS gate static timing analysis. In this paper, the overshooting effect is modeled for CMOS inverter delay analysis in nanometer technologies. The results produced by the proposed model are close to simulation program with integrated circuit emphasis (SPICE). Moreover, the influence of the overshooting effect on CMOS inverter analysis is discussed. An analytical model is presented to calculate the CMOS inverter delay time based on the proposed overshooting effect model, which is verified to be in good agreement with SPICE results. Furthermore, the proposed model is used to improve the accuracy of the switch-resistor model for approximating the inverter output waveform.

With the scaling of complementary metal-oxidesemiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacitance has more significant influence on CMOS gate analysis, especially on CMOS gate static timing analysis. In this paper, the overshooting effect is modeled for CMOS inverter delay analysis in nanometer technologies. The results produced by the proposed model are close to simulation program with integrated circuit emphasis (SPICE). Moreover, the influence of the overshooting effect on CMOS inverter analysis is discussed. An analytical model is presented to calculate the CMOS inverter delay time based on the proposed overshooting effect model, which is verified to be in good agreement with SPICE results. Furthermore, the proposed model is used to improve the accuracy of the switch-resistor model for approximating the inverter output waveform.

A bulk-current model for advanced metal oxide semiconductor field effect transistors (MOSFETs) is proposed and implemented. The model consists of,in impact ionization mechanism, the drain to bulk current and a tunneling mechanism, the gate to bulk Current. and requires totally 21 model parameters covering all bias conditions. The simulated results With the parameter values reproduce measurements for any device size without binning. Validity of the model has been tested With Circuits, which are sensitive to the change of the stored charge due to impact ionization current and tunneling current. (C) 2010 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

This paper presents a low voltage CMOS full-wave rectifier for wirelessly powered devices. By using a simple comparator-controlled switch, the lowest input voltage amplitude can be reduced to 0.7V when using a standard CMOS 0.18 mu m process. With only one comparator, the proposed design dramatically reduces the production cost. In combination with unbalanced transistor scale, the proposed rectifier can achieve a maximum peak voltage conversion efficiency of more than 93% and power efficiency near to 87%.

In this paper, a CMOS sub-1-V nanopower reference is proposed, which is implemented without resistors and with only standard CMOS transistors. The proposed circuit has the most attractive merit that it can afford reference current and reference voltage simultaneously. Moreover, the leakage compensation technique is utilized, and thus it has very low temperature coefficient for a wide temperature range. The proposed circuit is verified by SPICE simulation with CMOS 0.18um process. The temperature coefficient of the reference voltage and reference current are 0.0037%/°C and 0.0091%/°C, respectively. Also, the power supply voltage can be as low as 0.85V and its power consumption is only 5.1nW. ©2010 IEEE.

In Static Timing Analysis, the conventional methods usually use an iterative method to ensure the accuracy of the effective capacitance G ef f which is usually used to compute the delay of gate with interconnect load and to capture the output signal shape of the real gate response. In this paper, a polynomial approximation method is used to make the nonlinear Gef f equation be solved without iterative method. Compared to the conventional methods, the proposed method has the merit of improving the efficiency for Gef f calculation. Meanwhile, experimental results show that the proposed method is in agreement with the Spice simulation. © 2010 IEEE.

This paper presents a low voltage CMOS full-wave rectifier for transcutaneous power transmission in low power battery-less devices such as biomedical implants. By using a simple comparator-controlled switch which needs a small supply voltage, the lowest input voltage amplitude can be reduced to 0.7V with a standard CMOS 0.18µm process. With only one comparator, the proposed design dramatically reduces the power loss and the production cost. In combination with current offset which minimize the reverse current of the rectifier under different input amplitudes, the proposed rectifier can achieve a maximum peak voltage conversion efficiency of more than 93% and a power efficiency of approximately 87%.

A bulk-current model for advanced metal oxide semiconductor field effect transistors (MOSFETs) is proposed and implemented. The model consists of,in impact ionization mechanism, the drain to bulk current and a tunneling mechanism, the gate to bulk Current. and requires totally 21 model parameters covering all bias conditions. The simulated results With the parameter values reproduce measurements for any device size without binning. Validity of the model has been tested With Circuits, which are sensitive to the change of the stored charge due to impact ionization current and tunneling current. (C) 2010 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

This paper presents a low voltage CMOS full-wave rectifier for wirelessly powered devices. By using a simple comparator-controlled switch, the lowest input voltage amplitude can be reduced to 0.7V when using a standard CMOS 0.18 mu m process. With only one comparator, the proposed design dramatically reduces the production cost. In combination with unbalanced transistor scale, the proposed rectifier can achieve a maximum peak voltage conversion efficiency of more than 93% and power efficiency near to 87%.

In this paper, a CMOS sub-1-V nanopower reference is proposed, which is implemented without resistors and with only standard CMOS transistors. The proposed circuit has the most attractive merit that it can afford reference current and reference voltage simultaneously. Moreover, the leakage compensation technique is utilized, and thus it has very low temperature coefficient for a wide temperature range. The proposed circuit is verified by SPICE simulation with CMOS 0.18um process. The temperature coefficient of the reference voltage and reference current are 0.0037%/°C and 0.0091%/°C, respectively. Also, the power supply voltage can be as low as 0.85V and its power consumption is only 5.1nW. ©2010 IEEE.

In Static Timing Analysis, the conventional methods usually use an iterative method to ensure the accuracy of the effective capacitance G ef f which is usually used to compute the delay of gate with interconnect load and to capture the output signal shape of the real gate response. In this paper, a polynomial approximation method is used to make the nonlinear Gef f equation be solved without iterative method. Compared to the conventional methods, the proposed method has the merit of improving the efficiency for Gef f calculation. Meanwhile, experimental results show that the proposed method is in agreement with the Spice simulation. © 2010 IEEE.

This paper presents a low voltage CMOS full-wave rectifier for transcutaneous power transmission in low power battery-less devices such as biomedical implants. By using a simple comparator-controlled switch which needs a small supply voltage, the lowest input voltage amplitude can be reduced to 0.7V with a standard CMOS 0.18µm process. With only one comparator, the proposed design dramatically reduces the power loss and the production cost. In combination with current offset which minimize the reverse current of the rectifier under different input amplitudes, the proposed rectifier can achieve a maximum peak voltage conversion efficiency of more than 93% and a power efficiency of approximately 87%.

In deep submicron designs, predicting gate delays with interconnect load is a noteworthy work for Static Timing Analysis (STA). The effective capacitance C-eff concept and the Thevenin model that replaces the gate with a linear resistor and a voltage source are usually used to calculate the delay of gate with interconnect load. In conventional methods, it is not considered that the charges transferred into interconnect load and C-eff in the Thevenin model rue not equal. The charge difference between interconnect load and C-eff has the large influence to the accuracy of computing C-eff. In this paper, an advanced effective capacitance model is proposed to consider the above problem in the Thevenin model, where the influence of the charge difference is modeled as one part of the effective capacitance to compute the gate delay. Experimental results show a significant improvement in accuracy when the charge difference between interconnect load and C-eff is considered.

In deep submicron designs, predicting gate delays with interconnect load is a noteworthy work for Static Timing Analysis (STA). The effective capacitance C-eff concept and the Thevenin model that replaces the gate with a linear resistor and a voltage source are usually used to calculate the delay of gate with interconnect load. In conventional methods, it is not considered that the charges transferred into interconnect load and C-eff in the Thevenin model rue not equal. The charge difference between interconnect load and C-eff has the large influence to the accuracy of computing C-eff. In this paper, an advanced effective capacitance model is proposed to consider the above problem in the Thevenin model, where the influence of the charge difference is modeled as one part of the effective capacitance to compute the gate delay. Experimental results show a significant improvement in accuracy when the charge difference between interconnect load and C-eff is considered.

A PN junction current model for advanced MOSFETs is proposed and implemented into HiSIM2, a complete surface-potential-based MOSFET model. The model includes forward diode currents and reverse diode currents, and requires a total of 13 model parameters covering all bias conditions. Model simulation results reproduce measurements for different device geometries over a wide range of bias and temperature values.

A PN junction current model for advanced MOSFETs is proposed and implemented into HiSIM2, a complete surface-potential-based MOSFET model. The model includes forward diode currents and reverse diode currents, and requires a total of 13 model parameters covering all bias conditions. Model simulation results reproduce measurements for different device geometries over a wide range of bias and temperature values.

A GIDL (Gate Induced Drain Leakage) current model for advanced MOS-FETs is proposed and implemented into HiSIM2, complete surface potential based MOSFET model. The model considers two tunneling mechanisms, the band-to-band tunneling and the trap assisted tunneling. Totally 7 model parameters are introduced. Simulation results of NFETs and PFETs reproduce measurements for any device size without binning of model parameters. The influence of the GIDL current is investigated with circuits, which are sensitive to the change of the stored charge due to the GIDL current. © 2009 Information Processing Society of Japan.

A Cockcroft-Walton type charge pump circuit is proposed in this paper. Compared with Dickson type, each transistor and capacitor in the proposed circuit just stand against the voltage less than one Vdd, so that a low break-down voltage process can be applied to this kind of charge pump to reduce the chip area cost and break-down risk. By using the proposed structure, the performances of voltage boosting efficiency and power efficiency can reach 98.9% and 87%.

A GIDL (Gate Induced Drain Leakage) current model for advanced MOS-FETs is proposed and implemented into HiSIM2, complete surface potential based MOSFET model. The model considers two tunneling mechanisms, the band-to-band tunneling and the trap assisted tunneling. Totally 7 model parameters are introduced. Simulation results of NFETs and PFETs reproduce measurements for any device size without binning of model parameters. The influence of the GIDL current is investigated with circuits, which are sensitive to the change of the stored charge due to the GIDL current. © 2009 Information Processing Society of Japan.

A Cockcroft-Walton type charge pump circuit is proposed in this paper. Compared with Dickson type, each transistor and capacitor in the proposed circuit just stand against the voltage less than one Vdd, so that a low break-down voltage process can be applied to this kind of charge pump to reduce the chip area cost and break-down risk. By using the proposed structure, the performances of voltage boosting efficiency and power efficiency can reach 98.9% and 87%.

In deep submicron designs, predicting gate delay time is a noteworthy work for Static Timing Analysis. The effective capacitance C-eff concept is usually used to calculate the gate delay with interconnect loads. Conventionally, the input-signal to the gate is always assumed as a ramp waveform. However, the input signal is also the output of CMOS gates with interconnect loads and not the ramp waveform. Thus the simple assumption as a ramp signal results in significant influence on the delay calculation. In this paper, an advanced effective capacitance model is proposed to consider both the input waveform effect and the interconnect loads, where the nonlinear influence of input waveform is modeled as one part of the effective capacitance for calculating the gate delay. Experimental results show a significant improvement in accuracy when the input waveform effect is considered.

In deep submicron designs, predicting gate delay time is a noteworthy work for Static Timing Analysis. The effective capacitance C-eff concept is usually used to calculate the gate delay with interconnect loads. Conventionally, the input-signal to the gate is always assumed as a ramp waveform. However, the input signal is also the output of CMOS gates with interconnect loads and not the ramp waveform. Thus the simple assumption as a ramp signal results in significant influence on the delay calculation. In this paper, an advanced effective capacitance model is proposed to consider both the input waveform effect and the interconnect loads, where the nonlinear influence of input waveform is modeled as one part of the effective capacitance for calculating the gate delay. Experimental results show a significant improvement in accuracy when the input waveform effect is considered.

This paper proposes a 12-bit 3.7-MS/s pipelined A/D Converter based on the novel capacitor mismatch calibration technique. The conventional stage is improved to an algorithmic circuit involving charge summing, capacitors' exchange and charge redistribution, simply through introducing some extra switches into the analog circuit. This proposed ADC obtains the linearity beyond the accuracy of the capacitor match and verifies the validity of reducing the nonlinear error from the capacitor mismatch to the second order without additional power dissipation through the novel capacitor mismatch calibration technique. It is processed in 0.5 mu m CMOS technology. The transistor-level simulation results show that 72.6 dB SNDR, 78.5 dB SFDR are obtained for a 2 V V-pp 159.144 kHz sine input sampled at 3.7 MS/s. The whole power dissipation of this ADC is 33.4 mW at the power supply of 5 V.

This paper proposes a 12-bit 3.7-MS/s pipelined A/D Converter based on the novel capacitor mismatch calibration technique. The conventional stage is improved to an algorithmic circuit involving charge summing, capacitors' exchange and charge redistribution, simply through introducing some extra switches into the analog circuit. This proposed ADC obtains the linearity beyond the accuracy of the capacitor match and verifies the validity of reducing the nonlinear error from the capacitor mismatch to the second order without additional power dissipation through the novel capacitor mismatch calibration technique. It is processed in 0.5 mu m CMOS technology. The transistor-level simulation results show that 72.6 dB SNDR, 78.5 dB SFDR are obtained for a 2 V V-pp 159.144 kHz sine input sampled at 3.7 MS/s. The whole power dissipation of this ADC is 33.4 mW at the power supply of 5 V.

We have proposed a random curved surface model as a new mathematical concept which enables the expression of spatial correlation. The model gives us an appropriate methodology to deal with the systematic components of device variation in an LSI chip. The key idea of the model is the fitting of a polynomial to an array of Gaussian random numbers. The curved surface is expressed by a new extension from the Legendre polynomials to form two-dimensional formulas. The formulas were proven to be suitable to express the spatial correlation with reasonable computational complexity. In this paper, we show that this approach is useful in analyzing characteristics of device variation of actual chips by using experimental data.

We have proposed a random curved surface model as a new mathematical concept which enables the expression of spatial correlation. The model gives us an appropriate methodology to deal with the systematic components of device variation in an LSI chip. The key idea of the model is the fitting of a polynomial to an array of Gaussian random numbers. The curved surface is expressed by a new extension from the Legendre polynomials to form two-dimensional formulas. The formulas were proven to be suitable to express the spatial correlation with reasonable computational complexity. In this paper, we show that this approach is useful in analyzing characteristics of device variation of actual chips by using experimental data.

A gate leakage current model for advanced MOSFETs; has been developed and implemented into the Hiroshima-university STARC IGFET Model (HiSIM), the first complete surface-potential-based model. The model consists of four tunneling mechanisms, the gate to channel/bulk/source/drain, and requires totally 15 model parameters covering all bias conditions. Simulation results reproduce measurement for any device size and temperature without binning. Validity of the model has been tested with circuits that are sensitive to the change of stored charge due to tunneling current. (C) 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

In this paper the stability analysis and design are presented for amplifier-based CMOS analog signal and information prooessing cells. By analyzing the influence of dominant pole of feedback path on the frequency response of feedback circuits, several design criteria are proposed to keep amplifier-based CMOS analog processing cells stable such as divider and square root. Moreover, several methods to avoid oscillation are discussed for amplifier-based CMOS analog signal and information processing cells. To verify the proposed design, test circuits are fabricated using CMOS 0.6 um process and experimental results show that the proposed analysis and design can be used to improve the stability of amplifier-based CMOS analog and information processing cells significantly.

In deep submicron designs, predicting gate delays is a noteworthy work for Static Timing Analysis (STA). The effective capacitance C-eff concept is usually used to calculate the gate delay of interconnect load. Conventionally, the input-signal is assumed as ramp waveform. However, the input waveform is also the output of CMOS gates with interconnect wires. Thus the simple assumption as a ramp signal results in significant influence on the delay calculating. In this paper, an advanced effective capacitance model is proposed to consider both the input waveform effect and interconnect wire load, where the nonlinear influence of input waveform is modeled as one part of effective capacitance of capacitive load to compute the gate delay. Experimental results show a significant improvement in accuracy when the input waveform effect is considered.

In this paper, a four-phase all PMOS charge pump based on the voltage doubler structure is proposed. The proposed charge pump is designed in 1.8V 0.18 mu m standard CMOS process with high voltage boosting efficiency and little output tipple. Moreover, it solves the voltage overstress problem which exists in the conventional charge pump and eliminates the body effect as well by means of adding two auxiliary substrate switching PMOS transistors. The simulation results show that the proposed charge pump circuits have an improvement about 93.2% compared with the original two-phase Dickson charge pump and an improvement about 28.2% compared with the negative four-phase Dickson charge pump when the supply voltage is 1.8V. Moreover it can even work as long as the supply power voltage is larger than the threshold voltage, which makes it quite suitable to be utilized in low supply voltage applications.

Due to aggressively scaling down the size of MOS transistor, leakage power dissipation becomes the key issue that is always concerned in SRAM design. In this paper, a novel structure named Dynamic Standby Mode SRAM is proposed, which is based on the theory that both raising negative supply voltage, Vss, and reducing the difference between Vdd and Vss to its limit could cut down leakage current substantially. Furthermore, the impact of performance and the cost of additional area are also carefully considered. The simulation results based on a 45nm technology model of BPTM (Berkeley Predictive Technology Method) show that 55.8% and 80.2% leakage power is saved compared to DRV method and Gated-Vdd SRAM, respectively [1] [2]. Meanwhile, the stability of SRAM is guaranteed by choosing an appropriate value of Vss.

A gate leakage current model for advanced MOSFETs; has been developed and implemented into the Hiroshima-university STARC IGFET Model (HiSIM), the first complete surface-potential-based model. The model consists of four tunneling mechanisms, the gate to channel/bulk/source/drain, and requires totally 15 model parameters covering all bias conditions. Simulation results reproduce measurement for any device size and temperature without binning. Validity of the model has been tested with circuits that are sensitive to the change of stored charge due to tunneling current. (C) 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

In this paper the stability analysis and design are presented for amplifier-based CMOS analog signal and information prooessing cells. By analyzing the influence of dominant pole of feedback path on the frequency response of feedback circuits, several design criteria are proposed to keep amplifier-based CMOS analog processing cells stable such as divider and square root. Moreover, several methods to avoid oscillation are discussed for amplifier-based CMOS analog signal and information processing cells. To verify the proposed design, test circuits are fabricated using CMOS 0.6 um process and experimental results show that the proposed analysis and design can be used to improve the stability of amplifier-based CMOS analog and information processing cells significantly.

In this paper, a four-phase all PMOS charge pump based on the voltage doubler structure is proposed. The proposed charge pump is designed in 1.8V 0.18 mu m standard CMOS process with high voltage boosting efficiency and little output tipple. Moreover, it solves the voltage overstress problem which exists in the conventional charge pump and eliminates the body effect as well by means of adding two auxiliary substrate switching PMOS transistors. The simulation results show that the proposed charge pump circuits have an improvement about 93.2% compared with the original two-phase Dickson charge pump and an improvement about 28.2% compared with the negative four-phase Dickson charge pump when the supply voltage is 1.8V. Moreover it can even work as long as the supply power voltage is larger than the threshold voltage, which makes it quite suitable to be utilized in low supply voltage applications.

Due to aggressively scaling down the size of MOS transistor, leakage power dissipation becomes the key issue that is always concerned in SRAM design. In this paper, a novel structure named Dynamic Standby Mode SRAM is proposed, which is based on the theory that both raising negative supply voltage, Vss, and reducing the difference between Vdd and Vss to its limit could cut down leakage current substantially. Furthermore, the impact of performance and the cost of additional area are also carefully considered. The simulation results based on a 45nm technology model of BPTM (Berkeley Predictive Technology Method) show that 55.8% and 80.2% leakage power is saved compared to DRV method and Gated-Vdd SRAM, respectively [1] [2]. Meanwhile, the stability of SRAM is guaranteed by choosing an appropriate value of Vss.

An energy management circuit is proposed for self-powered ubiquitous sensor modules using vibration-based energy. With the proposed circuit, the sensor modules work with low duty cycle operation. Moreover, a two-tank circuit as a part of the energy management circuit is utilized to solve the problem that the average power density of ambient energy always varies with time while the power consumption of the sensor modules is constant and larger than it. In addition, the long start-up time problem is also avoided with the timing control of the proposed energy management circuit. The CMOS implementation and silicon verification results of the proposed circuit are also presented. Its validity is further confirmed with a vibration-based energy generation. The sensor module is used to supervise the vibration of machines and transfer the vibration signal discontinuously. A piezoelectric element acts as the vibration-to-electricity converter to realize battery-free operation.

The compound element pseudo-transient analysis (PTA) algorithm is an effective practical method for finding the DC operating point when the Newton-Raphson method fails. It is able to effectively prevent from the oscillation problems compared with conventional PTA algorithms. In this paper, an effective SPICE3 implementation method for the compound element PTA algorithm is proposed. It has the characteristic of not expanding the Jacobian matrix and not changing the Jacobian matrix structure when the pseudo-transient numerical simulation is being done. Thus a high simulation efficiency is guaranteed. The ability of the proposed SPICE3 implementation to avoid the oscillation problems and the simulation efficiency are demonstrated by examples.

An energy management circuit is proposed for self-powered ubiquitous sensor modules using vibration-based energy. With the proposed circuit, the sensor modules work with low duty cycle operation. Moreover, a two-tank circuit as a part of the energy management circuit is utilized to solve the problem that the average power density of ambient energy always varies with time while the power consumption of the sensor modules is constant and larger than it. In addition, the long start-up time problem is also avoided with the timing control of the proposed energy management circuit. The CMOS implementation and silicon verification results of the proposed circuit are also presented. Its validity is further confirmed with a vibration-based energy generation. The sensor module is used to supervise the vibration of machines and transfer the vibration signal discontinuously. A piezoelectric element acts as the vibration-to-electricity converter to realize battery-free operation.

The compound element pseudo-transient analysis (PTA) algorithm is an effective practical method for finding the DC operating point when the Newton-Raphson method fails. It is able to effectively prevent from the oscillation problems compared with conventional PTA algorithms. In this paper, an effective SPICE3 implementation method for the compound element PTA algorithm is proposed. It has the characteristic of not expanding the Jacobian matrix and not changing the Jacobian matrix structure when the pseudo-transient numerical simulation is being done. Thus a high simulation efficiency is guaranteed. The ability of the proposed SPICE3 implementation to avoid the oscillation problems and the simulation efficiency are demonstrated by examples.

A low-power sub-1-V self-biased low-voltage reference is proposed for micropower electronic applications based on body effect. The proposed reference has a very low temperature dependence by using a MOSFET with body effect compared with other reported low-power references. An HSPICE simulation shows that the reference voltage and the total power dissipation are 181 mV and 1.1 mu W, respectively. The temperature coefficient of the reference voltage is 33 ppm/degrees C at temperatures from -40 to 100 degrees C. The supply voltage can be as low as 0.95 V in a standard CMOS 0.35 mu m technology with threshold voltages of about 0.5 V and -0.65 V for n-channel and p-channel MOSFETs, respectively. Furthermore, the supply voltage dependence is -0.36 mV/V (Vdd = 0.95-3.3 V).

Accurate estimating or measuring the intake manifold absolute pressure plays an important role in automobile engine control. In order to achieve the real-time estimation of the absolute pressure, the high accuracy and high speed processing ability are required for automobile engine control systems. Therefore, in this paper, an analog method is discussed and a fully integrated analog circuit is proposed to simulate automobile intake systems. Furthermore, a novel behavioral macromodeling is proposed for the analog circuit design. With the analog circuit, the intake manifold absolute pressure, which plays an important role for the effective automobile engine control, can be accurately estimated or measured in real time.

A low-power sub-1-V self-biased low-voltage reference is proposed for micropower electronic applications based on body effect. The proposed reference has a very low temperature dependence by using a MOSFET with body effect compared with other reported low-power references. An HSPICE simulation shows that the reference voltage and the total power dissipation are 181 mV and 1.1 mu W, respectively. The temperature coefficient of the reference voltage is 33 ppm/degrees C at temperatures from -40 to 100 degrees C. The supply voltage can be as low as 0.95 V in a standard CMOS 0.35 mu m technology with threshold voltages of about 0.5 V and -0.65 V for n-channel and p-channel MOSFETs, respectively. Furthermore, the supply voltage dependence is -0.36 mV/V (Vdd = 0.95-3.3 V).

Accurate estimating or measuring the intake manifold absolute pressure plays an important role in automobile engine control. In order to achieve the real-time estimation of the absolute pressure, the high accuracy and high speed processing ability are required for automobile engine control systems. Therefore, in this paper, an analog method is discussed and a fully integrated analog circuit is proposed to simulate automobile intake systems. Furthermore, a novel behavioral macromodeling is proposed for the analog circuit design. With the analog circuit, the intake manifold absolute pressure, which plays an important role for the effective automobile engine control, can be accurately estimated or measured in real time.

In general, a corner model with best- and worst-case delay conditions is used in static timing analysis (STA). The best- and worst-case delays of a stage are defined as the fastest and slowest delays from a cell input to the next cell input. In this paper, we present a methodology for determining the parameters that yield the best- and worst-case delays when interconnect structural parameters have the minimum and maximum values with process variations. We also present analysis results of our circuit model using the methodology. The min and max conditions for the time constant are found to be (+Delta w, +Delta t, +Delta h) & (-Delta w, -Delta t, -Delta h), respectively. Here, +Delta or -Delta means the max or min corner value of each parameter variation, where w is the width, t is the interconnect thickness, and h is the height. Best and worst conditions for delay time are as follows: 1) given a circuit with an optimum driver, dense interconnects, and small branch capacitance, the best and worst conditions are respectively (-Delta w. +Delta t, +Delta h) & (+Delta w, +Delta t, -Delta h), 2) given driver and/or via resistances that are higher than the interconnect resistance, dense interconnects, and small branch capacitance, they are (-Delta w, -Delta t, +Delta h) & (+Delta w, +Delta t, -Delta h), and 3) for other conditions, they are (+Delta w, +Delta t. +Delta h) & (-Delta w, -Delta t, -Delta h). Moreover, if there must be only one condition each for the best- and worst-case delays, they are (+Delta w, +Delta t, +Delta h) & (-Delta w, -Delta t, -Delta h).

In advanced ASIC/SoC physical designs, interconnect parasitic extraction is one of the important factors to determine the accuracy of timing analysis. We present a formula-based method to efficiently extract interconnect capacitances of interconnects with dummy fills for VLSI designs. The whole flow is as follows: 1) in each process, obtain capacitances per unit length using a 3-D field solver and then create formulas, and 2) in the actual design phase, execute a well-known 2.5-D capacitance extraction. Our results indicated that accuracies of the proposed formulas were almost within 3% error. The proposed formula-based method can extract interconnect capacitances with high accuracy for VLSI circuits. Moreover, we present formulas to evaluate the effect of dummy fills on interconnect capacitances. These can be useful for determining design guidelines, such as metal density before the actual design, and for analyzing the effect of each structural parameter during the design phase.

The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of the input-to-output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.

In general, a corner model with best- and worst-case delay conditions is used in static timing analysis (STA). The best- and worst-case delays of a stage are defined as the fastest and slowest delays from a cell input to the next cell input. In this paper, we present a methodology for determining the parameters that yield the best- and worst-case delays when interconnect structural parameters have the minimum and maximum values with process variations. We also present analysis results of our circuit model using the methodology. The min and max conditions for the time constant are found to be (+Delta w, +Delta t, +Delta h) & (-Delta w, -Delta t, -Delta h), respectively. Here, +Delta or -Delta means the max or min corner value of each parameter variation, where w is the width, t is the interconnect thickness, and h is the height. Best and worst conditions for delay time are as follows: 1) given a circuit with an optimum driver, dense interconnects, and small branch capacitance, the best and worst conditions are respectively (-Delta w. +Delta t, +Delta h) & (+Delta w, +Delta t, -Delta h), 2) given driver and/or via resistances that are higher than the interconnect resistance, dense interconnects, and small branch capacitance, they are (-Delta w, -Delta t, +Delta h) & (+Delta w, +Delta t, -Delta h), and 3) for other conditions, they are (+Delta w, +Delta t. +Delta h) & (-Delta w, -Delta t, -Delta h). Moreover, if there must be only one condition each for the best- and worst-case delays, they are (+Delta w, +Delta t, +Delta h) & (-Delta w, -Delta t, -Delta h).

In advanced ASIC/SoC physical designs, interconnect parasitic extraction is one of the important factors to determine the accuracy of timing analysis. We present a formula-based method to efficiently extract interconnect capacitances of interconnects with dummy fills for VLSI designs. The whole flow is as follows: 1) in each process, obtain capacitances per unit length using a 3-D field solver and then create formulas, and 2) in the actual design phase, execute a well-known 2.5-D capacitance extraction. Our results indicated that accuracies of the proposed formulas were almost within 3% error. The proposed formula-based method can extract interconnect capacitances with high accuracy for VLSI circuits. Moreover, we present formulas to evaluate the effect of dummy fills on interconnect capacitances. These can be useful for determining design guidelines, such as metal density before the actual design, and for analyzing the effect of each structural parameter during the design phase.

The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of the input-to-output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.

Interconnect wires give large influences on circuit delay in very deep submicron designs. The venin model and effective capacitance C-eff concept are usually used to calculate the delay of gate with interconnect loads. In the researches before, the condition that the charges transferred to C-eff and RC - pi are not equal was not considered. With the progress of IC process technology, its influence on Static Timing Analysis becomes larger. In this paper, we consider this condition, and propose an new algorithm for calculating the effective capacitance based on The venin model. Experimental results show that it is in agreement with the Spice simulation.

This paper describes how to realize the high speed laser diode driver (LDD) circuit with high performance signal and large output current to drive the laser diode device. Based on the introduced idea of "Switch Position Modification (SPM)", two types of LDD circuit architectures, including "Combination Switch Mode (CSM)" and "Source Follower Mode (SFM)", have been proposed to satisfy the output signal requirements. Under the corresponding design specification, the CSM architecture was selected to realize the effective LDD circuit design. Moreover, the signal integrity problems, such as overshoot, undershoot and slew-rate, have also been improved in the new CSM architecture. In addition, appropriate transistor size selection and circuit combination can further amend the signal waveform. The LDD circuit was realized in a 0.6-mu m CMOS technology. And the output current can reach several hundred milliampere with good signal integrity in the experimental simulation results. Thus the introduced "Switch Position Modification" idea and the proposed "Combination Switch Mode" architecture assure the high performance LDD circuit realization and signal output.

A sub-1-V self-biased low-voltage low-power voltage reference is presented for micropower electronic applications. And the proposed circuit has very low temperature dependence by using a back-gate connection MOSFET. An Hspice simulation shows that the reference voltage and total power dissipation are 181 mV and 1.1 mu W, respectively. The temperature coefficient of the reference voltage is 33 ppm/degrees C within a temperature range from -40 to 100 degrees C. The supply voltage dependence is -0.36 mV/V (Vdd=0.95 similar to 3.3 V). Supply voltage can be as low as 0.95 V in a standard CMOS 0.35 mu m technology with threshold voltages of about 0.5 V and -0.65 V for n-channel and p-channel MOSFETs, respectively.

This paper proposes a 15-bit 10-MS/s pipelined ADC. To implement the incomplete settling principle, the traditional complete settling stage is improved to the incomplete settling structure through dividing the sampling clock of the traditional stage into two parts for discharging the sampling and feedback capacitors and completing the sampling, respectively. It verifies the correction and validity of optimizing ADCs' conversion speed without increasing power consumption through the incomplete settling. It is processed in 0.18 mu m 1P6M CMOS mixed-mode technology. Simulation results show that 82dB SNDR and 87dB SFDR are obtained at the sampling rate of 10MHz with the input sine frequency of 100KHz and the whole static power dissipation is 21.94mW.

Interconnect wires give large influences on circuit delay in very deep submicron designs. Thevenin model and effective capacitance Ceff concept are usually used to calculate the delay of gate with interconnect loads. In the researches before, the condition that the charges transferred to C eff and RC -π are not equal was not considered. With the progress of IC process technology, its influence on Static Timing Analysis becomes larger. In this paper, we consider this condition, and propose an new algorithm for calculating the effective capacitance based on Thevenin model. Experimental results show that it is in agreement with the Spice simulation. © 2006 IEEE.

This paper describes how to realize the high speed laser diode driver (LDD) circuit with high performance signal and large output current to drive the laser diode device. Based on the introduced idea of "Switch Position Modification (SPM)", two types of LDD circuit architectures, including "Combination Switch Mode (CSM)" and "Source Follower Mode (SFM)", have been proposed to satisfy the output signal requirements. Under the corresponding design specification, the CSM architecture was selected to realize the effective LDD circuit design. Moreover, the signal integrity problems, such as overshoot, undershoot and slew-rate, have also been improved in the new CSM architecture. In addition, appropriate transistor size selection and circuit combination can further amend the signal waveform. The LDD circuit was realized in a 0.6-mu m CMOS technology. And the output current can reach several hundred milliampere with good signal integrity in the experimental simulation results. Thus the introduced "Switch Position Modification" idea and the proposed "Combination Switch Mode" architecture assure the high performance LDD circuit realization and signal output.

A sub-1-V self-biased low-voltage low-power voltage reference is presented for micropower electronic applications. And the proposed circuit has very low temperature dependence by using a back-gate connection MOSFET. An Hspice simulation shows that the reference voltage and total power dissipation are 181 mV and 1.1 μW, respectively. The temperature coefficient of the reference voltage is 33 ppm/°C within a temperature range from -40 to 100°C. The supply voltage dependence is -0.36 m V/V (Vdd=0.95-3.3 V). Supply voltage can be as low as 0.95 V in a standard CMOS 0.35 °m technology with threshold voltages of about 0.5 V and -0.65 V for n-channel and p-channel MOSFETs, respectively. © 2006 IEEE.

This paper proposes a 15-bit 10-MS/s pipelined ADC. To implement the incomplete settling principle, the traditional complete settling stage is improved to the incomplete settling structure through dividing the sampling clock of the traditional stage into two parts for discharging the sampling and feedback capacitors and completing the sampling, respectively. It verifies the correction and validity of optimizing ADCs' conversion speed without increasing power consumption through the incomplete settling. It is processed in 0.18μm 1P6M CMOS mixed-mode technology. Simulation results show that 82dB SNDR and 87dB SFDR are obtained at the sampling rate of 10MHz with the input sine frequency of 100KHz and the whole static power dissipation is 21.94mW. © 2006 IEEE.

Floating dummy metal fills inserted for planarization of multi-dielectric layers have created serious problems because of increased interconnect capacitance and the enormous number of fills. We present new dummy filling methods to reduce the interconnect capacitance and the number of dummy metal fills needed. These techniques include three ways of filling: 1) improved floating square fills, 2) floating parallel lines, and 3) floating perpendicular lines (with spacing between dummy metal fills above and below signal lines). We also present efficient formulas for estimating the appropriate spacing and number of fills. In our experiments, the capacitance increase using the conventional regular square method was 13.1%. while that using the methods of improved square fills, extended parallel lines, and perpendicular lines were 2.7%, 2.4%, and 1.0%, respectively. Moreover, the number of necessary dummy metal fills can be reduced by two orders of magnitude through use of the parallel line method.

Simple closed-form expressions for efficiently calculating on-chip interconnect capacitances are presented. The formulas are expressed with second-order polynomial functions which do not include exponential functions. The runtime of the proposed formulas is about 2-10 times faster than those of existing formulas. The root mean square (RMS) errors of the proposed formulas are within 1.5%, 1.3%, 3.1%, and 4.6% of the results obtained by a field solver for structures with one line above a ground plane, one line between ground planes, three lines above a ground plane, and three lines between ground planes, respectively. The proposed formulas are also superior in accuracy to existing formulas.

In deep submicron designs, predicting gate stews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance C-eff concept is usually used to calculate the gate delay of interconnect loads. Many C-eff algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a C-eff algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating the C-eff of interconnect load for gate slew. We firstly establish a new expression for C-eff in 0.8Vdd point. Then the Integration Approximation method is used to calculate the value of C-eff in 0.8Vdd point. In this method, the integration of a complicated nonlinear gate output is approximated with that of a piecewise linear waveform. Based on the value of C-eff in 0.8Vdd point, C-eff of interconnect load for gate slew is obtained. The simulation results demonstrate a significant improvement in accuracy.

In this paper we propose a novel and efficient method for the optimization of the power/ground (P/G) network in VLSI circuit layouts with reliability constraints. Previous algorithms in the P/G network sizing used the sequence-of-linear-programming (SLP) algorithm to solve the nonlinear optimization problems. However the transformation from nonlinear network to linear subnetwork is not optimal enough. Our new method is inspired by the biological evolution and use the grid-genetic-algorithm (GGA) to solve the optimization problem. Experimental results show that new P/G network sizes are smaller than previous algorithms, as the fittest survival in the nature. Another significant advance is that GGA method can be applied for all P/G network problems because it can get the results directly no matter whether these problems are linear or not. Thus GGA can be adopted in the transient behavior of the P/G network sizing in the future, which recently faces on the obstacles in the solution of the complex nonlinear problems.

Floating dummy metal fills inserted for planarization of multi-dielectric layers have created serious problems because of increased interconnect capacitance and the enormous number of fills. We present new dummy filling methods to reduce the interconnect capacitance and the number of dummy metal fills needed. These techniques include three ways of filling: 1) improved floating square fills, 2) floating parallel lines, and 3) floating perpendicular lines (with spacing between dummy metal fills above and below signal lines). We also present efficient formulas for estimating the appropriate spacing and number of fills. In our experiments, the capacitance increase using the conventional regular square method was 13.1%. while that using the methods of improved square fills, extended parallel lines, and perpendicular lines were 2.7%, 2.4%, and 1.0%, respectively. Moreover, the number of necessary dummy metal fills can be reduced by two orders of magnitude through use of the parallel line method.

Simple closed-form expressions for efficiently calculating on-chip interconnect capacitances are presented. The formulas are expressed with second-order polynomial functions which do not include exponential functions. The runtime of the proposed formulas is about 2-10 times faster than those of existing formulas. The root mean square (RMS) errors of the proposed formulas are within 1.5%, 1.3%, 3.1%, and 4.6% of the results obtained by a field solver for structures with one line above a ground plane, one line between ground planes, three lines above a ground plane, and three lines between ground planes, respectively. The proposed formulas are also superior in accuracy to existing formulas.

In deep submicron designs, predicting gate stews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance C-eff concept is usually used to calculate the gate delay of interconnect loads. Many C-eff algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a C-eff algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating the C-eff of interconnect load for gate slew. We firstly establish a new expression for C-eff in 0.8Vdd point. Then the Integration Approximation method is used to calculate the value of C-eff in 0.8Vdd point. In this method, the integration of a complicated nonlinear gate output is approximated with that of a piecewise linear waveform. Based on the value of C-eff in 0.8Vdd point, C-eff of interconnect load for gate slew is obtained. The simulation results demonstrate a significant improvement in accuracy.

In this paper we propose a novel and efficient method for the optimization of the power/ground (P/G) network in VLSI circuit layouts with reliability constraints. Previous algorithms in the P/G network sizing used the sequence-of-linear-programming (SLP) algorithm to solve the nonlinear optimization problems. However the transformation from nonlinear network to linear subnetwork is not optimal enough. Our new method is inspired by the biological evolution and use the grid-genetic-algorithm (GGA) to solve the optimization problem. Experimental results show that new P/G network sizes are smaller than previous algorithms, as the fittest survival in the nature. Another significant advance is that GGA method can be applied for all P/G network problems because it can get the results directly no matter whether these problems are linear or not. Thus GGA can be adopted in the transient behavior of the P/G network sizing in the future, which recently faces on the obstacles in the solution of the complex nonlinear problems.

We present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances for system-on-chip (SoC) designs. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy metal fills on the parasitic capacitance, signal delay, and crosstalk noise. Moreover, we address that interlayer dummy metal fills have more significant influences than intralayer ones in terms of the impact on coupling capacitances. When dummy metal fills are ignored, the error of capacitance extraction can be more than 30%, whereas the error of the proposed method is less than about 10% for many practical geometries. We also demonstrate, by comparison with capacitance results measured for a 90-nm test chip, that the error of the proposed method is less than 8%.

We present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances for system-on-chip (SoC) designs. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy metal fills on the parasitic capacitance, signal delay, and crosstalk noise. Moreover, we address that interlayer dummy metal fills have more significant influences than intralayer ones in terms of the impact on coupling capacitances. When dummy metal fills are ignored, the error of capacitance extraction can be more than 30%, whereas the error of the proposed method is less than about 10% for many practical geometries. We also demonstrate, by comparison with capacitance results measured for a 90-nm test chip, that the error of the proposed method is less than 8%.

In deep submicron designs, the interconnect wires play a major role in the timing behavior of logic gates. The effective capacitance C-eff concept is usually used to calculate the delay of gate with interconnect loads. In this paper, we present a new method of Integration Approximation to calculate C-eff. In this new method, the complicated nonlinear gate output is assumed as a piecewise linear (PWL) waveform. A new model is then derived to compute the value of C-eff. The introduction of Integration Approximation results in C-eff being insensitive to output waveform shape. Therefore, the new method can be applied to various output waveforms of CMOS gates with RC-pi loads. Experimental results show a significant improvement in accuracy.

Finding DC operating points of nonlinear circuits is an important problem in circuit simulation. The Newton-Raphson method employed in SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. There are several types of homotopy methods, one of which succeeded in solving bipolar analog circuits with more than 20000 elements with the theoretical guarantee of global convergence. In this paper, we propose an improved version of the homotopy method that can find DC operating points of practical nonlinear circuits smoothly and efficiently. Numerical examples show the effectiveness of the proposed method.

In deep submicron designs, the interconnect wires play a major role in the timing behavior of logic gates. The effective capacitance C-eff concept is usually used to calculate the delay of gate with interconnect loads. In this paper, we present a new method of Integration Approximation to calculate C-eff. In this new method, the complicated nonlinear gate output is assumed as a piecewise linear (PWL) waveform. A new model is then derived to compute the value of C-eff. The introduction of Integration Approximation results in C-eff being insensitive to output waveform shape. Therefore, the new method can be applied to various output waveforms of CMOS gates with RC-pi loads. Experimental results show a significant improvement in accuracy.

Finding DC operating points of nonlinear circuits is an important problem in circuit simulation. The Newton-Raphson method employed in SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. There are several types of homotopy methods, one of which succeeded in solving bipolar analog circuits with more than 20000 elements with the theoretical guarantee of global convergence. In this paper, we propose an improved version of the homotopy method that can find DC operating points of practical nonlinear circuits smoothly and efficiently. Numerical examples show the effectiveness of the proposed method.

Finding DC operating points of transistor circuits is a very important and difficult task. The Newton-Raphson method employed in SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. For efficiency of homotopy methods, it is important to construct an appropriate homotopy function. In conventional homotopy methods, linear auxiliary functions have been commonly used. In this paper, a homotopy method for solving transistor circuits using a nonlinear auxiliary function is proposed. The proposed method utilizes the nonlinear function closely related to circuit equations to be solved, so that it efficiently finds DC operating points of practical transistor circuits. Numerical examples show that the proposed method is several times more efficient than conventional three homotopy methods.

Finding DC operating points of transistor circuits is a very important and difficult task. The Newton-Raphson method employed in SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. For efficiency of homotopy methods, it is important to construct an appropriate homotopy function. In conventional homotopy methods, linear auxiliary functions have been commonly used. In this paper, a homotopy method for solving transistor circuits using a nonlinear auxiliary function is proposed. The proposed method utilizes the nonlinear function closely related to circuit equations to be solved, so that it efficiently finds DC operating points of practical transistor circuits. Numerical examples show that the proposed method is several times more efficient than conventional three homotopy methods.

Path following circuits (PFC's) are circuits for solving nonlinear problems on the circuit simulator SPICE. In the method of PFC's, formulas of numerical methods are described by circuits, which are solved by SPICE. Using PFC's, numerical analysis without programming is possible, and various techniques implemented in SPICE will make the numerical analysis very efficient. In this paper, we apply the PFC's of the homotopy method to various nonlinear problems (excluding circuit analysis) where the homotopy method is proven to be globally convergent; namely, we apply the method to fixed-point problems, linear programming problems, and nonlinear programming problems. This approach may give a new possibility to the fields of applied mathematics and operations research. Moreover, this approach makes SPICE applicable to a broader class of scientific problems.

Path following circuits (PFC's) are circuits for solving nonlinear problems on the circuit simulator SPICE. In the method of PFC's, formulas of numerical methods are described by circuits, which are solved by SPICE. Using PFC's, numerical analysis without programming is possible, and various techniques implemented in SPICE will make the numerical analysis very efficient. In this paper, we apply the PFC's of the homotopy method to various nonlinear problems (excluding circuit analysis) where the homotopy method is proven to be globally convergent; namely, we apply the method to fixed-point problems, linear programming problems, and nonlinear programming problems. This approach may give a new possibility to the fields of applied mathematics and operations research. Moreover, this approach makes SPICE applicable to a broader class of scientific problems.

In recent system-on-chip (SoC) designs, floating dummy metals inserted for planarization have created serious problems because of increased interconnect capacitance and the enormous amount of fill required. We present new methods to reduce the interconnect capacitance and the amount of dummy metals needed. These techniques include three ways of filling: 1) improved floating square fills, 2) floating parallel lines, and 3) floating perpendicular lines (with spacing between dummy metals above and below signal lines). We also present efficient simple formulas for estimating the appropriate spacing and number of fills. In our experiments, the capacitance increase using the traditional regular square method was 13.1%, while that using the methods of improved square fills, extended parallel lines, and perpendicular lines was 2.5%, 2.4%, and 1.1%, respectively. Moreover, the number of necessary dummy metals can be reduced by two orders of magnitude through use of the parallel line method.

In the VLSI design of sub-100-nm technologies, most engineers in the process, chip-design, and EDA areas are acutely aware of a tough "Red Brick Wall" emerging because of process variability and physical integrity issues. Process variability is not only a fabrication problem, but also a serious design issue. Similarly, physical integrity problems are not only design and EDA issues, but also process-related architecture problems.
In this paper, we investigate the practicality of a dense power-ground interconnect architecture [1,2] developed to ensure physical design integrity. The interconnect architecture basically consists of adjoining power and ground lines. We describe the design methodologies and a simple method for calculating the decoupling capacitance (decap) values, and report both calculated and measured decap values for the architecture. We also report measurement results regarding the signal line capacitance and the interconnect defect-type yield of a 90-nm process technology.

In this paper, it is shown that various scientific problems such as fixed-point problems, linear programming problems, and nonlinear programming problems can be solved by using the circuit simulator SPICE. The basic idea of the proposed method is that formulas of the homotopy method are described by circuits, and then they are solved by SPICE. Since SPICE is an excellent software that includes various excellent techniques, this approach will make the numerical analysis very efficient, especially for stiff problems. Moreover, for SPICE users, the proposed method will be useful because they can easily solve a broad class of problems by the homotopy method realized on SPICE without programming, although they do not know the homotopy method well. © 2005 IEEE.

In deep submicron designs, the resistance of interconnect is playing dominant role on the timing behavior of logic gates. The concept of effective capacitance Ceff is usually used to calculate the gate delay for interconnect loads. In this paper, a new method to derive the expression C eff is presented, and the accuracy of the expression is discussed. In our approach, the output waveform is assumed as linear. Thus, the expression of effective capacitance is simple and efficient. Moreover, the result of effective capacitance is insensitive to output wave shape because C eff is determined by the curve area. Therefore, it is appropriate for various output waveform of CMOS gate with RC loads. Experimental results show it is in agreement with the Spice simulation. © 2005 IEEE.

Band matrix multiplication is widely used in DSP systems. However traditional Kung-Leiserson systolic array for band matrix multiplication cannot be realized with high cell-efficiency. In this paper, three high-performance band matrix multiplication systolic arrays (BMMSA) are presented based on the ideas of "Matrix Compression" and "Super Pipelined". These new systolic arrays are realized by compressing the data matrix skillfully and adjusting the operation sequence carefully. The results show that the best systolic array for band matrix multiplication uses almost 100% processing elements(PE) in each step. Also, these modifications increase the operation speed and at best spend only 1/3 processing time to complete the multiplication operation.

The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of input-to output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.

A new architecture for ubiquitous sensor modules using vibration-based energy generation is proposed and the CMOS implementation of the proposed architecture is presented. The sensor module only scavenges vibration-based energy as energy source by using piezoelectric element to realize no batteries operation. The sensor module is used to supervise the vibration of machines and transfer the vibration signal discontinuously. Based on the proposed new architecture, the sensor module can sense signal and scavenge energy from the same piece of piezoelectric element and can avoid the long time start-up time. The sensor module also realizes short range (about ten meters) wireless transmission.

In recent system-on-chip (SoC) designs, floating dummy metals inserted for planarization have created serious problems because of increased interconnect capacitance and the enormous amount of fill required. We present new methods to reduce the interconnect capacitance and the amount of dummy metals needed. These techniques include three ways of filling: 1) improved floating square fills, 2) floating parallel lines, and 3) floating perpendicular lines (with spacing between dummy metals above and below signal lines). We also present efficient simple formulas for estimating the appropriate spacing and number of fills. In our experiments, the capacitance increase using the traditional regular square method was 13.1%, while that using the methods of improved square fills, extended parallel lines, and perpendicular lines was 2.5%, 2.4%, and 1.1%, respectively. Moreover, the number of necessary dummy metals can be reduced by two orders of magnitude through use of the parallel line method.

In the VLSI design of sub-100-nm technologies, most engineers in the process, chip-design, and EDA areas are acutely aware of a tough "Red Brick Wall" emerging because of process variability and physical integrity issues. Process variability is not only a fabrication problem, but also a serious design issue. Similarly, physical integrity problems are not only design and EDA issues, but also process-related architecture problems.
In this paper, we investigate the practicality of a dense power-ground interconnect architecture [1,2] developed to ensure physical design integrity. The interconnect architecture basically consists of adjoining power and ground lines. We describe the design methodologies and a simple method for calculating the decoupling capacitance (decap) values, and report both calculated and measured decap values for the architecture. We also report measurement results regarding the signal line capacitance and the interconnect defect-type yield of a 90-nm process technology.

In this paper, it is shown that various scientific problems such as fixed-point problems, linear programming problems, and nonlinear programming problems can be solved by using the circuit simulator SPICE. The basic idea of the proposed method is that formulas of the homotopy method are described by circuits, and then they are solved by SPICE. Since SPICE is an excellent software that includes various excellent techniques, this approach will make the numerical analysis very efficient, especially for stiff problems. Moreover, for SPICE users, the proposed method will be useful because they can easily solve a broad class of problems by the homotopy method realized on SPICE without programming, although they do not know the homotopy method well. © 2005 IEEE.

In deep submicron designs, the resistance of interconnect is playing dominant role on the timing behavior of logic gates. The concept of effective capacitance Ceff is usually used to calculate the gate delay for interconnect loads. In this paper, a new method to derive the expression C eff is presented, and the accuracy of the expression is discussed. In our approach, the output waveform is assumed as linear. Thus, the expression of effective capacitance is simple and efficient. Moreover, the result of effective capacitance is insensitive to output wave shape because C eff is determined by the curve area. Therefore, it is appropriate for various output waveform of CMOS gate with RC loads. Experimental results show it is in agreement with the Spice simulation. © 2005 IEEE.

Band matrix multiplication is widely used in DSP systems. However traditional Kung-Leiserson systolic array for band matrix multiplication cannot be realized with high cell-efficiency. In this paper, three high-performance band matrix multiplication systolic arrays (BMMSA) are presented based on the ideas of "Matrix Compression" and "Super Pipelined". These new systolic arrays are realized by compressing the data matrix skillfully and adjusting the operation sequence carefully. The results show that the best systolic array for band matrix multiplication uses almost 100% processing elements(PE) in each step. Also, these modifications increase the operation speed and at best spend only 1/3 processing time to complete the multiplication operation.

The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of input-to output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.

A new architecture for ubiquitous sensor modules using vibration-based energy generation is proposed and the CMOS implementation of the proposed architecture is presented. The sensor module only scavenges vibration-based energy as energy source by using piezoelectric element to realize no batteries operation. The sensor module is used to supervise the vibration of machines and transfer the vibration signal discontinuously. Based on the proposed new architecture, the sensor module can sense signal and scavenge energy from the same piece of piezoelectric element and can avoid the long time start-up time. The sensor module also realizes short range (about ten meters) wireless transmission.

Finding DC operating points of transistor circuits is an important and difficult task. The Newton-Raphson method adopted in SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. For efficiency of globally convergent homotopy methods, it is important to give an appropriate initial solution as a starting point. However, there are few studies concerning such initial solution algorithms, In this paper, initial solution problems in homotopy methods are discussed, and an effective initial solution algorithm is proposed for globally convergent homotopy methods, which finds DC operating points of transistor circuits efficiently. Numerical examples using practical transistor circuits show the effectiveness of the proposed algorithm.

Finding DC operating points of transistor circuits is an important and difficult task. The Newton-Raphson method adopted in SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. For efficiency of globally convergent homotopy methods, it is important to give an appropriate initial solution as a starting point. However, there are few studies concerning such initial solution algorithms, In this paper, initial solution problems in homotopy methods are discussed, and an effective initial solution algorithm is proposed for globally convergent homotopy methods, which finds DC operating points of transistor circuits efficiently. Numerical examples using practical transistor circuits show the effectiveness of the proposed algorithm.

The accuracy of parasitic extraction has become increasingly important for system-on-chip (SoC) designs. In this paper, we present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by the chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy metal fills on the parasitic capacitance, signal delay, and crosstalk noise. Moreover, we address that the existence of the interlayer dummy metal fills has more significant influences than the intralayer dummies in terms of the impact on coupling capacitances. When dummy metal fills are ignored, the error of capacitance extraction can be more than 30%, whereas the error of the proposed method is less than about 10% for many practical geometries. We also demonstrate, by comparison with capacitance results measured for a 90-nm test chip, that the error of the proposed method is less than 8%.

The accuracy of parasitic extraction has become increasingly important for system-on-chip (SoC) designs. In this paper, we present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by the chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy metal fills on the parasitic capacitance, signal delay, and crosstalk noise. Moreover, we address that the existence of the interlayer dummy metal fills has more significant influences than the intralayer dummies in terms of the impact on coupling capacitances. When dummy metal fills are ignored, the error of capacitance extraction can be more than 30%, whereas the error of the proposed method is less than about 10% for many practical geometries. We also demonstrate, by comparison with capacitance results measured for a 90-nm test chip, that the error of the proposed method is less than 8%.

Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. For the global convergence of homotopy methods, it is a necessary condition that a given initial solution is the unique solution to the homotopy equation. According to the conventional criterion, such an initial solution, however, is restricted in some very narrow region. In this paper, considering the circuit interpretation of homotopy equations, we prove theorems on the uniqueness of an initial solution for globally convergent homotopy methods. These theorems give new criteria extending the region wherein any desired initial solution satisfies the uniqueness condition.

Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. For the global convergence of homotopy methods, it is a necessary condition that a given initial solution is the unique solution to the homotopy equation. According to the conventional criterion, such an initial solution, however, is restricted in some very narrow region. In this paper, considering the circuit interpretation of homotopy equations, we prove theorems on the uniqueness of an initial solution for globally convergent homotopy methods. These theorems give new criteria extending the region wherein any desired initial solution satisfies the uniqueness condition.

In this paper, an effective initial solution algorithm is proposed for globally convergent homotopy methods, which Pnds DC operating points of transistor circuits efPciently. A new criterion on the initial solution necessary for guaranteeing the global convergence is presented for a practical class of transistor circuits. Numerical examples show the effectiveness of the proposed algorithm.

An efficient algorithm is proposed for finding all solutions of nonlinear (not piecewise-linear) resistive circuits with mathematical certainty. This algorithm is based on interval analysis, the dual simplex method, and the contraction method. By numerical examples, it is shown that the proposed algorithm could find all solutions of systems of 500 similar to 700 nonlinear circuit equations in acceptable computation time.

In this paper, an effective initial solution algorithm is proposed for globally convergent homotopy methods, which Pnds DC operating points of transistor circuits efPciently. A new criterion on the initial solution necessary for guaranteeing the global convergence is presented for a practical class of transistor circuits. Numerical examples show the effectiveness of the proposed algorithm.

It is a very important, but difficult, task to calculate the multiple dc solutions in circuit simulations. In this paper, we show a very simple SPICE-oriented Newton homotopy method which can efficiently find out the multiple dc solutions. In the paper, we show our solution curve-tracing algorithm based on the arc-length method and the Newton homotopy method. We will also prove an important theorem about how many variables should be chosen to implement our algorithm. It verifies that our simulator can be efficiently applied even if the circuit scales are relatively large. In Section III, we show that our Newton homotopy method is implemented by the transient analysis of SPICE. Thus, we do not need to formulate a troublesome circuit equation or the Jacobian matrix. Finally, applying our method to solve many important benchmark problems, all the solutions for the transistor circuits could be found on each homotopy path. Thus, our simulator can be efficiently applied to calculate the multiple de solutions and perhaps all the solutions.

Finding DC operating-points of nonlinear circuits is an important and difficult task. The Newton-Raphson method employed in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. The fixed-point homotopy method is one of the excellent methods. However, from the viewpoint of implementation, it is important to study it further so that the method can be easily and widely used by many circuit designers. This paper presents a practical method to implement the fixed-point homotopy method. A special circuit called the solution-tracing circuit for the fixed-point homotopy method is proposed. By using this circuit, the solution curves of homotopy equations can be traced by performing the SPICE transient analysis. Therefore, no modification to the existing programs is necessary. Moreover, it is proved that the proposed method is globally convergent. Numerical examples show that the proposed technique is effective and can be easily implemented. By the proposed technique, many SPICE users can easily implement the fixed-point homotopy method.

Recently, an efficient algorithm has been proposed for finding all solutions of systems of nonlinear equations using inverses of approximate Jacobian matrices. In this letter, an effective technique is proposed for improving the computational efficiency of the algorithm with a little bit of computational effort.

This paper presents a practical implementation approach for the fixed-point homotopy method which determines DC operating-points of nonlinear circuits. We propose a special circuit called the "solution-tracing circuit". By using this circuit, SPICE transient analysis is performed to trace the solution curves of the homotopy equations and to reach the DC operating points of the circuits to be solved. The proposed technique is effective and can be easily implemented. © 2001 IEEE.

Recently, the application of homotopy methods to practical circuit simulation has been remarkably developed, and bipolar analog integrated circuits with more than 10000 elements are now solved efficiently by the homotopy methods, There are several approaches to applying the homotopy methods to large-scale circuit simulation. One of them is combining the publicly available software package of the homotopy methods (such as HOMPACK) with the general-purpose circuit simulators such as SPICE. However, the homotopy method using the fixed-point (FP) homotopy (that is provided as a default in HOMPACK) is not guaranteed to converge for the modified nodal (MN) equations that are used in SPICE. In this paper, we propose a modified algorithm of the homotopy method using the FP homotopy and prove that this algorithm is globally convergent for the MN equations. We also show that the proposed algorithm converges to a stable operating point with high possibility from any initial point.

Recently, the application of homotopy methods to practical circuit simulation has been remarkably developed, and bipolar analog integrated circuits with more than 10000 elements are now solved efficiently by the homotopy methods, There are several approaches to applying the homotopy methods to large-scale circuit simulation. One of them is combining the publicly available software package of the homotopy methods (such as HOMPACK) with the general-purpose circuit simulators such as SPICE. However, the homotopy method using the fixed-point (FP) homotopy (that is provided as a default in HOMPACK) is not guaranteed to converge for the modified nodal (MN) equations that are used in SPICE. In this paper, we propose a modified algorithm of the homotopy method using the FP homotopy and prove that this algorithm is globally convergent for the MN equations. We also show that the proposed algorithm converges to a stable operating point with high possibility from any initial point.

The ability to design analog LSIs largely depends on the experience and knowledge of skilled engineers, and automating the design of such circuits by using the computer poses a difficult challenge. Thus, to develop analog LSIs in a relatively short period it is impotant to provide a system environment where skilled engineers can fully employ their collective creativity and make proper decisions, and where design information is efficiently shared, while promoting the repeated use of design properties. It is for these reasons that the authors have developed and put to practical use an interactive support system with a hierarchical library to support the design and verification of analog LSIs. This paper describes the system configuration of this support system for analog circuit design, outlines the system functions, and proposes a practical approach to building a hierarchical library suitable for the hierarchical design of analog LSIs. Moreover, this paper presents an application example of the hierarchical design of LSIs to illustrate the effectiveness of this system.

The ability to design analog LSIs largely depends on the experience and knowledge of skilled engineers, and automating the design of such circuits by using the computer poses a difficult challenge. Thus, to develop analog LSIs in a relatively short period it is impotant to provide a system environment where skilled engineers can fully employ their collective creativity and make proper decisions, and where design information is efficiently shared, while promoting the repeated use of design properties. It is for these reasons that the authors have developed and put to practical use an interactive support system with a hierarchical library to support the design and verification of analog LSIs. This paper describes the system configuration of this support system for analog circuit design, outlines the system functions, and proposes a practical approach to building a hierarchical library suitable for the hierarchical design of analog LSIs. Moreover, this paper presents an application example of the hierarchical design of LSIs to illustrate the effectiveness of this system.