Data stored in non-volatile memories may be destructed due to crosstalk and radiation but we can restore their data by using error-correcting codes. However, non-volatile memories consume a large amount of energy in writing. How to reduce writing bits even when using error-correcting codes is one of the challenges in non-volatile memory design. We have proposed a Doughnut code, which is a new bit-write-reducing and error-correcting code. In addition, we have proposed a code expansion method. When we apply our code expansion method to Doughnut code, we can obtain expanded Doughnut codes. Expanded Doughnut codes are error-correcting codes which can reduce the number of writing bits. In this paper, we demonstrate experimental evaluations from the viewpoint of energy reduction of our proposed expanded Doughnut codes. Experimental results show that the write-reducing code reduces energy consumption by up to 32% compared to Hamming code.

In lithography, we generate patterns on a wafer through a photomask, where patterns generated have to be close to ideal patterns by optimizing a photomask as well as an exposure source. One of the most important tasks here is to speed-up exposure source optimization to have overall optimized photomask and exposure source. In this paper, we propose a speeding-up method for exposure source optimization by clustering for lithography. In our method, we cluster several source grid-points utilizing the lithography property and reduce the number of parameters to be optimized simultaneously. Experimental results demonstrate that our method achieves 8X speed-up compared with a conventional method.

Non-volatile memory has many advantages over SRAM, such as high density, low leakage power, and non-volatility. However, one of its largest problems is that it consumes a large amount of energy in writing. It is quite necessary to reduce the number of writing bits and thus decrease its writing energy. We have proposed a memory writing reduction method based on error correcting codes. When a data is written into a memory, we do not write it directly but encode it into a codeword. Then the number of writing bits into memory is also limited in data writing. In this paper, we demonstrate several experimental evaluations from the viewpoints of energy reduction and discuss the effectiveness of our proposed writing-reduction codes.

Non-volatile memory has many advantages over SRAM, such as high density, low leakage power, and non-volatility. However, one of its largest problems is that it consumes a large amount of energy in writing. It is quite necessary to reduce the number of writing bits and thus decrease its writing energy. In this paper, we propose a memory writing reduction method based on state encoding limiting maximum Hamming distance. When a data is written into a memory, we do not write it directly but encode it into a codeword. Then we write the codeword into a memory. At this time, we encode a data into a codeword limiting its maximum Hamming distance from another codeword. If the maximum Hamming distance is limited among all the codewords, the number of flipped bits are also limited and then the number of writing bits will be reduced. We show several experimental evaluations and discuss the effectiveness of our proposed algorithm.

A non-volatile memory has advantages such as low leak energy and non-volatility compared with SRAM or DRAM has high leak energy. It is strongly expected to use a non-volatile memory for realizing normally-off systems. A non-volatile memory, however, consumes more energy to write than SRAM or DRAM. In this paper, we evaluate energy consumption of a cache memory in an embedded processor with non-volatile memories. In our evaluation, we assume that their write energy is 1.0x to 10.0x higher than that of SRAM. Experimental evaluations demonstrate that using non-volatile memories in a cache is better choice in some cases, even when write energy of non-volatile memories is 10.0x higher than that of SRAM.

In trace-based cache simulation, we perform cache simulation based on a particular memor/access trace obtained by cycle-accurate memory simulation. While cycle-accurate simulation takes too many time to run, trace-based cache simulation runs very fast and then we can evaluate many cache configurations in a short time. Let us consider a multi-core processor cache. We can obtain a memory access trace by using a cycle-accurate memory simulation but it can be changed when we consider another multi-core processor cache configuration. One of the main concerns in trace-based cache simulation applied to multi-core processor caches is its accuracy when the cache configuration that the memory access trace assumed is different from those the trace-based cache simulation targets. In this paper, we evaluate how much memory access traces affect cache configuration simulation when cache configurations simulated are different from the one that memory access traces assume, using several benchmark applications.

Recently, multi-core processors are used in embedded systems very often. Since application programs is much limited running on embedded systems, there must exists an optimal cache memory configuration in terms of power and area. Simulating application programs on various cache configurations is one of the best options to determine the optimal one. Multi-core cache configuration simulation, however, is much more complicated and takes much more time than single-core cache configuration simulation. In this paper, we propose a very fast dual-core L1 cache configuration simulation algorithm. We first propose a new data structure where just a single data structure represents two or more multi-core cache configurations with different cache associativities. After that, we propose a new multi-core cache configuration simulation algorithm using our new data structure associated with new theorems. Experimental results demonstrate that our algorithm obtains exact simulation results but runs 20 times faster than a conventional approach. Copyright © 2013 The Institute of Electronics, Information and Communication Engineers.

Recently, multiple-core processors are used in embedded systems very often. Since application programs running are much limited on embedded systems, there must exist an optimal cache memory in terms of power and area. Simulating application programs on various cache configurations is one of the best options to determine the optimal cache configuration. Multicore cache configuration simulation, however, is much more complicated and takes much more time than single-core cache configuration simulation. In this paper, we propose a very fast two-core L1 cache configuration simulation algorithm. We first propose a new data structure where just a single data structure represents two or more multicore cache configurations with different cache associativities. After that, we propose a new multicore cache configuration simulation algorithm using our new data structure associated with new theorems.

The number of sets, block size, and associativity determine processor's cache configurations. Particularly in embedded systems, their cache configuration can be optimized since their target applications are much limited. Recently, the CRCB method has been proposed for LRU-based (Least Recently Used-based) cache configuration simulation, which can calculate cache hit/miss counts accurately and very fast changing the three parameters. However many recent processors use FIFO-based (First-In-First-Out-based) caches instead of LRU-based caches due to the viewpoints of their hardware costs. In this paper, we propose a speeding-up cache configuration simulation method for embedded applications that uses FIFO as a cache replacement policy. We first prove several properties for FIFO-based caches and then propose a simulation method that can process two or more FIFO-based cache configurations with different cache associativities simultaneously. Experimental results show that our proposed method can obtain accurate cache hits/misses and runs up to 32% faster than the conventional simulators.

In hierarchical cache configurations, L1 cache uses LRU as cache replacement policy but L2 and/or L3 caches use FIFO due to its low hardware cost. This paper proposes a fast cache configuration simulation method for hierarchical cache configurations composed of LRU-based L1-cache and FIFO-based L2-cache. In our proposed method, we fix L1 data cache and simulate several L1 instruction cache configurations and L2 unified cache configurations simultaneously with varying their cache parameters. By using L1/L2 cache properties, we can skip to simulate several cache configurations but can obtain exact cache hit/miss counts for all the L1/L2 cache configurations. Experimental evaluations demonstrate that our proposed method boosts up the simulation speed by up to 1900 times.

The number of sets, block size and associativity determine processor's cache configuration. Particularly in embedded systems, cache configuration can be optimized due to the limitation of target applications. For LRU cache replacement policy, Recently, the CRCB approach has been proposed for LRU-based cache configuration simulation, that can calculate cache hit/miss rate accurately and very fast changing the three parameters described above. However many recent processors use FIFO-based caches instead of LRU-based caches. In this paper, we propose a faster cache configuration simulation method for embedded applications that uses FIFO as a cache replacement policy. We first prove several properties for FIFO-based caches and then we propose a simulation method that can process two or more FIFO-based cache configurations with different cache associativity simultaneously. Experimental results show that our proposed method can obtain accurate cache hits/misses and an average of 18% faster than the conventional simulators.