Recently, SiC (silicon carbide) has attracted attention as a new material to replace silicon power semiconductors. Since SiC is a wide-bandgap semiconductor and has high heat resistance, it can be operated in a high temperature environment. However, the conventional power module package is mainly joined by a low melting point material such as lead-free solder, and interconnection does not have enough heat resistance. Therefore, we have been proposing and experimenting with Nickel Micro-Plating Bonding (NMPB) using Ni (nickel), which has excellent heat resistance and strong bonding strength, as a new bonding method. Although various researches have been conducted on the bonding reliability of NMPB, long-term reliability evaluated from the aspect of metal fatigue has not been much discussed. In this study, a test has been conducted using a resonant type fatigue testing machine and examined whether acceleration of fatigue evaluation time and long-term reliability of NMPB were confirmed.

Stainless steel is applied in a wide range of fields as a material with high heat and corrosion resistance. Welding, brazing, and solid-phase bonding are the most common joining techniques for stainless steel. Conventional joining methods have issues such as local thermal distortion of the joining area and the need for high-temperature heat treatment at 800-1000℃. In this paper, we investigated a new joining technique for stainless steel. With the aim of establishing a new joining technology for stainless steel, we joined stainless steel using the Ni Micro-Plating Bonding method (NMPB) and evaluated the shear stress and the tensile stress of the joints. The joining process is performed at about 55℃, followed by heat treatment at a relatively low temperature of 300℃ or higher. Shear and tensile tests were conducted on the NMPB-joined SUS304, and the results showed that the shear stress was 114MPa and the tensile stress was 77MPa without annealing. After heat treatment at 300-400℃ for 1.5h, the shear stress of 200MPa and the tensile stress of 240MPa were obtained. In addition, the heat treatment at 600-800℃ for 1.5h resulted in the shear stress of 230MPa and the tensile stress of 400MPa. The plating crystallographic structure before heat treatment showed preferential orientation to <001>, but after heat treatment, recrystallization progressed beyond the boundary interface at 400℃ or higher, and a non-oriented crystalline was observed.

We added nanofillers of MgO, Mg(OH)₂, SiO₂, and TiO₂ to epoxy resin by high‐pressure shearing at a content of 1 vol%. The glass transition temperature (T_g), dielectric properties, and mechanical properties were measured for these nanocomposites. As a result, T_g decreases in all the nanocomposites. When the filler is MgO or Mg(OH)₂, the increase of the real part (ϵ_r′) and that of the imaginary part (ϵ_r″) of complex permittivity are significantly suppressed at high temperatures by the filler loading. On the other hand, when the filler is SiO₂ and TiO₂, the suppression of the increase in ϵ_r′ and ϵ_r″ is not obvious. Furthermore, regardless of the filler material, the addition of nanofiller hardly affects the mechanical storage modulus at 200°C. These results indicate that the difference in filler material gives more significant effects on dielectric properties than on mechanical properties. © 2020 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

© 2020 IEEE. As for the IGBT power device based on Si used for the vehicle, the performance limit of the Si semiconductor has been pointed out, and the SiC semiconductor has been attracting attention as a next-generation semiconductor. The SiC semiconductor has advantages such as a wider band gap, a larger breakdown electric field, and high temperature operation (about 300 ° C.). If these features can be maximized, a SiC power semiconductor module that can be significantly improved in efficiency, downsized, and operable in a high-temperature environment as compared with a Si semiconductor can be more widely implemented.In this study, two sets of SiC-MOS and SiC-SBD devices are embedded in a ceramic substrate, and their electrodes and the copper electrodes of the substrate are interconnected by NMPB (Nickel Micro-plating Bonding) method, so that one-leg prototype inverter modules of a highly heat-resistant and ultra-small size (47x30x1.3mm) could be manufactured. The NMPB method is a technology that we have originally developed to connect a chip electrode and a lead formed in a chevron shape by Ni plating. High-temperature operation and excellent switching characteristics of the SiC power module were demonstrated.

There is an increasing expectation to incorporate silicon carbide (SiC) as inverter power modules for hybrid electric vehicles (HEVs) and electric vehicles (EVs). In order to maximize the performance of SiC devices, new packaging technologies that can realize high-temperature heat resistance by replacing solder joint or Al wire bonding, have been strongly demanded. In order to meet these demands, we have developed a new interconnection technology named Nickel micro-plating bonding (NMPB), that enables the interconnection in a narrow gap between electrodes of SiC devices and substrates via our newly designed lead frame, whose lead surface is formed into chevron shape. The plating bath for NMPB is a sulfamic acid bath consisting of nickel sulfamate and several additives, and was specifically prepared to plate narrow areas at the bonding interface without plating defects. It was found that when columnar crystal grains grow from both facing electrode surfaces, a strong bond without defects such as micro-voids at the interface is obtained. The bonding strength of NMPB was confirmed by shear test to be higher than that of Pb free solder joints and not to deteriorate even after high temperature storage (HTS) tests at 250 degrees C for 1000hrs and after 1000cycle thermal cycle tests (TCTs, 250 degrees C/-45 degrees C). The NMPB was applied to the manufacture of one leg SiC inverter power module using two pairs of SiC MOS-FETs and SBDs, which were interconnected with a newly designed lead frame for double sided cooling structure. After molding resin copper heat spreaders were formed on the outer surfaces of both sides of the NMPB leads by additive method. Our newly developed SiC power module showed stable I-V characteristics over 250 degrees C and lower switching loss. The reliability of the modules was confirmed by TCTs and power cycle tests.

<title>Abstract</title>
In power modules using SiC devices, high temperature operation is expected. Therefore, a bonding technology having high temperature resistance of 250°C or more is required. In recent years, research on low temperature sintering bonding by Ag nanoparticles, Cu nanoparticles and sub-micron particles has been conducted as a new bonding technology corresponding to SiC power devices. Nanoparticles are sintered at a temperature much lower than the sintering temperature in ordinary powder metallurgy. We focus on Ni having high melting point and excellent corrosion resistance as a new bonding material and are conducting research on high temperature resistant interconnection technology using Ni nanoparticles. We have found that bonding is possible at a bonding temperature of 400°C or less and enable to interconnect SiC devices for high temperature operation. However, there are still following problems to be improved, as follows, especially for a large chip size : Voids formed in the bonding layer and cracks generaled stress caused by a difference in thermal expansion coefficient(CTE). In this paper, we propose a bonding material of composite paste in which Ni nanoparticles and Al particles are mixed. From the results of the research, it was found that the occurrence of cracks and gas void was suppressed by mixing Al particles. Also the thermal stress analysis by FEM, the addition of Al particles shows to reduce the thermal stress during thermal cycle test (TCT).

<title>Abstract</title>
Recent years, with the development of intelligent vehicles, power devices would be widely used. But traditional Si power devices have problems under high temperature. Now, there is a tendency that using SiC instead of Si in power devices, as SiC has a higher band gap 3.25 eV comparing with 1.12 eV of Si. So that SiC power devices can withstand higher temperature and voltage. Also SiC power devices have the advantages of lower parasitic parameters, smaller device size and shorter response time. In this study, to investigate the reliability of Ag wedge bonding, Ag wires were bonded on Al pad and Au-Ni pad. And then we did shear test after high temperature storage life test (HTSL). Finally, we used energy dispersive X-ray spectroscopy (EDS) to do cross-section observation. The results show that, for Al pad, the shear strength has decreased after annealing at 300°C with mold packages, cracks and corrosion were observed. For Au-Ni pad, the shear strength has increased after annealing, and no cracks or corrosion formed. So Ag bonding wire is proposed as an alternative to Al bonding wire for selected metal pads in power devices.

Recently there is a trend toward to use SiC instead of Si in power devices since SiC can withstand higher temperature (above 300°C) and higher voltage with less power loss than Si. So there is a great interest to improve interconnection technique for power devices package. In this study, Ag wire with diameter of 200 μm was bonded on Al pad, after annealing at 200°C and 300°C, intermetallic compounds (IMC) were investigated by energy dispersive X-ray spectroscopy (EDS). The results show that, when annealed in air, two kinds of IMC Ag2Al and Ag3 Al formed and no voids or cracks were observed; but when annealed with epoxy molded IC package, voids were observed, and between Ag wire and IMC there was a corrosion layer.

Highly filled dielectric polymer nanocomposites with high dielectric constant nanoparticles (e. g., BaTiO3) have promising application in many fields such as energy storage. The effectiveness of these nanoparticles to increase the dielectric constant and energy density of the resulting nanocomposites has already been demonstrated. However, the role of interface between the nanoparticles and polymer matrix on thermal expansion, energy storage and breakdown strength-the three parameters that are important for practical application of the dielectric polymer nanocomposites, has not been systematically documented. In this contribution, we investigated the effect of six kinds of nanoparticle surface chemistry on the processing, coefficient of thermal expansion, energy storage and breakdown strength of highly filled epoxy/BaTiO3 nanocomposites. It was found that all these aspects, in particular the processability of the nanocomposites, are associated with the nanoparticle surface chemistry. Combining the processability, coefficient of thermal expansion, energy storage and breakdown strength of the nanocomposites, we conclude that the nanoparticles functionalized by silane coupling agents with terminal groups capable of reacting with the epoxy matrix are more suitable for preparing highly filled dielectric polymer nanocomposites.

The interface is critical for the design of polymer nanocomposites with desirable properties. The effect of interface behavior on the properties of polymer nanocomposites with low nanoparticle loading has been well documented. However, our understanding of the role of the interface in highly filled polymer nanocomposites is still limited because of the lack of comprehensive research work. In this contribution, by using BaTiO3 nanoparticles with six kinds of surface chemistry, we have prepared highly filled epoxy nanocomposites (50 vol% nanoparticle loading). The role of nanoparticle surface chemistry on the dielectric properties of epoxy nanocomposites is investigated at a wide frequency and temperature range by using broadband dielectric spectroscopy. Combining the microstructure analysis of the highly filled nanocomposites with a comprehensive X-ray photoelectron spectroscopy characterization of the surface chemistry of the BaTiO3 nanoparticles, an understanding is formed of the correlation between the nanoparticle surface chemistry and the dielectric properties of the nanocomposites. The functional group density, functional group type, and electrical properties of the modifier-the three parameters that are inherent from the nanoparticle surface modification-have a strong impact on the temperature and frequency dependence of the dielectric constant and dielectric loss tangent. This work demonstrates the great importance of surface chemistry in tuning the electrical properties of dielectric polymer nanocomposites.

High temperature SiC devices require the materials for packaging also capable of working at higher temperature than those for Si devices. SiC devices are expected to help hybrid vehicle power control units (PCUs) produce higher power in a more compact size as SiC can withstand higher voltages and temperatures (above 300 degrees C) than silicon with less power loss. The improvement of interconnection technologies is increasingly becoming a top priority, particularly for the operation of SiC devices at relatively high temperatures. We propose a new interconnection method using nickel electroplating to replace Al wire bonding or die-bonding using solder materials. During the evaluation of the reliability of interconnections annealed at up to 500 degrees C, we observed no significant changes in mechanical or electrical properties. We found that micro-plating connections can be used successfully for high-temperature-resistant packaging for SiC devices.

In this paper, viability of electroplated Ag film into device application was studied. Alloying behavior of the Ag film with its underlying Pd(50 nm)/Ti(100 nm) film stack was investigated with respect to heat treatment at different temperatures from 400 °C to 800 °C in an argon ambient. After annealing at 400 °C, the electrical resistivity of the Ag film increased due to Pd alloying with Ag. Formation of Pd-Ti intermetallic phases became dominant over Ag-Pd alloying with increasing annealing temperature, leading to the resistivity decrease of the Ag film. The resistivity of the 800 °C annealed Ag film approached that of its as-plated Ag film. The excess Ti atoms which were not consumed to form the intermetallic phases with the Pd atoms migrated to the Ag film surface to form Ti oxides along the Ag grain boundaries on the topmost film surface. The Ag/Pd/Ti film stack has been confirmed to maintain the resistivity of the Ag film at as-plated low levels after high temperature annealing. This paper also discusses process integration issues to enable the Ag metallization process for future scaled and three dimensionally chip stacked devices. © 2013 Elsevier B.V. All rights reserved.

A nano-composite powder composed of silica and carbon with a unique property could be prepared from a mixture of a silicate compound and an epoxy compound, in which the silica within the nano-composite powder has a BET surface area of as high as greater than 800 m2/g although the nano-composite powder has a BET surface area of less than 10m2/g. It was estimated that the silica and the carbon are in a very finely and uniformly mixed state within the nano-composite powder and that the silica and the carbon form particles having a diameter of several tens nm and a number of silica particles having a diameter of several nm exist within the every particle of the nano-composite powder. It was demonstrated that the nano-composite powder exhibits characteristic behaviors under calcination at a temperature of 1450°C such that an amorphous state of the nano-composite powder is maintained, a large amount of gaseous reactant generates from the nano-composite powder, and a reaction product of SiC is synthesized in the presence of another ingredient. © 2013 The Ceramic Society of Japan. All rights reserved.

This paper deals with the process integration to produce a high performance processor with a large-scale and high-bandwidth DRAM chip stacked. Ten micrometres pitch Cu redistribution wiring has been implemented on 12 in. DRAM wafers to relocate the Al bond pads where 40 lm pitch SnCu bumps are formed for a large number of I/Os of the memory interface. A phenol-melamine based resin film which is curable at less than 250 °C can be used so as to avert detraction from memory retention yield as well as to insulate the Cu lines, leading to reduction of wafer warpage in an effort to enable fine pitch lithography. In a chip-on-chip joining process, the logic chip is interconnected with the DRAM chip with a less than 1 μm accuracy by mass reflow bonding of the SnCu micro-bumps on both of the chips, revealing the self-aligning effect of the solder bumps. No failures have been observed after reliability stressing on the packaged two-chip stack. The present process integration has been qualified for the mass producing line to provide some merchant LSI devices and will be viable to future generation devices with more chips stacked using through Si via technology.

Heavily nitrogen-doped n(+) 4H-SiC single crystals were grown by the physical vapor transport (PVT) method. The nitrogen incorporation kinetics in a heavily doped regime was studied in terms of growth temperature dependence, and it was revealed that the growth temperature substantially influenced the amount of nitrogen incorporated into the crystals and their surface step structures on the (0 0 0 (1) over bar )C facet plane. The structural quality of heavily nitrogen-doped 4H-SiC crystals was examined by X-ray rocking curve measurements and defect selective etching by molten KOH at around 500 degrees C. The crystals contained an extremely low density of 3C-SiC inclusions and stacking faults and showed a comparable crystalline quality to conventionally doped 4H-SiC substrates. Furthermore the structural stability of the heavily nitrogen-doped 4H-SiC substrates during high-temperature treatments has been investigated. The substrates with a large {0 0 0 1} surface roughness showed a resistivity increase after annealing at 1100 degrees C for 2 h, which was confirmed to be caused by the formation and expansion of double Shockley-type basal plane stacking faults in the substrates. The occurrence of the stacking faults largely depended on the surface preparation conditions of substrates, which indicate that the primary nucleation sites of stacking faults exist in the near-surface regions of substrates. (C) 2009 Elsevier B.V. All rights reserved.

The stacking fault formation in highly nitrogen-doped n+ 4H-SiC single crystal substrates during high temperature treatment has been investigated in terms of the surface preparation conditions of substrates. Substrates with a relatively large surface roughness showed a resistivity increase after annealing at 1100 degrees C, which was confirmed to be caused by the formation and expansion of double Shockley-type basal plane stacking faults in the substrates. The occurrence of the stacking faults largely depended on the surface preparation conditions of the substrates, which indicates that the primary nucleation sites of stacking faults exist in the near-surface regions of substrates. In this regard, mechano-chemically polished (MCP) substrates with a minimum surface roughness (&lt; 0.3 nm) exhibited no resistivity increase and very few stacking faults after annealing even when the nitrogen concentration of the substrates exceeded 1 X 10(19) cm(-3).

The theromoelastic stress in post-growth SiC crystals has been investigated in order to suppress the cracks which were frequently observed in SiC crystals with larger diameters. Optimizing the temperature distribution in growing crystals lead to reduction of tensile stress components, and thus resulting in crack-free 100mm diameter SiC crystals with micropipe (MP) densities of 0.025/cm(2) The concept of process optimization we established is confirmed to be effective to the growth of large diameter SiC crystals with mechanical stability.

The development of lapping and polishing technologies for SiC single crystal wafers has realized the fabrication of an extremely flat SiC wafer with excellent surface quality. To improve the SiC wafer flatness, we developed a four-step lapping process consisting of four stages of both-side lapping with different grit-size abrasives. We have applied this process to lapping of 2-inch-diameter SiC wafers and obtained an excellent flatness with TTV (total thickness variation) of less than 3 Am, LTV (local thickness variation) of less than 1 mu m, and SORI smaller than 10 mu m. We also developed a novel MCP (mechano-chemical polishing) process for SiC wafers to obtain a damage-free smooth surface. During MCP, oxidizing agents added to colloidal silica slurry, such as NaOCl and H(2)O(2), effectively oxidize the SiC wafer surface, and then the resulting oxides are removed by colloidal silica. AFM (atomic force microscope) observation of polished wafer surface revealed that this process allows us to have excellent surface smoothness as low as Ra=0.168 nm and RMS=0.2 nm.

Thermal fatigue properties of Sn-xAg-0.5Cu (x51,1.2 and 3, mass%) lead free solder interconnects were discussed from the viewpoints of both morphology and grain boundary character distribution. 3Ag showed the longer thermal fatigue life than 1Ag and 1.2Ag. Both cracks, which were initiated by thermal strain, and grain boundary damage due to grain boundary sliding degraded the thermal fatigue lives. From a microstructural observation using orientation imaging microscopy, recrystallisation of tin grains was observed, and 3Ag suppressed coarsening of tin grains after further thermal fatigue as compared with 1Ag and 1.2Ag. Moreover, 3Ag showed a larger amount of coincidence site lattice boundaries than 1Ag and 1.2Ag. It is suggested that in 3Ag not only smaller tin grains but also larger amount of coincidence site lattice boundaries suppressed crack propagation and grain boundary sliding.

Micro-ball wafer bumping (MBB) technology, which has capability of fine pitch bumping such as 150-mu m pad pitch and the advantages of adjusting the optimum material combinations of joints, was brought into practice. High productivity and yield were achieved by employing an inspection and the repair process with special equipment, and a void-less reflow process was established. Package-level reliability tests were performed for chips with Ti/NiV/Cu-UBM and Sn-Ag-Cu solder bumps using MBB technology with excellent results. An evaluation on reliability was also conducted with Sn-1.2Ag-0.5Cu-Ni solder and pure tin solder bumps. As a result of multiple reflow cycle tests for Ti/NiV/Cu-UBM and various lead-free solders, the shape of IMC and the spalling of IMC were influenced by the total amount of Cu and Ni in the solder and the UBM composition. Ti/NiV/Cu-UBM can be applied to, various solders by changing the thickness of the surface Cu layer according to the composition of the solder.

Equal-channel angular pressing (ECAP) is a valuable technique for refining grain sizes to the submicrometer or the nanometer range. This study explores the reason for the difference in the grain refining behavior between pure Al and pure Cu. First, very high purity levels were adopted in order to minimize any effects of impurities: 99.999% for Al and 99.99999% for Cu. Second, high purity (99.999%) Au was also used in order to examine the effect of stacking fault energy. All three pure metals were subjected to ECAP and microstructural observations and hardness measurements were undertaken with respect to the number of ECAP passes. It is concluded that the stacking fault energy plays an important role and accounts for the difference in the grain refining behavior in the ECAP process.

Effect of Ni addition on the bending properties of Sn-Ag-Cu lead-free solder joints was investigated. Three point bending tests were conducted with a 324pin flip chip specimen at 10 Hz frequency and with 3mm substrate displacement. The test temperatures were 298K and 398K. At each temperature, Sn-1.2Ag-0.5Cu with a small amount of Ni addition, LF35 showed higher performance. The reason LF35 showed higher bending performance was discussed based on a mechanical fatigue test using a micro bulk specimen. Ni addition caused a fine subgrain of beta-Sri, hence the crack propagation mechanism is changed, resulting in the improved fatigue performance of LF35.

The drop shock reliability of an Sn-Ag-Cu solder system in ball grid array (BGA) interconnects were improved by selecting a lower Ag chemical content and the addition of a small amount of Ni. The drop shock reliability of Sn-Ag-Cu solder in BGA interconnects was enhanced by the addition of small amount of Ni, and LF35(Sn-1.2Ag-0.5Cu-Ni) had twice better drop shock reliability than LF45(Sn-3.OAg-0.5Cu). One of the main reasons is the solder with lower Ag contents in the Sn-Ag-Cu solder system demonstrated softer properties in terms of hardness. Different intermetallic compound (IMC) layer morphologies were found on the Cu electrodes after reflow between Sn-1.2Ag-0.5Cu-Ni and Sn3.0Ag-0.5Cu, in which the former is smooth IMC and the latter is like a peninsula IMC. Different cracks modes were also detected. Cracks in Sn-1.2Ag-0.5Cu-Ni were mainly inside solder and cracks in Sn-3.OAg-0.5Cu were near the solder/electrode interface for all drop shocks tested. From SEM, EPMA mapping and TEM analysis, the small amount of doped Ni was mostly segregated at the interface. The doped Ni mainly existed in the Cu6Sn5 IMC layer region as formed (Cu,Ni)(6)Sn-5, and the Cu3Sn IMC region contains less Ni. Both different IMC morphologies and crack locations were discussed on the basis of the lattice distortion relaxation. The Cu6Sn5 peninsula IMC growth was discussed that was caused by the compression stress of itself, and the Sn-3.0Ag-0.5Cu crack inside the IMC was also discussed that was caused by the difference stress between Cu6Sn5 (compression stress) and Cu3Sn (tensile stress). Namely, the: doped Ni was substituted for the Cu site Of Cu6Sn5 and their lattice distortions were relaxed due to the smaller atomic radius of Ni compared with Cu. The stress difference between (Cu,Ni)6Sn5 and Cu3Sn was relieved by the Ni substitutions, which improved the drop shock reliability in BGA of Sn1.2Ag-0.5Cu-Ni.

The bumps for flip chip interconnection are becoming smaller and smaller. Since lead-free solders became popular, Ni-based under bump metallization (UBM) has attracted attention in recent years because of their slower reaction rate than traditional Cu-based UBM. However, there is little data concerning the solid state reaction between small lead-free solder bumps and Ni-based UBM. In this work, Sn-3Ag-0.5Cu and Sn3.5Ag solder bumps were fabricated with 110-mu m-diameter solder balls on electrolytic Ni, and the growth kinetics of intermetallic compound (IMC) layers and the morphology of bumps during long-term aging were investigated. The IMC layer exhibited parabolic growth, and the activation energy values for the Sn-3Ag-0.5Cu or Sn-3.5Ag solder/Ni UBM were obtained. The growth rate accelerated at 463 K or above. (Ni,Cu)(3)Sn-4 or Ni3Sn4 IMC was formed mainly at the solder/Ni interface after long-term aging. Large voids were formed at the solder/IMC interface at 463 K or above. The voids are the result of stress by volume expansion due to IMC growth. Coarse Ag(3)sn grains were observed adjacent to the voids and contributed to void initiation.

Micro-ball wafer bumping method was applied to forming double ball bumps, which increased the bump height to improve the reliability of the flip chip interconnection. The micro solder balls of 100um in diameter were transferred and connected to the whole electrode-pads covered with UBMs(Under Bump Metals) of an 8 inch wafer in one stroke using a fully automated micro ball mounter, which was originally developed. The balls were held on fluxed pads and melted in a reflow furnace. After cleaning the flux residue, the wafer bumped with micro-balls was then encapsulated with epoxy resin containing silica fillers by using Apic Yamada's wafer level molding system. The molding resin was spread to the whole wafer by compressing with a heated flat plate, where the top of the solder bumps were covered with an elastic parting film. The supplied resin volume was previously adjusted to the desired molding thickness. The exposed top of the ball bumps was cleaned and then second micro-ball bumping was processed on the top of the first bumps. The first and second balls were connected by reflowing to form the double ball bumps. The height variation and shear strength of double ball bumps were evaluated. To compare the reliability for the different type of bumps the TCTs and FEM analysis were performed for the chips connected with PCBs.

Significant reduction of the wire sweep in molding is proposed because the wire sweep is considered to be the major problem to realise wire bonding with ultra fine pitches of under 30 micrometers. In the present proposal, Ni was plated for several micrometers before molding on bonded Au wires. Ni plating was carried out by means of electroless plating for several minutes in the aqueous solution kept at 358K containing Ni and P. The wire sweep ratio for Ni plated wire (total diameter was 21 micrometers) was almost half of that for Au wire with the diameter of 15 micrometers except Ni plate, and was slightly smaller than that for Au wire with the diameter of 25 micrometers except Ni plate even the total diameter was smaller. It is considered that wire sweep suppression by this technique was due to the enhancement of both elastic and plastic properties.

In order to clarify the reliability of Au wire bonds to Al pads, failure causes such as void formation and corrosion behavior of Au-Al intermetallics were investigated in accelerated tests. The effects of annealing environments, temperatures and bonding conditions on bond reliability were also examined. The molding resin has a great influence on the corrosion behavior, GC-MASS (gas chromatography) analyses of outgasses produced from the resin revealed that a major Br-containing species was methyl bromide (CH_3Br). The corrosion reaction between the intermetallics and bromides produced minute Au precipitates and amorphous Al oxides. This corrosion behavior caused significant fluctuations in electrical resistivity. Non-uniform formation of intermetallics at the bonds accelerated the corrosion behavior. It was confirmed that initial conditions at the bond interface affected bond failure. Activation processes of void-induced and corrosion-induced failures were compared in the respect of bond lifetime. The void formation was controlled by an interdiffusion process, whereas the corrosion behavior was controlled by a decomposition process of the resin. Au/Al bond failure could be governed by the intermetallic corrosion at higher temperatures and by void formation at lower temperatures.

A new wafer bumping method using micro-balls was developed that can be used for high-density LSI assembly, specifically for Flip Chip interconnection. Micro solder balls with the diameter ranging from 60 mum to 200 mum were first formed with a high level of accuracy and sphericity. These balls were transferred and bonded to the whole electrode-pads of an 8-inch wafer in one stroke using a fully automated micro ball mounter, which was newly developed. The balls were held on fluxed pads and melted in a reflow furnace. The fluxing was performed using unique stamp system. The productivity and the yield were evaluated under the following conditions. The number of chips on an 8 inch wafer was 616, Pad pitch was 250 mum, Pad number of a chip was 635 (25x25 area array), and the total number of balls on a wafer was 385,000. The yield of forming bumps was confirmed to be higher than 99.995% without repairing and the cycle time of micro ball bumping was ca. 5 min. for an 8 inch wafer. The bump height variation, the bump shear strength and the bond reliability were evaluated in comparison with other methods.

Highly-alloyed Au-Ag bonding wire could be effective in saving material costs. We investigated the effects of Ag alloying on ball formation, bond strength and bond reliability. Even with high Ag concentration (similar to 50at%), ball was formed spherically. Bond strength and ball deformability were good enough for IC's assembling when concentration of Ag was less than 30at%. Thermal reliability of bonds between Au-Ag wire and Al pad had the unique dependence of Ag concentration. Ball bonds of Au-14at%Ag yielded significant degradation through annealed. On the contrary bonds of Au-24at%Ag provided as good reliability as a commercial pure Au wire after annealed at 473K-1000h. The bond reliability has the connection with intermetallic growth as well as diffusion behavior at the bond interface. The growth of intermetallics was different from that of pure Au/Al bonds. Optimizing the Ag concentration in the wire was effective in improving the bond reliability.

Micro-ball bump technology has been developed for flip chip (FC) interconnections. This technology is based on (1) a production method of fine metal balls (micro-balls) and (2) a gang-bonding method for forming bumps (micro-ball bumps) on chip electrodes. Solder balls of 60-150mm and gold balls of 35-100mm in diameter were prepared with extremely uniform diameters and high sphericity. After holding these micro-balls on through-holes of an arrangement plate by a vacuum suction method, the micro-balls were transferred onto the electrodes of the chips in order to form the micro-ball bumps. An excess ball eliminating system and a ball bouncing system were developed for arranging the ball successfully on the plate. The cycle time of the originally developed mounter was 20 seconds for a chip with 300 bumps. Both bumping on a single chip and on multiple chips in a wafer were possible. The micro-solder bumps were formed onto the electrodes covered with under bump metals (UBMs). The micro-solder-balls of 150mm in diameter were transferred onto the flux printed electrodes of a chip with 220mm pitch and 45x45 area array. The micro-solder bumps were uniform in composition volume, and height because of the use of the micro-solder-balls with precisely controlled diameter and composition. Using the micro-gold-balls of 35mm in diameter, the bumps with 50mm pitch were formed on Al pads by means of thermocompression bonding. Proposed micro-ball bump technology could be applied to bumping not only for FC interconnections, but also for TABs.

Bond degradation of Au wire/Al pad has become a major problem, because of the use of molding resin with low thermal stability (ex. bi-phenyl epoxy resin) and the use of the IC devices under high thermal environments. it is therefore important to secure the Au/Al bond reliability under high temperatures. The lifetime to bond failure for bi-phenyl epoxy molding became shorter than that for cresol novolac epoxy. The failures were caused by the corrosion reaction of Au-Al intermetallics with bromine(Br) contained in the resin compounds. It was clarified that the reactive intermetallic was Au4Al phase formed in the bond interface.
The governing factors of the bond corrosion were investigated such as resin compound, gold wire material. Especially impurities in gold wire could affect the Au-Al intermetallic growing and therefore retard the corrosion. The use of the alloyed wire was effective in improving the bond reliability.