For anonymizing database tables containing personal information, we proposed a new framework such that privacy constraints are given as inference probabilities(accuracies) between person-identifying attributes and sensitive attributes. Also, information loss due to anonymization is modeled as cost functions, and an algorithm that finds an optimal anonymized table was developed. As related research, we also developed access control methods for globally distributed environments, as well as user assistance for privacy settings in social networking services

We have studied management methods for annotation data on information, and coreference analysis in order to keep the quality of information on Web servers high. We have developed a system for storage and retrieval of RDF data representing knowledge resource as well as integrated usage system of retrieval engines and user generated knowledge resource Wikipedia. Also, we have developed a system for consistency analysis and a method for incremental update of causal relation networks

Education systems utilizing the Web have been attracting attentions. By the increase of the volume of education contents and students, the efficiency of processing data becomes a problem. We have been proposing and developing web warehouses for efficient web information processing. In this research, we designed web warehouses from the point of views of education applications, and conducted a series of researches for developing necessary functionalities for the web warehouse and application systems, as summarized below :Web-base contents for environment education : For supporting environment education in field situations, we developed a system to collect various observation data, such as text, images from digital cameras and location information obtained by GPS, and assembles them into web contents. The system was demonstrated in EXPO2005.Teacher-assistance mechanism for web-based self-learning system utilizing operation histories : We developed a web-based self-learning system, which presents questions and records answers through web interface, and we applied the system in high-school supplementary classes. The system's feature is a recoding mechanism which records all the operations by students on PCs, and these records can be analyzed from various point of views, such as answering orders, answering time, hints referred by students, correctness of answers. Through the visualization of record analysis, teachers can evaluate performance of students.Access control of web warehouses : A web warehouse accumulates huge data as the time passes, and it is necessary to build an access control model for the data on web warehouses, where semantics of web warehouses, such as version derivation, content structure, and timestamps, need to be incorporated. We developed a new model which fits these requirements, and we also showed evaluation algorithms.Detecting anomalies of web servers : It is becoming a serious problem that web servers are heavily attacked by unknown adversaries for taking over or sabotaging the server. We have developed a system to visualize web access logs for detecting suspicious activities, utilizing data mining methodologies

Developing technologies for e-commerce, e-procurement and e-government can contribute for promoting productivity of the entire society as well as improving efficiency of economy. In this research, we focused on marketing functionality for establishing selling contracts, and supporting execution of selling contracts. In business-to-business (B2B) e-commerce and e-procurement, selling goods shall be compared not only by price, but also by various types of added values, discount rules, and cancel policies. Representing such business rules in a logical language and storing them in a database can be utilized for developing applications such as marketing including auctions, generating workflow definitions based on selling contracts, and so on.In this research, we developed a technology for extracting business rules from natural language texts in web pages. Such texts, like airline tickets and rent-a-car contracts, are often written in mostly uniform sentences, and providing transformation templates can greatly help the transformation task. The templates produce business rules in a constraint language and stored in a dynamic constraint database developed in this research. Those rules in the database can be queried for logical satisfiablity and implication. We showed evaluation results as well as query optimization methods.For understanding tendencies and characteristics of business rules, we proposed a method for constructing a user interface which reflects degree of relevancy between attributes of business rules. Using this interface, user-configurable goods, such as assembling PCs, can be easily constructed by users, because our interface visualizes relevancy between attributes of business rules, which reflects how parts can be independently chosen, thus reducing constraint violations.,For inter-organizational process collaboration, we have developed a database of e-contracts, where e-contracts hold clauses of agreements, duties, deadlines, exceptions, and so on. By linking intra-organizational workflows with these e-contracts, we can monitor execution of e-contracts. We also developed methods for querying workflow cases to obtain relevant e-contract calluses, and querying similar workflow cases in respect to e-contract relationships

The objective of this research project is to develop techniques(called "Syste Morph : System Morphing") of dynamic reconfiguration and optimization of hardware for system-LSI's and software for them, as (a)an approach for optimization of designing system-LSI's and (b)a solution for "design crisis". The project has performed the following research results.(1)Development and evaluation of online-pro filing techniques : The project has developed some techniques of online profiling which find a hot spot(for example, programming codes, data, or paths operated frequently in a program) by observing the behavior of a program. Then, the project has implemented the online profile to the, dynamically-reconfigurable processor, DAP/DNA, by IPFlex, and evaluated its accuracy and overheads.(2)Development and evaluation of dynamic-software-pipelining techniques : The project has developed some techniques of dynamic software pipelining for loops in the hot path found in (1). Then, the project has implemented the techniques for a hyper-scalar processor which has a VLIW as its coprocessor, and evaluated its improvement and overheads.(3)Development and evaluation of online-construction techniques for configuration data of hardware : The project has developed some techniques to construct the configuration data of a DNA dynamically and in a parallel with the operation of the program, to con figure dynamically the hot path in (1) to the DNA as a logical circuit. Then, the project has implemented the techniques and valuated its performanc

As the use of the Internet is widespread the application area is getting wider. However, while the Internet is a hug bundle of data and is analogous to databases, the data format is too diversified for the database-like use. Hence, it is difficult to utilize them efficiently. This research has achieved the following three contributions :(1) Analysis and application of local InternetThis research proposed retrieve methods of local information on the Internet, cooperating with ISP (Kyoto-Inet) that has many users around Kyoto. Especially, it consists mainly of two proposals ; computation methods of how strongly the information is associated with the local area, and caching technologies of web pages accessed frequently. In the latter we showed that it is practically useful, by applying the method to the real data of the ISP.(2) Advanced Education with WWWSince WWW is helpful to realize distant learning systems, we practiced and evaluated our long-time research proposals Cooperating with Kyoto board of education, the systems were applied to math classes at Horikawa high school. We have practiced educational activities to encourage to improve students' creativity at Takakura and Gosho-minami grade schools. We did researches on constructing databases of students' understanding processes. These systems are distinct from on another, but are still in practice now. Because of support by the teachers and students, the systems are getting widespread.(3) Database Technologies for Electronic Commerce (E-Commerc)This research presented statistical evaluations of methods to find out the items customers hope to get on e-commerce systems. It did theoretical researches on XML documents compatible among corporations. In E-Commerce, it is more importan to protect copyrights because of easier duplication of the items than in real commercial activities. It cooperated with Woodland, ASTEM and Kyoto Comparative Law Center to contribute to EC technology development and copyright protection

The objective of this research project is to develop architectures and design methodologies of customizable IP cores for system-LSI's. The project has performed the following research results.(1) Development of customizable IP core architectures : The project has developed several customizable processors and co-processors as customizable IP cores, and design methodologies for these IP cores. The technologies developed include (I) customizable processors where the performance and energy consumption of their functional units can be (re)configured and optimized at either compile time or run time, (ii)customizable co-processors whose functionality and organization can be reconfigured at run time, (iii) online hardware synthesis technology which produces hardware configuration information for the customizable co-processors, and so on.(2) Development of customizable memory core architectures : The project has developed several customizable memory cores and related technologies ; (I) customizing the instruction decoding for object programs, based on the statistical analysis on the appearance frequency of bit patterns of instructions, so that the power consumed for fetching instructions from a program ROM, (ii) customizing and reducing the number of tag lookups for instruction cache, based on the profile of instruction fetch addresses, so that the power consumed for checking the instruction cache tags, and so on.(3) Development of customization techniques for variable-size datapath and memory-path : The project has developed some techniques for analyzing the dynamic ranges of variables in source programs, and then determining the size of datapath and memory-path so that tradeoff between the performance and power consumption can be achieved

This work discusses some basic techniques of software for variable-voltage processors in order to realize low-energy design, together with modeling techniques and evaluations of their potential benefits by simulation. Details are listed as follows :1) A task scheduling technique for a real-time system with a variable-voltage processor, by which supply voltage is changed dynamically, is presented.2) A platform for datapath width optimization of soft-core processors is built and the presented methodology of datapath optimization is evaluated by using MPEG AAC decoder. In addition, an energy minimization methodology using datapath width optimization is proposed. To find the optimized datapath width for a given application in the early phase of designs, an effective bitwidth and access frequency of variables based performance estimation technique is also developed. A low-energy memory design technique is presented as well.3) A new datapath width optimization methodology considering computation precision targeting area and power reduction is presented.4) A power reduction technique by reducing switching of redundant bit is presented, here effective bit line on data bus is called active bit, the other bit is called redundant bit.5) A cost model for SoC (System on a Chip), in which each cost as a parameter is presented, and a design method by market scale and number of products is also presented.6) High-performance/low power cache architectures with variable cache-line size for merged DRAM/Logic LSIs are presented ; in addition, a low-power instruction cache architecture exploiting program execution footprints is presented

Recent significant advances in LSI technologies have been increasing the number of transistors on a chip dramatically. System designers can now build a large system on a single chip as a system-on-a-chip (SOC). They often use multiple pre-designed and pre-verified blocks to reduce the time required for design and verification. These cores include black-boxed cores whose details are unknown due to the protection of intellectual property (IP) information. The importance of testing the function and performance has been increasing as the LSI technologies have been increasing.We proposed function and performance test methods for Core-Based System LSIs. We proposed a function test method named as CBET (Combination of BIST and External Test) scheme. We theoretically and experimentally validated that the CBET scheme can reduce much testing time. We also proposed a performance test method in which the delay time at a node is treated stochastically. This method can reduce extra margins of the delay time and therefore can estimate the performance for LSIs accurately

The objective of this research project is to develop design methodologies for scalable system-LSI architectures. The project has performed the following research results.(1) Development of scalable system-LSI emulator : The project has developed an emulator, which consists of a CPCI-based PC card and two FPGA-mounted CPCI cards, for enabling designers to explore large design space of system-LSI quickly.(2) Development of architectures for scalable system-LSI and the design space : The project has developed a couple of technologies good for scalable system-LSI, such as (i) PPRAM (Parallel Processing RAM) architectures (inter-LSI communication interface, dynamically variable line-size cache, and so on), (ii) optimizing techniques for variable datapath/memorypath width, (iii) techniques for alleviating data/control dependences on CMP (chip multiprocessor), (iv) intra-LSI signaling technique reducing the effect of crosstalk.(3) Development of CAD tools : The project has developed a couple of CAD tools, such as (i) realtime online profiler for detecting program hot-spots, (ii) hardware/software codesign environment for soft-core processor and Valen-C programs.(4) Development and evaluation of high-performance/low-power microprocessor architectures : The project has developed a couple of technologies good for high-performance/low-power microprocessors, such as (i) dynamic module selection technique utilizing multiple functional modules with different performance/power properties, (ii) realtime task scheduling algorithm for DVS (dynamic voltage scaling) processors, (iii) power-aware memory hierarchy, (iv) cache memory architectures adapting CCC (common case computation) principle to memory reference behavior.(5) Development of applications of scalable system-LSI : The project has developed some scalable system-LSI applications, including (i) RSA cipher processor, (ii) MPEG2 AAC decoder, (iii) special-purpose processor for ERI (electron repulsion integral) calculations in computational chemistry programs

The objectives of this research project are to develop system-LSI architectures and computer-system architectures, or PPRAM (Parallel Processing RAM), which are based mainly on merged memory/logic technology, parallel/distributed processing technology , and inter-LSI high-speed interconnect technology. The project has performed the following research results.
(1) Inter-LSI high-speed interconnect standard, or PPRAM-Link : The project has defined a set of specifications for physical layer, logical layer, and API of PPRAM-Link ; and then it has implemented these specifications in several ways.
(2) Reference PPRAM architectures : The project has developed a couple of architectures good for merged DRAM/logic system-LSI, such as (I) shared-register CMP (chip multiprocessor), (ii) statically/dynamically variable line-size cache, (iii) way-predicting set-associative cache.
(3) DRAM refresh architectures for merged DRAM/logic LSI : The project has developed a couple of architectures good for merged DRAM/logic system-LSI so that alleviate the DRAM refresh characteristics to be worsened by on-chip logic.
(4) Hardware/software codesign methodology for embedded system-LSI : The project has developed a hardware/software codesign methodology based on soft-core processor and Valen-C technologies.
(5) Software-controlled low power architectures : The project has designed a processor architecture, or PowerPro, which can optimize the power consumption by means of software control according to the system load.
(6) Test methodology for system-LSI : The project has proposed a test methodology good for system-LSI, which combines BIST and external test.
(7) PPRAM-based MOE (molecular orbital calculation engine) : The project has developed some PPRAM applications, including MOE chips and MOE system. The MOE chip consists of a 32-bit integer RISC processor, a 76-bit MO-specific floating-point processor, 1Mb SRAM, and a PPRAM-Link interface. The MOE system consists of a number of MOE boards, each of which includes five MOE chips and a bridge chip for PPRAM-Link and IEEE1394.
(8) PPRAM-based realtime digital-watermarking engine for movies : Another PPRAM application is a realtime digital-watermarking engine for movies. The project has implemented a suite of wavelet transformation function, PPRAM-Link interface and PCI-bus interface by means of FPGA.

We proposed novel design techniques for low-power consumption microprocessor systems utilizing characteristics of LSIs. The research covers low-power architectures of processors and memories, an optimum control strategy of supply voltage for minimizing power consumption, and hardware/software codesign techniques for low-power design. The following results have been obtained.1) Development of low-power systems with a variable voltage processor architecture : In this architecture, we provide several supply voltage levels and clock frequency corresponding to each voltage level. Programmers can select the optimum voltage levels according to the required load of programs. We proved a basic theorem for the selection of the optimum voltage and implemented a prototype processor with a voltage control instruction. More than 70% power reduction is achieved for practical programs.2) Development of a low-power processor with variable data-path width : We proposed a new processor architecture in which active data-path width can be controlled from programs. This architecture can be easily combined with the hardware/software codesign technique based on Soft-core processor.3) A compiler technique for reducing bus transitions and a low-power design technique of cache memories : We proposed a compiler technique which controls coding and order of transfer of instructions and data on buses. We also developed a power reduction method in which instructions and data read from cache memory are expected.4) A low-power architecture of logic-DRAM mixed LSIs : For the memory hierarchy of logic-DRAM mixed LSI, we have proposed a. technique to reduce the number of refresh of DRAM to minimize the power consumption in the memory system.5) Development of logic synthesis method for low-power circuits : We developed a new logic synthesis algorithm combined with Transduction method to generate the power minimum combinational circuits

This project aims to develop curriculums and teaching materials for education of VLSI system design in universities, which should be arranged by the own hands of educational organizations. Since 1997, VDEC (VLSI design and education center of University of Tokyo) started their regular services of chip implementation and distribution of CAD tools for Japanese universities. Corresponding to the activities of VDEC,we pursued the development of design environment for VDEC users, test run for the new service of VDEC and implementation of education curriculums using services of VDEC.
We have developed two sets of cell libraries for VDEC under the cooperation of Kyushu Univ., Kyoto Univ.and Waseda Univ.In order to verify the cell libraries, we designed several VLSI chips using the libraries. We also design other chips for establishing a newly introduced process and LPGA's. The designs were done in the following universities : Tokyo, Kyoto, Waseda, Kyushu, Hiroshima City, Kyushu Institute of Technologies, Tohohashi, Osaka, and Keio. The libraries will open for all VDEC users from 1998.
Based on the above experiences of chip designs, we have developed curriculums of VLSI system design education. The curriculums are applied to classes in some universities. We also reviewed a textbook for VLSI design using VDEC service and made tutorial courses of usage of the libraries developed in this project. Several teaching materials including educational microprecessor boards, simulators and CAE tools have implemented and opened for public through WWW.

ハードウェア記述言語とは,ディジタルシステム設計における仕様記述,設計検証のためのシミュレーション,論理回路合成など,種々の目的に用いられている,いわばハードウェアの高級言語である.現在の複雑化したマイクロプロセッサ開発においては,ハードウェア記述言語は必要不可欠なものとなってきている.今後ハードウェア記述言語のソース形式による設計資産の蓄積が増大するため,これらの設計検証・保守・再利用は重要な問題となるであろう。ソフトウェア工学の分野では,これらの問題に対し,プログラムスライシング(以下,単にスライシング)と呼ばれる手法に基づく研究が多くなされている.ハードウァエ記述言語に対するスライシング技術は幅広い応用は期待できるにもかかわらず,いまだ本格的な研究がなされていない.
本年度は以下の成果が得られた.
1,標準的なハードウェア記述言語であるVHDLに対するグラフ表現を用いたスライシング・アルゴリスムを開発した.VHDLのプロセス文などを考慮し,記述の構造を有向グラフとして表現し,スライシングはそのグラフ上での探索問題に帰着される.
2,スライシング・アルゴリズムの実装を部分的に行ない,いくつかの小規模の記述に適用してみた.信号線の削除/追加などの設計保守の問題について適用し,スライシングにより自動化できる作業が多く見つかった.

The purpose of this research is to develop a comprehensive technology for evaluating the performance, cost, and power consumption of high-performance computer systems. We have performed the following researches in particular.
(a) Comprehensive performance evaluation on the compiler and the architecture for high-end microprocessors.
(b) Developing and benchmarking the compiler, targetted for application-specific embedded microprocessors, which is enable to optimize the object-code according to the instruction-cache configurations.
(c) Developing a modeling methodology for estimating the performance, area cost, and power consumption for "system-on-silicon" class VLSI,and then establishing a platform for evaluating tradeoff among these factors.
(d) For parallel computer systems such as workstation-clusters and MPPs (Massively Parallel Processors) ;
・Development of performance estimation models,
・Study of quantitative evaluation index on scalability, and
・Correlation analysis of benchmark programs.

本研究は、演繹オブジェクト指向データベース(Deductive Object-Oriented Databases;DOOD)のための記憶効率の良いデータ構造の開発を目的としている。
そのために、論理構造CADの分野で注目されている二分決定グラフ(Binary Decision Diagram;BDD)に着目し、これを関係の記憶構造として用いることを検討した。この方法では関係を論理関数に符号化し、BDDとして実現するところに考慮すべき課題がある。さらにBDDに基づく符号化法では、理論的に超えられない表現サイズの限界がこれまでの研究で分っている。この限界を克服するために、データベース向きの新たなデータ構造として、Patrica BDDを提案した。またこれまでに提案しているBDDに基づく符号化法についても、実装して評価を行なった。
(1)Patricia BDDの定義および理論的解析:BDDに代るDOODのための記憶効率のよいデータベース構造としてPAtricia BDDを定義し、その最悪記憶サイズを解析した。
(2)効率の解析:対数/線形符号化を用いたBDD、およびPatricia BDDの記憶効率および演算効率を、主記憶型データベースにおいて、種々のパラメータにおける演算効率・記憶効率を評価し、これらBDD型のデータ構造が有効となる状況を明らかにした。
(3)二次記憶に対応したシステム:線形符号化に基づくBDDについては、二次記憶格納方式を考案し、その処理系を実装した。そして演繹データベース質問処理について評価を行なった。

Current computer education curricula of universities and higher educational institutes put emphasis on computer literacy and programming, and it is not sufficient for understanding the total picture of computer systems, from software to hardware, and principles of computing mechanisms. This research project is aimed at developing microprocessor systems suitable for education of computer science, and designing course curricula for systematic education of computer systems, utilizing those educational microprocessors. Our achievements are summarized below :
1.32-bit RISC educational microprocessors : We have developed QP-DLX (Kyushu Univ.) and DLX-FPGA (Kyushu Inst. Tech.) ; both microprocessors have modern architectures such as 32-bit RISC, instruction pipeline, and exception handling. They also have educational features such as observability of internal processor states.
2. FPGA educational microprocessors : FPGA is a reconfigurable device and it can be used for implementing student-designed microprocessors in classrooms. We have developed several FPGA microprocessor boards for different education levels. DLX-FPGA is a 32-bit microprocessor suitable for graduate microprocessor design projects, and a model curriculum using DLX-FPGA is also developed for design courses using hardware description languages. PICO (Keio Univ.) is suitable for entry-level computer education and its curriculum takes account of use in classes of a large number of students.
3. Public release of design data and benchmarks : Various design data, documents, and course texts developed in this project, together with CAD benchmarks, are released for public use through the Internet.

Traditional logic synthesis technology principally aims at generating topological information of logic circuits, realizing function given by functional description. Geometric information which appears in a final mask-pattern is decided in layout synthesis stage independently from logic synthesis. Therefore, in the case of random circuits like control-path, it is possible to get better performance than manual design. But, in the case of regular circuits like data-path, iti is hard to design good synthesis method in which geometric restriction on layout is considered in logic synthesis, and a design description language for that purpose.
(a) Study on design description language that canrepresent regularity of layout-pattern : We proposed a language which can specigy the regularity on layout-pattern and the outline of placement and routing information in functional design.
(b) Study on logic synthesis considering areas and wiring delays : We investigated a logic sythesis method considering wiring delays and areas in logic synthesis, and proposed a circuit synthesis method using the commutative law.
(c) Comparisons of methods to design the practical circuits : We examined the effect of the several synthesis methods, applying them to practical development of a microprocessor. We concretely point out problems on commercial tools and languages.
(d) Applocation of the logic synthesis method : As an application of our method, we propose hardware/software codesign using soft core-processor.
Through the above researches, we unified logic synthesis and layout synthesis, which have been done independently. In our method, designers specify information on layout in architecture design, and logic synthesis and layout synthesis are done using its information. We also show a framework of new design automation system and its application method.

ハードウェア記述言語とは,ディジタルシステム設計における仕様記述,設計倹証のためのシミュレーション,論理回路合成など,種々の目的に用いられている,いわばハードウェアの高級言語である.現在の複雑化したマイクロプロセッサ開発においては,ハードウェア記述言語は必要不可欠なものとなってきでいる.今後ハードウェア記述言語のソース形式による設計資産の蓄積が増大するため,これらの設計検証・保守・再利用は重要な問題となると思われる.ソフトウェア工学の分野では,これらの問題に対し,プログラムスライシング(以下,単にスライシング)と呼ばれる手法に基づく研究が多くなされている.ハードウェア記述言語においては,プログラムスライシングは,例えば「マイクロプロセッサの記述から,ADD命令を実行するために必要な記述をのみを抽出する」という機能になり,形式的検証やテスト生成,保守・再利用のような幅広い応用が可能である.本研究は,スライシング・アルゴリズムの開発を行ない,その理論的性能を明らかにし,またこのアルゴリズムを実装したハードウェア設計記述支援環境を構築することである.本年度は本研究の最終年度にあたり,これまでに開発したスライシング・アルゴリズムの実装を進め,評価を行なった.[依存解析手法の開発]標準的ハードウェア記述言語VHDDLについで,その構文およびsignalの遅延の意味を考慮して,適切な依存関係をいくつか定義し,その・依存関係に基づいてスライスを定義する.そして,そのスライスを計算するアルゴリズムを完成し,正当性および効率性の証明を行なった.[スライシング・ツールの実装]上記アルゴリズムをワークステーション上に実装を行なった.[スライシング・ツールの評価]上記ツールを用いて,実際のハードウェア記述に適用して,以下の評価を行なった.(a)スライス計算間,およびスライスによる設計縮小効果を調ベるために,(B)記述行数と(c)論理合成結果の回路サイズの減少割合.以上の結果,実用的時間で設計縮小効果のあるスライスが計算できることを示した

これから急速かつ広範囲にわたって実用化が進むと予想されている企業間電子商取引は,売り手および買い手が複雑な条件を提示しながら進める交渉過程が重要な位置を占めると考えられる.売り手および買い手のそれぞれの条件を制約として形式的に記述し,それをデータベースに蓄積し検索することが考えられる.これにより,売り手および買い手が,条件が整合する可能性のある相手を探したり,相手の条件の充足を確認することが可能になり,高度な電子商取引サイトの構築が行なえる.本研究では,研究代表者が提案している動的制約代数というデータベース質問言語を基礎として,多様な交渉が可能な電子商取引データベースを開発することを目的とする.本年度は,以下の研究を行った.本研究の目的は以下からなる.動的制約代数の処理系を実装し,実験を行なった.これにより,売り手あるいは買い手側から相手の条件を検索したり,双方の条件の照合を行なう.1.動的制約データベース入出力ツール:昨年度開発した動的制約記述言語を改良し,簡略な制約記述が可能な言語を新たに設計し,その構文解析プログラムを実装した.2.動的制約代数質問インタフェース:動的質問代数の対話型およびバッチ型質問インタフェースであり,質問の構文解析を行ない,質問処理エンジンに渡す.3.動的制約代数質問処理エンジン:与えられた質問の局所的な最適化を行ない,それから動的制約データベースに対し質問評価を行なう.昨年度開発したエンジンに対し,改良したアルゴリズムに基づくあらたな処理系を行なった.本年度実装した動的制約代数質問処理エンジンにより,実行速度の大幅な向上を行なうことができた.今後さらに評価実験を進める予定である

行政機関や医療機関,民間企業などの組織間の情報流通において,個人情報保護などで重要でなXML文書のアクセス制御の特徴として,XML文書の木構造に対応し,部分木の細かい単位でのアクセス制御ルールを設定するという細粒度制御が重視される.XML文書による情報流通の特色として,多数の組織間で流通が行われるが,個々の組織間では異なるXML文書のアクセス制御ルールを採用していることである.地方公共団体や医療機関や民間企業では,組織ごとに異なる個人情報保護ポリシーを採用しているのが現実であり,また今後は個人が自己の情報に関するポリシーを定義することが重視される.本年度は,組織間でXML文書を流通させる場合に,共有がポリシーにより禁止されている文書を検出する手法の開発を行った.指定したキーワード集合を含むXML文書を情報送信の際にフィルタリングする簡便な手法があるが,これでは多くの指定した内容を含まない文書もフィルタリングされてしまい,人手による選別の手間が増大する.そこでXML文書の構造に基づいて,指定したキーワード集合が互いにどれくらい離れていれば,ひとつの内容を構成するキーワード集合とはならず,フィルタリング対象から外すことができるかについて検討し,XML文書の木構造での距離モデルをいくつか定義し,実際のXML文書に適用して有効性を確かめる実験を行った.一方,XML文書は企業や行政機関において,内部統制の面から更新で生じるすべての過去のバージョンを保存することが行われるようになってきている.アクセス制御の観点からは,1つのバージョンのアクセスを制限した場合,それと同じ内容を含むバージョンも同じ制限を行う必要がある.このために必要な,XML文書のバージョン集合のモデル,その上でのアクセス制御モデルを構築した.またXML文書のバージョン集合を差分により記憶効率よく蓄積する手法を示し,その上で提案したアクセス制御ポリシーを評価するアルゴリズムを示した

集合知の体系化として,Wikipediaの記事間のハイパーリンクを利用し,減衰流を用いて記事が表す事項間の関係の強弱を計測する新たな手法を開発した.減衰流による関係の強さの尺度は,既存の尺度である距離連結度,共引用の概念を包含したものとなり,他の尺度よりも高い精度を持つことを明らかにした.出発点から到達点に至る流路に存在する節点を説明オブジェクトとし,それを基に,入力された二つの項目の関係の全体または一部を説明する画像をWebから検索するアルゴリズムを開発した.さらに,Wikipediaの記事において,記事項目に対応するオブジェクトと何らかのオブジェクトとの関係を表す画像が,記事にふさわしいかどうかを判定する手法を開発した.集合知の信頼度推定としては,Wikipedia記事の多くの著者らによる記事の変更履歴に基づき,既存の素性に加え,新たに筆者グループ間における記事の更新を取り消し合う状況を表す素性を導入した手法を開発し,Wikipediaの情報の信頼度推定精度が向上することを確認した.また,大量のニュース記事からの因果関係抽出による因果関係ネットワークの増分構築手法を開発した.トピックと内容を独立して事象を表現するモデルを用いて事象間の同一性判定を類似トピック内に限定することによる計算量の削減を実現した.さらに,事象を表現する語彙の役割(SVO構造)と意味(概念)を考慮してネットワークを構築する手法を提案し,事象の内容を表す語の役割を考慮し,WordNetやオントロジーを用いて概念レベルで事象の類似性を計算することで,ネットワーク構築の一貫性を保つことを可能とした