WATANABE, Takahiro

写真a

Affiliation

Faculty of Science and Engineering

Job title

Professor Emeritus

Homepage URL

http://www.f.waseda.jp/watt

Education 【 display / non-display

  •  
    -
    1979

    Tohoku University   Graduate School of Engineering   Information Science  

  •  
    -
    1979

    Tohoku University   Graduate School of Engineering   Information Science  

  •  
    -
    1976

    Yamaguchi University   Graduate School of Engineering   Electrical Engineering  

  •  
    -
    1974

    Yamaguchi University   Faculty of Engineering   Electrical Engineering  

Degree 【 display / non-display

  • Touhoku University   Doctor of Engineering

Research Experience 【 display / non-display

  • 2003
    -
     

    Waseda University, Graduate School of Information, Production and Systems

  • 1990
    -
    2003

    Yamaguchi University, Faculty of Engineering

  • 1979
    -
    1990

    Toshiba Corporation, Research and Deveopment Center

Professional Memberships 【 display / non-display

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    Information Processing Society of Japan

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    The Institute of Ekectronics, Information and Communication Engineers

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    The Institute of Electronics, Information and Communication Engineers

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    The Japanese Society for Artificial Intelligence

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    Research Institute of Signal Processing, Japan

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Research Areas 【 display / non-display

  • Computer system

Research Interests 【 display / non-display

  • LSI , Electronic Circuit, Integrated Circuit, Design Automation, Computer-Aided Design, Algorithm

Papers 【 display / non-display

  • Predicting stock high price using forecast error with recurrent neural network

    Zhiguo Bao, Qing Wei, Tingyu Zhou, Xin Jiang, Takahiro Watanabe

    Applied Mathematics and Nonlinear Sciences    2021.05

     View Summary

    <title>Abstract</title>
    Stock price forecasting is an eye-catching research topic. In previous works, many researchers used a single method or combination of methods to make predictions. However, accurately predicting stock prices is very difficult. To improve the predicting precision, in this study, an innovative prediction approach was proposed by recurrent substitution of forecast error into the historical neural network model through three steps. According to the historical data, the initial predicted value of the next day is obtained through the neural network. Then, the prediction error of the next day is obtained through the neural network according to the historical prediction error. Finally, the initial predicted value and the prediction error are added to obtain the final predicted value of the next day. We use recurrent neural network prediction methods, such as Long Short-Term Memory Network Model and Gated Recurrent Unit, which are popular in the recent neural network study. In the simulations, the past stock prices of China from June 2010 to August 2017 are used as training data, and those from September 2017 to April 2018 are used as test data. The experimental findings demonstrate that the proposed method with forecast error gives a more accurate prediction result for the stock’s high price on the next day, which indicates that the performance of the proposed one is superior to that of the traditional models without forecast error.

    DOI

  • High performance virtual channel based fully adaptive 3D NoC routing for congestion and thermal problem

    Xin Jiang, Xiangyang Lei, Lian Zeng, Takahiro Watanabe

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E100A ( 11 ) 2379 - 2391  2017.11

     View Summary

    Recent Network on Chip (NoC) design must take the thermal issue into consideration due to its great impact on the network performance and reliability, especially for 3D NoC. In this work, we design a virtual channel based fully adaptive routing algorithm for the runtime 3D NoC thermal-aware management. To improve the network throughput and latency, we use two virtual channels for each horizontal direction and design a routing function which can not only avoid deadlock and livelock, but also ensure high adaptivity and routability in the throttled network. For path selection, we design a strategy that takes priority to the distance, but also considers path diversity and traffic state. For throttling information collection, instead of transmitting the topology information of the whole network, we use a 12 bits register to reserve the router state for one hop away, which saves the hardware cost largely and decreases the network latency. In the experiments, we test our proposed routing algorithm in different states with different sizes, and the proposed algorithm shows better network latency and throughput with low power compared with traditional algorithms.

    DOI

  • An adaptive routing algorithm based on network partitioning for 3D Network-on-Chip

    Jindun Dai, Xin Jiang, Takahiro Watanabe

    IEEE CITS 2017 - 2017 International Conference on Computer, Information and Telecommunication Systems     229 - 233  2017.09

     View Summary

    This paper presents an efficient routing algorithm for 3D meshes without virtual channels. The proposed routing algorithm is extended from 2D east-first routing algorithm and based on network partitioning. It is proven that the proposed method is free from deadlock. In comparison of previous routing algorithms, the average degree of adaptiveness is higher. This feature contributes to higher communication efficiency. Experimental results show that the proposed method can achieve lower communication latency and higher throughput over other traditional methods.

    DOI

  • Behavior-aware cache hierarchy optimization for low-power multi-core embedded systems

    Huatao Zhao, Xiao Luo, Chen Zhu, Takahiro Watanabe, Tianbo Zhu

    MODERN PHYSICS LETTERS B   31 ( 19-21 )  2017.07  [Refereed]

     View Summary

    In modern embedded systems, the increasing number of cores requires efficient cache hierarchies to ensure data throughput, but such cache hierarchies are restricted by their tumid size and interference accesses which leads to both performance degradation and wasted energy. In this paper, we firstly propose a behavior-aware cache hierarchy (BACH) which can optimally allocate the multi-level cache resources to many cores and highly improved the efficiency of cache hierarchy, resulting in low energy consumption. The BACH takes full advantage of the explored application behaviors and runtime cache resource demands as the cache allocation bases, so that we can optimally configure the cache hierarchy to meet the runtime demand. The BACH was implemented on the GEM5 simulator. The experimental results show that energy consumption of a three-level cache hierarchy can be saved from 5.29% up to 27.94% compared with other key approaches while the performance of the multi-core system even has a slight improvement counting in hardware overhead.

    DOI

  • Behavior-aware cache hierarchy optimization for low-power multi-core embedded systems

    Huatao Zhao, Xiao Luo, Chen Zhu, Tianbo Zhu, Takahiro Watanabe

    Modern Physics Letters B   31 ( 19 ) 1 - 7  2017.04  [Refereed]

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Books and Other Publications 【 display / non-display

  • Robot Soccer 〜 Chapter.1 The real-time and embedded soccer robot control system

    C. Li, T. Watanabe, Z. Wu, H. Li, Y. Huangfu, Edited, by Vladan Pap

    Sciyo, Vienna, Austria  2010.01 ISBN: 9789533070360

  • デジタル論理回路の基礎

    笹尾勤, 渡邊孝博, 見山友裕, 澤田直, 橋本浩二

    (財)福岡県産業・科学技術振興財団 システムLSI部  2007.04

  • 回路設計・物理設計の基礎知識

    井上靖秋, 渡邊孝博, 淡野公一, 築添明

    (財)福岡県産業・科学技術振興財団  2005.04

  • 情報工学実験及び演習Ⅰ テキスト

    古賀和利, 中村秀明, 伊藤暁, 山口静馬, 石川昌明, 久長穣, 渡邊孝博

    山口大学工学部知能情報システム工学科  2003.09

  • 最新VLSIの開発設計とCAD 第7章

    渡邊孝博, 大附辰夫, 後藤敏 監

    ミマツデータシステム  1994

Misc 【 display / non-display

Awards 【 display / non-display

  • IEICE Young Researchers' Award

    1983  

Research Projects 【 display / non-display

  • Research on NoC system robust to fluctuation of traffic patterns

    Project Year :

    2018.04
    -
    2021.03
     

  • A Study of a Tile-based NoC System using IPs and its Design

    Project Year :

    2011.04
    -
    2014.03
     

     View Summary

    NoC(Network on Chip) is one of a promising solution to implement the ultra large scale system with high performance on a chip. For improving the design efficiency of NoC, an IP-reused design method was proposed to implement a core in each tile, where design techniques for instruction-level customizable processor IP were developed and its design environment was constructed. Application-specific NoCs of Two- or Three-dimension were also discussed, and NoC architectures for high throughput, low latency and low power were explored and routing algorithms with high performance or fault-tolerancy were developed. Besides, to solve a signal-delay problem of the board-level system composed of NoCs and SoCs(System on Chip), several routing algorithm ware proposed and evaluated

  • A Study of a Tile-based NoC System using IPs and its Design

    Project Year :

    2011
    -
    2013
     

     View Summary

    NoC(Network on Chip) is one of a promising solution to implement the ultra large scale system with high performance on a chip. For improving the design efficiency of NoC, an IP-reused design method was proposed to implement a core in each tile, where design techniques for instruction-level customizable processor IP were developed and its design environment was constructed. Application-specific NoCs of Two- or Three-dimension were also discussed, and NoC architectures for high throughput, low latency and low power were explored and routing algorithms with high performance or fault-tolerancy were developed. Besides, to solve a signal-delay problem of the board-level system composed of NoCs and SoCs(System on Chip), several routing algorithm ware proposed and evaluated.

  • System Design Method for Communication SoC

    Project Year :

    2003
    -
    2008
     

  • ICT application LSI IP and Advanced Design Method

    Project Year :

    2007
    -
     
     

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Presentations 【 display / non-display

  • An Adaptive Adjustable Routing Algorithm for 3D Network-on-Chop

    Ma W, Watanabe T

    IEICE General Conf. 2018  Institute of Electronics, Infromation and Communication Engineering

    Presentation date: 2018.03

  • The High-speed Power Line Topology Check by Reducing Vias

    DAC 2011 User Truck (2011 IEEE 48th Deasign Automation Conference) 

    Presentation date: 2011.06

  • Via数削減による大規模LSIレイアウトの高速DRC手法

    情報処理学会 システムLSI設計技術研究会(SLDM) 

    Presentation date: 2011.01

  • ネットワークオンチップによるBPニューラルネットワークの一構成法

    電子情報通信学会2008年総合大会 

    Presentation date: 2008.03

Specific Research 【 display / non-display

  • Study of Congestion-aware and Fault-tolerant NoC Routing and its implementation on FPGAs

    2020  

     View Summary

    NoC(Network-on-Chip)はMPSoC(Multi-Processor System-on-a-Chip)の一種で、拡張性や通信性能および処理能力の点で非常に優れており、多くの研究が行われている。本研究ではNoCに故障が発生したとき、故障部分を避ける迂回路を効率よく求める手法を提案した。具体的にはNoC上の故障としてリンク遮断が発生した時、Hamiltonian-based Odd-Even Routing手法 を耐故障性を持つように改良した。実験でレイテンシとスループット値を評価した結果、提案手法の有効性を確認した。併せて、通信トラフィックの混雑による性能低下を事前に検出し、防止するための機構を研究した。過去の通信状況に基づいてトラフィック混雑を回避するルートを予測する提案を行い、実験で有効性を確認した。以上の研究成果は国際会議2件の論文として発表した。

  • Traffic-Congestion-Aware Routing Strategy for 2D/3D NoC

    2019  

     View Summary

    NoC(Network-on-Chip)は、コア間のパケット通信をオンチップ・ネットワークによって処理することで、スケーラビリティと通信性能の向上を目指し、大規模なマルチコアシステムを実現するものである。本研究の目的は、通信量が増大して局所的な通信混雑が発生した場合でも良好な性能を発揮できるNoCルーティング機構を開発することである。具体的には、トラフィックパターンに応じた混雑状況の検出機構、ホットスポット・トラフィックパターンでの混雑とアルゴリズム性能との関係分析、および、低コストな混雑検出回路を提案した。また、NoCに故障がある場合にその故障部分を回避するルーティング手法についても取り組んだ。研究成果は4件の査読付き国際会議論文として発表した。&nbsp;

  • 動的再構成可能デバイスによるオンライン・タスク配置問題の効率的解法

    2018   周 亭宇

     View Summary

    動的再構成可能プロセッサ(以下DRP)ではタスクを論理要素に割り当てて並列演算処理し、また、処理が完了したタスクは論理要素群から解放し、そこに別のタスクを割り当てて再利用することができる。オンラインタスク配置問題とは、DRPを効率よく使用しスループットを向上させるために、タスクの処理順序とDRP上の割り当てを最適化する問題である。割り当て問題については、DRP上の領域を管理するデータ構造MERを改良し、再利用可能領域の抽出の高速化手法を提案した。処理順序の最適化については、タスク間に一方向性の通信が存在する場合についてタスク処理順序グラフを定義し、効率の良い処理順序の決定手法を提案した。成果は国際会議等で発表した。

  • ミクスト・シグナルLSIの対称制約条件付き配線手法の研究

    2017   周 亭宇, 戴 Jindun, 黄 洪逸

     View Summary

    ミクスト・シグナルLSIでは信号の干渉や遅延など配線設計に起因する問題が顕著になっている。この問題を解決するため我々は「対称度」なる評価関数を導入し、対称制約を維持できる配線手法を提案した。今回は評価関数について(1)重み係数の影響、 (2)配線障害物がある場合の効果 を検証した。その結果、配線障害物がない場合には、人手設計と同等な経路が得られ、評価関数が機能することが示された。障害物がある場合、一層配線では評価関数の効果が認められるが、配線層数が増えるにつれて経路候補が多くなるため、対称度が同じでも対称性が乏しい配線結果が発生することが判った。今後の課題は配線層数や配線層毎の評価を組み入れることである。

  • LSI/PCBの自動配線アルゴリズムに関する研究

    2016   蒋 欣, 潘 鉄源, 張 子驕

     View Summary

    &nbsp; 集積回路の設計において回路動作や性能に影響を与える配線設計は重要である。そのために複数ネットの配線長を揃える等長配線の自動化手法があるが、バス配線やクロック配線での遅延やスキュをより高精度に考慮するために、ペア配線の対称性も問題となっている。本研究では多層配線においてペア配線を対象形状にする手法を研究した。配線経路探索では、最大フローアルゴリズムを利用して効率よく所望の経路を探索する。対称形状の評価のために、配線長、配線折曲数、配線方向の関数である対称度(symmetrical rate)を定義した。実験の結果、提案手法による配線経路は対称度か高く、少ない配線層で、経路探索時間も従来手法と比べて短縮できることが示された。&nbsp;

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