Updated on 2022/11/28

写真a

 
IKENAGA, Takeshi
 
Scopus Paper Info  
Paper Count: 0  Citation Count: 0  h-index: 9

Citation count denotes the number of citations in papers published for a particular year.

Affiliation
Faculty of Science and Engineering, Graduate School of Information, Production, and Systems
Job title
Professor
Profile

  Takeshi Ikenaga was born in Kitakyushu city, Japan on July 8, 1964. He received B.E. and M.E. degrees in electrical engineering from Waseda University, Tokyo, Japan, in 1988, and 1990, respectively, where he belonged to the Information Systems Laboratory directed by Professor Katsuhiko Shirai (past president of Waseda University). He also received Ph.D degree in information & computer science from Waseda university in March 2001.
He joined LSI Laboratories, Nippon Telegraph and Telephone Corporation (NTT) in 1990, where he has been undertaking research on the design and test methodologies for high-performance ASICs, a real-time MPEG2 encoder chip set, and a highly parallel LSI & system design for image-understanding processing.
From 1999 to 2000, he was a visiting researcher at the Architecture & Language Implementation (ALI) Group (directed by Professor Charles C. Weems) of the Department of Computer Science, University of Massachusetts, Amherst, USA. In 2002, he returned to Kitakyushu city and worked for the Kitakyushu Foundation for the Advancement of Industry, Science andTechnology (FAIS) as an invited researcher.
  He is presently a professor in the system LSI field of the Graduate School of Information, Production and Systems, the Graduate School of Fundamental Science and Engineering, and Department of Electronic and Photonics Systems, School of Fundamental Science and Engineering (FY2006-2013), Waseda University.
His current research interests are application SoCs for image and video processing, which covers video compression (e.g. H.264/AVC, H.264/SVC, H.265/HEVC), video filter (e.g. super resolution, noise reduction), video recognition (e.g. feature point detection, object tracking) and video communication (e.g. UWB, LDPC, public key encryption). He also has interests in application-oriented many-core processor design. He is promoting many national projects, such as Program for Leading Graduate Schools, Global COE, Core Research for Evolutional Science and Technology (CREST), Special Coordination Funds for Promoting Science and Technology, Knowledge Cluster project and Grants-in-Aid for Scientific Research. He is also promoting industry academia collaborations with many companies.

  Dr. Ikenaga is a senior member of the Institute of Electrical and Electronics Engineers (IEEE), a member of the Institute of Electronics, Information and Communication Engineers of Japan (IEICE), the Information Processing Society of Japan (IPSJ) and a board member of the Institute of Image Electronics Engineers of Japan (IIEEJ). He served as an associate editor and a secretary of the IEICE Transactions (incl. special sections) and a secretary of the system LSI technology commitee of the Japan Electronics and Information Technology Industries Association (JEITA). He also served as an organizing committee or a technical program committee members for many international conferences (e.g. ASP-DAC, IEEE ISCAS, IEEE MWSCAS, IEEE SiPS, ICFPT, ISPACS, ASSCC, IEEE ICME, SISA, ASICON, APSIPA ASC, VLSI-DAT and APCCAS) and a chair of Signal processing systems TC for Asia-Pacific Signal and Information Processing Association (APSIPA) .
  He received the Furukawa Sansui award from Waseda University in 1988. In 1992, he also received the IEICE Research Encouragement Award for his paper ``A Test Pattern Generation for Arithmetic Execution Units''. His team also awarded at the DAC/ISSCC 2006 student design contest (Conceputual 1st place), the 8th and 9th LSI IP design award (IP prize) in 2006 and 2007, the 10th LSI IP design award (IP excellent prize) in 2008, Excellent paper award from IIEEJ in 2008, CSPA best paper, ISOCC Samsun award in 2009, ICD best poster award in 2010, IMPS best poster award in 2011, and so on.

Concurrent Post

  • Faculty of Science and Engineering   School of Fundamental Science and Engineering

Research Institute

  • 2020
    -
    2022

    理工学術院総合研究所   兼任研究員

Education

  •  
    -
    1990

    Waseda University   Graduate School, Division of Science and Engineering   Electrical Engineering  

  •  
    -
    1988

    Waseda University   School of Science and Engineering   Electrical Engineering  

Degree

  • Waseda University (Japan)   Ph.D degree in information & computer science

Research Experience

  • 2010
    -
    2014

    Grad. School of Fundamental Science and Engineering

  • 2007
    -
     

    Dept. Electronics and Photonic Systems, School of Fundamental Science and Engineering

  • 2003
    -
    2006

    Associate professor, Grad. School of Information, Production and Systems, Waseda university

  • 2002
    -
    2003

    Invited resarcher, the Kitakyushu Foundation for the Advancement of Industry, Science and Technology (FAIS)

  • 1999
    -
    2002

    Senior research engineer, NTT Lifestyle and environmental tech laboratories

  • 1999
    -
    2000

    Visiting researcher, University of Massachsetts

  • 1996
    -
    1999

    Resarch engineer, NTT Sytem electronics laboratories

  • 1990
    -
    1996

    Researcher, NTT LSI laboratories

▼display all

Professional Memberships

  •  
     
     

    the Information Processing Society of Japan (IPSJ)

  •  
     
     

    the Institute of Electrical and Electronics Engineers (IEEE)

  •  
     
     

    the Institute of Electronics, Information and Communication Engineers of Japan (IEICE)

  •  
     
     

    The Institute of Image Electronics Engineers of Japan

  •  
     
     

    Asia-Pacific Signal and Information Processing Association (APSIPA)

 

Research Areas

  • Computer system

  • Human interface and interaction

  • Electron device and electronic equipment

  • Perceptual information processing

Research Interests

  • Video processing, Image processing, Signal processing, Hardware design, Computer architecture, FPGA design

Papers

  • Multi-scale and Bi-path method based on Image Entropy and CNN for Fast CU Partition in VVC

    Yifan Zhai, Xiao Yan, Yibo Fan, Takeshi Ikenaga

    Sixth International Conference on Imaging, Signal Processing and Communications (ICISPC 2022)    2022.07  [Refereed]

    Authorship:Corresponding author

  • Dual-Level Structural Information Learning Neural Network for Monocular 2D Pose Estimation

    Zhiwen Zhang, Songlin Du, Dingli Luo, Takeshi Ikenaga

    Sixth International Conference on Imaging, Signal Processing and Communications (ICISPC 2022)    2022.07  [Refereed]

    Authorship:Corresponding author

  • High Temporal Resolution-Based Temporal Iterative Tracking for High Framerate and Ultra-Low Delay Dynamic Tracking System

    Tingting HU, Ryuji FUCHIKAMI, Takeshi IKENAGA

    IEICE Transactions on Information and Systems   E105.D ( 5 ) 1064 - 1074  2022.05  [Refereed]

    Authorship:Corresponding author

    DOI

  • Automatic data volley: game data acquisition with temporal-spatial filters

    Xina Cheng, Linzi Liang, Takeshi Ikenaga

    Complex & Intelligent Systems    2022.04  [Refereed]

    Authorship:Corresponding author

     View Summary

    Abstract

    Data Volley is one of the most widely used sports analysis software for professional volleyball statistics analysis. To develop the automatic data volley system, the vision-based game data acquisition is a key technology, which includes the 3D multiple objects tracking, event detection and quality evaluation. This paper combines temporal and spatial features of the game information to achieve the game data acquisition. First, the time-vary fission filter is proposed to generate the prior state distribution for tracker initialization. By using the temporal continuity of image features, the variance of team state distribution can be approximated so that the initial state of each player can be filtered out. Second, the team formation mapping with sequential motion feature is proposed to deal with the detection of event type, which represents the players’ distribution from the spatial concept and the temporal relationship. At last, to estimate the quality, the relative spatial filters are proposed by extracting and describing additional features of the subsequent condition in different situations. Experiments are conducted on game videos from the Semifinal and Final Game of 2014 Japan Inter High School Games of Mens Volleyball in Tokyo Metropolitan Gymnasium. The results show 94.1% rounds are successfully initialized, the event type detection result achieves the average accuracy of 98.72%, and the success rate of the events’ quality evaluation achieves 97.27% on average.

    DOI

    Scopus

  • Attention-guided network with inverse tone-mapping guided up-sampling for HDR imaging of dynamic scenes

    Yipeng Deng, Qin Liu, Takeshi Ikenaga

    Multimedia Tools and Applications   81 ( 9 ) 12925 - 12944  2022.04  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

  • Straight-Line Detection within 1 Millisecond per Frame for Ultra-High-Speed Industrial Automation

    Songlin Du, Ziwei Dong, Yuan Li, Takeshi Ikenaga

    IEEE Transactions on Industrial Informatics     1 - 1  2022  [Refereed]

    Authorship:Corresponding author

    DOI

  • Subpixel Displacement Measurement at 784 FPS: From Algorithm to Hardware System

    Songlin Du, Kaidong Gu, Takeshi Ikenaga

    IEEE Transactions on Instrumentation and Measurement   71   1 - 10  2022  [Refereed]

    Authorship:Corresponding author

    DOI

  • Texture and exposure awareness based refill for HDRI reconstruction of saturated and occluded areas

    Jianming Zhou, Yipeng Deng, Qin Liu, Takeshi Ikenaga

    IET Image Processing   15 ( 11 ) 2705 - 2716  2021.09  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

  • Encoding-free Incrementing Hough Transform for High Frame Rate and Ultra-low Delay Straight-line Detection

    Ziwei Dong, Tingting Hu, Ryuji Fuchikami, Takeshi Ikenaga

    2021 17th International Conference on Machine Vision and Applications (MVA)    2021.07  [Refereed]

    Authorship:Corresponding author

    DOI

  • Critically Compressed Quantized Convolution Neural Network based High Frame Rate and Ultra-Low Delay Fruit External Defects Detection

    Jihan Zhang, Dongmei Huang, Tingting Hu, Ryuji Fuchikami, Takeshi Ikenaga

    2021 17th International Conference on Machine Vision and Applications (MVA)    2021.07  [Refereed]

    Authorship:Corresponding author

    DOI

  • Multi-physical and Temporal Feature Based Self-correcting Approximation Model for Monocular 3D Volleyball Trajectory Analysis

    Jiaxu Dong, Xina Cheng, Takeshi Ikenaga

    2021 17th International Conference on Machine Vision and Applications (MVA)    2021.07  [Refereed]

    Authorship:Corresponding author

    DOI

  • Image Information Assistance Neural Network for VideoPose3D-based Monocular 3D Pose Estimation

    Hao Wang, Dingli Luo, Takeshi Ikenaga

    2021 17th International Conference on Machine Vision and Applications (MVA)    2021.07  [Refereed]

    Authorship:Corresponding author

    DOI

  • Contextual Information based Network with High-Frequency Feature Fusion for High Frame Rate and Ultra-Low Delay Small-Scale Object Detection

    Dongmei Huang, Jihan Zhang, Tingting Hu, Ryuji Fuchikami, Takeshi Ikenaga

    2021 17th International Conference on Machine Vision and Applications (MVA)    2021.07  [Refereed]

    Authorship:Corresponding author

    DOI

  • Multi-task neural network with physical constraint for real-time multi-person 3D pose estimation from monocular camera

    Dingli Luo, Songlin Du, Takeshi Ikenaga

    Multimedia Tools and Applications   80 ( 18 ) 27223 - 27244  2021.07  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

    1
    Citation
    (Scopus)
  • Selective Kernel and Motion-emphasized Loss Based Attention-guided Network for HDR Imaging of Dynamic Scenes

    Yipeng Deng, Qin Liu, Takeshi Ikenaga

    2020 25th International Conference on Pattern Recognition (ICPR)    2021.01  [Refereed]

    Authorship:Corresponding author

    DOI

  • Automatic Foreground Detection at 784 FPS for Ultra-High-Speed Human-Machine Interactions

    Songlin Du, Peikun Cai, Tingting Hu, Takeshi Ikenaga

    IEEE Transactions on Automation Science and Engineering     1 - 14  2021  [Refereed]

    Authorship:Corresponding author

    DOI

  • Highly-Parallel Hardwired Deep Convolutional Neural Network for 1-ms Dual-Hand Tracking

    Peiqi Zhang, Tingting Hu, Dingli Luo, Songlin Du, Takeshi Ikenaga

    IEEE Transactions on Circuits and Systems for Video Technology     1 - 1  2021  [Refereed]

    Authorship:Corresponding author

    DOI

  • STED-Net: Self-taught encoder-decoder network for unsupervised feature representation

    Songlin Du, Takeshi Ikenaga

    Multimedia Tools and Applications   80 ( 3 ) 4673 - 4691  2021.01  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

  • Body Part Connection, Categorization and Occlusion Based Tracking with Correction by Temporal Positions for Volleyball Spike Height Analysis

    Xina CHENG, Ziken LI, Songlin DU, Takeshi IKENAGA

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E103.A ( 12 ) 1503 - 1511  2020.12  [Refereed]

    Authorship:Corresponding author

    DOI

  • Backwards pre-analysis and flexible quantization group size adjustment based quality optimization for screen content coding

    Ziyan Zhao, Yihang Li, Qin Liu, Songlin Du, Takeshi Ikenaga

    2020 International Conference on Image, Video Processing and Artificial Intelligence    2020.11  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

  • Bottom-up check and temporal rate proportion based fast InterIMV algorithm in versatile video coding

    Yihang Li, Ziyan Zhao, Qin Liu, Songlin Du, Takeshi Ikenaga

    2020 International Conference on Image, Video Processing and Artificial Intelligence    2020.11  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

  • Local Spatio-Temporal Propagation Based Adaptive Model Generation and Update for High Frame Rate and Ultra-Low Delay Foreground Detection

    Peikun Cai, Songlin Du, Takeshi Ikenaga

    2020 IEEE 26th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)    2020.08  [Refereed]

    Authorship:Corresponding author

    DOI

  • 3D pose reconstruction with multi-perspective and spatial confidence point group for jump analysis in figure skating

    Limao Tian, Xina Cheng, Masaaki Honda, Takeshi Ikenaga

    Fifth International Workshop on Pattern Recognition    2020.06  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

  • Multi-Technology Correction Based 3D Human Pose Estimation for Jump Analysis in Figure Skating

    Limao Tian, Xina Cheng, Masaaki Honda, Takeshi Ikenaga

    The 13th Conference of the International Sports Engineering Association    2020.06  [Refereed]

    Authorship:Corresponding author

    DOI

  • Multi-scale contextual attention based HDR reconstruction of dynamic scenes

    Yipeng Deng, Qin Liu, Takeshi Ikenaga

    Twelfth International Conference on Digital Image Processing (ICDIP 2020)    2020.06  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

    4
    Citation
    (Scopus)
  • Temporally Forward Nonlinear Scale Space for High Frame Rate and Ultra-Low Delay A-KAZE Matching System

    Songlin DU, Yuan LI, Takeshi IKENAGA

    IEICE Transactions on Information and Systems   E103.D ( 6 ) 1226 - 1235  2020.06  [Refereed]

    Authorship:Corresponding author

    DOI

  • Resolution Irrelevant Encoding and Difficulty Balanced Loss Based Network Independent Supervision for Multi-Person Pose Estimation

    Haiyang Liu, Dingli Luo, Songlin Du, Takeshi Ikenaga

    2020 13th International Conference on Human System Interaction (HSI)    2020.06  [Refereed]

    Authorship:Corresponding author

    DOI

  • Hetero Complementary Networks with Hard-Wired Condensing Binarization for High Frame Rate and Ultra-Low Delay Dual-Hand Tracking

    Peiqi Zhang, Dingli Luo, Songlin Du, Takeshi Ikenaga

    2020 13th International Conference on Human System Interaction (HSI)    2020.06  [Refereed]

    DOI

  • Temporal Constraints and Block Weighting Judgement Based High Frame Rate and Ultra-Low Delay Mismatch Removal System

    Songlin DU, Zhe WANG, Takeshi IKENAGA

    IEICE Transactions on Information and Systems   E103.D ( 6 ) 1236 - 1246  2020.06  [Refereed]

    Authorship:Corresponding author

    DOI

  • Adaptive-Partial Template Update with Center-Shifting Recovery for High Frame Rate and Ultra-Low Delay Deformation Matching

    Songlin DU, Yuhao XU, Tingting HU, Takeshi IKENAGA

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E102.A ( 12 ) 1872 - 1881  2019.12  [Refereed]

    Authorship:Corresponding author

    DOI

  • 3D Global and Multi-View Local Features Combination Based Qualitative Action Recognition for Volleyball Game Analysis

    Xina CHENG, Yang LIU, Takeshi IKENAGA

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E102.A ( 12 ) 1891 - 1899  2019.12  [Refereed]

    Authorship:Corresponding author

    DOI

  • Representative Spatial Selection and Temporal Combination for 60fps Real-Time 3D Tracking of Twelve Volleyball Players on GPU

    Xina CHENG, Yiming ZHAO, Takeshi IKENAGA

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E102.A ( 12 ) 1882 - 1890  2019.12  [Refereed]

    Authorship:Corresponding author

    DOI

  • Multi-Task and Multi-Level Detection Neural Network Based Real-Time 3D Pose Estimation

    Dingli Luo, Songlin Du, Takeshi Ikenaga

    2019 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ASC)    2019.11  [Refereed]

    Authorship:Corresponding author

    DOI

  • Temporal Coherence Based Mismatch Removal for High Frame Rate and Ultra-Low Delay System

    Zhe Wang, Songlin Du, Takeshi Ikenaga

    International Workshop on Smart Info-Media Systems in Asia (SISA2019)    2019.09  [Refereed]

    Authorship:Corresponding author

  • Dense Trajectory Length and Direction Feature Based Player Receive Reaction Time Detection in Volleyball Game

    Yanchao Liu, Xina Cheng, Takeshi Ikenaga

    International Workshop on Smart Info-Media Systems in Asia (SISA2019)    2019.09  [Refereed]

    Authorship:Corresponding author

  • Body Part Categorization and Occlusion Detection Based Volleyball Players’ Spike Height Analysis

    Ziken Li, Xina Cheng, Takeshi Ikenaga

    International Workshop on Smart Info-Media Systems in Asia (SISA2019)    2019.09  [Refereed]

    Authorship:Corresponding author

  • Low-dimensional superpixel descriptor and its application in visual correspondence estimation

    Songlin Du, Takeshi Ikenaga

    Multimedia Tools and Applications   78 ( 14 ) 19457 - 19472  2019.07  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

    3
    Citation
    (Scopus)
  • Team Formation Mapping and Sequential Ball Motion State Based Event Recognition for Automatic Data Volley

    Linzi Liang, Xina Cheng, Takeshi Ikenaga

    2019 16th International Conference on Machine Vision Applications (MVA)    2019.05  [Refereed]

    Authorship:Corresponding author

    DOI

  • Temporally Forward Nonlinear Scale Space with Octave Prediction for High Frame Rate and Ultra-Low Delay A-KAZE Matching System

    Yuan Li, Songlin Du, Takeshi Ikenaga

    2019 16th International Conference on Machine Vision Applications (MVA)    2019.05  [Refereed]

    Authorship:Corresponding author

    DOI

  • End-to-End Feature Pyramid Network for Real-Time Multi-Person Pose Estimation

    Dingli Luo, Songlin Du, Takeshi Ikenaga

    2019 16th International Conference on Machine Vision Applications (MVA)    2019.05  [Refereed]

    Authorship:Corresponding author

    DOI

  • Iterative Autoencoding and Clustering for Unsupervised Feature Representation

    Songlin Du, Takeshi Ikenaga

    2019 IEEE International Symposium on Circuits and Systems (ISCAS)    2019.05  [Refereed]

    Authorship:Corresponding author

    DOI

  • Motion Statistic Based Local Homography Transformation Estimation for Mismatch Removal

    Songlin Du, Takeshi Ikenaga

    Proceedings of the 2019 3rd International Conference on Artificial Intelligence and Virtual Reality - AIVR 2019    2019  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

  • View Priority Based Threads Allocation and Binary Search Oriented Reweight for GPU Accelerated Real-Time 3D Ball Tracking

    Yilin HOU, Ziwei DENG, Xina CHENG, Takeshi IKENAGA

    IEICE Transactions on Information and Systems   E101.D ( 12 ) 3190 - 3198  2018.12  [Refereed]

    Authorship:Corresponding author

    DOI

  • Mutual-Information-Graph Regularized Sparse Transform for Unsupervised Feature Learning

    Songlin Du, Takeshi Ikenaga

    2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)    2018.11  [Refereed]

    Authorship:Corresponding author

    DOI

  • Model Selection based Parallel Prediction and Image-trajectory-independent Estimation for Real-time Ball Data Acquisition in Volleyball

    Xina Cheng, Takeshi Ikenaga

    2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)    2018.11  [Refereed]

    Authorship:Corresponding author

    DOI

  • Hierarchical Progressive Trust Model for Mismatch Removal under Both Rigid and Non-Rigid Transformations

    Songlin DU, Takeshi IKENAGA

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E101.A ( 11 ) 1786 - 1794  2018.11  [Refereed]

    Authorship:Corresponding author

    DOI

  • Court-Divisional Team Motion and Player Performance Curve Based Automatic Game Strategy Data Acquisition for Volleyball Analysis

    Xina CHENG, Takeshi IKENAGA

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E101.A ( 11 ) 1756 - 1765  2018.11  [Refereed]

    Authorship:Corresponding author

    DOI

  • Partial Descriptor Update and Isolated Point Avoidance Based Template Update for High Frame Rate and Ultra-Low Delay Deformation Matching

    Yuhao Xu, Tingting Hu, Songlin Du, Takeshi Ikenaga

    2018 24th International Conference on Pattern Recognition (ICPR)    2018.08  [Refereed]

    Authorship:Corresponding author

    DOI

  • Multi-Peak Estimation for Real-Time 3D Ping-Pong Ball Tracking with Double-Queue Based GPU Acceleration

    Ziwei DENG, Yilin HOU, Xina CHENG, Takeshi IKENAGA

    IEICE Transactions on Information and Systems   E101.D ( 5 ) 1251 - 1259  2018.05  [Refereed]

    Authorship:Corresponding author

    DOI

  • Pixel Selection and Intensity Directed Symmetry for High Frame Rate and Ultra-Low Delay Matching System

    Tingting HU, Takeshi IKENAGA

    IEICE Transactions on Information and Systems   E101.D ( 5 ) 1260 - 1269  2018.05  [Refereed]

    Authorship:Corresponding author

    DOI

  • Local Temporal Coherence for Object-Aware Keypoint Selection in Video Sequences

    Songlin Du, Takeshi Ikenaga

    Advances in Multimedia Information Processing – PCM 2017     539 - 549  2018  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

  • Vectorized Data Combination and Binary Search Oriented Reweight for CPU-GPU Based Real-Time 3D Ball Tracking

    Ziwei Deng, Yilin Hou, Xina Cheng, Takeshi Ikenaga

    Advances in Multimedia Information Processing – PCM 2017     508 - 516  2018  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

    1
    Citation
    (Scopus)
  • Motion State Detection Based Prediction Model for Body Parts Tracking of Volleyball Players

    Fanglu Xie, Xina Cheng, Takeshi Ikenaga

    Advances in Multimedia Information Processing – PCM 2017     280 - 289  2018  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

    2
    Citation
    (Scopus)
  • 3D Space Motion Dense Based Team Tactical Status Detection in Volleyball Game Analysis

    Xina Cheng, Takeshi Ikenaga

    Proceedings of the 2nd International Conference on Digital Signal Processing - ICDSP 2018    2018  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

  • 3D Ball Motion and Relative Position Feature Based Real-time Start Scene Detection for Volleyball Game Analysis on GPU

    Guixing Liang, Xina Cheng, Takeshi Ikenaga

    Proceedings of The 6th IIAE International Conference on Intelligent Systems and Image Processing 2018    2018  [Refereed]

    Authorship:Corresponding author

    DOI

  • Search-Free Gridding and Temporal Local Matching Based Observation for High Frame Rate and Ultra-Low Delay SLAM System

    Yuchen Yang, Songlin Du, Takeshi Ikenaga

    Proceedings of The 6th IIAE International Conference on Intelligent Systems and Image Processing 2018    2018  [Refereed]

    Authorship:Corresponding author

    DOI

  • Ball Motion State and Abrupt Pose Features based Player Qualitative Action Recognition for Volleyball Game Analysis

    Yang Liu, Xina Cheng, Takeshi Ikenaga

    Proceedings of The 6th IIAE International Conference on Intelligent Systems and Image Processing 2018    2018  [Refereed]

    Authorship:Corresponding author

    DOI

  • 3D Global Trajectory and Multi-view Local Motion Combined Player Action Recognition in Volleyball Analysis

    Yang Liu, Shuyi Huang, Xina Cheng, Takeshi Ikenaga

    Advances in Multimedia Information Processing – PCM 2018     134 - 144  2018  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

    1
    Citation
    (Scopus)
  • Spatial Pixels Selection and Inter-frame Combined Likelihood Based Observation for 60 fps 3D Tracking of Twelve Volleyball Players on GPU

    Yiming Zhao, Xina Cheng, Takeshi Ikenaga

    Advances in Multimedia Information Processing – PCM 2018     716 - 726  2018  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

    2
    Citation
    (Scopus)
  • Simultaneous physical and conceptual ball state estimation in volleyball game analysis

    Xina Cheng, Norikazu Ikoma, Masaaki Honda, Takeshi Ikenaga

    2017 IEEE Visual Communications and Image Processing (VCIP)    2017.12  [Refereed]

    Authorship:Corresponding author

    DOI

  • Low-dimensional superpixel descriptor for visual correspondence estimation in video

    Songlin Du, Takeshi Ikenaga

    2017 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)    2017.11  [Refereed]

    Authorship:Corresponding author

    DOI

  • Visual salience and stack extension based ghost removal for high-dynamic-range imaging

    Zijie Wang, Qin Liu, Takeshi Ikenaga

    2017 IEEE International Conference on Image Processing (ICIP)    2017.09

    Authorship:Corresponding author

    DOI

  • 3D Checking and Saturated Kernel Based GPU Accelerated Localization for ORB-SLAM

    Yuan Hu, Songlin Du, Takeshi Ikenaga

    International Workshop on Smart Info-Media Systems in Asia (SISA2017)    2017.09  [Refereed]

    Authorship:Corresponding author

  • Event state based particle filter for ball event detection in volleyball game analysis

    Xina Cheng, Norikazu Ikoma, Masaaki Honda, Takeshi Ikenaga

    2017 20th International Conference on Information Fusion (Fusion)    2017.07  [Refereed]

    Authorship:Corresponding author

    DOI

  • Minor Optical Flow Emphasis and Rough Shape Feature Extraction for Abnormal Motion Detection in Elevator Surveillance System

    Zhennan Wang, Songlin Du, Takeshi Ikenaga

    The 32nd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2017)    2017.07  [Refereed]

    Authorship:Corresponding author

  • Racket Color Judgment Based Template Selection and Ellipse Shape Likelihood for 3D Racket Tracking in Ping-Pong

    Guannan Wu, Xina Cheng, Takeshi Ikenaga

    The 32nd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2017)    2017.07  [Refereed]

    Authorship:Corresponding author

  • Multi-Feature and Balanced Search Tree Based Depth Range Definition in HEVC Inter Prediction for VLSI Implementation

    Gaoxing CHEN, Zhenyu LIU, Tetsunori KOBAYASHI, Takeshi IKENAGA

    IIEEJ Trans. on Image Electronics and Visual Computing   Vol. 5 ( No. 1 ) 1 - 9  2017.06  [Refereed]

    Authorship:Corresponding author

    CiNii

  • Mixture particle filter with block jump biomechanics constraint for volleyball players lower body parts tracking

    Fanglu Xie, Xina Cheng, Takeshi Ikenaga

    2017 Fifteenth IAPR International Conference on Machine Vision Applications (MVA)    2017.05  [Refereed]

    Authorship:Corresponding author

    DOI

  • Ball-like observation model and multi-peak distribution estimation based particle filter for 3D Ping-pong ball tracking

    Ziwei Deng, Xina Cheng, Takeshi Ikenaga

    2017 Fifteenth IAPR International Conference on Machine Vision Applications (MVA)    2017.05  [Refereed]

    Authorship:Corresponding author

    DOI

  • FPGA implementation of high frame rate and ultra-low delay vision system with local and global parallel based matching

    Tingting Hu, Takeshi Ikenaga

    2017 Fifteenth IAPR International Conference on Machine Vision Applications (MVA)    2017.05  [Refereed]

    Authorship:Corresponding author

    DOI

  • Quadrant segmentation and ring-like searching based FPGA implementation of ORB matching system for Full-HD video

    Tianmin Rao, Takeshi Ikenaga

    2017 Fifteenth IAPR International Conference on Machine Vision Applications (MVA)    2017.05  [Refereed]

    Authorship:Corresponding author

    DOI

  • Real-Time 3D Ball Tracking with CPU-GPU Acceleration Using Particle Filter with Multi-command Queues and Stepped Parallelism Iteration

    Yilin Hou, Xina Cheng, Takeshi Ikenaga

    2017 2nd International Conference on Multimedia and Image Processing (ICMIP)    2017.03  [Refereed]

    Authorship:Corresponding author

    DOI

  • Content Classification Based Reference Frame Reduction and Machine Learning Based Non-square Block Partition Skipping for Inter Prediction of Screen Content Coding

    Yawei Wang, Gaoxing Chen, Takeshi Ikenaga

    2017 2nd International Conference on Multimedia and Image Processing (ICMIP)    2017.03  [Refereed]

    Authorship:Corresponding author

    DOI

  • FPGA Implementation of High Frame Rate and Ultra-Low Delay Tracking with Local-Search Based Block Matching

    Tingting Hu, Hong Wu, Takeshi Ikenaga

    2017 International Conference on Machine Vision and Information Technology (CMVIT)    2017.02  [Refereed]

    Authorship:Corresponding author

    DOI

  • Multi-View 3D Ball Tracking with Abrupt Motion Adaptive System Model, Anti-Occlusion Observation and Spatial Density Based Recovery in Sports Analysis

    Xina CHENG, Norikazu IKOMA, Masaaki HONDA, Takeshi IKENAGA

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E100.A ( 5 ) 1215 - 1225  2017  [Refereed]

    Authorship:Corresponding author

     View Summary

    <p>Significant challenges in ball tracking of sports analysis by computer vision technology are: 1) accuracy of estimated 3D ball trajectory under difficult conditions; 2) external forces added by players lead to irregular motions of the ball; 3) unpredictable situations in the real game, i.e. the ball occluded by players and other objects, complex background and changing lighting condition. With the goal of multi-view 3D ball tracking, this paper proposes an abrupt motion adaptive system model, an anti-occlusion observation model, and a spatial density-based automatic recovery based on particle filter. The system model combines two different system noises that cover the motion of the ball both in general situation and situation subject to abrupt motion caused by external force. Combination ratio of these two noises and number of particles are adaptive to the estimated motion by weight distribution of particles. The anti-occlusion observation model evaluates image feature of each camera and eliminates influence of the camera with less confidence. The spatial density, which is calculated based on 3D ball candidates filtered out by spatial homographic relationship between cameras, is proposed for generating new set of particles to recover the tracking when tracking failure is detected. Experimental results based on HDTV video sequences (2014 Inter High School Men's Volleyball Games, Japan), which were captured by four cameras located at each corner of the court, show that the success rate achieved by the proposals of 3D ball tracking is 99.42%.</p>

    DOI CiNii

  • Ball State Based Parallel Ball Tracking and Event Detection for Volleyball Game Analysis

    Xina CHENG, Norikazu IKOMA, Masaaki HONDA, Takeshi IKENAGA

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E100.A ( 11 ) 2285 - 2294  2017  [Refereed]

    Authorship:Corresponding author

     View Summary

    <p>The ball state tracking and detection technology plays a significant role in volleyball game analysis, whose performance is limited due to the challenges include: 1) the inaccurate ball trajectory; 2) multiple numbers of the ball event category; 3) the large intra-class difference of one event. With the goal of broadcasting supporting for volleyball games which requires a real time system, this paper proposes a ball state based parallel ball tracking and event detection method based on a sequential estimation method such as particle filter. This method employs a parallel process of the 3D ball tracking and the event detection so that it is friendly for real time system implementation. The 3D ball tracking process uses the same models with the past work [8]. For event detection process, a ball event change estimation based multiple system model, a past trajectory referred hit point likelihood and a court-line distance feature based event type detection are proposed. First, the multiple system model transits the ball event state, which consists the event starting time and the event type, through three models dealing with different ball motion situations in the volleyball game, such as the motion keeping and changing. The mixture of these models is decided by estimation of the ball event change estimation. Secondly, the past trajectory referred hit point likelihood avoids the processing time delay between the ball tracking and the event detection process by evaluating the probability of the ball being hit at certain time without using future ball trajectories. Third, the feature of the distance between the ball and the specific court line are extracted to detect the ball event type. Experimental results based on multi-view HDTV video sequences (2014 Inter High School Men's Volleyball Games, Japan), which contains 606 events in total, show that the detection rate reaches 88.61% while the success rate of 3D ball tracking keeps more than 99%.</p>

    DOI CiNii

  • AIGIF: Adaptively Integrated Gradient and Intensity Feature for Robust and Low-Dimensional Description of Local Keypoint

    Songlin DU, Takeshi IKENAGA

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E100.A ( 11 ) 2275 - 2284  2017  [Refereed]

    Authorship:Corresponding author

     View Summary

    <p>Establishing local visual correspondences between images taken under different conditions is an important and challenging task in computer vision. A common solution for this task is detecting keypoints in images and then matching the keypoints with a feature descriptor. This paper proposes a robust and low-dimensional local feature descriptor named Adaptively Integrated Gradient and Intensity Feature (AIGIF). The proposed AIGIF descriptor partitions the support region surrounding each keypoint into sub-regions, and classifies the sub-regions into two categories: edge-dominated ones and smoothness-dominated ones. For edge-dominated sub-regions, gradient magnitude and orientation features are extracted; for smoothness-dominated sub-regions, intensity feature is extracted. The gradient and intensity features are integrated to generate the descriptor. Experiments on image matching were conducted to evaluate performances of the proposed AIGIF. Compared with SIFT, the proposed AIGIF achieves 75% reduction of feature dimension (from 128 bytes to 32 bytes); compared with SURF, the proposed AIGIF achieves 87.5% reduction of feature dimension (from 256 bytes to 32 bytes); compared with the state-of-the-art ORB descriptor which has the same feature dimension with AIGIF, AIGIF achieves higher accuracy and robustness. In summary, the AIGIF combines the advantages of gradient feature and intensity feature, and achieves relatively high accuracy and robustness with low feature dimension.</p>

    DOI CiNii

  • Robust Ghost-Free High-Dynamic-Range Imaging by Visual Salience Based Bilateral Motion Detection and Stack Extension Based Exposure Fusion

    Zijie WANG, Qin LIU, Takeshi IKENAGA

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E100.A ( 11 ) 2266 - 2274  2017  [Refereed]

    Authorship:Corresponding author

     View Summary

    <p>High-dynamic-range imaging (HDRI) technologies aim to extend the dynamic range of luminance against the limitation of camera sensors. Irradiance information of a scene can be reconstructed by fusing multiple low-dynamic-range (LDR) images with different exposures. The key issue is removing ghost artifacts caused by motion of moving objects and handheld cameras. This paper proposes a robust ghost-free HDRI algorithm by visual salience based bilateral motion detection and stack extension based exposure fusion. For ghost areas detection, visual salience is introduced to measure the differences between multiple images; bilateral motion detection is employed to improve the accuracy of labeling motion areas. For exposure fusion, the proposed algorithm reduces the discontinuity of brightness by stack extension and rejects the information of ghost areas to avoid artifacts via fusion masks. Experiment results show that the proposed algorithm can remove ghost artifacts accurately for both static and handheld cameras, remain robust to scenes with complex motion and keep low complexity over recent advances including rank minimization based method and patch based method by 63.6% and 20.4% time savings averagely.</p>

    DOI CiNii

  • Player Feature Based Multi-Likelihood and Spatial Relationship Based Multi-View Elimination with Least Square Fitting Prediction for Volleyball Players Tracking in 3D Space

    Shuyi Huang, Xizhou Zhuang, Xina Cheng, Norikazu Ikoma, Masaaki Honda, Takeshi Ikenaga

    IIEEJ Trans. on Image Electronics and Visual Computing   Vol. 4 ( No. 2 ) 145 - 155  2016.12  [Refereed]

    Authorship:Corresponding author

    CiNii

  • Multi-feature based fast depth decision in HEVC inter prediction for VLSI implementation

    Gaoxing Chen, Zhenyu Liu, Tetsunori Kobayashi, Takeshi Ikenaga

    2016 9th International Congress on Image and Signal Processing, BioMedical Engineering and Informatics (CISP-BMEI)    2016.10  [Refereed]

    Authorship:Corresponding author

    DOI

  • PU Partition Based Mode and Depth Skipping for Inter Prediction of Spatial SHVC

    Guojing Zhu, Gaoxing Chen, Pei Liu, Takeshi Ikenaga

    International Workshop on Smart Info-Media Systems in Asia (SISA2016)    2016.09  [Refereed]

    Authorship:Corresponding author

  • センシング技術を用いたスポーツ情報解析

    誉田雅彰, 池永 剛

    情報処理   Vol. 57 ( No. 8 ) 738 - 743  2016.08  [Invited]

    Authorship:Corresponding author

  • Motion Prejudgment Dependent Mixture System Noise in System Model for Tennis Ball 3D Position Tracking by Particle Filter

    Yuan Wang, Xina Cheng, Norikazu Ikoma, Masaaki Honda, Takeshi Ikenaga

    2016 Joint 8th International Conference on Soft Computing and Intelligent Systems (SCIS) and 17th International Symposium on Advanced Intelligent Systems (ISIS)    2016.08  [Refereed]

    Authorship:Corresponding author

    DOI

  • Fast depth decision for HEVC inter prediction based on spatial and temporal correlation

    Gaoxing Chen, Zhenyu Liu, Takeshi Ikenaga

    SPIE Proceedings    2016.07  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

  • Relative Position Feature based Dense Trajectories with Density Adapted Noise Reduction for Tennis Player Action Recognition

    Zihan Ma, Shuyi Huang, Masaaki Honda, Takeshi Ikenaga

    The 31st International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2016)    2016.07  [Refereed]

    Authorship:Corresponding author

  • Visual Salience based Exposure Fusion Algorithm for Ghost Removal in High-dynamic-range Imaging

    Zijie Wang, Qin Liu, Tongwei Ren, Bin Luo, Takeshi Ikenaga

    The 31st International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2016)    2016.07  [Refereed]

    Authorship:Corresponding author

  • Upper Coding Unit Depth Rate Distortion Cost Comparison Based Fast Intra and Interlayer Inter Prediction Mode Selection for Enhancement Layer in All Intra Spatial SHVC

    Pei Liu, Guojing Zhu, Gaoxing Chen, Takeshi Ikenaga

    The 31st International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2016)    2016.07  [Refereed]

    Authorship:Corresponding author

  • 次世代の映像システムの実現を目指した国際的な研究教育の取り組み

    池永 剛

    画像電子学会誌(スキャニング)   Vol. 45 ( No. 2 ) 236 - 238  2016.03  [Invited]

    Authorship:Lead author

    CiNii

  • Anti-occlusion observation model and automatic recovery for multi-view ball tracking in sports analysis

    Xina Cheng, Masaaki Honda, Norikazu Ikoma, Takeshi Ikenaga

    2016 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)    2016.03  [Refereed]

    Authorship:Corresponding author

    DOI

  • Particle filter with least square fitting prediction and spatial relationship based multi-view elimination for 3D Volleyball players tracking

    Shuyi Huang, Xizhou Zhuang, Norikazu Ikoma, Masaaki Honda, Takeshi Ikenaga

    2016 IEEE 12th International Colloquium on Signal Processing &amp; Its Applications (CSPA)    2016.03  [Refereed]

    Authorship:Corresponding author

    DOI

  • Content based mode and depth skipping with Sharp and Directional Edges for intra prediction in Screen Content Coding

    Yutaro Kawakami, Gaoxing Chen, Takeshi Ikenaga

    2016 IEEE 12th International Colloquium on Signal Processing &amp; Its Applications (CSPA)    2016.03  [Refereed]

    Authorship:Corresponding author

    DOI

  • Fast enhancement layer intra coding based on inter-channel correlations and TU depth correlation in SHVC

    Guojing Zhu, Gaoxing Chen, Takeshi Ikenaga

    2016 IEEE 12th International Colloquium on Signal Processing &amp; Its Applications (CSPA)    2016.03  [Refereed]

    Authorship:Corresponding author

    DOI

  • Action detection of volleyball using features based on clustering of body trajectories

    Eijiro Kubota, Takahiro Suzuki, Masaaki Honda, Takeshi Ikenaga

    Journal of the Institute of Image Electronics Engineers of Japan   45 ( 3 ) 373 - 381  2016  [Refereed]

    Authorship:Corresponding author

     View Summary

    For creating new tactics of sports like volleyball, the analysis of player motion in real games becomes more and more important. However, since motion data needed for the analysis is captured by human observation currently, an automatic capturing system from video camera is highly expected to gather many useful data easily. This paper proposes an action detection algorithm of volleyball players using motion features based on clustering and aggregation of body trajectories. Since the body trajectories of arms and legs are similar, the clustering utilizes shape, location and density of their trajectories. Furthermore, the clustered feature values are aggregated by means of their mean and variance. Experimental results by using the motion detection system based on the proposed algorithm show that it averagely attains 0.9539 AUC of the ROC curve for the detection of four basic motions (block, receive, spike and toss) from the volleyball game video captured by high-definition cameras. This is 0.014775 higher than conventional methods.

    DOI

    Scopus

    3
    Citation
    (Scopus)
  • Hardware Oriented Enhanced Category Determination Based on CTU Boundary Deblocking Strength Prediction for SAO in HEVC Encoder

    Gaoxing CHEN, Zhenyu PEI, Zhenyu LIU, Takeshi IKENAGA

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E99.A ( 4 ) 788 - 797  2016  [Refereed]

    Authorship:Corresponding author

     View Summary

    High efficiency video coding (HEVC) is a video compression standard that outperforms the predecessor H.264/AVC by doubling the compression efficiency. To enhance the coding accuracy, HEVC adopts sample adaptive offset (SAO), which reduces the distortion of reconstructed pixels using classification based non-linear filtering. In the traditional coding tree unit (CTU) grain based VLSI encoder implementation, during the pixel classification stage, SAO cannot use the raw samples in the boundary of the current CTU because these pixels have not been processed by deblocking filter (DF). This paper proposes a hardware-oriented category determination algorithm based on estimating the deblocking strengths on CTU boundaries and selectively adopting the promising samples in these areas during SAO classification. Compared with HEVC test mode (HM11.0), experimental results indicate that the proposed method achieves an average 0.13%, 0.14%, and 0.12% BD-bitrate reduction (equivalent to 0.0055dB, 0.0058dB, and 0.0097dB increases in PSNR) in CTU sizes of 64 × 64, 32 × 32, and 16 × 16, respectively.

    DOI CiNii

  • Full-HD 60fps FPGA Implementation of Spatio-Temporal Keypoint Extraction Based on Gradient Histogram and Parallelization of Keypoint Connectivity

    Takahiro SUZUKI, Takeshi IKENAGA

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E99.A ( 11 ) 1937 - 1946  2016  [Refereed]

    Authorship:Corresponding author

     View Summary

    <p>Recently, cloud systems have started to be utilized for services which analyze user's data in the field of computer vision. In these services, keypoints are extracted from images or videos, and the data is identified by machine learning with a large database in the cloud. To reduce the number of keypoints which are sent to the cloud, Keypoints of Interest (KOI) extraction has been proposed. However, since its computational complexity is large, hardware implementation is required for real-time processing. Moreover, the hardware resource must be low because it is embedded in devices of users. This paper proposes a hardware-friendly KOI algorithm with low amount of computations and its real-time hardware implementation based on dual threshold keypoint detection by gradient histogram and parallelization of connectivity of adjacent keypoint-utilizing register counters. The algorithm utilizes dual-histogram based detection and keypoint-matching based calculation of motion information and dense-clustering based keypoint smoothing. The hardware architecture is composed of a detection module utilizing descriptor, and grid-region-parallelization based density clustering. Finally, the evaluation results of hardware implementation show that the implemented hardware achieves Full-HD (1920x1080)-60 fps spatio-temporal keypoint extraction. Further, it is 47 times faster than low complexity keypoint extraction on software and 12 times faster than spatio-temporal keypoint extraction on software, and the hardware resources are almost the same as SIFT hardware implementation, maintaining accuracy.</p>

    DOI CiNii

  • Ghost-free high dynamic range imaging via moving objects detection and extension

    Benkang Zhang, Qin Liu, Takeshi Ikenaga

    2015 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA)    2015.12  [Refereed]

    DOI

  • Deblocking strength prediction based CTU-level SAO category determination in HEVC encoder

    Gaoxing Chen, Zhenyu Pei, Zhenyu Liu, Takeshi Ikenaga

    2015 Visual Communications and Image Processing (VCIP)    2015.12  [Refereed]

    Authorship:Corresponding author

    DOI

  • Edge Detection and Frame Difference Based Exposure Fusion Algorithm for Ghost Removal in Motion-Intense High Dynamic Range Video Generation

    Qin Liu, Hao Wang, Takeshi Ikenaga

    The 1st International Conference on Advanced Imaging (ICAI 2015)    2015.06  [Refereed]

    Authorship:Corresponding author

  • Feature Detection for Gait Recognition Based on Dual Histogram of Relative Optical Flow

    Chenming DING, Takeshi IKENAGA

    IIEEJ Trans. on Image Electronics and Visual Computing   Vol. 3 ( No. 1 ) 44 - 53  2015.06  [Refereed]

    Authorship:Corresponding author

    CiNii

  • Temporal Information based Adaptive Coding Unit Depth Decision for Low-Complexity HEVC Inter Prediction

    Jiawang Gu, Gaoxing Chen, Zhenyu Liu, Takeshi Ikenaga

    SOFT九州支部 中国・四国支部合同支部大会    2015.03

    Authorship:Corresponding author

  • Particle Filter with Ball Size Adaptive Tracking Window and Ball Feature Likelihood Model for Ball’s 3D Position Tracking in Volleyball Analysis

    Xina Cheng, Xizhou Zhuang, Yuan Wang, Masaaki Honda, Takeshi Ikenaga

    Lecture Notes in Computer Science     203 - 211  2015  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

    5
    Citation
    (Scopus)
  • Motion Vector and Players’ Features Based Particle Filter for Volleyball Players Tracking in 3D Space

    Xizhou Zhuang, Xina Cheng, Shuyi Huang, Masaaki Honda, Takeshi Ikenaga

    Lecture Notes in Computer Science     393 - 401  2015  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

    3
    Citation
    (Scopus)
  • Player tracking using prediction after intersection based particle filter for volleyball match video

    Xina Cheng, Yuhi Shiina, Xizhou Zhuang, Takeshi Ikenaga

    Signal and Information Processing Association Annual Summit and Conference (APSIPA), 2014 Asia-Pacific    2014.12  [Refereed]

    Authorship:Corresponding author

    DOI

  • Hardware oriented category pre-determination algorithm for SAO in HEVC

    Gaoxing Chen, Zhenyu Pei, Zhenyu Liu, Takeshi Ikenaga

    Signal and Information Processing Association Annual Summit and Conference (APSIPA), 2014 Asia-Pacific    2014.12  [Refereed]

    Authorship:Corresponding author

    DOI

  • Motion area based exposure fusion algorithm for ghost removal in high dynamic range video generation

    Shu-Yi Huang, Qin Liu, Hao Wang, Takeshi Ikenaga

    Signal and Information Processing Association Annual Summit and Conference (APSIPA), 2014 Asia-Pacific    2014.12  [Refereed]

    Authorship:Corresponding author

    DOI

  • Spatio-Temporal Feature and MRF Based Keypoint of Interest for Cloud Video Recognition

    Takahiro Suzuki, Takeshi Ikenaga

    IIEEJ Trans. on Image Electronics and Visual Computing   Vol. 2 ( No. 2 ) 150 - 158  2014.12  [Refereed]

    Authorship:Corresponding author

  • Linear adaptive search range model for uni-prediction and motion analysis for bi-prediction in HEVC

    Longshan Du, Zhenyu Liu, Takeshi Ikenaga, Dongsheng Wang

    2014 IEEE International Conference on Image Processing (ICIP)    2014.10  [Refereed]

    Authorship:Corresponding author

    DOI

  • Low complexity SAO in HEVC base on class combination, pre-decision and merge separation

    Gaoxing Chen, Zhenyu Pei, Zhenyu Liu, Takeshi Ikenaga

    2014 19th International Conference on Digital Signal Processing    2014.08  [Refereed]

    Authorship:Corresponding author

    DOI

  • Car tracking in rear view based on bicycle specific motions in vertical vibration and angular variation via prediction and likelihood models with particle filter for rear confirmation support

    Norikazu Ikoma, Yohei Mikami, Takeshi Ikenaga

    2014 World Automation Congress (WAC)    2014.08  [Refereed]

    Authorship:Corresponding author

    DOI

  • Smart feature detection device for cloud based video recognition system

    Takeshi Ikenaga, Takahiro Suzuki

    Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test    2014.04  [Refereed]

    Authorship:Corresponding author

    DOI

  • Keypoint of Interest Based on Spatio-temporal Feature Considering Mutual Dependency and Camera Motion

    Takahiro Suzuki, Takeshi Ikenaga

    The Sixth International Conferences on Advances in Multimedia (MMEDIA 2014)    2014.02  [Refereed]

    Authorship:Corresponding author

  • A Mode Mapping and Optimized MV Conjunction Based H.264/SVC to H.264/AVC Transcoder with Medium-Grain Quality Scalability for Videoconferencing

    Lei SUN, Zhenyu LIU, Takeshi IKENAGA

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E97.A ( 2 ) 501 - 509  2014  [Refereed]

    Authorship:Corresponding author

     View Summary

    Scalable Video Coding (SVC) is an extension of H.264/AVC, aiming to provide the ability to adapt to heterogeneous networks or requirements. It offers great flexibility for bitstream adaptation in multi-point applications such as videoconferencing. However, transcoding between SVC and AVC is necessary due to the existence of legacy AVC-based systems. The straightforward re-encoding method requires great computational cost, and delay-sensitive applications like videoconferencing require much faster transcoding scheme. This paper proposes a 3-stage fast SVC-to-AVC transcoder with medium-grain quality scalability (MGS) for videoconferencing applications. Hierarchical-P structured SVC bitstream is transcoded into IPPP structured AVC bitstream with multiple reference frames. In the first stage, mode decision is accelerated by proposed SVC-to-AVC mode mapping scheme. In the second stage, INTER motion estimation is accelerated by an optimized motion vector (MV) conjunction method to predict the MV with a reduced search range. In the last stage, hadamard-based all zero block (AZB) detection is utilized for early termination. Simulation results show that proposed transcoder achieves very similar coding efficiency to the optimal result, but with averagely 89.6% computational time saving.

    DOI CiNii

  • Fast mode and depth decision HEVC intra prediction based on edge detection and partitioning reconfiguration

    Gaoxing Chen, Lei Sun, Zhenyu Liu, Takeshi Ikenaga

    2013 International Symposium on Intelligent Signal Processing and Communication Systems    2013.11  [Refereed]

    Authorship:Corresponding author

    DOI

  • Keypoints of interest based on spatio-temporal feature and MRF for cloud recognition system

    Takahiro Suzuki, Takeshi Ikenaga

    2013 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference     1 - 4  2013.10  [Refereed]

    Authorship:Corresponding author

    DOI

  • Fast intra prediction for HEVC based on pixel gradient statistics and mode refinement

    Gaoxing Chen, Zhenyu Pei, Lei Sun, Zhenyu Liu, Takeshi Ikenaga

    2013 IEEE China Summit and International Conference on Signal and Information Processing    2013.07  [Refereed]

    Authorship:Corresponding author

    DOI

  • Hand Gesture Interface Using Fourier Descriptor Filter and SVM

    Lei Gu, Takeshi Ikenaga

    The 28th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2013)    2013.06  [Refereed]

    Authorship:Corresponding author

  • Local-threshold 2D-tophat Cell Segmentation for the Two-photon Confocal Microscope Image

    Xiaoyang Yuan, Lei Gu, Takeshi Ikenaga

    IAPR International COnference on Machine Vision and Applications (MVA 2013)    2013.05  [Refereed]

    Authorship:Corresponding author

  • Fast HEVC intra mode decision using matching edge detector and kernel density estimation alike histogram generation

    Guang Chen, Zhenyu Liu, Takeshi Ikenaga, Dongsheng Wang

    2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)    2013.05  [Refereed]

    Authorship:Corresponding author

    DOI

  • A mode-mapping and optimized MV conjunction based MGS-scalable SVC to AVC IPPP transcoder

    Lei Sun, Zhenyu Liu, Takeshi Ikenaga

    2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)    2013.05  [Refereed]

    Authorship:Corresponding author

    DOI

  • A Low-Complexity Quantization-Domain H.264/SVC to H.264/AVC Transcoder with Medium-Grain Quality Scalability

    Lei Sun, Zhenyu Liu, Takeshi Ikenaga

    Lecture Notes in Computer Science     336 - 346  2013  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

  • Low Complexity Keypoint Extraction Based on SIFT Descriptor and Its Hardware Implementation for Full-HD 60fps Video

    Takahiro SUZUKI, Takeshi IKENAGA

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E96.A ( 6 ) 1376 - 1383  2013  [Refereed]

    Authorship:Corresponding author

     View Summary

    Scale-Invariant Feature Transform (SIFT) has lately attracted attention in computer vision as a robust keypoint detection algorithm which is invariant for scale, rotation and illumination changes. However, its computational complexity is too high to apply in practical real-time applications. This paper proposes a low complexity keypoint extraction algorithm based on SIFT descriptor and utilization of the database, and its real-time hardware implementation for Full-HD resolution video. The proposed algorithm computes SIFT descriptor on the keypoint obtained by corner detection and selects a scale from the database. It is possible to parallelize the keypoint detection and descriptor computation modules in the hardware. These modules do not depend on each other in the proposed algorithm in contrast with SIFT that computes a scale. The processing time of descriptor computation in this hardware is independent of the number of keypoints because its descriptor generation is pipelining structure of pixel. Evaluation results show that the proposed algorithm on software is 12 times faster than SIFT. Moreover, the proposed hardware on FPGA is 427 times faster than SIFT and 61 times faster than the proposed algorithm on software. The proposed hardware performs keypoint extraction and matching at 60fps for Full-HD video.

    DOI CiNii

  • Content-Aware Write Reduction Mechanism of 3D Stacked Phase-Change RAM Based Frame Store in H.264 Video Codec System

    Sanchuan GUO, Zhenyu LIU, Guohong LI, Takeshi IKENAGA, Dongsheng WANG

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E96.A ( 6 ) 1273 - 1282  2013  [Refereed]

     View Summary

    H.264 video codec system requires big capacity and high bandwidth of Frame Store (FS) for buffering reference frames. The up-to-date three dimensional (3D) stacked Phase change Random Access Memory (PRAM) is the promising approach for on-chip caching the reference signals, as 3D stacking offers high memory bandwidth, while PRAM possesses the advantages in terms of high density and low leakage power. However, the write endurance problem, that is a PRAM cell can only tolerant limited number of write operations, becomes the main barrier in practical applications. This paper studies the wear reduction techniques of PRAM based FS in H.264 codec system. On the basis of rate-distortion theory, the content oriented selective writing mechanisms are proposed to reduce bit updates in the reference frame buffers. With the proposed control parameter a, our methods make the quantitative trade off between the quality degradation and the PRAM lifetime prolongation. Specifically, taking a in the range of [0.2,2], experimental results demonstrate that, our methods averagely save 29.9-35.5% bit-wise write operations and reduce 52-57% power, at the cost of 12.95-20.57% BDBR bit-rate increase accordingly.

    DOI CiNii

  • A Drift-Constrained Frequency-Domain Ultra-Low-Delay H.264/SVC to H.264/AVC Transcoder with Medium-Grain Quality Scalability for Videoconferencing

    Lei SUN, Zhenyu LIU, Takeshi IKENAGA

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E96.A ( 6 ) 1253 - 1263  2013  [Refereed]

    Authorship:Corresponding author

     View Summary

    Scalable Video Coding (SVC) is an extension of H.264/AVC, aiming to provide the ability to adapt to heterogeneous networks or requirements. It offers great flexibility for bitstream adaptation in multi-point applications such as videoconferencing. However, transcoding between SVC and AVC is necessary due to the existence of legacy AVC-based systems. The straightforward re-encoding method requires great computational cost, and delay-sensitive applications like videoconferencing require much faster transcoding scheme. This paper proposes an ultra-low-delay SVC-to-AVC MGS (Medium-Grain quality Scalability) transcoder for videoconferencing applications. Transcoding is performed in pure frequency domain with partial decoding/encoding in order to achieve significant speed-up. Three fast transcoding methods in frequency domain are proposed for macroblocks with different coding modes in non-KEY pictures. KEY pictures are transcoded by reusing the base layer motion data, and error propagation is constrained between KEY pictures. Simulation results show that proposed transcoder achieves averagely 38.5 times speed-up compared with the re-encoding method, while introducing merely 0.71dB BDPSNR coding quality loss for videoconferencing sequences as compared with the re-encoding algorithm.

    DOI CiNii

  • Low-Complexity Hybrid-Domain H.264/SVC to H.264/AVC Spatial Transcoding with Drift Compensation for Videoconferencing

    Lei SUN, Zhenyu LIU, Takeshi IKENAGA

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E96.A ( 11 ) 2142 - 2153  2013  [Refereed]

    Authorship:Corresponding author

     View Summary

    As an extension of H.264/AVC, Scalable Video Coding (SVC) provides the ability to adapt to heterogeneous networks and user-end requirements, which offers great scalability in multi-point applications such as videoconferencing. However, transcoding between SVC and AVC becomes necessary due to the existence of legacy AVC-based systems. The straightforward full re-encoding method requires great computational cost, and the fast SVC-to-AVC spatial transcoding techniques have not been thoroughly investigated yet. This paper proposes a low-complexity hybrid-domain SVC-to-AVC spatial transcoder with drift compensation, which provides even better coding efficiency than the full re-encoding method. The macroblocks (MBs) of input SVC bitstream are divided into two types, and each type is suitable for pixel- or transform-domain processing respectively. In the pixel-domain transcoding, a fast re-encoding method is proposed based on mode mapping and motion vector (MV) refinement. In the transform-domain transcoding, the quantized transform coefficients together with other motion data are reused directly to avoid re-quantization loss. The drift problem caused by proposed transcoder is solved by compensation techniques for I frame and P frame respectively. Simulation results show that proposed transcoder achieves averagely 96.4% time reduction compared with the full re-encoding method, and outperforms the reference methods in coding efficiency.

    DOI CiNii

  • Hand gesture interface based on improved adaptive hand area detection and contour signature

    Lei Gu, Xiaoyang Yuan, Takeshi Ikenaga

    2012 International Symposium on Intelligent Signal Processing and Communications Systems    2012.11  [Refereed]

    Authorship:Corresponding author

    DOI

  • Subjective Assessment of Reconstruction of Super Resolution Images

    Seiichi Gohshi, Hiroyuki Sekiguchi, Yoshiyasu Shimizu, Takeshi Ikenaga

    International Conference on Signal and Image Processing (ICSIP 2012)    2012.09  [Refereed]

    Authorship:Corresponding author

  • Lagrangian Multiplier Optimization Using Markov Chain Based Rate and Piecewise Approximated Distortion Models

    Zhenyu Liu, Dongsheng Wang, Junwei Zhou, Takeshi Ikenaga

    2012 Data Compression Conference    2012.04  [Refereed]

    Authorship:Last author

    DOI

  • Corner Detection Based Low Complexity SIFT Algorithm for Real-time Keypoints Matching

    Takahiro Suzuki, Takeshi Ikenaga

    RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2012)    2012.03  [Refereed]

    Authorship:Corresponding author

  • Lagrangian multiplier optimization using correlations in residues

    Zhenyu Liu, Dongsheng Wang, Junwei Zhou, Takeshi Ikenaga

    2012 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)    2012.03  [Refereed]

    Authorship:Corresponding author

    DOI

  • Adaptive-Motion-Detector-Based Skip-Mode Predecision in Motion Estimation for Video Surveillance

    Jia Su, Takeshi Ikenaga

    Journal of Signal Processing   16 ( 1 ) 67 - 78  2012  [Refereed]

    Authorship:Corresponding author

    DOI CiNii

  • Low-Complexity Coarse-Level Mode-Mapping Based H.264/AVC to H.264/SVC Spatial Transcoding for Video Conferencing

    Lei SUN, Jie LENG, Jia SU, Yiqing HUANG, Hiroomi MOTOHASHI, Takeshi IKENAGA

    IEICE Transactions on Information and Systems   E95.D ( 5 ) 1313 - 1323  2012  [Refereed]

    Authorship:Corresponding author

     View Summary

    Scalable Video Coding (SVC) was standardized as an extension of H.264/AVC with the intention to provide flexible adaptation to heterogeneous networks and different end-user requirements, which provides great scalability in multi-point applications such as video conferencing. However, due to the existence of H.264/AVC-based systems, transcoding between AVC and SVC becomes necessary. Most existing works focus on temporal transcoding, quality transcoding or SVC-to-AVC spatial transcoding while the straightforward re-encoding method requires high computational cost. This paper proposes a low-complexity AVC-to-SVC spatial transcoder based on coarse-level mode mapping for video conferencing scenes. First, to omit unnecessary motion estimations (ME) for layers with reduced resolution, an ME skipping scheme based on AVC mode distribution is proposed with an adaptive search range. Then a probability-profile based scheme is proposed for further mode skipping. After that 3 coarse-level mode-mapping methods are presented for fast mode decision and the adaptive usage of the 3 methods is discussed. Finally, motion vector (MV) refinement is introduced for further lower-layer time reduction. As for the top layer, direct encapsulation is proposed to preserve better quality and another scheme involving inter-layer predictions is also provided for bandwidth-crucial applications. Simulation results show that proposed transcoder achieves up to 92.6% time reduction without significant coding efficiency loss compared to re-encoding method.

    DOI CiNii

  • A Low Complexity ALF based on Inter-Channel Correlation between Chroma and Luma in HEVC

    Wei-Jing Chen, Lei Sun, Lei Gu, Zhen-yu Liu, Takeshi Ikenaga

    Signal and Image Processing    2012  [Refereed]

    Authorship:Corresponding author

    DOI

  • A Pixel-domain Mode-mapping based SVC-to-AVC Transcoder with Coarse Grain Quality Scalability

    Lei Sun, Zhenyu Liu, Takeshi Ikenaga

    2012 21ST INTERNATIONAL CONFERENCE ON PATTERN RECOGNITION (ICPR 2012)     939 - 942  2012  [Refereed]

    Authorship:Corresponding author

     View Summary

    As an extension of AVC, SVC provides the ability to adapt to heterogeneous environments. However, transcoding between SVC and AVC becomes necessary due to the existence of legacy AVC-based systems. This paper proposes a low-complexity SVC-to-AVC CGS transcoder in the pixel domain, which achieves approximately the same coding efficiency as the MI reencoding method. The output AVC bitstream modes are deduced by the proposed mode-mapping strategy. Different from previous works which simply use full search for SVC modes, the SVC modes are also examined and refined to generate suitable AVC modes in the proposed method. Simulation results show that proposed transcoder achieves 10 times speed-up with only 2% BDBR increase and 0.08 dB BDPSNR loss, compared with the full re-encoding method.

  • A Videoconferencing-Oriented Hybrid-Domain H.264/SVC to H.264/AVC Spatial Transcoder

    Lei Sun, Zhenyu Liu, Takeshi Ikenaga

    Advances in Multimedia Information Processing – PCM 2012     129 - 141  2012  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

  • Recovery Method based Particle Filter for Object Tracking in Complex Environment

    Yuhi Shiina, Takeshi Ikenaga

    2012 ASIA-PACIFIC SIGNAL AND INFORMATION PROCESSING ASSOCIATION ANNUAL SUMMIT AND CONFERENCE (APSIPA ASC)    2012  [Refereed]

    Authorship:Corresponding author

     View Summary

    Object tracking is a key process for various image recognition applications, and many algorithms have been proposed in this field. Especially, particle filter has possibility for tracking objects steadily thanks to prediction using many particles. However, other objects that are a similar color or shape with a tracking object hijack a tracking region if there were such objects nearby the tracking object. It is a critical problem. This paper proposes a recovery method based particle filter by focusing a feature regions attached to an object. This proposal tracks both a feature region and an object including the region at once. This proposal utilizes a recovery method that pulls a tracking region back to an appropriate position using the prior frame's distance and angle between the two tracking regions when the tracking region is hijacked by other objects. Some video sequences including complex environment have been tested for evaluating this proposal. The experimental results show that this proposal can track a specified person in the sequences, while conventional method cannot track the person. This result represents that recovery method of proposal effectively works when other objects hijack the tracking region.

  • Real-Time Both Hands Tracking Using CAMshift with Motion Mask and Probability Reduction by Motion Prediction

    Ryosuke Araki, Seiichi Gohshi, Takeshi Ikenaga

    2012 ASIA-PACIFIC SIGNAL AND INFORMATION PROCESSING ASSOCIATION ANNUAL SUMMIT AND CONFERENCE (APSIPA ASC)    2012  [Refereed]

    Authorship:Corresponding author

     View Summary

    Hand gesture interfaces are more intuitive and convenient than traditional interfaces. They are the most important parts in the relationship between users and devices. Hand tracking for hand gesture interfaces is an active area of research in image processing. However, previous works have limits such as requiring the use of multiple camera or sensor, working only with single color background, etc. This paper proposes a real-time both hands tracking algorithm based on "CAMshift (Continuous Adaptive Mean Shift Algorithm)" using only a single camera in multi-color backgrounds. In order to track hands robustly, the proposed algorithm uses " motion mask" to combine color and movement probability distributions and " probability reduction" for multi-hand tracking in non-limiting environments. Experimental results demonstrate that this algorithm can precisely track both hands of an operator in multi-color backgrounds and process the VGA size input sequences from a web camera in real time (about 25 fps).

  • SIFT-Based Low Complexity Keypoint Extraction and Its Real-Time Hardware Implementation for Full-HD Video

    Takahiro Suzuki, Takeshi Ikenaga

    2012 ASIA-PACIFIC SIGNAL AND INFORMATION PROCESSING ASSOCIATION ANNUAL SUMMIT AND CONFERENCE (APSIPA ASC)    2012  [Refereed]

    Authorship:Corresponding author

     View Summary

    Scale-Invariant Feature Transform (SIFT) has lately attracted attention in computer vision as a robust keypoint detection algorithm which is invariant for scale, rotation and illumination change. However, its computational complexity is too high to apply practical real-time applications. This paper proposes a low complexity keypoint extraction algorithm based on SIFT descriptor and utilization of the database, and its real-time hardware implementation for Full-HD resolution video. The proposed algorithm computes SIFT descriptor on the keypoint obtained by corner detection and selects a scale from the database. It is possible to parallelize the keypoint detection and descriptor computation modules in the hardware. These modules do not depend on each other in the proposed algorithm in contrast with SIFT that computes a scale. The processing time of descriptor computation in this hardware is independent of the number of keypoints because its descriptor generation is pipelining structure of pixel. Evaluation results show that the proposed algorithm on software is 12 times faster than SIFT. Moreover, the proposed hardware on FPGA is 427 times faster than SIFT and 61 times faster than the proposed algorithm on software. The proposed hardware performs keypoint extraction and matching at 60 fps for Full-HD video.

  • Reversed intra prediction based on chroma extraction in HEVC

    Wei Jing Chen, Jia Su, Bin Li, Takeshi Ikenaga

    2011 International Symposium on Intelligent Signal Processing and Communications Systems (ISPACS)    2011.12  [Refereed]

    Authorship:Corresponding author

    DOI

  • Dual Model Particle Filter for Irregular Moving Object Tracking in Sports Scenes

    Yuhi Shiina, Takeshi Ikenaga

    APSIPA Annual Summit and Conference (ASC 2011)    2011.10  [Refereed]

    Authorship:Corresponding author

  • Video Conferencing Oriented Low-Complexity Coarse-Level Mode-Mapping Based H.264/AVC to H.264/SVC Spatial Transcoding

    Lei Sun, Jie Leng, Jia Su, Yiqing Huang, Hiroomi Motohashi, Takeshi Ikenaga

    APSIPA Annual Summit and Conference (ASC 2011)    2011.10  [Refereed]

    Authorship:Corresponding author

  • Low Complexity Quadtree based All Zero Block Detection Algorithm for HEVC

    Jia Su, Yiqing Huang, Lei Sun, Shinichi Sakaida, Takeshi Ikenaga

    APSIPA Annual Summit and Conference (ASC 2011)    2011.10  [Refereed]

    Authorship:Corresponding author

  • Adaptive fast DIRECT mode decision algorithm using mode and Lagrangian cost prediction for B frame in H.264/AVC

    Xiaocong Jin, Jun Sun, Jun Zhou, Yiqing Huang, Jia Su, Takeshi Ikenaga

    2011 IEEE International Conference on Multimedia and Expo    2011.07  [Refereed]

    Authorship:Corresponding author

    DOI

  • Coarse to fine adaptive interpolation filter for high resolution video coding

    Jia Su, Yiqing Huang, Lei Sun, Shinichi Sakaida, Takeshi Ikenaga

    2011 IEEE International Conference on Multimedia and Expo    2011.07  [Refereed]

    Authorship:Corresponding author

    DOI

  • Content Based Hierarchical Fast Coding Unit Decision Algorithm for HEVC

    Jie Leng, Lei Sun, Takeshi Ikenaga, Shinichi Sakaida

    2011 International Conference on Multimedia and Signal Processing    2011.05  [Refereed]

    Authorship:Corresponding author

    DOI

  • Multi Objective Optimization Based Fast Motion Detector

    Jia Su, Xin Wei, Xiaocong Jin, Takeshi Ikenaga

    Lecture Notes in Computer Science     492 - 502  2011  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

    1
    Citation
    (Scopus)
  • A Novel Cache Replacement Policy via Dynamic Adaptive Insertion and Re-Reference Prediction

    Xi ZHANG, Chongmin LI, Zhenyu LIU, Haixia WANG, Dongsheng WANG, Takeshi IKENAGA

    IEICE Transactions on Electronics   E94-C ( 4 ) 468 - 476  2011  [Refereed]

    Authorship:Last author

     View Summary

    Previous research illustrates that LRU replacement policy is not efficient when applications exhibit a distant re-reference interval. Recently RRIP policy is proposed to improve the performance for such kind of workloads. However, the lack of access recency information in RRIP confuses the replacement policy to make the accurate prediction. To enhance the robustness of RRIP for recency-friendly workloads, we propose an Dynamic Adaptive Insertion and Re-reference Prediction (DAI-RRP) policy which evicts data based on both re-reference prediction value and the access recency information. DAI-RRP makes adaptive adjustment on insertion position and prediction value for different access patterns, which makes the policy robust across different workloads and different phases. Simulation results show that DAI-RRP outperforms LRU and RRIP. For a single-core processor with a 1MB 16-way set last-level cache (LLC), DAI-RRP reduces CPI over LRU and Dynamic RRIP by an average of 8.1% and 2.7% respectively. Evaluations on quad-core CMP with a 4MB shared LLC show that DAI-RRP outperforms LRU and Dynamic RRIP (DRRIP) on the weighted speedup metric by an average of 8.1% and 15.7% respectively. Furthermore, compared to LRU, DAI-RRP consumes the similar hardware for 16-way cache, or even less hardware for high-associativity cache. In summary, the proposed policy is practical and can be easily integrated into existing hardware approximations of LRU.

    DOI CiNii

  • Highly Parallel and Fully Reused H.264/AVC High Profile Intra Predictor Generation Engine for Super Hi-Vision 4k*4k@60fps

    Yiqing HUANG, Xiaocong JIN, Jin ZHOU, Jia SU, Takeshi IKENAGA

    IEICE Transactions on Electronics   E94-C ( 4 ) 428 - 438  2011  [Refereed]

    Authorship:Corresponding author

     View Summary

    One high profile intra predictor generation engine is proposed in this paper. Firstly, hardware level algorithm optimization for intra 8 × 8 (I8MB) mode is introduced. The original candidate pixels for generating prediction samples of I8MB are replaced with boundary pixels of intra 4 × 4 (I4MB) blocks. Based on this adoption, full data reuse between predictors of I4MB and filtered samples of I8MB can be achieved with almost no quality loss. Secondly, one lossless two-4 × 4-block based parallel predictor generation flow is proposed. The original predictor generation flow is optimized from 16 stages to 10 stages for I4MB and Intra 16 × 16 (I16MB), which saves 37.5% processing cycles. For I8MB, similar methodology with different processing order of 4 × 4 scaled blocks is introduced. Thirdly, fully utilized hardwired engines for I4MB, I16MB and I8MB are proposed in this paper. Except DC (direct current) and plane modes, full data reuse among all intra modes of high profile can be achieved. Fourthly, for DC mode, one combined predictor generation process is introduced and predictor generation of I16MB's DC mode is merged into the process of I4MB's DC mode. Moreover, by configuring proposed hardwired engines, predictor generation of I16MB's plane mode and chrominance plane mode can be accomplished with only 50% cycles of original design. Totally, when compared with original full-mode design and latest dynamic mode reused design, the proposed predictor generation engine can achieve 89.5% and 73.2% saving of processing cycles, respectively. Synthesized by TSMC 0.18µm technology under worst work conditions (1.62V, 125°C), with 380MHz and 37.2k gates, the proposed design can handle real-time high profile intra predictor generation of Super Hi-Vision 4k × 4k@60fps. The maximum work frequency of our design under worst condition is 468MHz.

    DOI CiNii

  • Fast H.264/AVC DIRECT Mode Decision Based on Mode Selection and Predicted Rate-Distortion Cost

    Xiaocong JIN, Jun SUN, Yiqing HUANG, Jia SU, Takeshi IKENAGA

    IEICE Transactions on Information and Systems   E94-D ( 8 ) 1653 - 1662  2011  [Refereed]

    Authorship:Corresponding author

     View Summary

    Different encoding modes for variable block size are available in the H.264/AVC standard in order to offer better coding quality. However, this also introduces huge computation time due to the exhaustive check for all modes. In this paper, a fast spatial DIRECT mode decision method for profiles supporting B frame encoding (main profile, high profile, etc.) in H.264/AVC is proposed. Statistical analysis on multiple video sequences is carried out, and the strong relationship of mode selection and rate-distortion (RD) cost between the current DIRECT macroblock (MB) and the co-located MBs is observed. With the check of mode condition, predicted RD cost threshold and dynamic parameter update model, the complex mode decision process can be terminated at an early stage even for small QP cases. Simulation results demonstrate the proposed method can achieve much better performance than the original exhaustive rate-distortion optimization (RDO) based mode decision algorithm by reducing up to 56.8% of encoding time for IBPBP picture group and up to 67.8% of encoding time for IBBPBBP picture group while incurring only negligible bit increment and quality degradation.

    DOI CiNii

  • “Particle Filter based on Dual Model for Irregular Moving Object Tracking”

    Yuhi Shiina, Takeshi Ikenaga

    Journal of the Institute of Image Electronics Engineers of Japan   40 ( 5 ) 823 - 832  2011  [Refereed]

    Authorship:Corresponding author

     View Summary

    Particle filter is well known as a robust object tracking algorithm based on prediction with many distributed particles and is widely used for many practical applications. However, since conventional methods use one state transition model, the tracking accuracy is decreased for the objects with irregular motion. This paper proposes a dual model particle filter based on two state transition models which targets for irregular moving object tracking. By using two state transition models which have different properties each of them, the proposed method makes it possible to track stably even if the object suddenly change its direction. Evaluation results with a software simulation shows that the proposed method attains high tracking accuracy for a irregular moving scene, for example bounding ball on floor or wall, compared with conventional ones. © 2011, The Institute of Image Electronics Engineers of Japan. All rights reserved.

    DOI

    Scopus

  • “Real-time Both Hands Tracking Using Feature Point Gathering by KLT Tracker for Man-Machine Interface”

    Ryosuke Araki, Takeshi Ikenaga

    Journal of the Institute of Image Electronics Engineers of Japan   40 ( 5 ) 833 - 841  2011  [Refereed]

    Authorship:Corresponding author

     View Summary

    Intuitive man-machine interface based on a gesture with a touchpad device is becoming common. In the near future, the importance of gesture recognition using input from a video camera is expected to be high in order to widen applicable information terminals and their applications. Conventional works, however, use a complex input device combining plural cameras and sensors. Moreover, since most of their algorithms need high computational complexity and is good for images with a simple background, it's difficult to apply practical systems. This paper proposes a real-time single-input object tracking algorithm which can trace both hands precisely under a complex background. It makes it possible to attain both high accuracy and low complexity by applying a technique combining frame difference and color and decision of feature point gathering into the KLT (Kanade-Lucas-Tomasi) tracker, a kind of an optical flow. Software based evaluation results using a wide variety of test sequences (e.g. complex background and object shape change) show that the proposed algorithm achieves higher tracking accuracy compared with conventional ones. Furthermore, a processing performance is 13-16 frame per second, which means both hands can be tracked in real-time. © 2011, The Institute of Image Electronics Engineers of Japan. All rights reserved.

    DOI

    Scopus

  • Content Based Coarse to Fine Adaptive Interpolation Filter for High Resolution Video Coding

    Jia SU, Yiqing HUANG, Lei SUN, Shinichi SAKAIDA, Takeshi IKENAGA

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E94-A ( 10 ) 2013 - 2021  2011  [Refereed]

    Authorship:Corresponding author

     View Summary

    With the increasing demand of high video quality and large image size, adaptive interpolation filter (AIF) addresses these issues and conquers the time varying effects resulting in increased coding efficiency, comparing with recent H.264 standard. However, currently most AIF algorithms are based on either frame level or macroblock (MB) level, which are not flexible enough for different video contents in a real codec system, and most of them are facing a severe time consuming problem. This paper proposes a content based coarse to fine AIF algorithm, which can adapt to video contents by adding different filters and conditions from coarse to fine. The overall algorithm has been mainly made up by 3 schemes: frequency analysis based frame level skip interpolation, motion vector modeling based region level interpolation, and edge detection based macroblock level interpolation. According to the experiments, AIF are discovered to be more effective in the high frequency frames, therefore, the condition to skip low frequency frames for generating AIF coefficients has been set. Moreover, by utilizing the motion vector information of previous frames the region level based interpolation has been designed, and Laplacian of Gaussian based macroblock level interpolation has been proposed to drive the interpolation process from coarse to fine. Six 720p and six 1080p video sequences which cover most typical video types have been tested for evaluating the proposed algorithm. The experimental results show that the proposed algorithm reduce total encoding time about 41% for 720p and 25% for 1080p sequences averagely, comparing with Key Technology Areas (KTA) Enhanced AIF algorithm, while obtains a BDPSNR gain up to 0.004 and 3.122 BDBR reduction.

    DOI CiNii

  • Rate-distortion optimization based skip mode early detection in H.264

    Qin Liu, Takeshi Ikenaga

    2010 International Symposium on Intelligent Signal Processing and Communication Systems    2010.12  [Refereed]

    Authorship:Corresponding author

    DOI

  • Content based Low-Complexity Mode Decision using Super Macroblock for Next Generation Coding Standard

    Jie Leng, Shinichi Sakaida, Takeshi Ikenaga

    APSIPA Annual Summit and Conference (ASC 2010)    2010.12  [Refereed]

    Authorship:Corresponding author

  • One Pass Enhanced Adaptive Interpolation for High-Resolution Video Coding

    Jia Su, Shinichi Sakaida, Takeshi Ikenaga

    APSIPA Annual Summit and Conference (ASC 2010)    2010.12  [Refereed]

    Authorship:Corresponding author

  • Low Complexity Mode Depended Local Adaptive Interpolation Filter for Next Generation Video Coding

    Jin Zhou, Shinichi Sakaida, Takeshi Ikenaga

    2010 International Conference on Computational Intelligence and Software Engineering    2010.09  [Refereed]

    Authorship:Corresponding author

    DOI

  • Low Complexity Homography Matrix Based SIFT for Real-Time 2D Rigid Object Tracking

    Ying Lu, Chengjiao Guo, Jingbang Qiu, Peilin Liu, Takeshi Ikenaga

    2010 International Conference on Computational Intelligence and Software Engineering    2010.09  [Refereed]

    Authorship:Corresponding author

    DOI

  • Multiple Likelihoods and State Noises Based Particle Filter for Long-Lived Full Occlusion Handling

    Chengjiao Guo, Ying Lu, Xiangzhong Fang, Takeshi Ikenaga

    2010 International Conference on Computational Intelligence and Software Engineering    2010.09  [Refereed]

    Authorship:Corresponding author

    DOI

  • 未来を切り拓く最先端 VLSI テクノロジー : 1.メディア処理における超低消費電力SoC技術

    後藤 敏, 池永 剛, 吉村 猛, 木村 晋二, 戸川 望

    情報処理   Vol. 51 ( No. 7 ) 837 - 845  2010.07  [Invited]

    CiNii

  • Complicated Scene Retrieval Using Block Voting Mechanism and Weak Feature Selection Based on Bag-of-Features

    Bingrong Wang, Lei Sun, Jia Su, Takeshi Ikenaga

    4th International Conference on New Trends in Information Science and Service Science (NISS2010)    2010.05  [Refereed]

    Authorship:Corresponding author

  • Robust Online Tracking Using Orientation and Color Incorporated Adaptive Models in Particle Filter

    Cheng Guo, Ying Lu, Takeshi Ikenaga

    4th International Conference on New Trends in Information Science and Service Science (NISS2010)    2010.05  [Refereed]

    Authorship:Corresponding author

  • Estimation-Correction Scheme based Articulated Object Tracking using SIFT Features and Mean Shift Algorithm

    Ying Lu, Chengjiao Guo, Takeshi Ikenaga

    4th International Conference on New Trends in Information Science and Service Science (NISS2010)    2010.05  [Refereed]

    Authorship:Corresponding author

  • 北九州だより グローバルな情報化社会に向けたグローバルな人材育成を目指して

    池永 剛

    IEICE Fundamentals Review   Vol. 3 ( No. 4 )  2010.04  [Invited]

    Authorship:Lead author

  • Linear Divided Difference Filter and Weighted Erosion Filter based Fast Motion Estimation Algorithm

    Jia Su, Qin Liu, Takeshi Ikenaga

    International Conference on Computational Science and Applications (ICCSA 2010)    2010.03  [Refereed]

    Authorship:Corresponding author

  • 8x8 Transformation Based All Zero Block Detection for H.264/AVC Encoder

    Jia Su, Takeshi Ikenaga, Qin Liu

    Journal of the Institute of Image Electronics Engineers of Japan   39 ( 1 ) 12 - 22  2010  [Refereed]

    Authorship:Corresponding author

     View Summary

    Currently, 8x8 integer transformation was added to H.264/AVC for enhancing the performance of high profile, while much more complexity increased. All Zero Block (AZB) detection algorithms can help to early terminate DCT and quantization parts to reduce complexity with almost no PSNR loss. Due to the great complexity of 8x8 integer transform and quantization, however, the previous works are only concentrated on the 4×4 SAD all zero block detection. This paper proposes SAD and SATD based 8×8 AZB detection algorithms: By using the statistical analysis instead of complicated matrix derivation, through 17 QCIF sequences, 12 CIF sequences and 7 sequences of 720p test, which covers most video application, the 8×8 SAD value based all zero block threshold has been calculated. While using the SATD as the block matching criterion, the relationship between the 8x8 SAD and SATD has been derived theoretically from the energy point of view. Finally, according to this relationship and proposed SAD thresholds, the 8×8 SATD AZB thresholds have been derived. The proposed SAD value based AZB detection algorithm has saved nearly from 5% to 40% DCT and quantization calculation for QCIF, CIF and 720p sequences, while the SATD value based AZB detection algorithm achieved about from 10% to 43% calculation reduction. © 2010, The Institute of Image Electronics Engineers of Japan. All rights reserved.

    DOI

    Scopus

  • A 7-Round Parallel Hardware-Saving Accelerator for Gaussian and DoG Pyramid Construction Part of SIFT

    Jingbang Qiu, Tianci Huang, Takeshi Ikenaga

    Computer Vision – ACCV 2009     75 - 84  2010  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

    7
    Citation
    (Scopus)
  • Adaptively Adjusted Gaussian Mixture Models for Surveillance Applications

    Tianci Huang, Xiangzhong Fang, Jingbang Qiu, Takeshi Ikenaga

    Lecture Notes in Computer Science     689 - 694  2010  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

    5
    Citation
    (Scopus)
  • Fully Utilized and Low Design Effort Architecture for H.264/AVC Intra Predictor Generation

    Yiqing Huang, Qin Liu, Takeshi Ikenaga

    Lecture Notes in Computer Science     737 - 742  2010  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

  • Real-Time Non-rigid Object Tracking Using CAMShift with Weighted Back Projection

    Lei Sun, Bingrong Wang, Takeshi Ikenaga

    2010 International Conference on Computational Science and Its Applications    2010  [Refereed]

    Authorship:Corresponding author

    DOI

  • Highly Parallel Fractional Motion Estimation Engine for Super Hi-Vision 4k*4k@60 fps

    Yiqing HUANG, Takeshi IKENAGA

    IEICE Transactions on Electronics   E93-C ( 3 ) 244 - 252  2010  [Refereed]

    Authorship:Corresponding author

     View Summary

    One Super Hi-Vision (SHV) 4k×4k@60fps fractional motion estimation (FME) engine is proposed in our paper. Firstly, two complexity reduction schemes are proposed in the algorithm level. By analyzing the integer motion cost of sub blocks in each inter mode, the mode reduction based mode pre-filtering scheme can achieve 48% clock cycle saving compared with previous algorithm. By further check the motion cost of search points around best integer candidate, the motion cost oriented directional one-pass scheme can provide 50% clock cycle saving and 36% reduction in the number of processing units (PU). Secondly, in the hardware level, two parallel improved schemes namely 16-Pel processing and MB-parallel scheme are given out in our paper, which reduces design effort to only 145MHz for SHV FME processing. Also, quarter sub-sampling is adopted in our design and 75% hardware cost is reduced for each PU. Thirdly, one unified pixel block loading scheme is proposed. About 28.67% to 86.39% pixels are reused and the related memory access is saved. Furthermore, we also give out one parity pixel organization scheme to solve memory access conflict of MB-parallel scheme. By using TSMC 0.18µm technology in worst work conditions (1.62V, 125°C), our FME engine can achieve real-time processing for SHV 4k×4k@60fps with 412k gates hardware.

    DOI CiNii

  • Constant Bit-Rate Multi-Stage Rate Control for Rate-Distortion Optimized H.264/AVC Encoders

    Shuijiong WU, Peilin LIU, Yiqing HUANG, Qin LIU, Takeshi IKENAGA

    IEICE Transactions on Information and Systems   E93-D ( 7 ) 1716 - 1726  2010  [Refereed]

    Authorship:Corresponding author

     View Summary

    H.264/AVC encoder employs rate control to adaptively adjust quantization parameter (QP) to enable coded video to be transmitted over a constant bit-rate (CBR) channel. In this topic, bit allocation is crucial since it is directly related with actual bit generation and the coding quality. Meanwhile, the rate-distortion-optimization (RDO) based mode-decision technique also affects performance a lot for the strong relation among mode, bits, and quality. This paper presents a multi-stage rate control scheme for R-D optimized H.264/AVC encoders under CBR video transmission. To enhance the precision of the complexity estimation and bit allocation, a frequency-domain parameter named mean-absolute-transform-difference (MATD) is adopted to represent frame and macroblock (MB) residual complexity. Second, the MATD ratio is utilized to enhance the accuracy of frame layer bit prediction. Then, by considering the bit usage status of whole sequence, a measurement combining forward and backward bit analysis is proposed to adjust the Lagrange multiplier λMODE on frame layer to optimize the mode decision for all MBs within the current frame. On the next stage, bits are allocated on MB layer by proposed remaining complexity analysis. Computed QP is further adjusted according to predicted MB texture bits. Simulation results show the PSNR improvement is up to 1.13dB by using our algorithm, and the stress of output buffer control is also largely released compared with the recommended rate control in H.264/AVC reference software JM13.2.

    DOI CiNii

  • “Motion based Feature Point Selection Algorithms with KLT Tracker and Its Hardware Implementation”

    Tsuyoshi Sasaki, Kodai Kawane, Takeshi Ikenaga

    Journal of the Institute of Image Electronics Engineers of Japan   39 ( 5 ) 590 - 597  2010  [Refereed]

    Authorship:Corresponding author

     View Summary

    Surveillance camera systems play an important role for creating safe and secure society. Especially, real-time motion detection is a key to detect abnormal scenes. So, we picked up KLT (Kanade-Lucas-Tomasi) tracker and tried to implement a system. However, there are still many problems in accuracy and system cost. This paper proposes a score control by weighted mask and an adaptive feature point interval algorithms to increase accuracy of object detection. Moreover, to implement these algorithms onto a low cost FPGA, hardware architectures, such as weighted value generation circuit, insert position calculation circuit and feature point data update circuit, are proposed. Evaluation results shows that the proposed algorithm can detect motion vectors with high accuracy for various surveillance scenes. Moreover, hardware implementation results show that the proposed architecture attains real-time processing with around 20% FPGA resources. © 2010, The Institute of Image Electronics Engineers of Japan. All rights reserved.

    DOI

    Scopus

  • Multiple Likelihood Models based Particle Filter for Long-term Full Occlusion

    Chengjiao Guo, Ying Lu, Takeshi Ikenaga

    Journal of the Institute of Image Electronics Engineers of Japan   39 ( 5 ) 580 - 589  2010  [Refereed]

    Authorship:Corresponding author

     View Summary

    Object tracking is one of the most important applications in the field of computer vision. One of the common problems in object tracking is object occlusions. Especially in the presence of long-term full occlusion, or called long-lived full occlusion, during which the target remains invisible for tens of frames, the tracking is more difficult. This paper proposes an occlusion handling scheme based on particle filter. Compared with the conventional particle filter which usually utilizes color as tracking cue, multiple likelihood models: HSV color and gradient orientation likelihoods, are employed in the observation model during occlusion. The incorporation of these two features makes the target distinguishable even if it is occluded by a similar colored object in the background. Also, multiple state noises are introduced to ensure the redetection of the target at the end of full occlusion as well as keeping tracking accuracy under occlusion. Experimental results under different occlusion conditions show that the proposed particle filter achieves robust and accurate performance compared with the particle filter with appearance adaptive models and the color particle filter, even in the condition of long-lived full occlusion. © 2010, The Institute of Image Electronics Engineers of Japan. All rights reserved.

    DOI

    Scopus

    5
    Citation
    (Scopus)
  • Architecture and Circuit Optimization of Hardwired Integer Motion Estimation Engine for H.264/AVC

    Zhenyu LIU, Dongsheng WANG, Takeshi IKENAGA

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E93-A ( 11 ) 2065 - 2073  2010  [Refereed]

    Authorship:Corresponding author

     View Summary

    Variable block size motion estimation developed by the latest video coding standard H.264/AVC is the efficient approach to reduce the temporal redundancies. The intensive computational complexity coming from the variable block size technique makes the hardwired accelerator essential, for real-time applications. Propagate partial sums of absolute differences (Propagate Partial SAD) and SAD Tree hardwired engines outperform other counterparts, especially considering the impact of supporting variable block size technique. In this paper, the authors apply the architecture-level and the circuit-level approaches to improve the maximum operating frequency and reduce the hardware overhead of Propagate Partial SAD and SAD Tree, while other metrics, in terms of latency, memory bandwidth and hardware utilization, of the original architectures are maintained. Experiments demonstrate that by using the proposed approaches, at 110.8MHz operating frequency, compared with the original architectures, 14.7% and 18.0% gate count can be saved for Propagate Partial SAD and SAD Tree, respectively. With TSMC 0.18µm 1P6M CMOS technology, the proposed Propagate Partial SAD architecture achieves 231.6MHz operating frequency at a cost of 84.1k gates. Correspondingly, the maximum work frequency of the optimized SAD Tree architecture is improved to 204.8MHz, which is almost two times of the original one, while its hardware overhead is merely 88.5k-gate.

    DOI CiNii

  • Motion detection based motion estimation algorithm for video surveillance application

    Jia Su, Qin Liu, Takeshi Ikenaga

    2009 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)    2009.12  [Refereed]

    Authorship:Corresponding author

    DOI

  • Fast spatial Direct mode decision for B slice based on temporal information in H.264 standard

    Xiaocong Jin, Yiqing Huang, Qin Liu, Shuijiong Wu, Takeshi Ikenaga

    2009 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)    2009.12  [Refereed]

    Authorship:Corresponding author

    DOI

  • Hardware optimizations of variable block size Hadamard transform for H.264/AVC FRExt

    Zhenyu Liu, Dongsheng Wang, Takeshi Ikenaga

    2009 16th IEEE International Conference on Image Processing (ICIP)    2009.11  [Refereed]

    Authorship:Corresponding author

    DOI

  • Macroblock feature and motion involved multi-stage fast inter mode decision algorithm in H.264/AVC video coding

    Yiqing Huang, Qin Liu, Takeshi Ikenaga

    2009 16th IEEE International Conference on Image Processing (ICIP)    2009.11  [Refereed]

    Authorship:Corresponding author

    DOI

  • On bit allocation and Lagrange Multiplier adjustment for rate-distortion optimized H.264 rate control

    Shuijiong Wu, Peilin Liu, Yiqing Huang, Qin Liu, Takeshi Ikenaga

    2009 IEEE International Workshop on Multimedia Signal Processing    2009.10  [Refereed]

    Authorship:Corresponding author

    DOI

  • Highly parallel fractional motion estimation engine for Super Hi-Vision 4k&amp;#x00D7;4k@60fps

    Yiqing Huang, Qin Liu, Takeshi Ikenaga

    2009 IEEE International Workshop on Multimedia Signal Processing    2009.10  [Refereed]

    Authorship:Corresponding author

    DOI

  • Analysis of adaptive algorithm to power aware design for H.264/AVC integer motion estimation engine in HDTV application

    Yiqing Huang, Takeshi Ikenaga

    2009 IEEE 8th International Conference on ASIC    2009.10  [Refereed]

    Authorship:Corresponding author

    DOI

  • Parallel enhanced low design effort H.264/AVC fractional motion estimation engine for Super Hi-Vision application

    Yiqing Huang, Takeshi Ikenaga

    2009 IEEE 8th International Conference on ASIC    2009.10  [Refereed]

    Authorship:Corresponding author

    DOI

  • 実時間KLT Tracker向きハードウェアエンジンの実現

    坂寄貴宏, 池永 剛

    画像電子学会誌   Vol. 38 ( No. 5 ) 656 - 663  2009.09  [Refereed]

    Authorship:Corresponding author

    CiNii

  • An FPGA-Based Real-Time Hardware Accelerator for Orientation Calculation Part in SIFT

    Jingbang Qiu, Ying Lu, Tianci Huang, Takeshi Ikenaga

    2009 Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing    2009.09  [Refereed]

    Authorship:Corresponding author

    DOI

  • Rate-Distortion Optimized Multi-Stage Rate Control Algorithm for H.264/AVC Video Coding

    Shuijiong Wu, Yiqing Huang, Qin Liu, Takeshi Ikenaga

    17th European Signal Processing Conference (EUSIPCO 2009)    2009.08  [Refereed]

    Authorship:Corresponding author

  • 二一世紀 アンビエント情報化社会の実現に向けて

    池永 剛

    早稲田学報   ゲンダイを読む第17回  2009.08  [Invited]

    Authorship:Lead author

  • Fast Inter Mode Decision Algorithm Based On Macroblock and Motion Feature Analysis For H.264/AVC Video Coding

    Yiqing Huang, Qin Liu, Takeshi Ikenaga

    17th European Signal Processing Conference (EUSIPCO 2009)    2009.08  [Refereed]

    Authorship:Corresponding author

  • Motion Estimation Optimization for H.264/AVC Using Source Image Edge Features

    Zhenyu Liu, Junwei Zhou, Satoshi Goto, Takeshi Ikenaga

    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY   19 ( 8 ) 1095 - 1107  2009.08  [Refereed]

    Authorship:Corresponding author

     View Summary

    The H.264/AVC coding standard processes variable block size motion-compensated prediction with multiple reference frames to achieve a pronounced improvement in compression efficiency. Accordingly, the computation of motion estimation increases in proportion to the product of the number of reference frame and the number of intermode. The mathematical analysis in this paper illustrates that the motion-compensated prediction errors are mainly determined by the detailed textures in the source image. The image block being rich in textures contains numerous high-frequency signals, which make variable block size and multiple reference frame techniques essential. On the basis of rate-distortion theory, in this paper, the spatial homogeneity of an image block is made as a relative concept with respect to the current quantization step. For the homogenous block, its futile reference frames and intermodes can be eliminated efficiently. It is further revealed that the sum of absolute differences value of an image block is mainly determined by the sum of its edge gradient amplitude and the current quantization step. Consequently, the image content-based early termination algorithm is proposed, and it outperforms the original method adopted by JVT reference software. Moreover, the dynamic search range algorithm based on the edge gradient amplitude of source image block is analyzed. One eminent advantage of the proposed edge-based algorithms is their efficiency to the macroblock-pipelining architecture, and another desirable feature is their orthogonality to fast block-matching algorithms. Experimental results show that when these algorithms are integrated with hybrid unsymmetrical-cross multi-hexagongrid search, an averaged 31.4-60.0% motion estimation time can be saved, whereas the averaging BDPSNR loss is 0.0497 dB for all tested sequences.

    DOI

    Scopus

    12
    Citation
    (Scopus)
  • Intra Mode Decision for Reducing Block Types and Prediction Modes Based on Edge Information in H.264/AVC

    Zhewen Zheng, Yiqing Huang, Qin Liu, Takeshi Ikenaga

    The 24th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2009)    2009.07  [Refereed]

    Authorship:Corresponding author

  • Bit-Usage Analysis Based Frame Layer QP Adjustment for H.264/AVC Rate Control at Low Bit-Rate

    Shuijiong Wu, Yiqing Huang, Qin Liu, Takeshi Ikenaga

    The 24th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2009)    2009.07  [Refereed]

    Authorship:Corresponding author

  • Spatial feature based reconfigurable H.264/AVC integer motion estimation architecture for HDTV video encoder

    Yiqing Huang, Qin Liu, Takeshi Ikenaga

    2009 16th International Conference on Digital Signal Processing    2009.07  [Refereed]

    Authorship:Corresponding author

    DOI

  • Content aware configurable architecture for H.264/AVC integer motion estimation engine

    Yiqing Huang, Qin Liu, Takeshi Ikenaga

    2009 IEEE International Conference on Multimedia and Expo    2009.06  [Refereed]

    Authorship:Corresponding author

    DOI

  • A Hardware Accelerator with Variable Pixel Representation &amp; Skip Mode Prediction for Feature Point Detection Part of SIFT Algorithm

    Jingbang Qiu, Tianci Huang, Yiqing Huang, Takeshi Ikenaga

    IAPR Conference on Machine Vision Applications (MVA 2009)    2009.05  [Refereed]

    Authorship:Corresponding author

  • Robust Background Segmentation Using Background Models for Surveillance Application

    anci Huang, Jingbang Qiu, Takahiro Sakayori, Takeshi Ikenaga

    IAPR Conference on Machine Vision Applications (MVA 2009)    2009.05  [Refereed]

    Authorship:Corresponding author

  • Hardware-Oriented Early Detection Algorithms for 4 x 4 and 8 x 8 All-Zero Blocks in H.264

    Qin Liu, Yiqing Huang, Satoshi Goto, Takeshi Ikenaga

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E92A ( 4 ) 1063 - 1071  2009.04  [Refereed]

    Authorship:Corresponding author

     View Summary

    H.264 is the latest HDTV video compression standard, which provides a significant improvement in coding efficiency at the cost of huge computation complexity. After transform and quantization, if all the coefficients of the block's residue data are zero, this block is called all-zero block (AZB). Provided that an AZB can be detected early, the process of transform and quantization on an AZB can be skipped, which reduces significant redundant Computations. In this paper, a theoretical analysis is performed for the sufficient condition for AZB detection. As a result, a partial sum of absolute difference (SAD) based 4 x 4 AZB detection algorithm is derived. And then, a hardware-oriented AZB detection algorithm is proposed by modifying the order of SAD calculation. Furthermore, a quantization parameter (QP) oriented 8 x 8 AZB detection algorithm is proposed according to the AZB's statistical analysis. Experimental results show that the proposed algorithm outperforms the previous methods in all cases and achieves major improvement of computation reduction in the range from 6.7% to 42.3% for 4 x 4 blocks, from 0.24% to 79.48% for 8 x 8 blocks. The computation reduction increases as QP increases.

    DOI

    Scopus

    2
    Citation
    (Scopus)
  • VLSI oriented fast motion estimation algorithm based on macroblock and motion feature analysis

    Yiqing Huang, Qin Liu, Takeshi Ikenaga

    2009 5th International Colloquium on Signal Processing &amp; Its Applications    2009.03  [Refereed]

    Authorship:Corresponding author

    DOI

  • Hardware Accelerator for Feature Point Detection Part of SIFT Algorithm &amp; Corresponding Hardware-Friendly Modification

    Jingbang Qiu, Takeshi Ikenaga, Tianci Huang

    The 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009)    2009.03  [Refereed]

    Authorship:Corresponding author

  • HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis

    Zhenyu Liu, Yang Song, Ming Shao, Shen Li, Lingfeng Li, Shunichi Ishiwata, Masaki Nakagawa, Satoshi Goto, Takeshi Ikenaga

    IEEE Journal of Solid-State Circuits   44 ( 2 ) 594 - 608  2009.02  [Refereed]

    Authorship:Corresponding author

    DOI

  • Motion Detection Based on Background Modeling and Performance Analysis for Outdoor Surveillance

    Tianci Huang, Jingbang Qiu, Takahiro Sakayori, Satoshi Goto, Takeshi Ikenaga

    2009 International Conference on Computer Modeling and Simulation    2009.02  [Refereed]

    Authorship:Corresponding author

    DOI

  • A Macroblock-Level Rate Control Algorithm for H.264/AVC Video Coding with Context-Adaptive MAD Prediction Model

    Shuijiong Wu, Yiqing Huang, Takeshi Ikenaga

    2009 International Conference on Computer Modeling and Simulation    2009.02  [Refereed]

    Authorship:Corresponding author

    DOI

  • A Fast Hybrid Decision Algorithm for H.264/AVC Intra Prediction Based on Entropy Theory

    Guifen Tian, Tianruo Zhang, Takeshi Ikenaga, Satoshi Goto

    Lecture Notes in Computer Science     85 - 95  2009  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

    4
    Citation
    (Scopus)
  • A high performance LDPC decoder for IEEE802.11n standard

    Wen Ji, Yuta Abe, Takeshi Ikenaga, Satoshi Goto

    2009 Asia and South Pacific Design Automation Conference    2009.01  [Refereed]

    DOI

  • A High Throughput LDPC Decoder Design Based on Novel Delta-value Message-passing Schedule

    Wen Ji, Xing Li, Takeshi Ikenaga, Satoshi Goto

    IPSJ Transactions on System LSI Design Methodology   2   122 - 130  2009  [Refereed]

     View Summary

    In this paper, we propose a partially-parallel irregular LDPC decoder for IEEE 802.11n standard targeting high throughput applications. The proposed decoder has several merits: (i) The decoder is designed based on a novel delta-value based message passing algorithm which facilitates the decoding throughput by redundant computation removal. (ii) Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message-passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648, 324) irregular LDPC code, our decoder can achieve 8 times increasement in throughput, reaching 418Mbps at the frequency of 200MHz.

    DOI CiNii

    Scopus

  • A low bandwidth Integer Motion Estimation module for MPEG-2 to H.264 transcoding

    Xianghui Wei, Takeshi Ikenaga, Satoshi Goto

    IPSJ Transactions on System LSI Design Methodology   2   114 - 121  2009  [Refereed]

     View Summary

    A low-bandwidth Integer Motion Estimation (IME) module is proposed for MPEG-2 to H.264 transcoding. Based on bandwidth reduction method proposed in Ref. 1), a ping-pang memory control scheme combined with Partial Sum of Absolute Differences (SAD) Variable Block Size Motion Estimation (VBSME) architecture are realized. Experiment results show bandwidth of the proposed architecture is 70.6% of H.264 regular IME (Level C+ scheme, 2 Macro Block (MB) stitched vertically), while the on-chip memory size is 11.7% of that. © 2009 Information Processing Society of Japan.

    DOI

    Scopus

    1
    Citation
    (Scopus)
  • An Ultra-Low Bandwidth Design Method for MPEG-2 to H.264/AVC Transcoding

    Xianghui WEI, Takeshi IKENAGA, Satoshi GOTO

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E92-A ( 4 ) 1072 - 1079  2009  [Refereed]

    DOI

  • Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application

    Yiqing Huang, Qin Liu, Satoshi Goto, Takeshi Ikenaga

    Proceedings of the 19th ACM Great Lakes symposium on VLSI - GLSVLSI '09    2009  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

    2
    Citation
    (Scopus)
  • A Foreground Extraction Algorithm Based on Adaptively Adjusted Gaussian Mixture Models

    Tianci Huang, JingBang Qiu, Takeshi Ikenaga

    2009 Fifth International Joint Conference on INC, IMS and IDC    2009  [Refereed]

    Authorship:Corresponding author

    DOI

  • A FPGA-Based Dual-Pixel Processing Pipelined Hardware Accelerator for Feature Point Detection Part in SIFT

    Jingbang Qiu, Tianci Huang, Takeshi Ikenaga

    2009 Fifth International Joint Conference on INC, IMS and IDC    2009  [Refereed]

    Authorship:Corresponding author

    DOI

  • Macroblock feature based adaptive propagate partial SAD architecture for HDTV application

    Yiqing Huang, Qin Liu, Takeshi Ikenaga

    IPSJ Transactions on System LSI Design Methodology   2   263 - 273  2009  [Refereed]

    Authorship:Corresponding author

     View Summary

    A macroblock (MB) feature based adaptive propagate partial SAD architecture is proposed in this paper. Firstly, by using edge detection operator, the homogeneous MB is detected before motion estimation and three hardware friendly subsampling patterns are adaptively selected for MB with different homogeneity. The proposed architecture uses four different processing elements to realize adaptive subsampling scheme. Secondly, in order to achieve data reuse and power reduction in memory part, the reference pixels in search window are reorganization into two memory groups, which output pixel data interactively for adaptive subsampling. Moreover, a compressor tree based circuit level optimization is included in our design to reduce hardware cost. Synthesized with TSMC 0.18 um technology, averagely 10 k gates hardware can be reduced for the whole IME engine based on our optimization. With 481 k gates at 110.5 MHz, an 720-p, 30-fps HDTV integer motion estimation engine is designed. Compared with previous work, our design can achieve 39.8% reduction in power consumption with only 3.44% increase in hardware. © 2009 Information Processing Society of Japan.

    DOI

    Scopus

  • VLSI Oriented Fast Motion Estimation Algorithm Based on Pixel Difference, Block Overlapping and Motion Feature Analysis

    Yiqing HUANG, Qin LIU, Satoshi GOTO, Takeshi IKENAGA

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E92-A ( 8 ) 1986 - 1999  2009  [Refereed]

    Authorship:Corresponding author

     View Summary

    One VLSI friendly fast motion estimation (ME) algorithm is proposed in this paper. Firstly, theoretical analysis shows that image rich of sharp edges and texture is regarded as high frequency abundant image and macroblocks (MBs) in such image will express large pixel difference. In our paper, we apply adaptive subsampling method during ME process based on pixel difference analysis, so the computation complexity of full pixel pattern can be reduced. Secondly, statistic analysis shows that for MBs with static feature, the ratio of selecting previous reference frame as best one is very high and multiple reference frame technique is not required for these MBs. Based on this analysis, we give out a block overlapping method to pick out static MBs and apply MRF elimination process. Thirdly, since many redundant search positions exist in MB with small motion trend and large search range is only contributive to MB with big motion, we extract motion feature after ME on first reference frame and use it to adjust search range for rest ME process. So, the computation complexity of redundant search positions is eliminated. Experimental results show that, compared with hardware friendly full search algorithm, our proposed algorithm can reduce 71.09% to 95.26% ME time with negligible video quality degradation. Moreover, our fast algorithm can be combined with existing fast ME algorithms like UMHexagon method for further reduction in complexity and it is friendly to hardware implementation.

    DOI CiNii

  • Temporal information cooperated Gaussian Mixture Models for real-time surveillance with ghost detection

    Tianci Huang, Chengjiao Guo, Jingbang Qiu, Takeshi Ikenaga

    IIH-MSP 2009 - 2009 5th International Conference on Intelligent Information Hiding and Multimedia Signal Processing     1338 - 1341  2009  [Refereed]

    Authorship:Corresponding author

     View Summary

    This paper describes a new real-time approach for detecting motions in the video streams taken from stationary cameras. This method combines a temporal recording scheme with the adaptive background model subtraction scheme. To save the computation brought from conventional Gaussian Mixture Models (GMM) and achieve real-time processing, an adaptively adjusted mechanism is proposed. On the other hand, illumination changes, shadow influence, and ghost in scene, these three important problems which result in low segmentation quality are settled down by utilizing proposed features and temporal information from video streams. The experimental results validate the improvement of detection accuracy. Meanwhile, the execution time for each component per frame is calculated and compared with that of conventional Gaussian Mixture Models. © 2009 IEEE.

    DOI

    Scopus

    1
    Citation
    (Scopus)
  • Architecture optimization for H.264/AVC propagate partial SAD engine in HDTV application

    Yiqing Huang, Takeshi Ikenaga

    2009 International SoC Design Conference (ISOCC)    2009  [Refereed]

    Authorship:Corresponding author

    DOI

  • Adaptive Sub-Sampling Based Reconfigurable SAD Tree Architecture for HDTV Application

    Yiqing HUANG, Qin LIU, Satoshi GOTO, Takeshi IKENAGA

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E92-A ( 11 ) 2819 - 2829  2009  [Refereed]

    Authorship:Corresponding author

     View Summary

    This paper presents a reconfigurable SAD Tree (RSADT) architecture based on adaptive sub-sampling algorithm for HDTV application. Firstly, to obtain the the feature of HDTV picture, pixel difference analysis is applied on each macroblock (MB). Three hardware friendly sub-sampling patterns are selected adaptively to release complexity of homogeneous MB and keep video quality for texture MB. Secondly, since two pipeline stages are inserted, the whole clock speed of RSADT structure is enhanced. Thirdly, to solve data reuse and hardware utilization problem of adaptive algorithm, the RSADT structure adopts pixel data organization in both memory and architecture level, which leads to full data reuse and hardware utilization. Additionally, a cross reuse structure is proposed to efficiently generate 16 pixel scaled configurable SAD (sum of absolute difference). Experimental results show that, our RSADT architecture can averagely save 61.71% processing cycles for integer motion estimation engine and accomplish twice or four times processing capability for homogeneous MBs. The maximum clock frequency of our design is 208MHz under TSMC 0.18µm technology in worst work conditions(1.62V, 125°C). Furthermore, the proposed algorithm and reconfigurable structure are favorable to power aware real-time encoding system.

    DOI CiNii

  • Macroblock and Motion Feature Analysis to H.264/AVC Fast Inter Mode Decision

    Yiqing HUANG, Qin LIU, Shuijiong WU, Zhewen ZHENG, Takeshi IKENAGA

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E92-A ( 12 ) 3361 - 3368  2009  [Refereed]

    Authorship:Corresponding author

     View Summary

    One fast inter mode decision algorithm is proposed in this paper. The whole algorithm is divided into two stages. In the pre-stage, by exploiting spatial and temporal information of encoded macrobocks (MBs), a skip mode early detection scheme is proposed. The homogeneity of current MB is also analyzed to filter out small inter modes in this stage. Secondly, during the block matching stage, a motion feature based inter mode decision scheme is introduced by analyzing the motion vector predictor's accuracy, the block overlapping situation and the smoothness of SAD (sum of absolute difference) value. Moreover, the rate distortion cost is checked in an early stage and we set some constraints to speed up the whole decision flow. Experiments show that our algorithm can achieve a speed up factor of up to 53.4% for sequences with different motion type. The overall bit increment and quality degradation is negligible compared with existing works.

    DOI CiNii

  • High Throughput VLSI Architecture of a Fast Mode Decision Algorithm for H.264/AVC Intra Encoding

    Tianruo Zhang, Guifen Tian, Takeshi Ikenaga, Satoshi Goto

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 12 ) 3630 - 3637  2008.12  [Refereed]

    Authorship:Corresponding author

     View Summary

    Intra coding in H.264/AVC has significantly enhanced video compression efficiency. However, computation complexity increases by the rate-distortion (RD) based mode decision. This paper proposes a novel fast mode decision algorithm in H.264/AVC intra prediction and its VLSI architecture. A novel edge-detection pattern is proposed and both edge-detection technique and spatial mode prediction technique are combined together to reduce the number of intra 4 x 4 candidate modes from 9 to an average of 2.50. VLSI architecture of intra mode decision module is designed with TSMC 0.18 mu m CMOS technology. The maximum frequency of 285 MHz is achieved and 13.1k NAND gates are required. High frequency, efficient processing cycle reduction and small area make this design to be an excellent accelerator for HDTV 1080p@30 fps real time encoder.

    DOI

    Scopus

  • A High Performance Partially-Parallel Irregular LDPC Decoder Based on Sum-Delta Message Passing Schedule

    Wen Ji, Yuta Abe, Takeshi Ikenaga, Satoshi Goto

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 12 ) 3622 - 3629  2008.12  [Refereed]

     View Summary

    In this paper, we propose a partially-parallel irregular LDPC decoder based on IEEE 802.1 In standard targeting high throughput and small area applications. The design is based on a novel sum-delta message passing algorithm characterized as follows: (i) Decoding throughput is greatly improved by utilizing the difference value between the updated and the original value to remove redundant computations. (H) Registers and memory are optimized to store only the frequently used messages to decrease the hardware cost. (iii) Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed lip the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200 MHz, with 11% area reduction. The synthesis result also demonstrates the competitiveness to the fully-parallel regular LDPC decoders in terms of the tradeoff between throughput, area and power.

    DOI

    Scopus

    2
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    (Scopus)
  • A 820 Mb/s baseband processor LSI based on LDPC coded OFDM for UWB systems

    Shinsuke Ushiki, Koichi Nakamura, Kazunori Shimizu, Qi Wang, Yuta Abe, Satoshi Goto, Takeshi Ikenaga

    2008 IEEE Asian Solid-State Circuits Conference    2008.11  [Refereed]

    Authorship:Corresponding author

    DOI

  • Compressor tree based processing element optimization in propagate partial SAD architecture

    Yiqing Huang, Qin Liu, Takeshi Ikenaga

    APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems    2008.11  [Refereed]

    Authorship:Corresponding author

    DOI

  • Early detection algorithms for 8&amp;#x00D7;8 all-zero blocks in H.264/AVC

    Qin Liu, Yiqing Huang, Takeshi Ikenaga

    2008 IEEE 10th Workshop on Multimedia Signal Processing     359 - 362  2008.10  [Refereed]

    Authorship:Corresponding author

     View Summary

    8 x 8 transform has been introduced in H.264&apos;s high profile to improve the video quality. After transform and quantization, if all the coefficients of the block&apos;s residue data become zero, this block is called all-zero block (AZB). Many 4 x 4 transform AZB early detection algorithms have been proposed to skip transform and quantization process. In this paper, after theoretical analysis performed for the sufficient condition of 8 x 8 AZB detection, sum of absolute differences(SAD) and sum of absolute transformed(SATD) based 8 x 8 AZB detection algorithms are proposed. Experimental results show that the proposed algorithms achieve major improvement of computation reduction from 0.95% to 79.48% for 720p sequences. The computation reduction increases as QP increases.

    DOI

  • Optimized 2-D SAD Tree Architecture of Integer Motion Estimation for H.264/AVC

    Yibo FAN, Takeshi Ikenaga, Satoshi Goto

    16th IFIP/IEEE international conference on very large scale integration (VLSI-SoC 2008)    2008.10  [Refereed]

  • Optimization of Propagate Partial SAD and SAD tree motion estimation hardwired engine for H.264

    Zhenyu Liu, Satoshi Goto, Takeshi Ikenaga

    2008 IEEE International Conference on Computer Design    2008.10  [Refereed]

    Authorship:Corresponding author

    DOI

  • Macroblock Feature Based Complexity Reduction for H.264/AVC Motion Estimation

    Yiqing Huang, Qin Liu, Takeshi Ikenaga

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 10 ) 2934 - 2944  2008.10  [Refereed]

    Authorship:Corresponding author

     View Summary

    In H.264/AVC standard, many new techniques Such as variable block size (VBS) and multiple reference frame (MRF) are used in motion estimation (ME) part to achieve superior coding performance, However, the use of new techniques will also cause great burden on computation complexity, which leads to problems in low power hardware implementation. Many software based fast ME algorithms are proposed to reduce complexity. For real-time hardwired encoder, the huge throughput of fractional motion estimation (FME) and integer motion estimation (IME) makes pipeline stage a must. In this case. IME is arranged in a single stage. which deteriorates the efficiency of many software based algorithms. Based on the hardware data flow, this paper provides a complexity reduction algorithm which speeds up ME procedure through three schemes. Firstly, the proposed algorithm executes similarity analysis to detect big mode MB and apply early termination in IME stage. Secondly, for normal MB. motion feature is extracted after IME of each frame and a 6-ring based search range adjustment scheme is introduced to remove redundant search positions. Thirdly, for MBs which have large motion feature, the pixel difference is very small due to the blur effect on video sensor. So, we use sub-sampling technique to reduce computation complexity for such MBs. Experimental results show that. compared with hardware friendly full search algorithm, the proposed fast ME algorithm can reduce 52.63% to 83.21% ME time with negligible video quality degradation. Furthermore, since the proposed algorithm works in a hardware friendly way, it can be embedded into 3-stage real-time hardwired video encoder to achieve low power design.

    DOI

    Scopus

    1
    Citation
    (Scopus)
  • Variable Block Size Motion Vector Retrieval Schemes for H.264 Inter Frame Error Concealment

    Lei Wang, Jun Wang, Satoshi Goto, Takeshi Ikenaga

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 10 ) 2945 - 2953  2008.10  [Refereed]

    Authorship:Corresponding author

     View Summary

    With the ubiquitous application of Internet and wireless networks, H.264 video communication becomes more and more common. However, due to the high-efficiently predictive coding and the variable length entropy coding, it is more sensitive to transmission errors. The current error concealment (EC) scheme, which utilizes the spatial and temporal correlations to conceal the corrupted region, produces unsatisfied boundary artifacts. In this paper, first we propose variable block size error concealment (VBSEC) scheme inspired by variable block size motion estimation (VBSME) in H.264. This scheme provides four EC modes and four sub-block partitions. The whole corrupted macro-block (MB) will be divided into variable block size adaptively according to the actual motion. More precise motion vectors (MV) will be predicted for each sub-block. Then MV refinement (MVR) scheme is proposed to refine the MV of the heterogeneous sub-block by utilizing three step search (TSS) algorithm adaptively. Both VBSEC and MVR are based on our directional spatio-temporal boundary matching algorithm (DSTBMA). By utilizing these schemes, we can reconstruct the corrupted MB in the inter frame more accurately. The experimental results show that our proposed scheme can obtain better objective and subjective EC quality, respectively compared with the boundary matching algorithm (BMA) adopted in the JM 11.0 reference software, spatio-temporal boundary matching algorithm (STBMA) and other comparable EC methods.

    DOI

    Scopus

    1
    Citation
    (Scopus)
  • Standard Deviation and Intra Prediction Mode Based Adaptive Spatial Error Concealment (SEC) in H.264/AVC

    Jun Wang, Lei Wang, Takeshi Ikenaga, Satoshi Goto

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 10 ) 2954 - 2962  2008.10  [Refereed]

     View Summary

    Transmission of compressed video over error prone channels may result in packet losses or errors, which can significantly degrade the image quality. Therefore an error concealment scheme is applied at the video receiver side to mask the damaged video. Considering there are 3 types of MBs (Macro Blocks) in natural video frame, i.e., Textural MB. Edged MB, and Smooth MB, this paper proposes an adaptive spatial error concealment which can choose 3 different methods for these 3 different MBs. For criteria of choosing appropriate method, 2 factors are taken into consideration. Firstly, standard deviation of our proposed edge statistical model is exploited. Secondly, some new features of latest video compression standard H.264/AVC. i.e.. intra prediction mode is also considered for criterion formulation. Compared with previous works. which are only based on deterministic measurement, proposed method achieves the best image recovery. Subjective and objective image quality evaluations in experiments confirmed this.

    DOI

    Scopus

    5
    Citation
    (Scopus)
  • 適応的な画素間引きと計算予測打ち切りによる超低計算量動き検出アルゴリズム

    平塚 誠一郎, 後藤 敏, 池永 剛

    電子情報通信学会論文誌D   Vol. J91-D ( No. 8 ) 2080 - 2088  2008.08  [Refereed]

    Authorship:Corresponding author

  • Fast VBSME Design using Reconfigurable Hardware Architecture and Search Range Reduction

    Yibo Fan, Takeshi Ikenaga, Satoshi Goto

    The 10th IASTED International Conference on Signal and Image Processing (SIP 2008)    2008.08  [Refereed]

  • Half Pixel Cost Distribution based Simplified Fractional Motion Estimation

    Yiqing Huang, Qin Liu, Takeshi Ikenaga

    The 10th IASTED International Conference on Signal and Image Processing (SIP 2008)    2008.08  [Refereed]

    Authorship:Corresponding author

  • VLSI Oriented Group-based Algorithm for Multiply reference Frame Fractional Motion Estimation in H.264/AVC

    Wenqi You, Yao Ma, Yang Song, Yan Zhuang, Takeshi Ikenaga, S. Goto

    The 10th IASTED International Conference on Signal and Image Processing (SIP 2008)    2008.08  [Refereed]

  • 4 x 4 SAD and SATD based all Zero Block Detection Algorithm in H.264/AVC

    Qin Liu, Yiqing Huang, Takeshi Ikenaga

    The 10th IASTED International Conference on Signal and Image Processing (SIP 2008)    2008.08  [Refereed]

  • Bandwidth Reduction Schemes for MPEG-2 to H.264 Transcoder Design

    Xianghui Wei, Wenqi You, Gui-fen Tian, Yan Zhuang, Takeshi Ikenaga, Satoshi Goto

    16th European Signal Processing Conference (EUSIPCO 2008)    2008.08  [Refereed]

  • Edge block detection and motion vector information based fast VBSME algorithm

    Qin Liu, Yiqing Huang, Satoshi Goto, Takeshi Ikenaga

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 8 ) 1935 - 1943  2008.08  [Refereed]

    Authorship:Corresponding author

     View Summary

    Compared with previous standards, H.264/AVC adopts variable block size motion estimation (VBSME) and multiple reference frames (MRF) to improve the video quality. Full search motion estimation algorithm (FS), which calculates every search candidate in the search window for 7 block type with multiple reference frames, consumes massive computation power. Mathematical analysis reveals that the aliasing problem of subsampling algorithm comes from high frequency signal components. Moreover, high frequency signal components are also the main issues that make MRF algorithm essential. As we know, a picture being rich of texture must contain lots of high frequency signals. So based on these mathematical investigations, two fast VBSME algorithms are proposed in this paper, namely edge block detection based subsampling method and motion vector based MRF early termination algorithm. Experiments show that strong correlation exists among the motion vectors of those blocks belonging to the same macroblock. Through exploiting this feature, a dynamically adjustment of the search ranges of integer motion estimation is proposed in this paper. Combing our proposed algorithms with UMHS almost saves 96-98% Integer Motion Estimation (IME) time compared to the exhaustive search algorithm. The induced coding quality loss is less than 0.8% bitrate increase or 0.04 dB PSNR decline on average.

    DOI

    Scopus

    3
    Citation
    (Scopus)
  • Content-aware fast motion estimation for H.264/AVC

    Zhenyu Liu, Satoshi Goto, Takeshi Ikenaga

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 8 ) 1944 - 1952  2008.08  [Refereed]

    Authorship:Corresponding author

     View Summary

    The key to high performance in video coding lies on efficiently reducing the temporal redundancies. For this purpose, H.264/AVC coding standard has adopted variable block size motion estimation on multiple reference frames to improve the coding gain. However, the computational complexity of motion estimation is also increased in proportion to the product of the reference frame number and the intermode number. The mathematical analysis in this paper reveals that the prediction errors mainly depend on the image edge gradient amplitude and quantization parameter. Consequently, this paper proposes the image content based early termination algorithm, which outperforms the original method adopted by JVT reference software, especially at high and moderate bit rates. In light of rate-distortion theory, this paper also relates the homogeneity of image to the quantization parameter. For the homogenous block, its search computation for futile reference frames and intermodes can be efficiently discarded. Therefore, the computation saving performance increases with the value of quantization parameter. These content based fast algorithms were integrated with Unsymmetrical-cross Multihexagon-grid Search (UMHexagonS) algorithm to demonstrate their performance. Compared to the original UMHexagonS fast matching algorithm, 26.14-54.97% search time can be saved with an average of 0.0369 dB coding quality degradation.

    DOI

    Scopus

    3
    Citation
    (Scopus)
  • 8x8 transformation based all zero block detection for H.264/AVC encoder

    Jia Su, Qin Liu, Satoshi Goto, Takeshi Ikenaga

    The 23rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2008)    2008.07  [Refereed]

    Authorship:Corresponding author

  • A Novel Rate Control Algorithm for H.264/AVC

    Zhao Min, Takeshi Ikenaga, Satoshi Goto

    The 23rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2008)    2008.07  [Refereed]

  • A Power-Saving 1GBPS Irregular LDPC Decoder based on High-Efficiency Message-Passing

    Wenming Tang, Wen Ji, Xianghui Wei, Takeshi Ikenaga, Satoshi Goto

    The 23rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2008)    2008.07  [Refereed]

  • A Resource Preserved MAC Protocol for QoS Provided UWB Ad Hoc Network

    Jiachen Zhou, Yiqing Huang, Takeshi Ikenaga

    The 23rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2008)    2008.07  [Refereed]

    Authorship:Corresponding author

  • An Extended Small Diamond Search Algorithm for Fast Block Motion Estimation

    Chang-Uk Jeong, Takeshi Ikenaga, Satoshi Goto

    The 23rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2008)    2008.07  [Refereed]

  • A Low-cost Reconfigurable Architecture for AES Algorithm

    Yibo Fan, Takeshi Ikenaga, Satoshi Goto

    International Conference on Information and Communications Security (ICICS 2008)    2008.07  [Refereed]

  • Hardware-oriented direction-based fast fractional motion estimation algorithm in H.264/AVC

    Yang Song, Yao Ma, Zhenyu Liu, Takeshi Ikenaga, Satoshi Goto

    2008 IEEE International Conference on Multimedia and Expo    2008.06  [Refereed]

    DOI

  • Fast motion estimation for H.264/AVC using image edge features

    Zhenyu Liu, Satoshi Goto, Takeshi Ikenaga

    2008 IEEE International Conference on Multimedia and Expo    2008.06  [Refereed]

    Authorship:Corresponding author

    DOI

  • High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction

    Tianruo Zhang, Shen Li, Guifen Tian, Takeshi Ikenaga, Satoshi Goto

    2008 International Conference on Communications, Circuits and Systems    2008.05  [Refereed]

    DOI

  • モバイル向け0.3mW 1.4mm2 動き検出プロセッサLSI

    平塚 誠一郎, 後藤 敏, 池永 剛

    電子情報通信学会論文誌C   Vol. J91-C ( No. 5 ) 304 - 310  2008.05  [Refereed]

    Authorship:Corresponding author

  • VLSI friendly computation reduction scheme in H.264/AVC motion estimation

    Yiqing Huang, Satoshi Goto, Takeshi Ikenaga

    2008 IEEE International Symposium on Circuits and Systems    2008.05  [Refereed]

    Authorship:Corresponding author

    DOI

  • Motion feature and Hadamard coefficient-based fast multiple reference frame motion estimation for H.264

    Zhenyu Liu, Lingfeng Li, Yang Song, Shen Li, Satoshi Goto, Takeshi Ikenaga

    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY   18 ( 5 ) 620 - 632  2008.05  [Refereed]

    Authorship:Corresponding author

     View Summary

    In the state-of-the-art video coding standard&apos;, H.264/AVC, the encoder is allowed to search for its prediction signals among a large number of reference pictures that have been decoded and stored in the decoder to enhance its coding efficiency. Therefore, the computation complexity of the motion estimation (ME) increases linearly with the number of reference picture. Many fast multiple reference frame ME algorithms have been proposed, whose performance, however, will be considerably degraded in the hardwired encoder design due to the macroblock (MB) pipelining architecture. Considering the limitations of the traditional four-stage MB pipelining architecture, two fast multiple reference frame ME algorithms are proposed here. First, on the basis of mathematical analysis, which reveals that the efficiency of multiple reference frames will be degraded by the relative motion between the camera and the objects, for the slow-moving MB, the authors adopt the multiple reference frames but reduce their search range. On the other hand, for the fast-moving MB, the first previous reference frame is used with the full search range during the ME processing. The mutually exclusive feature between the large search range and the multiple reference frames makes the computation saving performance of the proposed algorithm insensitive to the nature of video sequence. Second, following the Hadamard transform coefficient-based all_zeros block early detection algorithm, two early termination criteria are proposed. These methods ensure the pronounced computation saving efficiency when the encoded video has strong spatial homogeneity or temporal stationarity. Experimental results show that 72.7%-93.7% computation can be saved by the proposed fast algorithms with an average of 0.0899 dB coding quality degradation. Moreover, these fast algorithms can be combined with fast block matching algorithms to further improve their speedup performance.

    DOI

    Scopus

    29
    Citation
    (Scopus)
  • Efficiency-Complexity Curve Based Method for Evaluating Adaptive Search Range Algorithms in Motion Estimation

    Zhenxing Chen, Takeshi Ikenaga, Satoshi Goto

    2008 Congress on Image and Signal Processing    2008.05  [Refereed]

    DOI

  • A Video Quality Preserved Fast Motion Estimation Algorithm for H.264/AVC

    Wenqi You, Yang Song, Takeshi Ikenaga, Satoshi Goto

    Congress on Image and Signal Processing (CISP 2008)    2008.05  [Refereed]

  • A 41 mW VGA@30 fps quadtree video encoder for video surveillance systems

    Qin Liu, Seiichiro Hiratsuka, Kazunori Shimizu, Shinsuke Ushiki, Satoshi Goto, Takeshi Ikenaga

    IEICE TRANSACTIONS ON ELECTRONICS   E91C ( 4 ) 449 - 456  2008.04  [Refereed]

    Authorship:Corresponding author

     View Summary

    Video surveillance systems have a huge market, as indicated by the number of installed cameras, particularly for low-power systems. In this paper, we propose a low-power quadtree video encoder for video surveillance systems. It features a low-complexity motion estimation algorithm, an application-specific ME-MC processor, a dedicated quadtree encoder engine and a processor control-based clock-gating technique. A chip capable of encoding 30 fps VGA (640 x 480) at 80 MHz is fabricated using 0.18 mu m CMOS technology. A total of 153 K gates with 558 kbits SRAM have been integrated into a 5.0 mm x 3.5 mm die. The power consumption is 40.87 mW at 80 MHz for VGA at 30 fps and 1.97 mW at 3.3 MHz for QCIF at 15 fps.

    DOI

  • Reconfigurable variable block size motion estimation architecture for search range reduction algorithm

    Yibo Fan, Takeshi Ikenaga, Satoshi Goto

    IEICE TRANSACTIONS ON ELECTRONICS   E91C ( 4 ) 440 - 448  2008.04  [Refereed]

     View Summary

    Variable Block Size Motion Estimation (VBSME) costs a lot of computation during video coding. Search range reduction algorithm is widely used to reduce computational cost of motion estimation. Current VBSME designs are not suitable for this algorithm. This paper proposes a reconfigurable design of VBSME which can be efficiently used with search range reduction algorithm. While using proposed design, n x m reference MBs form an MB array which can be processed in parallel. n and m can be configured according to the new search range shape calculated by algorithm. In this way, the parallelism of proposed design is very flexible and can be adapted to any search range shape. The hardware resource is also fully used while performing VBSME. There are two primary reconfigurable modules in this design: PEGA (PE Group Array) and SAD comparator. By using TSMC 0.18 mu m standard cell library, the implementation results show that the hardware cost of design which uses 16 PEGs (PE Groups) is about 179 K Gates, the clock frequency is 167 MHz.

    DOI

  • Low power LDPC code decoder architecture based on intermediate message compression technique

    Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 4 ) 1054 - 1061  2008.04  [Refereed]

     View Summary

    Reducing the power dissipation for LDPC code decoder is a major challenging task to apply it to the practical digital communication systems. In this paper, we propose a low power LDPC code decoder architecture based on an intermediate message-compression technique which features as follows: (i) An intermediate message compression technique enables the decoder to reduce the required memory capacity and write power dissipation. (H) A clock gated shift register based intermediate message memory architecture enables the decoder to decompress the compressed messages in a single clock cycle while reducing the read power dissipation. The combination of the above two techniques enables the decoder to reduce the power dissipation while keeping the decoding throughput. The simulation results show that the proposed architecture improves the power efficiency up to 52% and 18% compared to that of the decoder based on the overlapped schedule and the rapid convergence schedule without the proposed techniques respectively.

    DOI

    Scopus

  • A high-speed design of Montgomery multiplier

    Yibo Fan, Takeshi Ikenaga, Satoshi Goto

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 4 ) 971 - 977  2008.04  [Refereed]

     View Summary

    With the increase of key length used in public cryptographic algorithms such as RSA and ECC, the speed of Montgomery multiplication becomes a bottleneck. This paper proposes a high speed design of Montgomery multiplier. Firstly, a modified scalable high-radix Montgomery algorithm is proposed to reduce critical path. Secondly, a high-radix clock-saving dataflow is proposed to support high-radix operation and one clock cycle delay in dataflow. Finally, a hardware-reused architecture is proposed to reduce the hardware cost and a parallel radix-16 design of data path is proposed to accelerate the speed. By using HHNEC 0.25 mu m standard cell library, the implementation results show that the total cost of Montgomery multiplier is 130 KGates, the clock frequency is 180 MHz and the throughput of 1024-bit RSA encryption is 352 kbps. This design is suitable to be used in high speed RSA or ECC encryption/decryption. As a scalable design, it supports any key-length encryption/decryption up to the size of OD-chip memory.

    DOI

    Scopus

    4
    Citation
    (Scopus)
  • Adaptive search range algorithms for variable block size motion estimation in H.264/AVC

    Zhenxing Chen, Yang Song, Takeshi Ikenaga, Satoshi Goto

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 4 ) 1015 - 1022  2008.04  [Refereed]

     View Summary

    Comparing with search pattern motion estimation (ME) algorithms, adaptive search range (ASR) algorithms are more fundamental, regular and flexible. In variable block size motion estimation (VBSME), ASR algorithms can be applied whether on a whole frame (frame level), or on an entire macroblock which includes up to forty-one blocks (macroblock level), or just on a single block (block level). In the other hand, in H.264/AVC, not the motion vectors (MVs) but the motion vector differences (MVDs) are coded and the median motion vector predictors (median-MVPs) are used to place the search centers. In this sense, it can be thought that the search windows (SWs) are centered at the positions pointed by median-MVPs, the search ranges (SRs) play the role of limiting MVDs. Thus it is reasonable for considering using MVDs to predict SRs. In this paper, one of the MB level and two of the block level, at all three MVD based SR prediction algorithms are proposed. VBSME based experiments are carried out to assess the proposed algorithms. Comparisons between the proposed three algorithms and the previously proposed one given in [8] are done in terms of encoding quality and computational complexity.

    DOI

    Scopus

    9
    Citation
    (Scopus)
  • Parallel improved HDTV720p targeted propagate partial SAD architecture for variable block size motion estimation in H.264/AVC

    Yiqing Huang, Zhenyu Liu, Yang Song, Satoshi Goto, Takeshi Ikenaga

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 4 ) 987 - 997  2008.04  [Refereed]

    Authorship:Corresponding author

     View Summary

    One hardware efficient and high speed architecture for variable block size motion estimation (VBSME) in H.264 is presented in this paper. By improving the pipeline structure and processing element (PE) circuits, the system latency and hardware cost is reduced, which makes this structure more hardware efficient than the original Propagate Partial SAD architecture. For small and middle frame size picture's coding, the proposed structure can save 12.1% hardware cost compared with original Propagate Partial SAD structure. In the case of HDTV, since small inter modes trivially contribute to the coding quality, we remove modes below 8 x 8 in our design. By adopting mode reduction technique, when the set number of PE array is less than 8, the proposed mode reduction based Propagate Partial SAD structure can work at faster clock speed and consume less hardware cost than widely used SAD Tree architecture. It is more robust to the high speed timing constraint when parallel processing is considered. With TSMC 0.18 mu m technology in worst work conditions (1.62 V, 125 degrees C), its peak throughput of 8-set PE array structure is 720p@30 Hz with 128 x 64 search range and 5 reference frames. 12 k gates hardware cost can be reduced by our design compared with the parallel SAD Tree architecture.

    DOI

    Scopus

    10
    Citation
    (Scopus)
  • High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule

    Wen Ji, Xing Li, Takeshi Ikenaga, Satoshi Goto

    2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)    2008.04  [Refereed]

    DOI

  • A hardware/software co-solution to achieving high throughput required by motion estimation part in H.264/AVC HDTV real-time application

    Zhenxing Chen, Takeshi Ikenaga, Satoshi Goto

    2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)    2008.04  [Refereed]

    DOI

  • Rate Estimation in RDO of H.264/AVC

    Yan Zhuang, Takeshi Ikenaga, Satoshi Goto

    第21回回路 とシステム軽井沢ワークショップ    2008.04  [Refereed]

  • SAD Accumulation Termination Algorithm and Early Loop Termination Decision based High Quality Fast Motion Estimation for H.264/AVC

    Wenqi You, Yang Song, Xianghui Wei, Takeshi Ikenaga, Satoshi Goto

    第21回回路 とシステム軽井沢ワークショップ    2008.04  [Refereed]

  • A Low-cost LSI Design of AES against DPA Attack by Hiding Power Information

    Yibo Fan, Takeshi Ikenaga, Yukiyasu Tsunoo, Satoshi Goto

    第21回回路 とシステム軽井沢ワークショップ    2008.04  [Refereed]

  • High-throughput design of high-efficiency message passing partially parallel irregular-LDPC decoder based on 802.11n

    Yuta Abe, Xing Li, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto

    International Conference in Embedded Systems and Intelligent Technology (ICESIT 2008)    2008.02  [Refereed]

  • A High Quality Fast Motion Estimation Algorithm for H.264/AVC

    Wenqi You, Yang Song, Takeshi Ikenaga, Satoshi Goto

    2008 Congress on Image and Signal Processing    2008  [Refereed]

    DOI

  • An unequal secure encryption scheme for H.264/AVC video compression standard

    Yibo Fan, Jidong Wang, Takeshi Ikenaga, Yukiyasu Tsunoo, Satoshi Goto

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 1 ) 12 - 21  2008.01  [Refereed]

     View Summary

    H.264/AVC is the newest video coding standard. There are many new features in it which can be easily used for video encryption. In this paper, we propose a new scheme to do video encryption for H.264/AVC video compression standard. We define Unequal Secure Encryption (USE) as an approach that applies different encryption schemes (with different security strength) to different parts of compressed video data. This USE scheme includes two parts: video data classification and unequal secure video data encryption. Firstly, we classify the video data into two partitions: Important data partition and unimportant data partition. important data partition has small size with high secure protection, while unimportant data partition has large size with low secure protection. Secondly, we use AES as a block cipher to encrypt the important data partition and use LEX as a stream cipher to encrypt the unimportant data partition. AES is the most widely used symmetric cryptography which can ensure high security. LEX is a new stream cipher which is based on AES and its computational cost is much lower than AES. In this way,our scheme can achieve both high security and low computational cost. Besides the USE scheme, we propose a low cost design of hybrid AES/LEX encryption module. Our experimental results show that the computational cost of the USE scheme is low (about 25% of naive encryption at Level 0 with VEA used). The hardware cost for hybrid AES/LEX module is 4678 Gates and the AES encryption throughput is about 50 Mbps.

    DOI

  • Hardware Evaluation of eSTREAM Stream Cipher Candidates in Phase 3 Profile 2: Moustique, Pomaranch and Decim v2

    Yibo Fan, Jidong Wang, Takeshi Ikenaga, Yukiyasu Tsunoo, Satoshi Goto

    Symposium on Cryptography and Information Security (SCIS2008)    2008.01  [Refereed]

  • A Hardware Architecture of CABAC Encoding and Decoding with Dynamic Pipeline for H.264/AVC

    Lingfeng Li, Yang Song, Shen Li, Takeshi Ikenaga, Satoshi Goto

    Journal of Signal Processing Systems   50 ( 1 ) 81 - 95  2008.01  [Refereed]

    DOI

    Scopus

    9
    Citation
    (Scopus)
  • A cost-efficient partially-parallel irregular LDPC decoder based on sum-delta message passing algorithm

    Wen Ji, Yuta Abe, Takeshi Ikenaga, Satoshi Goto

    Proceedings of the 18th ACM Great Lakes symposium on VLSI - GLSVLSI '08    2008  [Refereed]

    DOI

  • Rate Estimation of RD Optimization for Intra Mode Decision of H.264/AVC

    Yan Zhuang, Takeshi Ikenaga, Satoshi Goto

    2008 Congress on Image and Signal Processing    2008  [Refereed]

    DOI

  • A Hardware-Oriented High Precision Motion Vector Prediction Scheme for MPEG-2 to H.264 Transcoding

    Xianghui Wei, Wenming Tang, Guifen Tian, Takeshi Ikenaga, Satoshi Goto

    2008 Congress on Image and Signal Processing    2008  [Refereed]

    DOI

  • Adaptive Motion Vector Retrieval Schemes for H.264 Error Concealment

    Lei Wang, Jun Wang, Satoshi Goto, Takeshi Ikenaga

    2008 Congress on Image and Signal Processing    2008  [Refereed]

    DOI

  • An Efficient Fast Mode Decision Algorithm for H.264/AVC Intra Prediction

    Guifen Tian, Tianruo Zhang, Xianghui Wei, Takeshi Ikenaga, Satoshi Goto

    2008 Congress on Image and Signal Processing    2008  [Refereed]

    DOI

  • Adaptive Subsampling and Motion Feature Based Fast H.264 Motion Estimation

    Yiqing Huang, Qin Liu, Satoshi Goto, Takeshi Ikenaga

    2008 Congress on Image and Signal Processing    2008  [Refereed]

    Authorship:Corresponding author

    DOI

  • Aliasing Error Reduction Based Fast VBSME Algorithm

    Qin Liu, Yiqing Huang, Satoshi Goto, Takeshi Ikenaga

    2008 Congress on Image and Signal Processing    2008  [Refereed]

    Authorship:Corresponding author

    DOI

  • Adaptive spatial error concealment (SEC) with more accurate MB type decision in H.264/AVC

    Jun Wang, Lei Wang, T. Ikenaga, S. Goto

    5th International Conference on Visual Information Engineering (VIE 2008)    2008  [Refereed]

    DOI

    Scopus

    1
    Citation
    (Scopus)
  • An adaptive spatial error concealment for H.264/AVC video stream

    Jun Wang, Lei Wang, Takeshi Ikenaga, Satoshi Goto

    SIGMAP 2008: PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND MULTIMEDIA APPLICATIONS     23 - 28  2008  [Refereed]

     View Summary

    Transmission of compressed video over error prone channels may result in packet losses or errors, which can significantly degrade the image quality. Therefore an error concealment scheme is applied at the video receiver side to mask the damaged video. Considering there are 3 types of MBs (Macro Blocks) in natural video frame, i.e., Textural MB, Edged MB, and Smooth MB, this paper proposes an adaptive spatial error concealment which can choose 3 different methods for these 3 different MBs. For criteria of choosing appropriate method, 2 factors are taken into consideration. Firstly, standard deviation of our proposed edge statistical model is exploited. Secondly, some new features of latest video compression standard H.264/AVC, i.e., intra prediction mode is also considered for criterion formulation. Compared with previous works, which are only based on deterministic measurement, proposed method achieves the best image recovery. Subjective and objective image quality evaluations in experiments confirmed this.

  • A motion vector difference based self-incremental adaptive search range algorithm for variable block size motion estimation

    Zhenxing Chen, Qin Liu, Takeshi Ikenaga, Satoshi Goto

    2008 15th IEEE International Conference on Image Processing    2008  [Refereed]

    DOI

  • A High Throughput Multiple Transform Architecture for H.264/AVC Fidelity Range Extensions

    Yao Ma, Yang Song, Takeshi Ikenaga, Satoshi Goto

    JSTS:Journal of Semiconductor Technology and Science   7 ( 4 ) 247 - 253  2007.12  [Refereed]

    DOI

  • A High Throughput Multiple Transform Architecture for H.264/AVC Fidelity Range Extensions

    Yao Ma, Yang Song, Takeshi Ikenaga, Satoshi Goto

    JSTS:Journal of Semiconductor Technology and Science   7 ( 4 ) 247 - 253  2007.12  [Refereed]

    DOI

  • A Novel Dynamic Search Range Decision Method for Variable Block Size Motion Estimation in H.264/AVC

    Zhenxing Chen, Yang Song, Takeshi Ikenaga, Satoshi Goto

    Sixth International Conference on Information, Communications and Signal Processing (ICICS 2007)    2007.12  [Refereed]

  • A New Video Encryption Scheme for H.264/AVC

    Yibo Fan, Jidong Wang, Takeshi Ikenaga, Yukiyasu Tsunoo, Satoshi Goto

    Advances in Multimedia Information Processing – PCM 2007     246 - 255  2007.12  [Refereed]

    DOI

    Scopus

    13
    Citation
    (Scopus)
  • An MRF model-based approach to the detection of rectangular shape objects in color images

    Yangxing Liu, Takeshi Ikenaga, Satoshi Goto

    Signal Processing   87 ( 11 ) 2649 - 2658  2007.11  [Refereed]

    DOI

    Scopus

    30
    Citation
    (Scopus)
  • Rectangle Region Based Stereo Matching for Building Reconstruction

    Jing Wang, Toru Miyazaki, Hirokazu Koizumi, Makoto Iwata, Jongwha Chong, Hiroyuki Yagyu, Hideo Shimazu, Takeshi Ikenaga, Satoshi Goto

    Jornal of Ubiquitous Convergence Technology   Vol. 1 ( No. 1 ) 9 - 17  2007.11  [Refereed]

  • An improved inter frame error concealment in H.264/AVC

    Jun Wang, Lei Wang, Shen Li, Takeshi Ikenaga, Satoshi Goto

    2007 7th International Conference on ASIC    2007.10  [Refereed]

    DOI

  • H.264/AVC Fractional Motion Estimation Engine with Computation Reusing in HDTV1080P Real-Time Encoding Applications

    Yang Song, Ming Shao, Zhenyu Liu, Shen Li, Lingfeng Li, Takeshi Ikenaga, Satoshi Goto

    2007 IEEE Workshop on Signal Processing Systems    2007.10  [Refereed]

    DOI

  • 32-Parallel SAD Tree Hardwired Engine for Variable Block Size Motion Estimation in HDTV1080P Real-Time Encoding Application

    Zhenyu Liu, Yang Song, Ming Shao, Shen Li, Lingfeng Li, Satoshi Goto, Takeshi Ikenaga

    2007 IEEE Workshop on Signal Processing Systems    2007.10  [Refereed]

    Authorship:Corresponding author

    DOI

  • Mixed bus width architecture for low cost AES VLSI design

    Yibo Fan, Jidong Wang, Takeshi Ikenaga, Satoshi Goto

    2007 7th International Conference on ASIC    2007.10  [Refereed]

    DOI

  • A partial scramble scheme for H.264 video

    Jidong Wang, Yibo FaN, Takeshi Ikenaga, Satoshi Goto

    2007 7th International Conference on ASIC    2007.10  [Refereed]

    DOI

  • Unequal error protected transmission with dynamic classification in H.264/AVC

    Jun Wang, Shen Li, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto

    2007 7th International Conference on ASIC    2007.10  [Refereed]

    DOI

  • Cost efficient propagate partial SAD architecture for integer motion estimation in H.264/AVC

    Yiqing Huang, Zhenyu Liu, Satoshi Goto, Takeshi Ikenaga

    2007 7th International Conference on ASIC    2007.10  [Refereed]

    Authorship:Corresponding author

    DOI

  • A 41mW VGA@30fps quadtree video encoder for video surveillance systems

    Qin Liu, Seiichiro Hiratsuka, Satoshi Goto, Takeshi Ikenaga

    2007 7th International Conference on ASIC    2007.10  [Refereed]

    Authorship:Corresponding author

    DOI

  • Video Compression LSI: Past, Present, and Future Trends

    Takeshi Ikenaga

    The 7th International Conference on ASIC (ASICON2007)    2007.10  [Invited]

    Authorship:Lead author

  • Efficient fully-parallel LDPC decoder design with improved simplified min-sum algorithms

    Qi Wang, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto

    IEICE TRANSACTIONS ON ELECTRONICS   E90C ( 10 ) 1964 - 1971  2007.10  [Refereed]

     View Summary

    In this paper we introduce an area and power efficient fully-parallel LDPC decoder design, which keeps the BER performance while consuming less hardware resources and lower power compared with conventional decoders. For this decoder, we firstly propose two improved simplified min-sum algorithms, which enable the decoder to reduce the hardware implementation complexity and area: hardware consumption of check operation module is reduced by 40%, while achieving a negligible performance loss compared with the general min-sum algorithm. To reduce the power dissipation of the decoder, we also proposed a power-saved strategy according to which the message evolution halts as the parity-check condition is satisfied. This strategy reduces more than 50% power under food channel condition. The synthesis result in 0.18 mu m CMOS technology shows our decoder based on (648,540) irregular LDPC code of WLAN (802.11n) protocol achieves 8 10 [Mbps] throughput with 283 [mW] power consumption.

    DOI

  • Edge Gradient Based Fast Inter Motion Estimation for H.264/AVC

    Zhenyu Liu, Yang Song, Yiqing Huang, Lingfeng Li, Satoshi Goto, Takeshi Ikenaga

    2007 5th International Symposium on Image and Signal Processing and Analysis    2007.09  [Refereed]

    Authorship:Corresponding author

    DOI

  • Cost-Efficient Partially-Parallel Irregular LDPC Decoder with Message Passing Schedule

    Xing Li, Yuta Abe, Kazunori Shimizu, Zhen Qiu, Takeshi Ikenaga, Satoshi Goto

    2007 International Symposium on Integrated Circuits    2007.09  [Refereed]

    DOI

  • Partially-parallel irregular LDPC decoder based on improved message passing schedule

    Xing Li, Kazunori Shimizu, Zhen Qiu, Takeshi Ikenaga, Satoshi Goto

    2007 50th Midwest Symposium on Circuits and Systems    2007.08  [Refereed]

    DOI

  • Ultra Low-Complexity Fast Variable Block Size Motion Estimation Algorithm in H.264/AVC

    Yang Song, Zhenyu Liu, Takeshi Ikenaga, Satoshi Goto

    Multimedia and Expo, 2007 IEEE International Conference on    2007.07  [Refereed]

    DOI

    Scopus

    5
    Citation
    (Scopus)
  • VLSI Oriented Fast Multiple Reference Frame Motion Estimation Algorithm for H.264/AVC

    Zhenyu Liu, Lingfeng Li, Yang Song, Takeshi Ikenaga, Satoshi Goto

    Multimedia and Expo, 2007 IEEE International Conference on    2007.07  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

    5
    Citation
    (Scopus)
  • Adaptive Edge Detection Pre-Process Multiple Reference Frames Motion Estimation in H.264/AVC

    Yiqing Huang, Zhenyu Liu, S. Goto, T. Ikenaga

    2007 International Conference on Communications, Circuits and Systems    2007.07  [Refereed]

    Authorship:Corresponding author

    DOI

  • Two-Steps Cross-Diamond Fast Search Algorithm on Motion Estimation in H.264

    Qin Liu, S. Hiratsuka, S. Goto, T. Ikenaga

    2007 International Conference on Communications, Circuits and Systems    2007.07  [Refereed]

    Authorship:Corresponding author

    DOI

  • A 1.41W H.264/AVC Real-Time Encoder SOC for HDTV1080P

    Zhenyu Liu, Yang Song, Ming Shao, Shen Li, Lingfeng Li, Shunichi Ishiwata, Masaki Nakagawa, Satoshi Goto, Takeshi Ikenaga

    2007 IEEE Symposium on VLSI Circuits     12 - 13  2007.06  [Refereed]

    Authorship:Corresponding author

     View Summary

    A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30fps is implemented with the dedicated hardware engines and one 32-bit Media embedded Processor (MeP) equipped with hardware extensions. The 11.5Gbps 64Mb Svstem-in-Silicon DRAMA is embedded to alleviate the external memory bandwidth. With TSMC 0.18 mu m CMOS technology, the SoC core occupies 27.1mm(2) die area and consumes 1.41W at 200MHz in typical work conditions.

    DOI

  • Enhanced Strict Multilevel Successive Elimination Algorithm for Fast Motion Estimation

    Yang Song, Zhenyu Liu, Takeshi Ikenaga, Satoshi Goto

    2007 IEEE International Symposium on Circuits and Systems    2007.05  [Refereed]

    DOI

    Scopus

    4
    Citation
    (Scopus)
  • Hardware Architecture Design of CABAC Codec for H.264/AVC

    Lingfeng Li, Yang Song, Takeshi Ikenaga, Satoshi Goto

    2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)    2007.04  [Refereed]

    DOI

  • A Power-Saved 1Gbps Irregular LDPC Decoder based on Simplified Min-Sum Algorithm

    Qi WANG, Kazunori SHIMIZU, Takeshi IKENAGA, Satoshi GOTO

    2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)    2007.04  [Refereed]

    DOI

  • Lossless VLSI Oriented Full Computation Reusing Algorithm for H.264/AVC Fractional Motion Estimation

    M. SHAO, Z. LIU, S. GOTO, T. IKENAGA

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E90-A ( 4 ) 756 - 763  2007.04  [Refereed]

    Authorship:Corresponding author

    DOI CiNii

    Scopus

    10
    Citation
    (Scopus)
  • Lossy strict multilevel successive elimination algorithm for fast motion estimation

    Yang Song, Zhenyu Liu, Takeshi Ikenaga, Satoshi Goto

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E90A ( 4 ) 764 - 770  2007.04  [Refereed]

     View Summary

    This paper presents simple and effective method to further reduce the search points in multilevel successive elimination algorithm (MSEA). Because the calculated sea values of those best matching search points are much smaller than the current minimum SAD, we can simply increase the calculated sea values to increase the elimination ratio without much affecting the coding quality. Compared with the original MSEA algorithm, the proposed strict MSEA algorithm (SMSEA) can provide average 6.52 times speedup. Compared with other lossy fast ME algorithms such as TSS and DS, the proposed SMSEA can maintain more stable image quality. In practice, the proposed technique can also be used in the fine granularity SEA (FGSEA) algorithm and the calculation process is almost the same.

    DOI

    Scopus

    12
    Citation
    (Scopus)
  • An Efficient Encryption Scheme for H.264 Format Video Streams

    Jidong Wang, Yibo Fan, Takeshi Ikenaga, Satoshi Goto

    第20回回路 とシステム軽井沢ワークショップ    2007.04  [Refereed]

  • Motion-content based Search Range Prediction in Variable Block Size Motion Estimation

    ZhenXing Chen, Yang Song, Takeshi Ikenaga, Satoshi Goto

    第20回回路 とシステム軽井沢ワークショップ    2007.04  [Refereed]

  • Fragmented Edges Grouping for Monocular Building Extraction

    Jing Wang, Makoto Iwata, Hirokazu Koizumi, Hideo Shimazu, Satoshi Goto, Takeshi Ikenaga

    第20回回路 とシステム軽井沢ワークショップ    2007.04  [Refereed]

  • A real-time parallel architecture for human face detection based on the Algorithm Architecture Adequation approach

    Dmitriev Ivan, Grandpierre Thierry, Akil Mohamed, Ghorayeb Hicham, Satoshi Goto, Takeshi Ikenaga

    第20回回路 とシステム軽井沢ワークショップ    2007.04  [Refereed]

    Authorship:Corresponding author

  • A dynamic search range algorithm for variable block size motion estimation in H.264/AVC

    ZhenXing Chen, Yang Song, Takeshi Ikenaga, Satoshi Goto

    2007 6th International Conference on Information, Communications &amp; Signal Processing    2007  [Refereed]

    DOI

  • No Compression Ratio Reduction H.264 Video Scrambling

    Jidon Wang, Yibo Fan, Xiaoyang Zeng, Takeshi Ikenaga, Satoshi Goto

    Symposium on Cryptography and Information Security (SCIS2007)   3B3-1  2007.01  [Refereed]

  • Hardware Reuse Architecture for High-Radix Scalable Montgomery Multiplier

    Yibo Fan, Xiaoyang Zeng, Takeshi Ikenaga, Satoshi Goto

    Symposium on Cryptography and Information Security (SCIS2007)   2E2-1  2007.01  [Refereed]

  • Low-power partial distortion sorting fast motion estimation algorithms and VLSI implementations

    Yang Song, Zhenyu Liu, Takeshi Ikenaga, Satoshi Goto

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS   E90D ( 1 ) 108 - 117  2007.01  [Refereed]

     View Summary

    This paper presents two hardware-friendly low-power oriented fast motion estimation (ME) algorithms and their VLSI implementations. The basic idea of the proposed partial distortion sorting (PDS) algorithm is to disable the search points which have larger partial distortions during the ME process, and only keep those search points with smaller ones. To further reduce the computation overhead, a simplified local PDS (LPDS) algorithm is also presented. Experiments show that the PDS and LPDS algorithms can provide almost the same image quality as full search only with 36.7% computation complexity. The proposed two algorithms can be integrated into different FSBMA architectures to save power consumption. In this paper, the 1-D inter ME architecture [12] is used as an detailed example. Under the worst working conditions (1.62 V, 125 degrees C) and 166 MHz clock frequency, the PDS algorithm can reduce 33.3% power consumption with 4.05 K gates extra hardware cost, and the LPDS can reduce 37.8% power consumption with 1.73 K gates overhead.

    DOI

  • Content-based complexity reduction methods for MPEG-2 to H.264 transcoding

    Shen Li, Lingfeng Li, Takeshi Ikenaga, Shunichi Ishiwata, Masataka Matsui, Satoshi Goto

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS   E90D ( 1 ) 90 - 98  2007.01  [Refereed]

     View Summary

    The coexistence of MPEG-2 and its powerful successor H.264/AVC has created a huge need for MPEG-2/H.264 video transcoding. However, a traditional transcoder where an MPEG-2 decoder is simple cascaded to an H.264 encoder requires huge computational power due to the adoption of a complicated rate-distortion based mode decision process in H.264. This paper proposes a 2-D Sobel filter based motion vector domain method and a DCT domain method to measure macroblock complexity and realize content-based H.264 candidate mode decision. A new local edge based fast INTRA prediction mode decision method is also adopted to boost the encoding efficiency. Simulation results confirm that with the proposed methods the computational burden of a traditional transcoder can be reduced by 20% similar to 30% with only a negligible bit-rate increase for a wide range of video sequences.

    DOI

  • Geometrical, physical and text/symbol analysis based approach of traffic sign detection system

    Yangxing Liu, Takeshi Ikenaga, Satoshi Goto

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS   E90D ( 1 ) 208 - 216  2007.01  [Refereed]

     View Summary

    Traffic sign detection is a valuable part of future driver support system. In this paper, we present a novel framework to accurately detect traffic signs from a single color image by analyzing geometrical, physical and text/symbol features of traffic signs. First, we utilize an elaborate edge detection algorithm to extract edge map and accurate edge pixel gradient information. Then, we extract 2-D geometric primitives (circles, ellipses, rectangles and triangles) efficiently from image edge map. Third, the candidate traffic sign regions are selected by analyzing the intrinsic color features, which are invariant to different illumination conditions, of each region circumvented by geometric primitives. Finally, a text and symbol detection algorithm is introduced to classify true traffic signs. Experimental results demonstrated the capabilities of our algorithm to detect traffic signs with respect to different size, shape, color and illumination conditions.

    DOI

  • A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for h.264/avc

    Shen Li, Xianghui Wei, Takeshi Ikenaga, Satoshi Goto

    Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '07    2007  [Refereed]

    DOI

    Scopus

    17
    Citation
    (Scopus)
  • Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC

    Zhenyu Liu, Yiqing Huang, Yang Song, Satoshi Goto, Takeshi Ikenaga

    Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '07    2007  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

    19
    Citation
    (Scopus)
  • Power-efficient LDPC code decoder architecture

    Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

    Proceedings of the 2007 international symposium on Low power electronics and design - ISLPED '07    2007  [Refereed]

    DOI

    Scopus

    3
    Citation
    (Scopus)
  • Parallel CBM Algorithm and Architecture for JPEG 2000 Encoder for Digital Cinema

    Takeshi Ito, Sou Nakamura, Satoshi Goto, Takeshi Ikenaga

    Journal of the Institute of Image Electronics Engineers of Japan   36 ( 5 ) 650 - 656  2007  [Refereed]

    Authorship:Corresponding author

     View Summary

    Since JPEG 2000 is selected as the standard of Digital Cinema, it attracts a great deal of attention. However, JPEG 2000 coding requires huge amount of computational complexity for a high definition image with more than 200 million pixels required in Digital Cinema standard. Especially, EBCOT is a bottleneck because of its difficulty in parallel processing. This paper proposes a parallel coefficient bit modeling (CBM) algorithm which can process a bit plane, a stripe and a pass in parallel and a CBM architecture based on it. Hardware evaluation results show that a 733k Gate (TSMC 0.18 µm) circuit can process the code block (block size 32 × 32, 30 bit planes) which satisfies Digital Cinema standard in real time. © 2007, The Institute of Image Electronics Engineers of Japan. All rights reserved.

    DOI

    Scopus

  • High Quality Image Correction Algorithm with Cubic Interpolation and its Implementation of Dedicated Hardware Engine for Fish-eye Lens

    Takahiro Mori, Satoshi Goto, Takeshi Ikenaga, Motonobu Tonomura, Yuuji Ohsumi

    Journal of the Institute of Image Electronics Engineers of Japan   36 ( 5 ) 680 - 687  2007  [Refereed]

    Authorship:Corresponding author

     View Summary

    This paper proposes an interpolation algorithm and LSI architecture for a camera with a fish-eye lens. Since the fish-eye lens has around 180 degree field of view and a deep depth of field, it's very promising for a surveillance camera, a video conference system, and so on. Combination of a cubic spline interpolation and a direct interpolation from a RAW image enable to obtain high quality image. A three-stage linear interpolation scheme and a dedicate operators boost up processing performance. Evaluation results base on a subjective test show that our proposed algorithm can generate high-quality interpolation image. Furthermore, a dedicated image processing core with 290k gates can process HDTV (1920x1080, 60 fps) image by using 0.18 µm CMOS technology. © 2007, The Institute of Image Electronics Engineers of Japan. All rights reserved.

    DOI

    Scopus

    2
    Citation
    (Scopus)
  • Scale Invariance Based Salient Contour Detection

    Jing Wang, Takeshi Ikenaga, Satoshi Goto

    Journal of the Institute of Image Electronics Engineers of Japan   36 ( 5 ) 710 - 720  2007  [Refereed]

     View Summary

    Contour detection is a fundamental step to scene analysis and interpretation. However, because contours often locate in rich texture background it is still a difficult task in realistic vision. Through multi-scale analysis, it becomes clear that edge responses of real object contours are relatively stable across scales, while those from noise or texture background are not. In this paper, a salient contour detection method is proposed based on the scale invariance of piecewise linear approximation of real object contours. Firstly, an image pyramid is efficiently constructed by repeatedly smoothing and sub-sampling the image. Secondly, the piecewise linear approximation of contours in multiple scales are extracted and then a collinear line grouping process is implemented to improve the connectivity of the contours. Thirdly, the new salient line segments are generated based on the analysis on the stability of line segments across scales. Experimental results show that the proposed method can effectively improve the connectivity and saliency of the contour detection compared with the former method. © 2007, The Institute of Image Electronics Engineers of Japan. All rights reserved.

    DOI

    Scopus

  • A macroblock level adaptive search range algorithm for variable block size motion estimation in H.264/AVC

    Zhenxing Chen, Yang Song, Takeshi Ikenaga, Satoshi Goto

    2007 International Symposium on Intelligent Signal Processing and Communication Systems     618 - +  2007  [Refereed]

     View Summary

    Compared with previous video standards, the computational complexity of H.264/AVC is extraordinarily high due to newly adopted tools such as variable block size motion estimation (VBSME). In VBSME, to each macroblock (MB) there are at all 41 blocks corresponded. These 41 blocks are sized from 4 x 4 through 16 x 16. As each block of these 41 blocks accounts for one independent search window (SW), thus to each MB there exist 41 SWs corresponded. In the other hand, adaptive search range (ASR) algorithms are defined as algorithms which adaptively adjust the search ranges (SRs) and hence result in dynamically reduced SWs. While considering whether 41 SWs got changed in the same way or not, "macroblock level ASR (MB-ASR) algorithms" are defined as algorithms which adaptively change the search range all in-once and hence result in the 41 SWs got changed in the same way. "41 blocks level ASR (block - ASR) algorithms" are defined as algorithms that the changing ways of the SRs are specific to each block of the 41 blocks. Since in MB - ASR algorithms for each MB the SR is changed in same way, it is reasonable to consider that the control overhead of MB - ASR is less than that of block - ASR. In this paper, a MB-ASR algorithm is proposed and assessed from being compared with a previously proposed block - ASR algorithm given in [5]. According to experimental results, it is proved the proposed algorithm provides almost the same encoding quality and even a little better SW reducing efficiency (SW-RE) while compared with [5]. Meanwhile, as a MB - ASR one, the proposed algorithm is considered having less control overhead than block - ASR one - [5].

    DOI

  • Variable block size error concealment scheme based on H.264/AVC non-normative decoder

    Lei Wang, Jun Wang, Satoshi Goto, Takeshi Ikenaga

    2007 International Symposium on Intelligent Signal Processing and Communication Systems    2007  [Refereed]

    Authorship:Corresponding author

    DOI

  • Fast motion estimation algorithm based on edge block detection and motion vector information

    Qin Liu, Zhenxing Chen, Satoshi Goto, Takeshi Ikenaga

    2007 International Symposium on Intelligent Signal Processing and Communication Systems    2007  [Refereed]

    Authorship:Corresponding author

    DOI

  • Hardware friendly background analysis based comtlexity reduction in H.264/AVC multiple reference frames motion estimation

    Yiqing Huang, Zhenyu Liu, Satoshi Goto, Takeshi Ikenaga

    2007 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATION SYSTEMS, VOLS 1 AND 2     614 - 617  2007  [Refereed]

    Authorship:Corresponding author

     View Summary

    In H.264 standard, multiple reference frame motion estimation (MRF-ME) can help to generate small residues and improve the performance. However, MRF-ME is also a computation intensive task for video coding system. Many software oriented fast algorithms have been proposed to shorten MRF-ME process. For hardwired real-time encoder, the division of ME part into two pipeline stages degrades the efficiency of many fast algorithms. This paper gives one hardware friendly MRF-ME algorithm to reduce computation complexity in MRF-ME procedure. The proposed algorithm is based on the analysis of macroblock&apos;s (MB&apos;s) feature and restricts search range for static background MB. Through experiment results, with negligible video quality degradation, the proposed background analysis based MRF-ME algorithm can averagely reduce 41.75% ME time for sequences with static background. Moreover, the proposed algorithm is compatible to other fast algorithms and friendly to hardware implementation of H.264 real-time encoder.

  • Object-oriented unequal loss protection with product codes for wireless video transmission

    Zhen Qui, T. Ikenaga, S. Goto

    IET International Conference on Wireless Mobile and Multimedia Networks Proceedings (ICWMMN 2006)    2006.12  [Refereed]

    DOI

    Scopus

  • A VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization

    Y. SONG, Z. LIU, T. IKENAGA, S. GOTO

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E89-A ( 12 ) 3594 - 3601  2006.12  [Refereed]

    DOI

    Scopus

    15
    Citation
    (Scopus)
  • Power-efficient LDPC decoder architecture based on accelerated message-passing schedule

    Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E89A ( 12 ) 3602 - 3612  2006.12  [Refereed]

     View Summary

    In this paper, we propose a power-efficient LDPC decoder architecture based on an accelerated message-passing schedule. The proposed decoder architecture is characterized as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port SRAMs. (H) FIFO-based buffering reduces the number of SRAM banks and words of the LDPC. decoder based on the accelerated message-passing schedule.. The proposed LDPC decoder keeps a single message for each non-zero bit in a parity check matrix as well as a classical schedule while achieving the accelerated message-passing schedule. Implementation results in 0.18 [mu m] CMOS technology show that the proposed decoder architecture reduces an area of the LDPC decoder by 43% and a power dissipation by 29% compared to the conventional architecture based on the accelerated message-passing schedule.

    DOI

    Scopus

    5
    Citation
    (Scopus)
  • A Fine-Grain Scalable and Low Memory Cost Variable Block Size Motion Estimation Architecture for H.264/AVC

    Z. LIU, Y. SONG, T. IKENAGA, S. GOTO

    IEICE Transactions on Electronics   E89-C ( 12 ) 1928 - 1936  2006.12  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

    21
    Citation
    (Scopus)
  • A Novel Hybrid Approach of Color Image Segmentation

    Yangxing Liu, Takeshi Ikenaga, Satoshi Goto

    APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems    2006.12  [Refereed]

    DOI

  • Robust Scalable Video Transmission using Object-Oriented Unequal Loss Protection over Internet

    Zhen Qiu, Takeshi Ikenaga, Satoshi Goto

    APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems    2006.12  [Refereed]

    DOI

  • Enhanced Partial Distortion Sorting Fast Motion Estimation Algorithm for Low-Power Applications

    Yang Song, Takeshi Ikenaga, Satoshi Goto, Zhenyu Liu

    APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems    2006.12  [Refereed]

    DOI

  • A CABAC Encoding Core with Dynamic Pipeline for H.264/AVC Main Profile

    Lingfeng Li, Yang Song, Takeshi Ikenaga, Satoshi Goto

    APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems    2006.12  [Refereed]

    DOI

  • Complexity Based Fast Coding Mode Decision for MPEG-2 / H.264 Video Transcoding

    Shen Li, Lingfeng Li, Takeshi Ikenaga, Shunichi Ishiwata, Mastaka Matsui, Satoshi Goto

    APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems    2006.12  [Refereed]

    DOI

  • Memory-Efficient Accelerating Schedule for LDPC Decoder

    Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

    APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems    2006.12  [Refereed]

    DOI

  • Multi-resolution Analysis based Salient Contour Extraction

    Jing Wang, Kazuo Kunieda, Makoto Iwata, Hirokazu Koizumi, Hideo Shimazu, Takeshi Ikenaga, Satoshi Goto

    2006 International Symposium on Intelligent Signal Processing and Communications    2006.12  [Refereed]

    DOI

  • A 0.3mW 1.4mm2 Motion Estimation Processor for Mobile Video Application

    Seiichiro Hiratsuka, Satoshi Goto, Takeshi Ikenaga

    2006 IEEE Asian Solid-State Circuits Conference    2006.11  [Refereed]

    Authorship:Corresponding author

    DOI

  • A Fully Automatic Approach of Color Image Edge Detection

    Yangxing Liu, Takeshi Ikenaga, Satoshi Goto

    2006 IEEE International Conference on Systems, Man and Cybernetics    2006.10  [Refereed]

    DOI

  • High Speed Floorplanner with Soft Module

    Yukio Yamakoshi, Takeshi Yoshimura, Takeshi Ikenaga, Satoshi Goto

    International SoC Design Conference (ISOCC2006)    2006.10  [Refereed]

  • 奥行情報を用いた携帯端末向けリアルタイム人物抽出LSI

    有門 智弘, 平塚誠一郎, 後藤 敏, 池永 剛

    画像電子学会誌   Vol. 35 ( No. 5 ) 453 - 460  2006.09  [Refereed]

    Authorship:Corresponding author

  • Geometric Primitives Detection in Aerial Image

    Jing Wang, Satoshi Goto, Kazuo Kunieda, Makoto Iwata, Hirokazu Koizumi, Hideo Shimazu, Takeshi Ikenaga

    2006 5th IEEE International Conference on Cognitive Informatics    2006.07  [Refereed]

    DOI

  • A Novel Approach of Rectangular Shape Object Detection in Color Images Based on An MRF Model

    Yangxing Liu, Takeshi Ikenaga, Satoshi Goto

    2006 5th IEEE International Conference on Cognitive Informatics    2006.07  [Refereed]

    DOI

  • 適応型トリーに基づく低計算量動画圧縮方式

    平塚 誠一郎, 後藤 敏, 馬場 孝明, 池永 剛

    電子情報通信学会論文誌D   Vol. J89-D ( No. 6 ) 1297 - 1305  2006.06  [Refereed]

    Authorship:Corresponding author

  • Geometrical, Physical and Text/Symbol Analysis Based Approach of Traffic Sign Detection System

    Yangxing Liu, T. Ikenaga, S. Goto

    2006 IEEE Intelligent Vehicles Symposium    2006.06  [Refereed]

    DOI

  • High performance VLSI architecture of fractional motion estimation in H.264 for HDTV

    Changqi Yang, S. Goto, Takeshi Ikenaga

    2006 IEEE International Symposium on Circuits and Systems    2006.05  [Refereed]

    Authorship:Last author

    DOI

  • A parallel LSI architecture for LDPC decoder improving message-passing schedule

    K. Shimizu, T. Ishikawa, N. Togawa, T. Ikenaga, S. Goto

    2006 IEEE International Symposium on Circuits and Systems    2006.05  [Refereed]

    DOI

  • An ultra-low complexity motion estimation algorithm and its implementation of specific processor

    S. Hiratsuka, S. Goto, T. Ikenaga

    2006 IEEE International Symposium on Circuits and Systems    2006.05  [Refereed]

    Authorship:Corresponding author

    DOI

  • Hardware Architecture of Efficient Message-Passing Schedule based on Modified Min-Sum Algorithm for Decoding LDPC Codes

    Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

    The 13th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2006)    2006.04  [Refereed]

  • A 232MHz Variable Block Size Integer Motion Estimation Processor with System-in-Silicon DRAM for H.264/AVC

    Zhenyu Liu, Yang Song, Satoshi Goto, Takeshi Ikenaga, Kouichi Kumagai, Yoshihiro Mabuchi, Kenji Yoshida

    IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips IX)    2006.04  [Refereed]

    Authorship:Corresponding author

  • Loss Free VLSI Oriented Full Computation Reusing Algorithm for H.264 Fractional Motion Estimation

    Ming Shao, Zhenyu Liu, Satoshi Goto, Takeshi Ikenaga

    第19回 回路とシステム軽井沢ワークショップ    2006.04  [Refereed]

    Authorship:Corresponding author

  • High Performance Chip Design on H.264/AVC Integer Motion Estimation for 1080HDTV Based on SiS Multi-Chip Architecture

    Changqi Yang, Kouichi Kumagai, Yoshihiro Mabuchi, Kenji Yoshida, Takeshi Ikenaga, Satoshi Goto

    Picture Coding Symposium (PCS 2006)    2006.04  [Refereed]

  • Feature-Based Early-Termination Approach for Multi-Frame Motion Estimation of H.264/AVC

    Lingfeng Li, Shen Li, Takeshi Ikenaga, Shunichi Ishiwata, Masataka Matsui, Satoshi Goto

    Picture Coding Symposium (PCS 2006)    2006.04  [Refereed]

  • A Pipeline Parallel Tree Architecture for Full Search Variable Block Size Motion Estimation in H.264/AVC

    Zhenyu Liu, Yang Song, Takeshi Ikenaga, Satoshi Goto

    Picture Coding Symposium (PCS 2006)    2006.04  [Refereed]

  • 61.5mW 2048-bit RSA Cryptographic Co-processor LSI based on N bit-wised Modular Multiplier

    Toru Hisakado, Nobuyuki Kobayashi, Satoshi Goto, Takeshi Ikenaga, Kunihiko Higashi, Ichiro Kitao, Yukiyasu Tsunoo

    2006 International Symposium on VLSI Design, Automation and Test    2006.04  [Refereed]

    DOI

  • VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization

    Yang Song, Zhenyu Liu, Takeshi Ikenaga, Satoshi Goto

    2006 International Symposium on VLSI Design, Automation and Test    2006.04  [Refereed]

    DOI

  • High-Throughput LDPC Decoder for Long Code-Length

    Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto

    2006 International Symposium on VLSI Design, Automation and Test    2006.04  [Refereed]

    DOI

  • Scalable VLSI Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC

    Yang Song, Zhenyu Liu, Satoshi Goto, Takeshi Ikenaga

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E89-A ( 4 ) 979 - 988  2006.04  [Refereed]

    Authorship:Last author

    DOI

    Scopus

    14
    Citation
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  • Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule

    Kazunori Shimizui, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E89-A ( 4 ) 969 - 978  2006.04  [Refereed]

     View Summary

    In this paper, we propose a partially-parallel LDPC decoder which achieves a high-efficiency message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) The column operations follow the row operations in a pipelined architecture to ensure that the row and column operations are performed concurrently. (ii) The proposed parallel pipelined bit functional unit enables the column operation module to compute every message in each bit node which is updated by the row operations. These column operations can be performed without extending the single iterative decoding delay when the row and column operations are performed concurrently. Therefore, the proposed decoder performs the column operations more frequently in a single iterative decoding, and achieves a high-efficiency message-passing schedule within the limited decoding delay time. Hardware implementation on an FPGA and simulation results show that the proposed partially-parallel LDPC decoder improves the decoding throughput and bit error performance with a small hardware overhead.

    DOI CiNii

    Scopus

    9
    Citation
    (Scopus)
  • A Hardware Implementation of a Content-Based Motion Estimation Algorithm for Real-Time MPEG-4 Video Coding

    Shen Li, Takeshi Ikenaga, Hideki Takeda, Masataka Matsui, Satoshi Goto

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E89-A ( 4 ) 932 - 940  2006.04  [Refereed]

     View Summary

    Power efficiency and real-time processing capability are two major issues in today's mobile video applications. We proposed a novel Motion Estimation (ME) engine for power-efficient real-time MPEG-4 video coding based on our previously proposed content-based ME algorithm. By adopting Full Search (FS) and Three Step Search (TSS) alternatively according to the nature of video contents, this algorithm keeps the visual quality very close to that of FS with only 3% of its computational power. We designed a flexible Block Matching (BM) Unit with 16-PE SIMD data path so that the adaptive ME can be performed at a much lower clock frequency and hardware cost as compared with previous FS based work. To reduce the energy cost caused by excessive external memory access, on-chip SRAM is also utilized and optimized for parallel processing in the BM Unit. The ME engine is fabricated with TSMC 0.18μm technology. When processing QCIF (15fps) video, the estimated power is 2.88mW @ 4.16MHz (supply voltage: 1.62V). It is believed to be a favorable contribution to the video encoder LSI design for mobile applications.

    DOI CiNii

    Scopus

    2
    Citation
    (Scopus)
  • A Contour-Based Robust Algorithm for Text Detection in Color Images

    Yangxing Liu, Satoshi Goto, Takeshi Ikenaga

    IEICE Transactions on Information and Systems   E89-D ( 3 ) 1221 - 1230  2006.03  [Refereed]

    Authorship:Last author

     View Summary

    Text detection in color images has become an active research area in the past few decades. In this paper, we present a novel approach to accurately detect text in color images possibly with a complex background. The proposed algorithm is based on the combination of connected component and texture feature analysis of unknown text region contours. First, we utilize an elaborate color image edge detection algorithm to extract all possible text edge pixels. Connected component analysis is performed on these edge pixels to detect the external contour and possible internal contours of potential text regions. The gradient and geometrical characteristics of each region contour are carefully examined to construct candidate text regions and classify part non-text regions. Then each candidate text region is verified with texture features derived from wavelet domain. Finally, the Expectation maximization algorithm is introduced to binarize each text region to prepare data for recognition. In contrast to previous approach, our algorithm combines both the efficiency of connected component based method and robustness of texture based analysis. Experimental results show that our proposed algorithm is robust in text detection with respect to different character size, orientation, color and language and can provide reliable text binarization result.

    DOI CiNii

    Scopus

    55
    Citation
    (Scopus)
  • System-in-silicon architecture and its application to H.264/AVC motion estimation for 1080HDTV

    K. Kumagai, Changqi Yang, H. Izumino, N. Narita, K. Shinjo, S. Iwashita, Y. Nakaoka, T. Kawamura, H. Komabashiri, T. Minato, A. Ambo, T. Suzuki, Zhenyu Liu, Yang Song, S. Goto, T. Ikenaga, Y. Mabuchi, K. Yoshida

    2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers    2006.02  [Refereed]

    DOI

  • ASIC Implementation of LDPC Decoder Accelerating Message-Passing Schedule

    Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

    IEEE International Solid-State Circuits Conference (ISSCC2006), DAC/ISSCC 2006 Student Design Contest (Conceptual Category: 1st Place Winner)    2006.02  [Refereed]

  • An MRF Model Based Algorithm of Triangular Shape Object Detection in Color Images

    Yangxing Liu, Takeshi Ikenaga, Satoshi Goto

    International Journal of Information Technology   Vol. 12 ( No. 2 ) 55 - 65  2006.02  [Refereed]

  • A Real-time Object Detection LSI Based on Stereo Vision for Mobile Videophone

    Tomohiro Arikado, Satoshi Goto, Takeshi Ikenaga, Seiichiro Hiratsuka

    Journal of the Institute of Image Electronics Engineers of Japan   35 ( 5 ) 453 - 460  2006  [Refereed]

    Authorship:Corresponding author

     View Summary

    In this paper, we propose a real-time object detection LSI for mobile videophone. The LSI achieves real-time processing speed by stereo vision algorithm using temporal data relationship between frames. The algorithm uses a last frame result to reduce the detection area and search range to the edge of the object and the background. We have designed object detection LSI by using this algorithm. The LSI can process QCIF stereo images 30 frames/sec and logic area is 15182 gates. © 2006, The Institute of Image Electronics Engineers of Japan. All rights reserved.

    DOI

    Scopus

  • A new multiscale line detection approach for aerial image with complex scene

    Jing Wang, Takeshi Ikenaga, Satoshi Goto, Kazuo Kunieda, Makoto Iwata, Hirokazu Koizumi, Hideo Shimazu

    2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS     1968 - +  2006  [Refereed]

     View Summary

    Straight lines are important geometric features for aerial image understanding tasks like man-made object detection. As image scene becomes more complex, traditional method like Hough Transform may produce false detections and cannot work efficiently. In this paper, we propose a new multi-scale line detection approach that can efficiently detect semantic lines in aerial image with complex scene. Firstly, a method called "Trichotomy Line Extraction" detects reliable line segments locally. Then multi-scale image system is constructed by wavelet decomposition, from which global information is obtained to detect semantic lines. Experimental results show that proposed method can extract accurate linear features on complex scene aerial images in a robust and efficient way.

  • A power disturbance circuit for A5/1 resistant to power analysis attack

    Wei Dai, Tohru Hisakado, Zhenyu Liu, Satoshi Goto, Takeshi Ikenaga, Yukiyasu Tsunoo

    Symposium on Cryptography and Information Security (SCIS2006)    2006.01  [Refereed]

  • High-throughput decoder for low-density parity-check code

    T. Ishikawa, K. Shimizu, T. Ikenaga, S. Goto

    Asia and South Pacific Conference on Design Automation, 2006.    2006.01  [Refereed]

    DOI

  • A selective video encryption scheme for MPEG compression standard

    G Liu, T Ikenaga, S Goto, T Baka

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E89A ( 1 ) 194 - 202  2006.01  [Refereed]

    Authorship:Corresponding author

     View Summary

    With the increase of commercial multimedia applications using digital video, the security of video data becomes more and more important. Although several techniques have been proposed in order to protect these video data, they provide limited security or introduce significant overhead. This paper proposes a video security scheme for MPEG video compression standard, which includes two methods: DCEA (DC Coefficient Encryption Algorithm) and "Event Shuffle." DCEA is aim to encrypt group of codewords of DC coefficients. The feature of this method is the usage of data permutation to scatter the ciphertexts of additional codes in DC codewords. These additional codes are encrypted by block cipher previously. With the combination of these algorithms, the method provides enough security for important DC component of MPEG video data. "Event Shuffle" is aim to encrypt the AC coefficients. The prominent feature of this method is a shuffling of AC events generated after DCT transformation and quantization stages. Experimental results show that these methods introduce no bit overhead to MPEG bit stream while achieving low processing overhead to MPEG codec.

    DOI

    Scopus

    16
    Citation
    (Scopus)
  • Lossy strict multilevel successive elimination algorithm for fast motion estimation

    Yang Song, Zhenyu Liu, Takeshi Ikenaga, Satoshi Goto

    2006 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATIONS, VOLS 1 AND 2     402 - +  2006  [Refereed]

     View Summary

    This paper present a simple and effective method to further reduce the search points in the multilevel successive elimination algorithm (MSEA). Because the sea values for most of the best matching search positions are much smaller than the current minimum SAD, we can simply increase the calculated sea value to increase the elimination ratio without much affecting the coding efficiency. Compared with the MSEA algorithm, experiments show that the proposed strict MSEA algorithm (SMSEA) can provides almost 6.5 times speedup with stable image quality, which is better than diamond search (DS). In practice, the proposed technique can also be used in the fine granularity SEA (FGSE) algorithm and the calculation process can be traced by analogy.

  • A VLSI Array Processing Oriented Fast Fourier Transform Algorithm and Hardware Implementation

    Zhenyu Liu, Yang Song, Takeshi Ikenaga, Satoshi Goto

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E88-A ( 12 ) 3523 - 3530  2005.12  [Refereed]

    Authorship:Corresponding author

     View Summary

    Many parallel Fast Fourier Transform (FFT) algorithms adopt multiple stages architecture to increase performance. However, data permutation between stages consumes volume memory and processing time. One FFT array processing mapping algorithm is proposed in this paper to overcome this demerit. In this algorithm, arbitrary 2^k butterfly units (BUs) could be scheduled to work in parallel on n=2^s data (k=0, 1, ..., s-1). Because no inter stage data transfer is required, memory consumption and system latency are both greatly reduced. Moreover, with the increasing of BUs, not only does throughput increase linearly, system latency also decreases linearly. This array processing orientated architecture provides flexible tradeoff between hardware cost and system performance. In theory, the system latency is (s×2^<s-k>)×t_<clk> and the throughput is n/(s×2^<s-k>×t_<clk>), where t_<clk> is the system clock period. Based on this mapping algorithm, several 18-bit word-length 1024-point FFT processors implemented with TSMC0.18μm CMOS technology are given to demonstrate its scalability and high performance. The core area of 4-BU design is 2.991×1.121mm^2 and clock frequency is 326MHz in typical condition (1.8V, 25℃). This processor completes 1024 FFT calculation in 7.839μs.

    DOI CiNii

    Scopus

    6
    Citation
    (Scopus)
  • Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm

    K. Shimizu, T. Ishikawa, N. Togawa, T. Ikenaga, S. Goto

    2005 International Conference on Computer Design    2005.10  [Refereed]

    DOI

  • A VLSI Architecture for Motion Compensation Interpolation in H.264/AVC

    Yang Song, Zhenyu Liu, S. Goto, T. Ikenaga

    2005 6th International Conference on ASIC    2005.10  [Refereed]

    Authorship:Last author

    DOI

  • Inter-symbol Interference Suppression Employing Sub-carrier Group Selection for OFDM-TDD Transmit Diversity

    F. Maehara, T. Ikenaga, F. Takahata, S. Goto

    2005 2nd International Symposium on Wireless Communication Systems    2005.09  [Refereed]

    DOI

  • An efficient and accurate approach of detecting elliptical objects in color images

    Yangxing Liu, Takeshi Ikenaga, Satoshi Goto

    2006 8th international Conference on Signal Processing    2005.09  [Refereed]

    DOI

  • An MRF Model Based Algorithm of Triangular Shape Object Detection in Color Images

    Yangxing Liu, Satoshi Goto, Takeshi Ikenaga

    International Conference on Intelligent Computing (ICIC’05)    2005.08  [Refereed]

  • A highly parallel architecture for deblocking filter in H.264/AVC

    LF Li, S Goto, T Ikenaga

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS   E88D ( 7 ) 1623 - 1629  2005.07  [Refereed]

    Authorship:Last author

     View Summary

    This paper presents a highly parallel architecture for deblocking filter in H.264/AVC. We adopt various parallel schemes in memory sub-system and datapath. A 2-dimensional parallel memory scheme is employed to support efficient parallel access in both horizontal and vertical directions in order to speed up the whole filtering process. This parallel memory also eliminates the need for a transpose circuit. In the datapath, an algorithm optimization is performed to implement parallel filtering with hardware reuse. Pipeline techniques are also adopted to improve the throughput of filtering operations. Our design is implemented under TSMC 0.18 mu m technology. Results show that the core size is 0.82 x 1.13 mm(2) when the maximum frequency is 230 MHz. Compared to other existing architectures, our design has advantages in both speed and area.

    DOI

    Scopus

    31
    Citation
    (Scopus)
  • Reconfigurable adaptive FEC system based on Reed-Solomon code with interleaving

    K Shimizu, N Togawa, T Ikenaga, S Goto

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS   E88D ( 7 ) 1526 - 1537  2005.07  [Refereed]

     View Summary

    This paper proposes a reconfigurable adaptive FEC system based on Reed-Solomon (RS) code with interleaving. In adaptive FEC schemes, error correction capability t is changed dynamically according to the communication channel condition. For given error correction capability t, we can implement an optimal RS decoder composed of minimum hardware units for each t. If the hardware units of the RS decoder can be reduced for any given error correction capability t, we can embed as large deinterleaver as possible into the RS decoder for each.t. Reconfiguring the RS decoder embedded with the expanded deinterleaver dynamically for each error correction capability t allows us to decode larger interleaved codes which are more robust error correction codes to burst errors. In a reliable transport protocol, experimental results show that our system achieves up to 65% lower packet error rate and 5.9% higher data transmission throughput compared to the adaptive FEC scheme on a conventional fixed hardware system. In an unreliable transport protocol, our system achieves up to 76% better bit error performance with higher code rate compared to the adaptive FEC scheme on a conventional fixed hardware system.

    DOI

    Scopus

    3
    Citation
    (Scopus)
  • Content-based motion estimation with extended temporal-spatial analysis

    S Li, Y Jiang, T Ikenaga, S Goto

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS   E88D ( 7 ) 1561 - 1568  2005.07  [Refereed]

     View Summary

    In adaptive motion estimation, spatial-temporal correlation based motion type inference has been recognized as an effective way to guide the motion estimation strategy adjustment according to video contents. However, the complexity and the reliability of those methods remain two crucial problems. In this paper, a motion vector field model is introduced as the basis for a new spatial-temporal correlation based motion type inference method. For each block, Full Search with Adaptive Search Window (ASW) and Three Step Search (TSS), as two search strategy candidates, can be employed alternatively. Simulation results show that the proposed method can constantly reduce the dynamic computational cost to as low as 3% to 4% of that of Full Search (FS), while remaining a closer approximation to FS in terms of visual quality than other fast algorithms for various video sequences. Due to its efficiency and reliability, this method is expected to be a favorable contribution to the mobile video communication where low power real-time video coding is necessary.

    DOI

    Scopus

    4
    Citation
    (Scopus)
  • A Locally Adaptive Subsampling Algorithm for Software Based Motion Estination

    S. Hiratsuka, S. Goto, T. Baba, T. Ikenaga

    2005 IEEE International Symposium on Circuits and Systems    2005.05  [Refereed]

    Authorship:Corresponding author

    DOI

  • Low-Pass Filter Based Vlsi Oriented Variable Block Size Motion Estimation Algorithm for H.264

    Zhenyu Liu, Yang Song, Takeshi Ikenaga, S. Goto

    2006 IEEE International Conference on Acoustics Speed and Signal Processing Proceedings    2005.05  [Refereed]

    Authorship:Corresponding author

    DOI

  • Motion Estimation Algorithm Modification and Implementation in H.264/AVC

    Yang Song, Zhenyu Liu, Satoshi Goto, Takeshi Ikenaga

    第18回回路とシステム軽井沢ワークショップ    2005.04  [Refereed]

  • Content-based Motion Estimation VLSI Design for Real-time MPEG-4 Video Coding

    Shen Li, Satoshi Goto, Takeshi Ikenaga, Hideki Takeda, Masataka Matusi

    第18回回路とシステム軽井沢ワークショップ    2005.04  [Refereed]

  • A robust algorithm for text detection in color images

    Y. Liu, S. Goto, T. Ikenaga

    Eighth International Conference on Document Analysis and Recognition (ICDAR'05)    2005  [Refereed]

    DOI

  • An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC

    Lingfeng Li, S. Goto, T. Ikenaga

    Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.    2005.01  [Refereed]

    DOI

  • Reconfigurable adaptive FEC system with interleaving

    Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

    Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05    2005.01  [Refereed]

    DOI

    Scopus

  • A HIGH SECURITY AND LOW OVERHEAD SELECTIVE VIDEO ENCRYPTION SCHEME FOR MPEG COMPRESSION STANDARD

    Gang Liu, Satoshi Goto, Takaaki Baba, Takeshi Ikenaga

    Symposium on Cryptography and Information Security (SCIS2005)    2005.01  [Refereed]

  • A VLSI array processing oriented fast fourier transform algorithm and hardware implementation

    Zhenyu Liu, Yang Song, Takeshi Ikenaga, Satoshi Goto

    Proceedings of the 15th ACM Great Lakes symposium on VLSI - GLSVSLI '05    2005  [Refereed]

    Authorship:Corresponding author

    DOI

    Scopus

    1
    Citation
    (Scopus)
  • An accurate and low complexity approach of detecting circular shape objects in still color images

    Liu Yangxing, Goto Satoshi, Ikenaga Takeshi

    IEEE International Conference on Image Processing 2005    2005  [Refereed]

    Authorship:Last author

    DOI

  • Real-time automatic moving object extraction and tracing based on improved active contour model

    YC Geng, YX Liu, S Goto, T Ikenaga

    ISPACS 2005: PROCEEDINGS OF THE 2005 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATION SYSTEMS     149 - 152  2005  [Refereed]

     View Summary

    A real-time moving object extraction and tracing algorithm is proposed for videophone application. Semantic objects, mainly moving objects in this specified case, are extracted by block based change detection from first several frames. Improved active contour model is then utilized for object tracing. Since there is little difference between continuous two frames, only limited pixels need to be searched instead of whole frame scan so that computing complexity is greatly decreased. Therefore, it is able to be used for real-time applications such as that in videophone. However, previous active contour model is sensitive to noise. Error originating from noise traps accumulates and deteriorates the tracing results. So gradient projection (GP) and jump back (JB) mechanisms are introduced to suppress noise trap effect and error accumulation in this paper. Experiment results demonstrate that proposed algorithm is an efficient noise tolerable real-time approach.

  • Video coding algorithm based on adaptive tree for low electricity consumption

    S. Hiratsuka, S. Goto, T. Baba, T. Ikenaga

    The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.    2004.12  [Refereed]

    Authorship:Corresponding author

    DOI

  • A reconfigurable adaptive FEC system for reliable wireless communications

    K. Shimizu, N. Togawa, T. Ikenaga, M. Yanagisawa, S. Goto, T. Ohtsuki

    The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.    2004.12  [Refereed]

    DOI

  • No bit overhead MPEG video scrambling based on event shuffle in frequency domain

    Gang Liu, S. Goto, T. Baba, T. Ikenaga

    The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.    2004.12  [Refereed]

    Authorship:Corresponding author

    DOI

  • N bit-wise modular multiplier architecture for public key cryptography

    T. Hisakado, N. Kobayashi, T. Ikenaga, T. Baba, S. Goto, K. Higashi, I. Kitao, Y. Tsunoo

    38th Annual 2004 International Carnahan Conference on Security Technology, 2004.    2004.10  [Refereed]

    DOI

  • Improving the TCP performance to support mobile multimedia application

    Chao Liu, Satoshi Goto, Takeshi Ikenaga, Takaaki Baba

    The Second International Conference on Advances in Mobile Multimedia (MoMM2004)    2004.09  [Refereed]

  • Content-based motion estimation with extended temporal-spatial analysis

    Shen Li, Yong Jiang, T. Ikenaga, S. Goto

    The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.    2004.07  [Refereed]

    DOI

  • An efficient algorithm/architecture codesign for image encoders

    Jinku Choi, N. Togawa, T. Ikenaga, S. Goto, M. Yanagisawa, T. Ohtsuki

    The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.    2004.07  [Refereed]

    DOI

  • Real-time morphology processing using highly parallel 2-D cellular automata CAM/sup 2/

    T. Ogura, T. Ikenaga

    IEEE Transactions on Image Processing   9 ( 12 ) 2018 - 2026  2000.12  [Refereed]

    Authorship:Lead author

    DOI

    Scopus

    15
    Citation
    (Scopus)
  • A fully parallel 1-Mb CAM LSI for real-time pixel-parallel image processing

    T. Ikenaga, T. Ogura

    IEEE Journal of Solid-State Circuits   35 ( 4 ) 536 - 544  2000.04  [Refereed]

    Authorship:Lead author

    DOI

    Scopus

    27
    Citation
    (Scopus)
  • Content Addressable Memory LSI for 2D Cellular Automata Machine

    Takeshi Ikenaga, Takeshi Ogura

    International Workshop on Advanced LSIs and Devices    1999.06  [Refereed]

    Authorship:Lead author

  • A fully-parallel 1 Mb CAM LSI for real-time pixel-parallel image processing

    T. Ikenaga, T. Ogura

    1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278)    1999.02  [Refereed]

    Authorship:Lead author

    DOI

  • CAM/sup 2/: a highly-parallel two-dimensional cellular automaton architecture

    T. Ikenaga, T. Ogura

    IEEE Transactions on Computers   47 ( 7 ) 788 - 801  1998.07  [Refereed]

    Authorship:Lead author

    DOI CiNii

    Scopus

    16
    Citation
    (Scopus)
  • A DTCNN universal machine based on highly parallel 2-D cellular automata CAM/sup 2/

    T. Ikenaga, T. Ogura

    IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications   45 ( 5 ) 538 - 546  1998.05  [Refereed]

    Authorship:Lead author

     View Summary

    The discrete-time cellular neural network (DTCNN) is a promising computer paradigm that fuses artificial neural networks with the concept of cellular automaton (CA) and has many applications to pixel-level image processing. Although some architectures have been proposed for processing DTCNN, there are no compact, practical computers that can process real-world images of several hundred thousand pixels at video rates. So, in spite of its great potential, DTCNN's are not being used for image processing outside the laboratory. This paper proposes a DTCNN processing method based on a highly parallel two-dimensional (2-D) cellular automata called CAM 2. CAM 2 can attain pixel-order parallelism on a single PC board because it is composed of a content addressable memory (CAM), which makes it possible to embed enormous numbers of processing elements, corresponding to CA cells, onto one VLSI chip. A new mapping method utilizes maskable search and parallel and partial write commands of CAM 2 to enable high-performance DTCNN processing. Evaluation results show that, on average, CAM 2 can perform one transition for various DTCNN templates in about 12 microseconds. And it can perform practical image processing through a combination of DTCNN's and other CA-based algorithms. CAM 2 is a promising platform for processing DTCNN. © 1998 IEEE.

    DOI

    Scopus

    17
    Citation
    (Scopus)
  • Real-time morphology processing using highly parallel 2D cellular automata CAM/sup 2/

    T. Ikenaga, T. Ogura

    Proceedings of International Conference on Image Processing    1997.11  [Refereed]

    Authorship:Lead author

    DOI

  • Discrete-time Cellular Neural Networks using Highly-parallel 2D Cellular Automata CAM2

    Takeshi Ikenaga, Takeshi Ogura

    International Symp. Nonlinear Theory and its Applications (NOLTA 1996)    1996.10  [Refereed]

    Authorship:Lead author

  • CAM2: A Highly-parallel 2-D Cellular Automata Architecture for Real-time and Palm-top Pixel-level Image Processing

    Takeshi Ikenaga, Takeshi Ogura

    Euro-Par 1996    1996.08  [Refereed]

    Authorship:Lead author

  • Two-chip MPEG-2 video encoder

    T. Kondo, K. Suguri, M. Ikeda, T. Abe, H. Matsuda, T. Okubo, K. Ogura, Y. Tashiro, N. Ono, T. Minami, R. Kusaba, T. Ikenaga, N. Shibata, R. Kasai, K. Otsu, F. Nakagawa, Y. Sato

    IEEE Micro   16 ( 2 ) 51 - 58  1996.04  [Refereed]

    DOI CiNii

    Scopus

    33
    Citation
    (Scopus)
  • A DISTRIBUTED BIST TECHNIQUE AND ITS TEST DESIGN PLATFORM FOR VLSIS

    T IKENAGA, T OGURA

    IEICE TRANSACTIONS ON ELECTRONICS   E78C ( 11 ) 1618 - 1623  1995.11  [Refereed]

    Authorship:Lead author

     View Summary

    This paper proposes a distributed built-in self-test (BIST) technique and its test design platform for VLSIs. This BIST has lower hardware overhead pattern generators, compressors and a controller. The platform cuts down on the number of complicated operations needed for the BIST insertion and evaluation, so the BIST implementation turn-around-lime (TAT) is dramatically reduced. Experimental results for the 110 k-gate arithmetic execution blocks of an image-processing LSI show that using this BIST structure and platform enables the entire BIST implementation within five days. The implemented BIST has a 1% hardware overhead and 96% fault coverage. This platform will significantly reduce testing costs for time-to-market and mass-produced LSIs.

  • A built-in self-test structure for arithmetic execution units of VLSIs

    Takeshi Ikenaga, Jun-Ichi Takahashi

    Electronics and Communications in Japan (Part II: Electronics)   78 ( 4 ) 68 - 78  1995.04  [Refereed]

    Authorship:Lead author

    DOI

    Scopus

  • A Test Design Platform for Shorter TAT Implementation of a Distributed BIST Structure

    Takeshi Ikenaga, Takeshi Ogura

    European Design and Test Conf. (ED&TC95)    1995.03  [Refereed]

    Authorship:Lead author

  • Special Purpose Processor Design System Realizing Algorithm Described by Higher Level Language

    Takeshi Ikenaga, Katsuhiko Shirai

    IPSJ Trans.   Vol.32 ( No.11 ) 1445 - 1456  1991.11  [Refereed]

    Authorship:Lead author

  • Design system for special purpose processor executing algorithms described by higher level language

    Katsuhiko Shirai, Takeshi Ikenaga, H. Kitabatake

    Third Annual IEEE ASIC Seminar and Exhibit    1990.03  [Refereed]

    Authorship:Corresponding author

▼display all

Books and Other Publications

  • 情報システムとヒューマンインタフェース:情報化社会を変革する動画像圧縮LSIの技術動向

    白井克彦監修, 池永 剛他

    早稲田大学出版部  2010.03 ISBN: 9784657101099

Misc

  • D-12-84 Particle Filter based on Dual Model for Irregular Moving Object Tracking

    Shiina Yuhi, Ikenaga Takeshi

    Proceedings of the IEICE General Conference   2011 ( 2 ) 187 - 187  2011.02

    CiNii

  • D-11-97 Low Complexity Super Resolution Filter by Nonlinear Filter Using High Pass Filter and Neighborhood Sum of Square Differences

    Shimizu Yoshiyasu, Ikenaga Takeshi

    Proceedings of the IEICE General Conference   2011 ( 2 ) 97 - 97  2011.02

    CiNii

  • D-11-103 Hand Tracking Using Feature Point Gathering by KLT Tracker

    ARAKI Ryosuke, IKENAGA Takeshi

    Proceedings of the IEICE General Conference   2011 ( 2 ) 103 - 103  2011.02

    CiNii

  • A-4-34 Motion based Feature Point Extraction for KLT Tracker

    Sasaki Tsuyoshi, Kawane Kodai, Ikenaga Takeshi

    Proceedings of the Society Conference of IEICE   2009   97 - 97  2009.09

    CiNii

  • Implementation of Hardware Engine for Real-Time KLT Tracker

    SAKAYORI Takahiro, IKENAGA Takeshi

    IEICE technical report   108 ( 485 ) 47 - 52  2009.03

     View Summary

    The real-time object tracking are required in vehicle video and surveillance video systems. This paper focuses on the realization of hardware engine for real-time KLT Tracker (Kanade-Lucas-Tomasi) which is known as object tracking algorithm. Firstly, the proposed stream data and parallel processing in real-time system. Secondly, by using FIFO and image block buffer, the problem of memory access delay is well solved. We implement the proposed architecture to show that it demonstrates within 9ms by using FPGA under 100 feature numbers, 640x480 image size and 100MHz.

    CiNii

  • D-12-28 An Implementation of Feature Extracting Hardware of Real-Time KLT Tracker

    Kawane Kodai, Sakayori Takahiro, Ikenaga Takeshi

    Proceedings of the IEICE General Conference   2009 ( 2 ) 137 - 137  2009.03

    CiNii

  • D-12-27 An Implementation of Feature Tracking Hardware of Real-Time KLT Tracker

    Sakayori Takahiro, Kawane Kodai, Ikenaga Takeshi

    Proceedings of the IEICE General Conference     136 - 136  2009

    CiNii

  • DPA on Stream Cipher of eSTREAM Project

    HISAKADO Toru, TSUNOO Yukiyasu, IKENAGA Takeshi, GOTO Satoshi

    The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Japanese edition) A   91 ( 11 ) 1036 - 1044  2008.11

    CiNii

  • BS-12-18 A Novel Hardware-Friendly Regular 3-Step Integer Motion Estimation Algorithm for H.264/AVC(BS-12. Network Planning, Control, and Management)

    YOU Wenqi, WEI Xianghui, SONG Yang, IKENAGA Takeshi, GOTO Satoshi

    Proceedings of the Society Conference of IEICE   2008 ( 2 ) "S - 152"  2008.09

     View Summary

    This paper proposed a novel hardware friendly regular 3-step search for integer motion estimation in H.264/AVC. The algorithm takes use of a mix of rood, square and compact square search pattern together. Each pattern only concerns about 9 search points, which encourages a reusable feature of the hardware resource. Moreover, it achieves almost the same video quality with that of diamond search, which averagely saved search points to about 3.17% of fast full search's in cif sequences and 0.27% in HDTV ones, respectively.

    CiNii

  • BS-12-20 VLSI Design of Level C Bandwidth Reduction Scheme for MPEG-2 to H.264/AVC Transcoding(BS-12. Network Planning, Control, and Management)

    Wei Xianghui, Ikenaga Takeshi, Goto Satoshi

    Proceedings of the Society Conference of IEICE   2008 ( 2 ) "S - 154"  2008.09

     View Summary

    Based on the search window reuse method proposed in [1], a low-bandwidth hardware architecture is proposed for integer motion estimation (IME) of MPEG-2 to H.264 transcoding.

    CiNii

  • BS-12-19 A Fast Block Type Decision Algorithm for H.264/AVC Intra Prediction(BS-12. Network Planning, Control, and Management)

    Tian Guifen, Zhang Tianruo, Ikenaga Takeshi, Goto Satoshi

    Proceedings of the Society Conference of IEICE   2008 ( 2 ) "S - 153"  2008.09

    CiNii

  • Design of high throughput multi-rate irregular LDPC decoder based on accelerated message-passing schedule: the format of technical report (subtitle)

    ABE Yuta, TAJIMA Naoki, RI Xing, SHIMIZU Kazunori, IKENAGA Takeshi, GOTO Satoshi

    IEICE technical report   107 ( 508 ) 25 - 30  2008.03

     View Summary

    In this paper, We Design of High Throughput Multi-rate Irregular LDPC Decoder based on Accelerated Message-Passing Schedule. The irregular LDPC decoder which adopts high-efficiency message passing method is reported in Ref. [9], however Ref. [9] has problem. LDPC decoder of Ref. [9] has only 54Mbps processing speed even though the request speed of IEEE802.11n is 330Mbps (Code rate is 1/2). In addition, The code-rate of IEEE802.11n has number of 4 code-rate(1/2, 2/3, 3/4 5/6). Then in this paper, we propose high-throughput and multi-rate method for The irregular LDPC decoder.

    CiNii

  • An adaptive error concealment order in H.264/AVC

    Wang Jun, Ikenaga Takeshi, Goto Satoshi

    IEICE technical report   107 ( 508 ) 37 - 40  2008.03

     View Summary

    Transmission of compressed video over error prone channels may result in packet losses or errors, which can significantly degrade the image quality. Aimed this problem, this paper proposed an adaptive concealment order based on well know Boundary matching algorithm. The concealment order is carefully chose according to a lost MB's priority, which is formulated considering 2 factors, the lost MB's MV, and its available neighborhood information. Compared with Chen's work, the experiments show our proposal always achieves the best performance of video recovery under different packet lost rate channel.

    CiNii

  • A-16-1 Group-Based Prediction Scheme on Multiple Reference Frame Fractional Motion Estimation in H.264/AVC

    Ma Yao, Song Yang, Zhuan Yang, You Wenqi, Ikenaga Takeshi, Goto Satoshi

    Proceedings of the IEICE General Conference   2008   287 - 287  2008.03

    CiNii

  • A-16-2 A Fast Mode Decision Algorithm for H.264/AVC Intra Prediction

    Tian Guifen, Zhang Tianruo, You Wenqi, Ikenaga Takeshi, Goto Satoshi

    Proceedings of the IEICE General Conference   2008   288 - 288  2008.03

    CiNii

  • A-4-18 Integer Search Position Based Fast Motion Estimation in H.264/AVC

    HUANG Yiqing, GOTO Satoshi, IKENAGA Takeshi

    Proceedings of the IEICE General Conference   2008   108 - 108  2008.03

    CiNii

  • A-4-33 High Throughput Rate-1/2 Partially-Parallel Irregular LDPC Decoder

    JI Wen, ABE Yuta, IKENAGA Takeshi, GOTO Satoshi

    Proceedings of the IEICE General Conference   2008   123 - 123  2008.03

    CiNii

  • A-4-15 Cross Low Pass Filter Based Subsampling Algorithm for H.264/AVC Motion Estimation

    LIU Qin, GOTO Satoshi, IKENAGA Takeshi

    Proceedings of the IEICE General Conference   2008   105 - 105  2008.03

    CiNii

  • A-4-16 Diamond Web-grid Search Algorithm for H.264/AVC Motion Estimation

    Jeong Chang-Uk, Ikenaga Takeshi, Goto Satoshi

    Proceedings of the IEICE General Conference   2008   106 - 106  2008.03

    CiNii

  • A-3-15 A area-reduction method for decoding irregular LDPC codes based on High efficient message-passaing

    Tang Wenming, Abe Yuta, Ikenaga Takeshi, Goto Satoshi

    Proceedings of the IEICE General Conference   2008   90 - 90  2008.03

    CiNii

  • D-11-70 Adaptive Spatial EC based on Numerical Measures of Edge Statistical Model

    WANG Jun, IKENAGA Takeshi, GOTO Satoshi

    Proceedings of the IEICE General Conference   2008 ( 2 ) 70 - 70  2008.03

    CiNii

  • D-11-50 A Novel Fast Block Type Decision Algorithm for Intra Prediction in H.264/AVC High Profile

    Zhang Tianruo, Tian Guifen, Ikenaga Takeshi, Goto Satoshi

    Proceedings of the IEICE General Conference   2008 ( 2 ) 50 - 50  2008.03

    CiNii

  • C-12-21 Memory Mapping Method for Memory-Based Parallel FFT Circuits

    Ushiki Shinsuke, Nakamura Koichi, Shimizu Kazunori, Goto Satoshi, Ikenaga Takeshi

    Proceedings of the IEICE General Conference   2008 ( 2 ) 111 - 111  2008.03

    CiNii

  • A-4-20 Real-Time Motion Vector Extraction using Simplified KLT Tracker

    Sakayori Takahiro, Goto Satoshi, Ikenaga Takeshi

    Proceedings of the Society Conference of IEICE     80 - 80  2008

    CiNii

  • Video compression LSI for Ubiquitous and Ambient Information Society

    IKENAGA Takeshi

    IEICE technical report   107 ( 287 ) 29 - 34  2007.10

     View Summary

    MPEG-2 became a video coding international standard in 1995. Since then, a wide variety of video compression LSIs have been developed and actually deployed in many applications such as digital HDTV broadcasting, TV conference system, mobile and so forth. Since video coding technology is essential to the efficient storage and transmission of video data, it continues to play an important role in ubiquitous (anywhere, anytime, etc) and coming ambient (safe, comfortable, etc) information society. This paper provides video compression LSI technologies from past, present and future points of view. The MPEG-2 encoder chip set developed by NTT in 1996 is picked up as a pioneer work. Academia and industry LSI trends based on international conference publications and commercial products are also shown. As a current hot topic, a H.264/AVC encoder SoC for HDTV1080p developed in Waseda University is introduced. It is implemented with the dedicated hardware engines and a 32-bit Media embedded Processor (MeP). The SoC core occupies 27.1mm^2 die with 0.18μm CMOS technology and dissipates 1.41W at 1.8V and 200MHz. As future trends, let me describe two directions that I believe important : a low power LSI based on a low complexity video compression algorithm and a media-codec-centric application SoC.

    CiNii

  • Low Complexity Video Compression System with Unequal Error Protection

    TAJIMA Naoki, SHIMIZU Kazunori, IKENAGA Takeshi, GOTO Satoshi

    IPSJ SIG Notes   2007 ( 96 ) 9 - 14  2007.09

     View Summary

    We proposed low complexity video compression system with unequal error protection(UEP). In this proposal, we combine H.264/AVC and LDPC codes. If H.264/AVC bit stream has some errors during transfer, the error concealment is done at the decoder side. If the slice which is referred to complement the lost part has some errors, quality of error concealment is become worse. We use UEP to avoid this situation. UEP is known as the method to reduce computational complexity. We reduce computational complexity by using UEP, while quality of video is kept. Our system can reduce 28.48% computational time compared with the system without UEP.

    CiNii

  • Technical trend of video compression LSI

    IKENAGA Takeshi

    IPSJ SIG Notes   58   1 - 8  2007.09

     View Summary

    So far, a wide variety of video compression LSIs have been developed and actually deployed in many applications such as digital HDTV broadcasting, TV conference system, mobile and so forth. Since video coding technology is essential to the efficient storage and transmission of video data, it continues to play an important role in ubiquitous (anywhere, anytime, etc) and coming ambient (safe, comfortable, etc) information society. This paper provides video compression LSI technologies from past, present and future points of view. The MPEG-2 encoder chip set developed by NTT in 1996 is picked up as a pioneer work. Academia and industry LSI trends based on international conference publications and commercial products are also shown. As a current hot topic, a H.264/AVC encoder SoC for HDTV1080p developed in Waseda University is introduced. As future trends, let me describe two directions that I believe important : a low power LSI based on a low complexity video compression algorithm and a media-codec-centric application SoC.

    CiNii

  • A high-throughput, low-power FFT circuit for OFDM based wireless communication systems

    USHIKI Shinsuke, SHIMIZU Kazunori, NAKAMURA Koichi, GOTO Satoshi, IKENAGA Takeshi

    IPSJ SIG Notes   2007 ( 55 ) 55 - 60  2007.05

     View Summary

    OFDM attracts attention in digital wireless communication systems. In the FFT circuit which is main processing of digital section in OFDM, a circuit scale and power consumption increase in depending on the number of the carrier waves. However, there is standards carrier waves more than 1024 for a high-performance which becomes a big problem in hardware design. In this paper, we propose a high-throughput, low-power method which gives a good tradeoff between throughput, power dissipation and hardware complexity. Two SRAM and radix4 circuits which are necessary for 1 word memory read/write operation enables the FFT circuits to reduce the number of processing cycles. We implemented FFT circuits based on our proposed method. The proposed architecture can reduce processing cycles by about 88% compared to the comventional circuit. As a result, We can reduce power by about 46% compared to the conventional circuit in the same throughput.

    CiNii

  • A high-throughput, low-power FFT circuit for OFDM based wireless communication systems

    USHIKI Shinsuke, SHIMIZU Kazunori, NAKAMURA Koichi, GOTO Satoshi, IKENAGA Takeshi

    IEICE technical report   107 ( 76 ) 55 - 60  2007.05

     View Summary

    OFDM attracts attention in digital wireless communication systems. In the FFT circuit which is main processing of digital section in OFDM, a circuit scale and power consumption increase in depending on the number of the carrier waves. However, there is standards carrier waves more than 1024 for a high-performance which becomes a big problem in hardware design. In this paper, we propose a high-throughput, low-power method which gives a good tradeoff between throughput, power dissipation and hardware complexity. Two SRAM and radix4 circuits which are necessary for 1 word memory read/write operation enables the FFT circuits to reduce the number of processing cycles. We implemented FFT circuits based on our proposed method. The proposed architecture can reduce processing cycles by about 88% compared to the comventional circuit. As a result, We can reduce power by about 46% compared to the conventional circuit in the same throughput.

    CiNii

  • A high-speed design of Montgomery multiplier (第20回 回路とシステム軽井沢ワークショップ論文集) -- (システム実現技術)

    Fan Yibo, Ikenaga Takeshi, Goto Satoshi

    回路とシステム軽井沢ワークショップ論文集   20   137 - 142  2007.04

    CiNii

  • Partially-parallel decoder based on high-efficiency message-passing schedule for irregular LDPC code

    LI Xing, SHIMIZU Kazunori, IKENAGA Takeshi, GOTO Satoshi

    IEICE technical report   106 ( 550 ) 13 - 18  2007.02

     View Summary

    In this paper we propose an efficient Message-Passing schedule which is suitable for irregular LDPC decoder. For the decoding matrix of high column degree, our proposed decoder can complete all the column omerations which is relate to intermediate messages updated by row operations. We compare the performances of proposed schedule and conventional schedule based on irregular parity check matrixes in IEEE 802.11n protocol. We design the irregular LDPC decoder using TSMC 0.18μm CMOS technology. According to the synthesis results, our proposed decoder doubles the throughput by consuming 36% larger area, compared with the conventional decoders.

    CiNii

  • A Real-time Object Detection LSI Based on Stereo Vision for Mobile Videophone

    ARIKADO Tomohiro, GOTO Satoshi, IKENAGA Takeshi

    IEICE technical report   105 ( 646 ) 61 - 66  2006.03

     View Summary

    In this paper, we propose a real-time object detection LSI for mobile videophone. The LSI achieves real-time processing speed by stereo vision algorithm using temporal data relationship between frames. The algorithm uses a last frame result to reduce the detection area and search range to the edge of the object and the background. We have designed object detection LSI by using this algorithm. The LSI can process QCIF stereo images 30 frames/sec and logic area is 15182 gates.

    CiNii

  • High-Throughput LDPC Decoder Based on Memory-Reduction Method

    ISHIKAWA Tatsuyuki, SHIMIZU Kazunori, IKENAGA Takeshi, GOTO Satoshi

    ITE technical report   30 ( 9 ) 29 - 34  2006.01

    CiNii

  • High-Throughput LDPC Decoder Based on Memory-Reduction Method

    ISHIKAWA Tatsuyuki, SHIMIZU Kazunori, IKENAGA Takeshi, GOTO Satoshi

    IEICE technical report   105 ( 570 ) 29 - 34  2006.01

     View Summary

    In this paper, we propose a high-throughput partially-parallel LDPC decoder for long code-length. The decoder achieves high-throughput by operating row-operations and column-operations concurrently. Furthermore, we propose a memory-reduction method by using characteristic of row-operation data on Min-Sum algorithm and correlation of row-operation data and column-operation data. We have designed partially-parallel decoder by using these method. The decoder decodes (3, 6)-11520 bit LDPC codes and achieves throughput of 598 Mb/s.

    CiNii

  • 261MHz Parallel Tree Architecture for Full Search Variable Block Size Motion Estimation in H.264/AVC

    LIU Zhenyu, SONG Yang, IKENAGA Takeshi, GOTO Satoshi

    ITE technical report   105 ( 570 ) 17 - 22  2006.01

     View Summary

    A parallel tree architecture for full search variable block size motion estimation (VBSME) with integer pixel accuracy is proposed in this paper. Through exploiting the spatial data correlations between horizontal candidate block searches, 256 process elements are scheduled to work in parallel and fully utilized. In this architecture, the search window memory partition number is largely reduced. Consequently no trivial hardware cost and power consumption can be saved. One design with 48×32 search range has been implemented with TSMC 0.18um CMOS technology. The core area is 1717μm×1713μm and the clock frequency is 261MHz in typical working condition.

    CiNii

  • An Ultra-low Complexity Motion Estimation Algorithm and its Implementation of Specific Processor

    HIRATSUKA Seiichiro, GOTO Satoshi, IKENAGA Takeshi

      2005 ( 102 ) 43 - 48  2005.10

     View Summary

    Motion estimation (ME) requires huge computation complexity. Many motion estimation algorithms have been proposed to reduce its complexity. But they are still insufficient for embedded video coding systems. So we propose an ultra-low complexity ME algorithm with adaptive block sub-sampling and several techniques. The simulation results show that proposed algorithm has about 1, 000 times the speedup than full search (FS) maintaining high image quality. And we also propose the implementation of the application specific instruction-set processor (ASIP). It is based on a reduced instruction set computer (RISC) with sum of absolute difference (SAD) operation circuit. Our ME ASIP is implemented on FPGA. It is required about 3, 313 logic elements (LEs) and its hardware scale is about quarter of the previous ME ASIP. This ME ASIP will make a significant contribution to the development of compact video coding systems.

    CiNii

  • An Ultra-low Complexity Motion Estimation Algorithm and its Implementation of Specific Processor

    HIRATSUKA Seiichiro, GOTO Satoshi, Ikenaga Takeshi

    IEICE technical report   105 ( 351 ) 43 - 48  2005.10

     View Summary

    Motion estimation (ME) requires huge computation complexity. Many motion estimation algorithms have been proposed to reduce its complexity. But they are still insufficient for embedded video coding systems. So we propose an ultra-low complexity ME algorithm with adaptive block sub-sampling and several techniques. The simulation results show that proposed algorithm has about 1,000 times the speedup than full search (FS) maintaining high image quality. And we also propose the implementation of the application specific instruction-set processor (ASIP). It is based on a reduced instruction set computer (RISC) with sum of absolute difference (SAD) operation circuit. Our ME ASIP is implemented on FPGA. It is required about 3,313 logic elements (LEs) and its hardware scale is about quarter of the previous ME ASIP. This ME ASIP will make a significant contribution to the development of compact video coding systems.

    CiNii

  • A Highly Parallel Architecture for Deblocking Filter in H.264/AVC

    LI Lingfeng, GOTO Satoshi, IKENAGA Takeshi

    IEICE Trans. Inf. & Syst., D   88 ( 7 ) 1623 - 1629  2005.07

     View Summary

    This paper presents a highly parallel architecture for deblocking filter in H.264/AVC. We adopt various parallel schemes in memory sub-system and datapath. A 2-dimensional parallel memory scheme is employed to support efficient parallel access in both horizontal and vertical directions in order to speed up the whole filtering process. This parallel memory also eliminates the need for a transpose circuit. In the datapath, an algorithm optimization is performed to implement parallel filtering with hardware reuse. Pipeline techniques are also adopted to improve the throughput of filtering operations. Our design is implemented under TSMC 0.18μm technology. Results show that the core size is 0.82×1.13 mm^2 when the maximum frequency is 230 MHz. Compared to other existing architectures, our design has advantages in both speed and area.

    CiNii

  • A Memory-Reduction Method for Partially-Parallel LDPC Decoder Based on Min-Sum Algorithm

    ISHIKAWA Tatsuyuki, SHIMIZU Kazunori, IKENAGA Takeshi, GOTO Satoshi

    Technical report of IEICE. VLD   105 ( 148 ) 43 - 48  2005.06

     View Summary

    In this paper, we propose a memory-reduction method for partially-parallel LDPC decoder based on min-sum algorithm. We focus on the reliability messages by the row-operation can be obtained from only two absolute value or three signed value. In our proposed LDPC decoder, the row-operation module outputs the minimum absolute value, second minimum value, the flag signals and the signed bits, and they are stored in memory of row-operation module. These values and signals are fed to column operation module. We implemented partially-parallel LDPC decoder based on our proposed method. Implementation result shows that memory requirement can be reduced by our implemented LDPC decoder.

    CiNii

  • Low Complex Computational Video Coding Algorithm Based on Adaptive Tree

    HIRATSUKA Seiichiro, GOTO Satoshi, BABA Takaaki, IKENAGA Takeshi

    IEICE technical report. Image engineering   104 ( 752 ) 31 - 36  2005.03

     View Summary

    MPEG1/2/4, H.261/3 are based on discrete cosine transform (DCT) and motion compensation (MC). Since they require high computational complexity, they consume a lot of energy. Therefore, they are not suitable for communication with mobile terminals, such as personal digital assistants (PDA). On the other hand, the video coding using 3-D hierarchical tree-structure, such as octree, has been proposed with low computational complexity. The drawback of it, however, is low compression efficiency. This paper proposes a new video coding and presents some evaluation results. It can attain both low computational complexity and high compression efficiency. The most prominent feature of the algorithm is that a upper 3-D block is adaptively segmented to arbitrarily shaped lower blocks. The experimental results show that the computational complexity of our method is one-tenth of MPEG4 codec, and the compression efficiency is about 1.2 dB better than that of the octree method. Moreover we design the region discrimination circuit by HDL and verify the possibility. The new algorithm makes a significant contribution to the development of lower electricity consumption video communication systems.

    CiNii

  • A-4-8 A variable-speed fast-forwarding algorithm and its hardware development for MPEG video stream of camcorder

    Masunaga Koichi, Goto Satoshi, Ikenaga Takeshi

    Proceedings of the IEICE General Conference   2005   89 - 89  2005.03

    CiNii

  • Implementation and Evaluation of Partial-Parallel LDPC Decoder Improving Belief Propagation based on Sum-Product Algorithm

    SHIMIZU Kazunori, ISHIKAWA Tatsuyuki, TOGAWA Nozomu, IKENAGA Takeshi, GOTO Satoshi

    Technical report of IEICE. VLD   104 ( 709 ) 73 - 78  2005.03

     View Summary

    In this paper, we propose a partial-parallel LDPC decoder improving belief propagation based on sum-product algorithm. Our proposed partial-parallel LDPC decoder processes column operations for bit nodes in conjunction with row operations for check nodes. Bit functional unit with pipeline architecture in our LDPC decoder allows us to process column operations for every bit node connected to each of check nodes which are processed by row operations in parallel. Thus, our proposed LDPC decoder increases the number of belief propagations in the sum-product algorithm. We implemented the proposed partial-parallel LDPC decoder on a FPGA, and simulated its decoding performance. Practical simulation shows that our proposed partial-parallel LDPC decoder improves the number of iterations and bit error performance in the sum-product algorithm.

    CiNii

  • A variable-speed fast-forwarding algorithm and its hardware development for MPEG video stream

    MASUNAGA Koichi, GOTO Satoshi, IKENAGA Takeshi

    Technical report of IEICE. VLD   104 ( 708 ) 53 - 58  2005.03

     View Summary

    This paper proposes a content-based variable-speed fast-forwarding algorithm for MPEG video stream. This algorithm utilizes both motion vector and macro block type to detect important scenes and play them back adaptively. Simulation results show this algorithm enables to play important scenes smoothly for video sequences taken by a surveillance camera and a camcorder. Moreover, hardware evaluation shows this function can be embedded into a MPEG decoder by adding a 2441 gate module."

    CiNii

▼display all

Industrial Property Rights

  • 画像処理装置、画像処理方法及び画像処理プログラム

    5337667

    池永 剛, 佐々木 毅

    Patent

  • 補間器及び小数動き推定装置

    後藤 敏, 池永 剛, 楊 長旗

    Patent

  • SAD演算器

    後藤 敏, 池永 剛, 宋 揚, 岡村 陽介

    Patent

  • 付加情報処理装置、情報処理装置、及び、記憶装置

    池永 剛, 後藤 敏

    Patent

  • 画像処理装置、画像処理方法、画素抽出方法、それらの方法をコンピュータにより実行可

    池永 剛, 馬場 孝明, 後藤 敏

    Patent

  • LDPC符号検出装置及びLDPC符号検出方法

    後藤 敏, 池永 剛, 戸川 望, 清水 一範

    Patent

  • 画像信号の符号化方法および装置

    池永 剛, 後藤 敏, 馬場 孝明

    Patent

  • 乗算剰余演算器及び情報処理装置

    4170267

    池永 剛, 後藤 敏

    Patent

  • 乗算剰余演算器及び情報処理装置

    4180024

    後藤 敏, 池永 剛

    Patent

  • 動き推定方法及び動き推定装置、並びにプログラム

    4537136

    後藤 敏, 李 申, 池永 剛

    Patent

▼display all

Other

  • Waseda University Researchers Database

     View Summary

    https://w-rdb.waseda.jp/html/100000676_en.html

  • SpaceLABO: Kitakyushu City Science Museum (Virtual museum: Japanese only)

     View Summary

    http://www.waseda.jp/sem-ikenaga/content/SpaceLABO/SpaceLABO.html

  • Waseda Research Profile

     View Summary

    https://waseda.pure.elsevier.com/en/persons/takeshi-ikenaga

  • Google Scholar

     View Summary

    https://scholar.google.com/citations?user=Q2ugsNcAAAAJ&hl=ja

  • DBLP

     View Summary

    http://www.informatik.uni-trier.de/~ley/db/indices/a-tree/i/Ikenaga:Takeshi.html

Awards

  • Best Presentation Award

    2022.08   Third International Conference on Computer Vision and Information Technology (CVIT 2022)   Relative Vectors Clustering and Temporal Constraint based Generalized Hough Transform for High Frame Rate and Ultra-low Delay Arbitrary Shape Detection

    Winner: Wenliang Yang, Yuan Li, TingTing Hu, Ryuji Fuchikami, Takeshi Ikenaga

  • Best Presentation Award

    2022.08   Third International Conference on Computer Vision and Information Technology (CVIT 2022)   Voxel-based Recovery and Trajectory Separable Error Rectification for Multi-view 3D Pose Reconstruction of Jump Analysis in Figure Skating

    Winner: Zisheng Zeng, Yanchao Liu, Xina Cheng, Takeshi Ikenaga

  • Best Presentation Award

    2022.07   Sixth International Conference on Imaging, Signal Processing and Communications (ICISPC 2022)   Multi-scale and Bi-path method based on Image Entropy and CNN for Fast CU Partition in VVC

    Winner: Yifan Zhai, Xiao Yan, Yibo Fan, Takeshi Ikenaga

  • Best Presentation Award

    2020.06   5th International Workshop on Pattern Recognition (IWPR 2020)   3D pose reconstruction with multi-perspective and spatial confidence point group for jump analysis in figure skating

    Winner: Limao Tian, Xina Cheng, Masaaki Honda, Takeshi Ikenaga

  • Waseda University Presidential Teaching Award

    2020.01   Waseda University  

    Winner: 池永 剛

  • Best Presentation Award

    2019.08   3rd International Conference on Artificial Intelligence and Virtual Reality (AIVR 2019)   Motion Statistic Based Local Homography Transformation Estimation for Mismatch Removal

    Winner: Songlin Du, Takeshi Ikenaga

  • Best Presentation Award

    2018.09   The 6th IIAE International Conference on Intelligent Systems and Image Processing (ICISIP2018)   Search-Free Gridding and Temporal Local Matching Based Observation for High Frame Rate and Ultra-Low Delay SLAM System

    Winner: Yuchen Yang, Songlin Du, Takeshi Ikenaga

  • Best Paper Award

    2017.11   IEEE International Symposium on Intelligent Signal Processing and Communication Systems 2017 (ISPACS2017)   Low-Dimensional Superpixel Descriptor for Visual Correspondence Estimation in Video

    Winner: Songlin Du, Takeshi Ikenaga

  • Best Presentation Award

    2017.03   Second International Conference on Multimedia and Image Processing (ICMIP 2017)   Real-time 3D Ball Tracking with CPU-GPU Acceleration Using Particle Filter with Multi-command queues and Stepped Parallelism Iteration

    Winner: Yilin Hou, Xina Cheng, Takeshi Ikenaga

  • Best Paper Award

    2016.03   12th IEEE Colloquium on Signal Processing and its Applications (CSPA 2016)  

    Winner: Yutaro Kawakami, Gaoxing Chen, Takeshi Ikenaga

  • Certificate of APSIPA Distinguished Lecturer Program

    2015.12   APSIPA  

    Winner: Takeshi Ikenaga

  • Best Paper Award

    2014.05   The Sixth International Conferences on Advances in Multimedia (MMEDIA 2014)   Keypoint of Interest Based on Spatio-temporal Feature Considering Mutual Dependencyand Camera Motion

    Winner: Takahiro Suzuki, Takeshi Ikenaga

  • Best Paper Award

    2014.03   Journal of Signal Processing   Adaptive-Motion-Detection-Based Skip-Mode Predecision in Motion Estimation for Video Surveillance

    Winner: Jia Su, Takeshi Ikenaga

  • ベストポスター賞

    2011.10   映像メディア処理シンポジウム   ウェアラブル型ハンズフリーデジカメ実現のためのハンドジェスチャインタフェース

    Winner: 岩﨑義将, 池永 剛

  • ICD最優秀ポスター賞

    2010.05   LSIとシステムのワークショップ2010   KLT Trackerを用いたリアルタイム動き検出システム

    Winner: 筬島 敏光, 河根 広大, 佐々木 毅, 下袴田 直樹, 岡本 隆浩, 大住 勇治, 池永 剛

  • Samsung Award

    2009.11   International SoC Design Conference (ISOCC2009)   Architecture Optimization for H.264/AVC Propagate Partial SAD Engine in HDTV Application

    Winner: Yiqing Huang, Takeshi Ikenaga

  • Best Paper Award

    2009.03   The 5th International Colloquium on Signal Processing and its Applications (CSPA 2009)   VLSI Oriented Fast Motion Estimation Algorithm Based on Macroblock and Motion Feature Analysis

    Winner: Yiqing Huang, Takeshi Ikenaga

  • 画像電子学会論文誌優秀論文賞

    2008.06   画像電子学会   キュービック補間に基づく魚眼画像の高画質補正アルゴリズム及び専用ハードウェアエンジンの提案

    Winner: 森隆 寛, 外村 元伸, 大住 勇治, 後藤 敏, 池永 剛

  • IP Excelent Award

    2008.04   第10回LSI IPデザイン・アワード   1.41W フルハイビジョン用H.264/AVCエンコーダSoC

    Winner: 池永 剛, 劉 振宇, 宋 楊, 邵 明, 李 申, 李 凌峰, 後藤 敏, 石渡俊一, 中河正樹

  • Samsung Electronics Award Silver Prize

    2007.10   International SoC Design Conference   A High Throughput Multiple Transform Architecture for H.264/AVC Fidelity Range Extensions

    Winner: Yao Ma, Yang Song, Takeshi Ikenaga, Satoshi Goto

  • IP Award

    2007.05   第9回LSI IPデザイン・アワード   1.14Gb/s 15360bit LDPC符号復号器

    Winner: 清水一範, 池永剛, 後藤敏

  • IP Award

    2006.05   第8回LSI IPデザイン・アワード   高セキュリティを実現するIPsecプラットフォーム

    Winner: 東 邦彦, 大塚 重和, 深澤 宏, 嶋崎 真也, 鈴木 孝一郎, 古川 輝幸, 久門 亨, 後藤 敏, 池永 剛

  • DAC/ISSCC 2006 Student Design Contest, Conceptual Category: 1st Place Winner

    2006.02   DAC/ISSCC   ASIC Implementation of LDPC Decoder Accelerating Message-Passing Schedule

    Winner: Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

  • 技術賞

    1999.01   NTT 入出力システム研究所  

    Winner: 池永 剛

  • 革新研究賞

    1996.12   NTTシステムエレクトロニクス研究所  

    Winner: 池永 剛

  • 研究実用化賞

    1995.12   NTT LSI研究所  

    Winner: 池永 剛

  • Research Encouragement Award

    1992.03   IEICE  

    Winner: 池永 剛

  • Furukawa Sansui Award

    1988.03   Waseda University  

    Winner: 池永 剛

▼display all

Research Projects

  • High frame rate and ultra-Low delay video sensing system for interactive applications

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (C)

    Project Year :

    2021.04
    -
    2024.03
     

  • Full automatic 3D sport analysis based on video sensing

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Challenging Exploratory Research

    Project Year :

    2016.04
    -
    2019.03
     

    Ikenaga Takeshi, CHENG Xina, HONDA Masaaki, IKOMA Norikazu

     View Summary

    The purpose of this research is to implement a full-automatic 3D sports analysis system from multiple high-definition video cameras for advanced game strategies based on analysis data and TV sports broadcasting. By creating various technologies based on abrupt motion feature and spatial importance in Volleyball analysis, 3D position and velocity of a ball and twelve players are obtained in video rate (60fps) with an accuracy of 99% or more. In addition, we confirm that the event data on what play (e.g. receive, toss, spikes) has been made and the strategy data to decide the play efficacy (e.g. the number of available attackers and blockers, the attack tempo, the attack type, the set zone) are obtained automatically with 92%-100% accuracy.

  • 実態情報学博士プログラム(プログラム担当)

    Project Year :

    2013
    -
    2019
     

  • スポーツ解析(研究代表)

    Project Year :

    2016
    -
    2018
     

  • Low-cost video compression systems for ultra-high-resolution video

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)

    Project Year :

    2014.04
    -
    2017.03
     

    Ikenaga Takeshi, LIU Zhenyu, LIU Qin

     View Summary

    This research focused on HEVC-based low-cost video compression systems for ultra-high-resolution video which is a key for creating the next generation high-reality video communication and broadcasting services. Through three years activities, we proposed many hardware friendly and low complexity algorithms for not only HEVC (High Efficiency Video Coding) but also SHVC (Scalability Extension) and SCC (Screen Content Coding Extension) which are the extension of HEVC. We also promoted discussion with video system, communication and broadcasting companies and engaged research on applications based on high resolution video systems such as sport analysis and surveillance camera for creating new industries.

  • 高速映像システム(研究代表)

    Project Year :

    2015
    -
     
     

  • Video compression LSI technologies for ultra-high definition video

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)

    Project Year :

    2011.04
    -
    2014.03
     

    IKENAGA Takeshi

     View Summary

    This research focused on low-complexity video compression algorithms and hardware architectures for ultra-high-resolution video which is a key for creating the next generation high-reality video communication and broadcasting services. Through three years activities, we proposed many low-complexity algorithms and LSI architectures for basic functions of video compression (e.g. a motion estimation, an adaptive interpolation filter and a translation/quantization). Furthermore, we proposed low-complexity intra prediction and SAO (Sample Adaptive Offset) algorithms which are new functions in HEVC (High Efficiency Video Coding) standardized on Jan. 2013. We also promoted collaboration with video system, communication and broadcasting industries. Now, new video broadcasting services based on 4K and super HDTV are going to appear.

  • カメラ向け画質評価(分担)

    Project Year :

    2013
    -
    2014
     

  • 映像トランスコード技術に関する研究(研究代表)

    Project Year :

    2012
     
     
     

  • 次世代画像符号化方式(研究代表)

    Project Year :

    2010
    -
    2012
     

  • High-Tech Research Center Project:Advanced material device and system development

    High-Tech Research Center Project

    Project Year :

    2007
    -
    2012
     

  • International Research and Education Center for Ambient SoC

    Global COE:

    Project Year :

    2007
    -
    2012
     

  • Ultra-low power media processing SoC

    CREST

    Project Year :

    2006
    -
    2012
     

  • スーパーハイビジョン映像符号化LSIの研究 (研究代表)

    Project Year :

    2008
    -
    2010
     

  • ローム研究助成 (研究代表)

    Project Year :

    2009
     
     
     

  • 画像処理認識技術の研究開発 (研究代表)

    Project Year :

    2008
    -
    2009
     

  • 画像符号化SoC開発 (研究代表)

    Project Year :

    2008
     
     
     

  • ICT application LSI IP and its design methodologies

    Knowledge Cluster Project

    Project Year :

    2007
    -
    2008
     

  • 次世代FPGA向けアプリケーション技術の研究 (研究代表)

    Project Year :

    2007
    -
    2008
     

  • 車載向け画像認識システムの研究開発 (分担)

    Project Year :

    2007
    -
    2008
     

  • ICTアプリケーションIP開発 (分担)

    Project Year :

    2007
    -
    2008
     

  • 超高精細画像向け画像コーデックの研究開発 (分担)

    Project Year :

    2007
    -
    2008
     

  • 超低消費電力画像圧縮LSI (分担)

    Project Year :

    2005
    -
    2007
     

  • 高速無線通信 (分担)

    Project Year :

    2005
    -
    2007
     

  • Basic software for System LSI design

    Project Year :

    2003
    -
    2007
     

  • JPEG2000の高速アルゴリズム (研究代表)

    Project Year :

    2005
    -
    2006
     

  • 耐タンパ暗号処理LSI (研究代表)

    Project Year :

    2005
    -
    2006
     

  • 画像処理用システムLSI (研究代表)

    Project Year :

    2005
    -
    2006
     

  • Silicon in Silicon技術を用いた画像処理LSI (分担)

    Project Year :

    2004
    -
    2006
     

  • 動的再構成可能LSI (研究代表)

    Project Year :

    2004
    -
    2006
     

  • 画像セキュリティLSI (研究代表)

    Project Year :

    2004
    -
    2006
     

  • System LSI for ubiquitus information processing

    Knowledge Cluster Project

    Project Year :

    2002
    -
    2006
     

  • 携帯機器用統合画像処理エンジンLSI (研究代表)

    Project Year :

    2002
    -
    2006
     

  • RSA暗号の高速演算アルゴリズム (研究代表)

    Project Year :

    2002
    -
    2006
     

  • 動画像圧縮アプリケーション開発 (研究代表)

    Project Year :

    2005
     
     
     

  • 高性能公開鍵暗号処理LSI (研究代表)

    Project Year :

    2002
    -
    2004
     

  • インテリジェントセンシング用インタフェースLSI (研究代表)

    Project Year :

    2003
     
     
     

  • ユビキタス無線通信用動的再構成可能LSI (研究代表)

    Project Year :

    2002
    -
    2003
     

▼display all

Presentations

  • 映像センサを用いたスポーツ情報解析

    池永 剛  [Invited]

    電子情報通信学会スマートインフォメディアシステム研究会 

    Presentation date: 2016.12

  • Video Processing System Industry - Challenge for innovation -

    Takeshi Ikenaga  [Invited]

    APSIPA Distinguished Lecture Program in Nanyang 

    Presentation date: 2015.12

  • Video Processing System Industry - Challenge for innovation -

    Takeshi Ikenaga  [Invited]

    APSIPA Distinguished Lecture Program in Tokyo Insititue of Technology 

    Presentation date: 2015.06

  • Video Processing System Industry - Challenge for innovation -

    Takeshi Ikenaga  [Invited]

    APSIPA Distinguished Lecture Program in Nanjing University 

    Presentation date: 2015.05

  • Video Processing System Industry - Challenge for innovation -

    Takeshi Ikenaga  [Invited]

    APSIPA Distinguished Lecture Program in Southeast University 

    Presentation date: 2015.05

  • Temporal Information based Adaptive Coding Unit Depth Decision for Low-Complexity HEVC Inter Prediction

    Jiawang Gu, Gaoxing Chen, Zhenyu Liu, Takeshi Ikenaga

    SOFT九州支部 中国・四国支部合同支部大会 

    Presentation date: 2015.03

  • 身体の動作軌跡のクラスタ化に基づく特徴量を用いたバレーボールの動作検出

    久保田 栄次郎, 誉田 雅彰, 池永 剛

    画像電子学会第272回研究会 

    Presentation date: 2015.02

  • APSIPA SPS TC Special lecture in Chulalongkorn University

    Takeshi Ikenaga  [Invited]

    APSIPA 

    Presentation date: 2014.12

  • APSIPA SPS TC Special lecture in Tohoku University

    Takeshi Ikenaga  [Invited]

    APSIPA 

    Presentation date: 2014.06

  • Smart Feature Detection Device for Cloud based Video Recognition System

    Takeshi Ikenaga  [Invited]

    International Symposium on VLSI Design, Automation & Test (VLSI-DAT 2014) 

    Presentation date: 2014.04

  • 自転車特有の角度変化と上下振動を考慮した予測・尤度モデルを用いたパーティクルフィルタによる後方確認支援向け車両追跡

    三上洋平, 生駒哲一, 池永 剛

    電子情報通信学会パターン認識・メディア理解研究会 

    Presentation date: 2014.03

  • 車載機器向けHCIのための動き特徴量と追跡を用いた手輪郭補正と指の長さの2段階閾値に基づくクリック動作検出

    北尾 雄一朗, 池永 剛

    電子情報通信学会パターン認識・メディア理解研究会 

    Presentation date: 2014.03

  • クラス結合とブロック境界予測に基づいたHEVCのハードウェア向けSAOアルゴリズム

    裴 振宇, 陳 高星, 劉 振宇, 池永 剛

    電子情報通信学会画像工学研究会 

    Presentation date: 2014.03

  • 画像内の肌色ノイズ領域除去を目的とした動き情報と追跡処理を用いた手領域検出手法

    北尾 雄一朗, 池永 剛

    28回信号処理シンポジウム 

    Presentation date: 2013.11

  • クラス結合と事前決定に基づいたHEVCのサンプルアダプティブオフセットにおける低演算処理

    裴 振宇, 陳 高星, 池永 剛

    28回信号処理シンポジウム 

    Presentation date: 2013.11

  • APSIPA SPS TC Special lecture in National Chao-Tung University

    Takeshi Ikenaga  [Invited]

    APSIPA 

    Presentation date: 2013.03

  • APSIPA SPS TC Special lecture in National Cheng-Kung University

    Takeshi Ikenaga  [Invited]

    APSIPA 

    Presentation date: 2013.03

  • 動的背景差分と照明環境を考慮した影面積変化によるプロジェクター向けジェスチャーインタフェース

    奥山顕太, 池永剛

    火の国シンポジウム2013 

    Presentation date: 2013.03

  • CAMshift法を用いた指追跡と指の長さ変化の分析による空中クリック動作認識

    北尾 雄一朗, 池永 剛

    2013年電子情報通信学会総合大会 

    Presentation date: 2013.03

  • 再構成超解像におけるイテレーションと画質

    合志 清一, 関口 裕之, 清水 嘉泰

    映像情報メディア学会2012年冬季大会 

    Presentation date: 2012.12

  • エンハンシングとスムージングを両立した非線形偏微分方程式に基づく高画質化手法

    清水 嘉泰, 池永 剛

    映像メディア処理シンポジウム(IMPS 2012) 

    Presentation date: 2012.10

  • 対象静止時にも対応した動きと色を特徴量とするCAMshift による実時間両手追跡手法

    荒木 良介, 池永 剛

    映像メディア処理シンポジウム(IMPS 2012) 

    Presentation date: 2012.10

  • CAMshift 法による手と指の同時追跡を用いたクリック動作認識

    北尾 雄一朗, 池永 剛

    映像メディア処理シンポジウム(IMPS 2012) 

    Presentation date: 2012.10

  • 配ヒストグラムを利用した特徴点検出と特徴量記述の並列ハードウェア実装

    鈴木 貴大, 池永 剛

    映像メディア処理シンポジウム(IMPS 2012) 

    Presentation date: 2012.10

  • 再構成型超解像の新たな課題

    合志 清一, 関口 裕之, 清水 嘉泰, 池永 剛

    2012年電子情報通信学会ソサイエティ大会 

    Presentation date: 2012.09

  • 超解像化映像の主観評価

    合志 清一, 関口 裕之, 清水 嘉泰, 池永 剛

    2012年電子情報通信学会ソサイエティ大会 

    Presentation date: 2012.09

  • 非線形処理を用いた映像の超解像化

    合志 清一, 関口 裕之, 清水 嘉泰, 池永 剛

    2012年電子情報通信学会ソサイエティ大会 

    Presentation date: 2012.09

  • 非線形超解像技術の提案と画質評価

    合志 清一, 関口 裕之, 清水 嘉泰, 池永 剛

    電子情報通信学会パターン認識・メディア理解研究会 

    Presentation date: 2012.09

  • 動きマスクと動き予測を適用したCAMshift による実時間両手領域検出・追跡手法

    荒木 良介, 池永 剛

    第18回画像センシングシンポジウム 

    Presentation date: 2012.06

  • 手領域における重みづけを用いたMeanshiftによる指先追跡

    北尾 雄一朗, 荒木 良介, 池永 剛

    第18回画像センシングシンポジウム 

    Presentation date: 2012.06

  • コーナー検出に基づく低演算SIFTのFPGAによる実時間処理

    鈴木 貴大, 池永 剛

    第18回画像センシングシンポジウム 

    Presentation date: 2012.06

  • 特徴領域に基づくパーティクルフィルタを用いた複雑環境下における物体追跡

    椎名 雄飛, 池永 剛

    第18回画像センシングシンポジウム 

    Presentation date: 2012.06

  • ウェアラブル型デジタルカメラ実現のための手指領域を用いたハンドジェスチャインタフェース

    岩義将, 池永 剛

    画像電子学会第260回研究会 

    Presentation date: 2012.03

  • 粒子予測と均等分割に基づくパーティクルフィルタの高速化手法

    三上洋平, 池永 剛

    2012年電子情報通信学会総合大会 

    Presentation date: 2012.03

  • パーティクルフィルタを用いた二物体同時追跡に基づくリカバリー手法

    椎名雄飛, 池永 剛

    2012年電子情報通信学会総合大会 

    Presentation date: 2012.03

  • モーションマスクを利用したCAMshiftによる実時間手領域検出・追跡手法

    荒木良介, 池永 剛

    2012年電子情報通信学会総合大会 

    Presentation date: 2012.03

  • コーナー検出に基づく低演算量SIFTアルゴリズムの実時間ハードウェア実装

    鈴木貴大, 池永 剛

    2012年電子情報通信学会総合大会 

    Presentation date: 2012.03

  • Special lecture in Shanghai Jiao Tong University

    Takeshi Ikenaga  [Invited]

    APSIPA 

    Presentation date: 2012.02

  • Special lecture in Fudan University

    Takeshi Ikenaga  [Invited]

    APSIPA 

    Presentation date: 2012.02

  • Special lecture in Nanjing University

    Takeshi Ikenaga  [Invited]

    APSIPA 

    Presentation date: 2012.02

  • Special lecture in Tsinghua University

    Takeshi Ikenaga  [Invited]

    APSIPA 

    Presentation date: 2012.02

  • 差分情報に基づくパーティクルフィルタを用いた複雑環境下における物体追跡

    椎名雄飛, 池永 剛

    電子情報通信学会パターン認識・メディア理解研究会 

    Presentation date: 2012.02

  • ウェアラブル型ハンズフリーデジカメ実現のためのハンドジェスチャインタフェース

    岩崎義将, 池永 剛

    映像メディア処理シンポジウム(IMPS 2011) 

    Presentation date: 2011.10

  • 積分画像によるコーナー検出とSIFT特徴量を組み合わせた実時間マッチング

    鈴木貴大, 池永 剛

    映像メディア処理シンポジウム(IMPS 2011) 

    Presentation date: 2011.10

  • 非線形フィルタに基づく高精細ディスプレイ向け実時間超解像システム

    清水 嘉泰, 池永 剛

    第17回画像センシングシンポジウム 

    Presentation date: 2011.06

  • スポーツシーンにおける不規則運動物体追跡を目指した2重モデル型パーティクルフィルタ

    椎名 雄飛, 池永 剛

    第17回画像センシングシンポジウム 

    Presentation date: 2011.06

  • マンマシンインターフェースを対象としたKLT Trackerの特徴点集合による両手領域追跡

    荒木 良介, 池永 剛

    第17回画像センシングシンポジウム 

    Presentation date: 2011.06

  • 輝度値の勾配変化とラプラシアンに基づいた非線形フィルタによる低演算量超解像とそのハードウェア実装

    清水嘉泰, 池永 剛

    第44回 機能集積情報システム研究会 

    Presentation date: 2011.03

  • 曲率に基く特徴点抽出とラベリングによる追跡を行う実時間ハンドジェスチャインタフェース

    岩崎義将, 池永 剛

    火の国シンポジウム2011 

    Presentation date: 2011.03

  • KLT Tracker を用いた特徴点集合による手領域追跡

    荒木良介, 池永 剛

    2011年電子情報通信学会総合大会 

    Presentation date: 2011.03

  • 2 重モデルに基づくパーティクルフィルタを用いた不規則運動物体の追跡

    椎名雄飛, 池永 剛

    2011年電子情報通信学会総合大会 

    Presentation date: 2011.03

  • ハイパスフィルタおよび周辺画素の差分二乗和を利用した非線形フィルタによる低演算量超解像フィルタ

    清水嘉泰, 池永 剛

    2011年電子情報通信学会総合大会 

    Presentation date: 2011.03

  • フレーム間移動量による適応型パーティクルフィルタを用いた垂直方向の不規則運動物体の追跡

    椎名 雄飛, 池永 剛

    画像電子学会第254回研究会 

    Presentation date: 2010.11

  • KLT Trackerを用いたリアルタイム動き検出システム

    筬島 敏光, 河根 広大, 佐々木 毅, 下袴田 直樹, 岡本 隆浩, 大住 勇治, 池永 剛

    LSIとシステムのワークショップ2010 

    Presentation date: 2010.05

  • 動きを考慮したKLT Tracker による実時間動き検出システムの実現

    河根広大, 佐々木毅, 岡本隆浩, 筬島敏光, 池永剛

    第41回 機能集積情報システム研究会 

    Presentation date: 2010.03

  • 普及型FPGAを用いたKLT Trackerの実時間処理システムの実現

    河根広大, 佐々木毅, 岡本隆浩, 筬島敏光, 池永剛

    画像電子学会第250回研究会 

    Presentation date: 2010.03

  • 動きを考慮したKLT Trackerによる特徴点選択ハードウェアエンジンの実現

    佐々木毅, 河根広大, 岡本隆浩, 筬島敏光, 池永剛

    画像電子学会第250回研究会 

    Presentation date: 2010.03

  • 重みマスクを用いたKLT Tracker による動きを考慮した特徴点抽出法

    佐々木 毅, 河根 広大, 池永 剛, 岡本 隆浩, 筬島 敏光

    第24回 信号処理シンポジウム 

    Presentation date: 2009.11

  • 普及型FPGAを用いた実時間KLT Trackerの低コスト実装

    河根 広大, 佐々木 毅, 池永 剛, 岡本 隆浩, 筬島 敏光

    第24回 信号処理シンポジウム 

    Presentation date: 2009.11

  • Analysis of Adaptive Algorithm to Power Aware Designs for H.264/AVC Integer Motion Estimation Engine in HDTV Application

    Yiqing Huang, Takeshi Ikenaga  [Invited]

    APSIPA 

    Presentation date: 2009.10

  • 動きを考慮したKLT Trackerの特徴点抽出法

    佐々木 毅, 河根 広大, 池永 剛

    電子情報通信学会ソサイエティ大会 

    Presentation date: 2009.09

  • 実時間KLT Trackerを用いた移動体検出システムの実現

    河根 広大, 坂寄 貴宏, 池永 剛

    LSIとシステムのワークショップ2009 

    Presentation date: 2009.05

  • 1D-based 2D Gaussian Convolution Unit Based Hardware Accelerator for Gaussian &amp; DoG Pyramid Construction in SIFT

    Jingbang Qiu, Tianci Huang, Takeshi Ikenaga

    電子情報通信学会総合大会 

    Presentation date: 2009.03

  • メディア処理応用からの機能集積情報システムの実現

    池永 剛  [Invited]

    第38回機能集積情報システム研究会 

    Presentation date: 2009.03

  • An Edge Information Based Block Size Decision Method for Intra Mode Decision in H.264/AVC

    Zhewen Zheng, Takeshi Ikenaga, Qin Liu, Yiqing Huang

    電子情報通信学会総合大会 

    Presentation date: 2009.03

  • Multi-Stage Based Inter Mode Decision Algorithm in H.264/AVC

    iqing Huang, Qin Liu, Takeshi Ikenaga

    電子情報通信学会総合大会 

    Presentation date: 2009.03

  • Bayesian Decision Based All-Zero Block Detection Algorithm in H.264/AVC

    Qin Liu, Yiqing Huang, Takeshi Ikenaga

    電子情報通信学会総合大会 

    Presentation date: 2009.03

  • Macroblock Level Rate Control for H.264/AVC Based on Model Parameter Update and Weighted Reference Calculation

    Shuijiong Wu, Yiqing Huang, Qin Liu, Takeshi Ikenaga

    電子情報通信学会総合大会 

    Presentation date: 2009.03

  • 1D-based 2D Gaussian Convolution Unit Based Hardware Accelerator for Gaussian & DoG Pyramid Construction in SIFT

    Jingbang Qiu, Tianci Huang, Takeshi Ikenaga

    電子情報通信学会総合大会 

    Presentation date: 2009.03

  • A GMM based Foreground Extraction Algorithm in Complex Background for Surveillance System

    Tian ci Huang, Jing bang Qiu, Takeshi Ikenaga

    電子情報通信学会総合大会 

    Presentation date: 2009.03

  • 実時間KLT Trackerの特徴点追跡ハードウェアの実現

    坂寄貴宏, 河根広大, 池永 剛

    電子情報通信学会総合大会 

    Presentation date: 2009.03

  • 実時間KLT Trackerの特徴点抽出ハードウェアの実現

    河根広大, 坂寄貴宏, 池永 剛

    電子情報通信学会総合大会 

    Presentation date: 2009.03

  • 実時間KLT Tracker向きハードウェアエンジンの実現

    坂寄貴宏, 池永 剛

    電子情報通信学会画像工学研究会 

    Presentation date: 2009.03

  • LDPC符号化OFDM-UWB方式に基づく820Mb/s ベースバンド処理LSI

    牛木 慎祐, 中村 浩一, 清水 一範, 王 棋, 阿部 裕太, 後藤 敏, 池永 剛

    電子情報通信学会集積回路研究会 

    Presentation date: 2009.01

  • eSTREAMストリーム暗号への差分電力解析

    久門 亨, 角尾 幸保, 池永 剛, 後藤 敏

    電子情報通信学会論文誌A 

    Presentation date: 2008.11

  • A Fast Block Type Decision Algorithm for H.264/AVC Intra Prediction

    Guifen Tian, Tianruo Zhang, Takeshi Ikenaga, Satoshi Goto

    電子情報通信学会ソサイエティ大会 

    Presentation date: 2008.09

  • A Novel Hardware-Friendly Regular 3-Step Integer Motion Estimation Algorithm for H.264/AVC

    Wenqi You, Xianghui Wei, Yang Song, Takeshi Ikenaga, Satoshi Goto

    電子情報通信学会ソサイエティ大会 

    Presentation date: 2008.09

  • VLSI Design of Level C Bandwidth Reduction Scheme for MPEG-2 to H.264/AVC Transcoding

    魏 湘輝, 池永 剛, 後藤 敏

    電子情報通信学会ソサイエティ大会 

    Presentation date: 2008.09

  • 簡易型KLT Trackerによる実時間動きベクトル抽出処理

    坂寄貴宏, 後藤 敏, 池永 剛

    電子情報通信学会ソサイエティ大会 

    Presentation date: 2008.09

  • メディア処理応用からのアンビエントSoC実現への取り組み

    池永 剛

    アンビエント グローバルCOEシンポジュウム 

    Presentation date: 2008.06

  • Rate Estimation in RDO of H.264/AVC

    Yan Zhuang, Takeshi Ikenaga, Satoshi Goto

    第21回回路 とシステム軽井沢ワークショップ 

    Presentation date: 2008.04

  • SAD Accumulation Termination Algorithm and Early Loop Termination Decision based High Quality Fast Motion Estimation for H.264/AVC

    Wenqi You, Yang Song, Xianghui Wei, Takeshi Ikenaga, Satoshi Goto

    第21回回路 とシステム軽井沢ワークショップ 

    Presentation date: 2008.04

  • A Low-cost LSI Design of AES against DPA Attack by Hiding Power Information

    Yibo Fan, Takeshi Ikenaga, Yukiyasu Tsunoo, Satoshi Goto

    第21回回路 とシステム軽井沢ワークショップ 

    Presentation date: 2008.04

  • 高効率Message-Passingスケジュールを用いたイレギュラーLDPC復号器の高速マルチレート設計

    阿部 裕太, 唐 文明, 李 星, 清水一範, 池永 剛, 後藤 敏

    第21回回路 とシステム軽井沢ワークショップ 

    Presentation date: 2008.04

  • An adaptive order for error concealment in H.264/AVC

    Jun Wang, Takeshi Ikenaga, Satoshi Goto

    電子情報通信学会集積回路研究会 

    Presentation date: 2008.03

  • Adaptive Spatial EC based on Numerical Measures of Edge Statistical Model

    Jun Wang, Takeshi Ikenaga, Satoshi Goto

    電子情報通信学会総合大会 

    Presentation date: 2008.03

  • A Mode Reduction Based Fast Integer Motion Estimation Algorithm for HDTV

    Wenqi You, Yang Song, Guifen Tian, Takeshi Ikenaga, Satoshi Goto

    電子情報通信学会総合大会 

    Presentation date: 2008.03

  • RATE ESTIMATION USING LINEAR PROGRAMMING IN RDO OF H.264AVC

    Yan Zhuang, Tianruo Zhang, Guifen Tian, Takeshi Ikenaga, Satoshi Goto

    電子情報通信学会総合大会 

    Presentation date: 2008.03

  • Level C+ Bandwidth Reduction Method for MPEG-2 to H.264 Transcoding

    Xianghui Wei, Hsing-Ying Ho, Weinqi You, Takeshi Ikenaga, Satoshi Goto

    電子情報通信学会総合大会 

    Presentation date: 2008.03

  • A Fast Mode Decision Algorithm for H.264/AVC Intra Prediction

    Guifen Tian, Tianruo Zhang, Wenqi You, Takeshi Ikenaga, Satoshi Goto

    電子情報通信学会総合大会 

    Presentation date: 2008.03

  • Group-Based Prediction Scheme on Multiple Reference Frame Fractional Motion Estimation in H.264/AVC

    Yao Ma, Yang Song, Yan Zhuang, Wenqi You, Takeshi Ikenaga, Satoshi Goto

    電子情報通信学会総合大会 

    Presentation date: 2008.03

  • High Throughput Rate-1/2 Partially-Parallel Irregular LDPC Decoder

    Wen Ji, Yuta Abe, Takeshi Ikenaga, Satoshi Goto

    電子情報通信学会総合大会 

    Presentation date: 2008.03

  • Integer Search Position Based Fast Motion Estimation in H.264/AVC

    Yiqing Huang, Satoshi Goto, Takeshi Ikenaga

    電子情報通信学会総合大会 

    Presentation date: 2008.03

  • Cross Low Pass Filter Based Subsampling Algorithm for H.264/AVC Motion Estimation

    Qin Liu, Satoshi Goto, Takeshi Ikenaga

    電子情報通信学会総合大会 

    Presentation date: 2008.03

  • A Novel Fast Block Type Decision Algorithm for Intra Prediction in H.264/AVC High Profile

    張 天若, 田 貴芬, 池永 剛, 後藤 敏

    電子情報通信学会総合大会 

    Presentation date: 2008.03

  • Prediction-based Center-bias Fast Fractional Motion Estimation Algorithm for H.264/AVC

    何 信瑩, 池永 剛, 後藤 敏

    電子情報通信学会総合大会 

    Presentation date: 2008.03

  • 長い符号長に適した低消費電力高効率Message-PassingLDPCデコーダーの設計

    田島直樹, 阿部裕太, 清水一範, 池永 剛, 後藤 敏

    電子情報通信学会集積回路研究会 

    Presentation date: 2008.03

  • 高効率Message-Passing スケジュールを用いた部分並列型イレギュラーLDPC復号器のマルチレート化設計

    阿部裕太, 田島直樹, 李 星, 清水一範, 池永 剛, 後藤 敏

    電子情報通信学会集積回路研究会 

    Presentation date: 2008.03

  • LDPC符号化OFDM方式における高速ベースバンド処理アーキテクチャの提案

    牛木慎祐, 中村浩一, 清水一範, 王 棋, 阿部裕太, 後藤 敏, 池永 剛

    電子情報通信学会集積回路研究会 

    Presentation date: 2008.03

  • H.264/AVCエラーコンシールメントに基づくUEPメディアシステムの消費電力削減手法

    田島直樹, 阿部裕太, 清水一範, 池永 剛, 後藤 敏

    電子情報通信学会総合大会 

    Presentation date: 2008.03

  • 動き予測のためのダイヤモンドウェッブ格子の探索アルゴリズム

    鄭 椙旭, 池永 剛, 後藤 敏

    電子情報通信学会総合大会 

    Presentation date: 2008.03

  • 高効率メッセージパッシングイレギュラーLDPC復号器の面積削減方法

    唐 文明, 阿部裕太, 池永 剛, 後藤 敏

    電子情報通信学会総合大会 

    Presentation date: 2008.03

  • メモリベース並列化FFT回路におけるメモリマッピング法

    牛木慎祐, 中村浩一, 清水一範, 後藤 敏, 池永 剛

    電子情報通信学会総合大会 

    Presentation date: 2008.03

  • A Hardware-oriented Hybrid Fast Mode Decision Algorithm in H.264/AVC Intra Encoder

    張 天若, 李 申, 林 恒遙, 池永 剛, 後藤 敏

    22回信号処理シンポジウム 

    Presentation date: 2007.11

  • Pixel Difference and Motion Feature Analysis to Complexity Reduction in H.264/AVC Motion Estimation

    黄 異青, 劉 振宇, 池永 剛, 後藤 敏

    22回信号処理シンポジウム 

    Presentation date: 2007.11

  • LDPC符号化UWB-OFDM方式におけるインターリーブ手法に関する提案

    中村浩一, 牛木慎祐, 清水一範, 後藤敏, 池永剛

    22回信号処理シンポジウム 

    Presentation date: 2007.11

  • 802.11nに準拠したLDPC誤り訂正符号の高速化設計

    阿部 裕太, 清水 一範, 李 星, 池永 剛, 後藤 敏

    第11回システムLSIワークショップ 

    Presentation date: 2007.11

  • ユビキタス・アンビエント情報化社会に向けた動画像圧縮LSI

    池永 剛  [Invited]

    電子情報通信学会信号処理研究会 

    Presentation date: 2007.10

  • Video Compression LSI: Past, Present, and Future Trends

    Takeshi Ikenaga  [Invited]

    The 7th International Conference on ASIC (ASICON2007) 

    Presentation date: 2007.10

  • ユビキタス・アンビエント情報化社会に向けた動画像圧縮LSI

    池永 剛  [Invited]

    電子情報通信学会信号処理研究会 

    Presentation date: 2007.10

  • 動画像圧縮LSIの技術動向

    池永 剛  [Invited]

    情報処理学会オーディオビジュアル複合情報処理研究会 

    Presentation date: 2007.09

  • 不均一誤り保護方式を用いたメディア処理システムの計算量削減手法

    田島直樹, 清水一範, 池永剛, 後藤敏

    情報処理学会オーディオビジュアル複合情報処理研究会 

    Presentation date: 2007.09

  • 動画像圧縮LSIの技術動向

    池永 剛  [Invited]

    情報処理学会オーディオビジュアル複合情報処理研究会 

    Presentation date: 2007.09

  • OFDM無線通信向き高速・低消費電力FFT回路の提案

    牛木 慎祐, 清水 一範, 中村 浩一, 後藤 敏, 池永 剛

    電子情報通信学会集積回路研究会 

    Presentation date: 2007.05

  • An Efficient Encryption Scheme for H.264 Format Video Streams

    Jidong Wang, Yibo Fan, Takeshi Ikenaga, Satoshi Goto

    第20回回路 とシステム軽井沢ワークショップ 

    Presentation date: 2007.04

  • Motion-content based Search Range Prediction in Variable Block Size Motion Estimation

    ZhenXing Chen, Yang Song, Takeshi Ikenaga, Satoshi Goto

    第20回回路 とシステム軽井沢ワークショップ 

    Presentation date: 2007.04

  • Inter Search Mode Reduction Based Parallel Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVC

    Yiqing Huang, Zhenyu Liu, Yang Song, Satoshi Goto, Takeshi Ikenaga

    第20回回路 とシステム軽井沢ワークショップ 

    Presentation date: 2007.04

  • Fragmented Edges Grouping for Monocular Building Extraction

    Jing Wang, Makoto Iwata, Hirokazu Koizumi, Hideo Shimazu, Satoshi Goto, Takeshi Ikenaga

    第20回回路 とシステム軽井沢ワークショップ 

    Presentation date: 2007.04

  • A real-time parallel architecture for human face detection based on the Algorithm Architecture Adequation approach

    Dmitriev Ivan, Grandpierre Thierry, Akil Mohamed, Ghorayeb Hicham, Satoshi Goto, Takeshi Ikenaga

    第20回回路 とシステム軽井沢ワークショップ 

    Presentation date: 2007.04

  • A High-speed Design of Montgomery Multiplier

    Yibo Fan, Takeshi Ikenaga, Satoshi Goto

    第20回回路 とシステム軽井沢ワークショップ 

    Presentation date: 2007.04

  • 高効率Message-Passingスケジュールを用いたLDPC復号器の低消費電力化

    清水 一範, 戸川 望, 池永 剛, 後藤 敏

    第20回回路 とシステム軽井沢ワークショップ 

    Presentation date: 2007.04

  • 高集積可能なソフトモジュール向けFixed-Outlineフロアプランナ

    山腰 由紀夫, 吉村 猛, 池永 剛, 後藤 敏

    第20回回路 とシステム軽井沢ワークショップ 

    Presentation date: 2007.04

  • 高効率Message-Passing スケジュールを用いた部分並列型イレギュラーLDPC復号器

    李 星, 清水一範, 池永 剛, 後藤 敏

    電子情報通信学会集積回路研究会 

    Presentation date: 2007.03

  • eSTREAM 提案暗号へのDPA解析報告

    久門 亨, 角尾 幸保, 深澤 宏, 庄司 陽彦, 後藤 敏, 池永 剛

    Symposium on Cryptography and Information Security (SCIS2007) 

    Presentation date: 2007.01

  • RSA暗号を実装したINSTAC-32に対するサイドチャネル攻撃実験

    深澤 宏, 東 邦彦, 後藤 敏, 池永 剛, 角尾 幸保, 久門 亨, 庄司 陽彦

    Symposium on Cryptography and Information Security (SCIS2007) 

    Presentation date: 2007.01

  • 楕円曲線暗号向けGF(2m) 上のDigit-Serial 乗算器の設計

    奈良竜太, 小原俊逸, 清水一範, 戸川望, 池永剛, 柳澤政生, 後藤敏, 大附辰夫

    電子情報通信学会VLSI設計技術研究会 

    Presentation date: 2007.01

  • モバイル向け0.3mW、1.4mm2動き検出プロセッサLSI

    平塚 誠一郎, 清水一範, 後藤 敏, 池永 剛

    電子情報通信学会集積回路研究会 

    Presentation date: 2006.12

  • キュービック補間を用いた魚眼レンズ画像の高画質補正アルゴリズムのFPGAを用いた実時間処理

    森 隆寛, 外村元伸, 大住 勇治, 池永 剛

    第10回システムLSIワークショップ 

    Presentation date: 2006.11

  • キュービック補間を用いた魚眼レンズ画像の高画質補正アルゴリズムの提案

    森 隆寛, 外村元伸, 池永 剛

    第5回情報科学技術フォーラム(FIT2006) 

    Presentation date: 2006.09

  • System-in-Silicon (SiS) 技術と動き探索エンジンへの応用

    熊谷浩一, Changqi Yang, 泉野人志, 成田信幸, 新城恵介, 岩下伸一, 中岡裕司, 河村智弘, 駒走英雄, 湊 司, 安保厚志, 鈴木隆昌, Zhenyu Liu, Yang Song, 後藤 敏, 池永 剛, 間淵 義宏, 吉田 健人

    電子情報通信学会集積回路研究会 

    Presentation date: 2006.05

  • Loss Free VLSI Oriented Full Computation Reusing Algorithm for H.264 Fractional Motion Estimation

    Ming Shao, Zhenyu Liu, Satoshi Goto, Takeshi Ikenaga

    第19回 回路とシステム軽井沢ワークショップ 

    Presentation date: 2006.04

  • A Strict Successive Elimination Algorithm for Fast Motion Estimation

    Yang Song, Zhenyu Liu, Takeshi Ikenaga, Satoshi Goto

    第19回 回路とシステム軽井沢ワークショップ 

    Presentation date: 2006.04

  • FIFOバッファによる高効率Message-Passingスケジュールを用いたLDPC復号器

    清水一範, 石川達之, 戸川望, 池永剛, 後藤敏

    第19回 回路とシステム軽井沢ワークショップ 

    Presentation date: 2006.04

  • A Derivative Bit Error Rate Model of UWB-Impulse Radio in the Presence of Inter-Symbol Interference

    Danyang Qu, Fumiaki Maehara, Satoshi Goto, Takeshi Ikenaga

    火の国情報シンポジウム2006 

    Presentation date: 2006.03

  • 動きベクトルによるスポーツ映像の競技シーン検出手法の提案

    奥川雄紀, 後藤 敏, 池永 剛

    情報処理学会第68回全国大会 

    Presentation date: 2006.03

  • 奥行情報を用いた携帯端末向けリアルタイム人物抽出LSI

    有門智弘, 後藤 敏, 池永 剛

    電子情報通信学会集積回路研究会 

    Presentation date: 2006.03

  • デジタルシネマ用JPEG 2000エンコーダ向け並列CBMアルゴリズム及びLSIアーキテクチャ

    伊東 健, 池永 剛, 中村 創

    電子情報通信学会集積回路研究会 

    Presentation date: 2006.03

  • 261MHz Parallel Tree Architecture for Full Search Variable Block Size Motion Estimation in H.264/AVC

    Zhenyu Liu, Yang Song, Takeshi Ikenaga, Satoshi Goto

    電子情報通信学会集積回路研究会 

    Presentation date: 2006.01

  • ストリーム暗号に対するDPA

    久門 亨, 角尾 幸保, 後藤 敏, 池永 剛

    Symposium on Cryptography and Information Security (SCIS2006) 

    Presentation date: 2006.01

  • メモリ容量削減手法を用いた高スループットLDPC復号器

    石川達之, 清水一範, 池永 剛, 後藤 敏

    電子情報通信学会集積回路研究会 

    Presentation date: 2006.01

  • Algorithm, architecture and system imtegration for video codec LSI

    Takeshi Ikenaga

    The 2nd Joint Waseda-NTU Workshop on Semiconductor Design 

    Presentation date: 2005.12

  • 復号特性を考慮した検査行列に基づく部分並列LDPC復号器

    劉 建廷, 清水 一範, 石川 達之, 池永 剛, 後藤 敏

    第9回システムLSIワークショップ 

    Presentation date: 2005.11

  • 携帯端末でのテレビ電話映像における奥行情報を用いた人物抽出アルゴリズム及びそのハードウェア化の提案

    有門智弘, 後藤 敏, 池永 剛

    第9回システムLSIワークショップ 

    Presentation date: 2005.11

  • 超低演算量な動き検出アルゴリズムと専用プロセッサへの実装

    塚誠一郎, 後藤 敏, 池永 剛

    電子情報通信学会信号処理/集積回路研究会 

    Presentation date: 2005.10

  • 携帯端末でのテレビ電話映像における奥行情報を用いた背景隠蔽

    有門智弘, 後藤 敏, 池永 剛

    電気関係学会九州支部第57回連合大会 

    Presentation date: 2005.09

  • Min-Sumアルゴリズムを用いたLDPC復号器のメモリ削減手法

    石川達之, 清水一範, 池永 剛, 後藤 敏

    電子情報通信学会VLD研究会 

    Presentation date: 2005.06

  • Motion Estimation Algorithm Modification and Implementation in H.264/AVC

    Yang Song, Zhenyu Liu, Satoshi Goto, Takeshi Ikenaga

    第18回回路とシステム軽井沢ワークショップ 

    Presentation date: 2005.04

  • Content-based Motion Estimation VLSI Design for Real-time MPEG-4 Video Coding

    Shen Li, Satoshi Goto, Takeshi Ikenaga, Hideki Takeda, Masataka Matusi

    第18回回路とシステム軽井沢ワークショップ 

    Presentation date: 2005.04

  • 信頼度の伝播効率を改善する部分並列LDPC復号器の実装と評価

    清水一範, 石川達之, 戸川望, 池永剛, 後藤敏

    第18回回路とシステム軽井沢ワークショップ 

    Presentation date: 2005.04

  • 適応型ツリーに基づく低計算量動画像圧縮アルゴズム

    平塚誠一郎, 後藤 敏, 馬場孝明, 池永 剛

    電子情報通信学会画像工学研究会(IE) 

    Presentation date: 2005.03

  • ハンディカムで撮影されたMPEG画像向け可変速早送りアルゴリズム及びそのハードウェア化の提案

    増永宏一, 後藤 敏, 池永 剛

    電子情報通信学会総合大会 

    Presentation date: 2005.03

  • MPEG画像向け可変速早送りアルゴリズム及びそのハードウェア化の提案

    増永宏一, 後藤 敏, 池永 剛

    電子情報通信学会ICD/VLD共催研究会 

    Presentation date: 2005.03

  • Sum-Productアルゴリズムにおける信頼度の伝播を改善する部分並列LDPC復号器の実装と評価

    清水一範, 石川達之, 戸川 望, 池永 剛, 後藤 敏

    電子情報通信学会ICD/VLD共催研究会 

    Presentation date: 2005.03

  • 低消費電力RSA暗号LSI

    久門 亨, 小林伸行, 池永 剛, 後藤 敏, 馬場孝明, 東 邦彦, 北尾一郎, 角尾幸保

    電子情報通信学会総合大会 

    Presentation date: 2005.03

  • 高性能GF(p)演算器を搭載した楕円曲線暗号LSI

    小林 伸行, 久門 亨, 内田 純平, 後藤 敏, 池永 剛, 角尾 幸保

    Symposium on Cryptography and Information Security (SCIS2005) 

    Presentation date: 2005.01

  • Video Processing SoC

    Takeshi Ikenaga

    NTU-Waseda System LSI Workshop 

    Presentation date: 2004.11

  • 動画圧縮のための三次元ウェーブレット変換

    張 青, 平塚誠一郎, 池永 剛, 後藤 敏, 馬場 孝明

    第19回信号処理シンポジウム 

    Presentation date: 2004.11

  • 固定カメラで撮影されたMPEG画像向け可変早送りのアルゴリズムおよびハードウェアの提案

    増永宏一, 後藤 敏, 池永 剛

    第8回システムLSIワークショップ 

    Presentation date: 2004.11

  • 楕円曲線暗号のLSI化

    小林伸行, 久門 亨, 内田純平, 後藤 敏, 池永 剛, 角尾幸保

    第8回システムLSIワークショップ 

    Presentation date: 2004.11

  • 公開鍵暗号向けモンゴメリ乗算剩余演算器

    久門 亨, 小林伸行, 池永 剛, 後藤 敏

    第8回システムLSIワークショップ 

    Presentation date: 2004.11

  • N bit-wise モンゴメリ乗算回路を搭載した楕円曲線暗号回路の実装

    小林伸行, 久門 亨, 内田純平, 後藤 敏, 池永剛, 角尾幸保

    電子情報通信学会ソサイエティ大会 

    Presentation date: 2004.09

  • ユビキタス情報化社会に向けたアプリケーションSoC

    池永 剛, 後藤 敏, 馬場孝明, 戸川 望

    計測自動制御学会 第4回 制御部門大会 

    Presentation date: 2004.05

  • System LSI education strategy at Waseda University

    Takeshi Ikenaga

    Waseda Univ. System LSI International Workshop 

    Presentation date: 2004.01

  • 多ビット乗算における演算回数の削減について

    久門 亨, 木村晋二, 池永 剛, 馬場孝明, 後藤 敏

    システムLSIワークショップ 2003 

    Presentation date: 2003.11

  • マルチモーダルインタフェースを用いた家庭内情報システム

    北端美紀, 池永剛, 野島久雄, 内村国治, 山下清美

    日本認知科学会第19回認知科学学会大会 

    Presentation date: 2002.06

  • キャラクターエージェントとのインタラクションの検討 —自己像表示を使ったインタフェースの評価—

    北端美紀, 池永剛, 野島久雄, 内村国治, 山下清美

    ヒューマンインタフェース学会第5回ノンバーバールインタフェース研究会 

    Presentation date: 2002.03

  • 個人化時代の家族間コミュニケーションを支援するシステムのあり方

    北端美紀, 池永剛, 野島久雄, 内村国治, 山下清美

    電子情報通信学会ネットワーク社会とライフスタイル時限研究会 

    Presentation date: 2001.12

  • 家庭内情報化におけるマルチモーダルインタフェースの役割

    北端美紀, 池永剛, 野島久雄, 内村国治, 山下清美

    日本認知科学会第18回認知科学学会大会 

    Presentation date: 2001.06

  • 超並列型2次元セルラーオートマトンCAM2を用いた実時間パターンスペクトラム処理

    池永 剛, 小倉 武

    情処第55回全大 

    Presentation date: 1997.09

  • トリー型ネットワークを用いた連想メモリへの高速データ転送法

    池永 剛, 小倉 武

    信学会全大97年秋 

    Presentation date: 1997.09

  • 超並列型2次元セルラーオートマトンCAM2を用いた実時間 Morphology

    池永 剛, 小倉 武

    信学技法 

    Presentation date: 1997.01

  • 超並列型2次元セルラーオートマトンCAM2を用いたDiscrete-time CNN

    池永 剛, 小倉 武

    情処第53回全大 

    Presentation date: 1996.09

  • 超並列型2次元セルラーオートマトンCAM2を用いたGray Scale Morphology

    池永 剛, 小倉 武

    信学会全大96年秋 

    Presentation date: 1996.09

  • 超並列型2次元セルラーオートマトン:CAM2

    池永 剛, 小倉 武

    信学技法 

    Presentation date: 1996.04

  • リアルタイムMPEG2符号化LSIの構成

    松田宏朗, 池田充郎, 安部哲哉, 草場律, 池永剛, 笠井良太

    96年春信学全大 

    Presentation date: 1996.03

  • 超並列型2次元セルラーオートマトン:CAM2

    池永 剛, 小倉 武

    情処第52回全大 

    Presentation date: 1996.03

  • 超並列型2次元セルラーオートマトンCAM2を用いたMorphology

    池永 剛, 小倉 武

    信学会全大96年春 

    Presentation date: 1996.03

  • 規則的パターンと乱数パターンを組み合わせたBIST構成法

    池永 剛, 小倉 武

    信学会全大 95年春 

    Presentation date: 1995.03

  • 大規模LSI用分散型BIST構成法とその設計支援環境

    池永 剛, 小倉 武

    信学技報 

    Presentation date: 1994.11

  • 大規模LSI用分散型BISTの設計環境

    池永 剛, 小倉 武

    情処第49回全大 

    Presentation date: 1994.09

  • 高性能DSP LSIの演算ユニットに対するBIST構成

    池永 剛, 小倉 武, 笠井 良太

    信学会全大 93年秋 

    Presentation date: 1993.09

  • 乱数伝搬度に着目したBIST評価手法

    池永 剛, 高橋 淳一, 小倉 武

    情処第45回全大 

    Presentation date: 1992.10

  • 分散型BIST向きパターン圧縮器

    池永 剛, 高橋 淳一

    信学会全大92年秋 

    Presentation date: 1992.09

  • DSP-LSIに適したBIST構成法

    池永 剛, 高橋 淳一

    信学技法 

    Presentation date: 1992.06

  • 演算器向きパターン発生器の提案-繰り返しLFSR-

    池永 剛, 高橋 淳一

    92年春季信学全大 

    Presentation date: 1992.03

  • 機能完全性を保証する加算器のテストパターン作成手法

    池永 剛, 山内 寛紀, 高橋 淳一

    信学技報 

    Presentation date: 1991.05

  • 複数のアルゴリズムを実行する専用プロセッサの設計とその評価

    池永 剛, 白井 克彦

    情処第40回全大 

    Presentation date: 1990.03

  • 複数のアルゴリズムを実行する専用プロセッサのアーキテクチャ設計

    池永 剛, 白井 克彦

    情処研報 

    Presentation date: 1990.02

  • 高位の仕様記述に基づく専用プロセッサ設計支援システム

    池永 剛, 竹沢 寿幸, 白井 克彦

    情処第39回全大 

    Presentation date: 1989.10

  • 専用プロセッサ設計における制御系の検討

    竹沢寿幸, 池永剛, 白井克彦

    情処研報 

    Presentation date: 1988.05

  • ハードウェアとソフトウェアを含んだ専用回路設計開発支援システム

    竹沢寿幸, 上野聡, 池永剛, 白井克彦

    88年春信学全大 

    Presentation date: 1988.03

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Specific Research

  • 映像センシングによる特定動作を対象とした3次元姿勢推定基盤の実現

    2021   Songlin Du

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    多様なスポーツ競技や医療・介護などに対し、高度な戦略立案・プレーの評価や異常検出などを可能とする解析システムの実現を目的として、カメラから撮影した映像を入力とした3次元動作取得システムの実現を目指した取り組みを行なった。2次元の姿勢データとカメラから直接得られる映像の両者を組み合わせた深層学習ネットワークを考案し、従来技術と比較して、0.9mm高精度化が図れることを確認した。複数のビデオカメラを用い、各視線方向からの姿勢情報を再構築・推定する事により、オクルージョンなどの厳しい条件下でも正確な動作取得が可能なシステムを実現した。本研究に関連する成果として、3件の英文論文誌、2件の国際会議に採択された

  • 映像センシングによるスポーツ選手の3次元動作取得システムの実現

    2020   Xian Cheng, Qin Liu

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    多様なスポーツ競技に対し、高度な戦略立案やプレーの評価を可能とするスポーツ解析システムの実現を目的として、ビデオカメラから撮影した実試合/競技の映像を入力としたスポーツ解析技術の検討を行った。バレーボールのスパイクの高さを自動取得に関しては、身体部分の分類と観察モデルに基づくオクルージョン検出手法を考案し、92.86%の精度で、平均誤差7.45cmでスパイクの高さを検出可能であることを確認した。フィギュアスケートのジャンプ動作時の3D姿勢推定に関しては、時間的な滑らかさと尤度分布に基づく離散確率ポイントの選択手法、マルチパースペクティブと組み合わせの統合に基づく大規模な会場の3D再構成技術、空間信頼点群と複数の制約に基づく人間の骨格推定などを考案し、関節レベルで92.96%、体全体で82.32%の精度で3D姿勢推定可能なことを確認した。本研究に関連する成果として、1件のIEICEの英文誌、6件の国際会議に採択された。&nbsp;

  • CNNを用いたカスタマイズ可能な3D人物姿勢推定基盤

    2020   Sonlin Du

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    ヒューマンマシンインタラクションや歩行動作など医療・介護などにおける人物の特徴的な動きに対する姿勢推定のためのカスタマイズ可能なCNN基盤実現を目指した取り組みを行った。人物の姿勢推定の高精度化のため、解像度に無関係なエンコーディングや難易度をバランスしたロス関数など、CNNのネットワークに依存しないSupervision手法を提案し、従来手法であるOpenPoseと比較して、4.9%の精度向上を達成した。さらに、2値のCNNネットワークを直接ハードワイヤー型で実装可能な技術やFPGA実装とGPU実装のヘテロ型のネットワーク構成により、超高速・超低遅延(1.3ms)と高精度化を両立可能な両手追跡技術を実現した。本研究に関連する成果として、3件の英文論文誌、3件の国際会議に採択された。&nbsp;

  • CNNに基づく1ms人物動作認識アルゴリズムおよびFPGA実装

    2019  

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    次世代の超臨場感インタラクティブ応用のコアとなる、マッチング処理、CNNに基づく分類処理を対象とした超高速、超低遅延映像処理システムの実現を目的として研究を行った。前年度実現したORBのロバスト化のため、時間的な一貫性に基づく独自のミスマッチ除去アルゴリズム、Temporally forwardingに基づく超低遅延A-KAZEアルゴリズムを考案し、FPGAに実装した結果、VGA動画を784fpsのフレームレート、0.8msの遅延で処理できることを実証した。また、2段のヘテロ型CNNネットワークに基づく両手追跡アルゴリズムを考案し、超高速処理実現への見通しを得た。本研究に関連する成果として、2件のIEICEの英文誌、4件の国際会議に採択された。&nbsp;

  • カメラからの映像情報を入力とした完全自動3次元スポーツ解析技術

    2019  

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    技術面から高度なバレーボールの戦略立案を可能とするシステムの実現を目的として、複数のビデオカメラから撮影した実試合の映像を入力とした種々の解析データの完全自動取得技術の検討を行なった。その結果、GTX1080Tiを用いることにより97%の追跡精度を保ったまま12人の選手を60fpsで追跡可能な技術、ボールや選手の3D位置情報と多視点からの局所特徴を組み合わせることによりバレーボールのプレーの質を自動評価可能とする技術、レシーブの反応時間を94%の精度で取得可能な技術、スパイクの手の高さを7cmの精度で取得可能な技術などを実現した。本研究に関連する成果として、2件のIEICEの英文誌、5件の国際会議に採択された。&nbsp;

  • スポーツTV中継のための実時間バレーボール複数選手追跡システムの実現

    2018   程 曦娜

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    複数の高精細ビデオカメラから撮影した実試合の映像を入力とした完全自動3次元スポーツシーン解析技術の検討を行ってきている。本研究では、スポーツTV中継等の応用をにらみ、12名の選手に対する既提案の追跡アルゴリズムに対し、GPUを用いる事により、実時間化(60fps)を行うことを目標として検討を行った。体の領域に制約を加えた予測モデル、色情報に重みを置いた画素選択法、HSV-Sovelを切り替える時間方向の高速化などの手法を提案し、処理の高速化を可能にした。GPU上に実装した結果、96.73%の追跡精度を保ったまま、16.01msで処理できることを確認した。本研究に関連する成果として、3件のIEICEの英文誌、6件の国際会議に採択された。&nbsp;

  • 実環境下における高臨場インタラクティブ応用のための超低遅延映像処理システムの実現

    2018  

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    次世代の超臨場感インタラクティブ応用のコアとなる、超高速、超低遅延映像処理システムの実現を目的として研究を行った。前年度実現した局所特徴量処理としてORBのロバスト化のため、剛体を想定した種々の変形に対する頑健性の向上に焦点を当てて取り組んだ。キーポイントを加える際に部分的にアップデートする手法、ハミング距離に基づく柔軟なROI算出方法、中心に重みを置いたリカバリー手法などの考案した。提案アルゴリズムに対するハードウェアを実現し、FPGAに実装した結果、VGA動画を、784fpsのフレームレート、0.8msの遅延で処理できることを実証した。本研究に関連する成果として、2件のIEICEの英文誌、5件の国際会議に採択された。

  • 実環境下における高臨場インタラクティブ応用のための超低遅延映像処理システムの実現

    2017  

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    次世代の超臨場感インタラクティブ応用のコアとなる、超高速、超低遅延映像処理システムの実現を目的として研究を行った。幅広い映像処理の基盤となる局所特徴量処理としてORBを取り上げ、Harrisを用いた特徴点検出やレジスターを用いた並列テンプレートマッチング方式、さらにはブロックを2つの領域に分けそれぞれの画素値の総和の差により対称性を求め、回転方向を算出するハード向きアルゴリズムなどを考案した。ハードウェアを実現し、FPGAに実装することにより、VGA動画を、1306fpsのフレームレート、0.8msの遅延で処理できることを実証した。本研究に関連する成果として、2件のIEICEの英文誌、4件の国際会議に採択された。

  • プレミアム・スポーツコンテンツ実現のための実時間スポーツ解析システムの実現

    2017  

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    複数の高精細ビデオカメラから撮影した実試合の映像を入力とした完全自動3次元スポーツシーン解析技術の検討を行ってきている。本研究では、スポーツTV中継等の応用をにらみ、既提案のアルゴリズムに対し、GPUを用いる事により、実時間化(60fps)を行うことを目標として検討を行った。視線を優先するスレッド割り当て方法、バイナリ探索に基づく再重み付け並列化手法を提案し、処理の高速化を可能にした。GPU上に実装した結果、99.23%の追跡精度を保ったまま、3.4msで処理(CPU実装の20倍以上)できることを確認した。本研究に関連する成果として、3件のIEICEの英文誌、7件の国際会議に採択された。

  • 高精細・高フレームレート映像を入力とした実時間特徴抽出システムの実現と応用展開

    2016  

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    次世代の超臨場感インタラクティブ応用のコアとなる、高精細・高フレームレート映像を入力とした実時間特徴抽出システムの研究を行った。ロバストな追跡アルゴリズムとして、既に幅広い実環境応用に用いられているKLT Trackerを取り上げ、ブロック毎の極大値検索による新たな特徴点選択手法、サブ画素精度でのブロックマッチングの最適構成、新たな特徴点座標のメモリ格納法を考案した。提案をFPGAに実装することにより、VGA動画を、784fpsのフレームレート、0.762msの遅延で処理できることを実証した。関連成果として、IEICEの英文誌、CMVIT2017、MVA2017の国際会議に採択された。

  • バレーボール戦略解析のための映像情報を用いたボール追跡・選手動作認識

    2015  

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    2020年の東京オリンピック開催に向けて、データ分析に基づくスポーツ戦略への取り組みが活発化している。中でもバレーボールは、各種解析データがゲームの勝敗に及ぼす効果は大きく、新たな技術開発が期待されている。本研究は、ビデオカメラからの映像情報を用いて、ボールの位置や、選手の動作などのデータを自動抽出するシステムの実現を目的として研究を行った。ボールや選手の3D位置追跡に関しては、バーティクルフィルターを用い、予測モデルや尤度推定を工夫することにより、いずれも99%を超える高い追跡精度を達成した。また、選手の動作解析は、Dense Trajectoriesを用いた手法を考案し、基本動作を検出できることを確認した。

  • 高精細映像を入力とした一般動物体認識システムの実現とその クラウド応用

    2014  

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    情報爆発の時代において、メディアデータそのものを検索のキーとしたクラウドサービスの重要性が高くなってきている。本研究は、Full HD映像を入力とした認識システムを実現し、将来のクラウドサービスの実現に資することを目的としている。キーとなる特徴抽出処理としては、厳しい条件下でロバストな抽出が可能なSIFTを取り上げ、映像に対応させるため、時間方向への拡張を行った。今年度は特に、特徴点の時空間的な特徴に加えて、特徴点間の連結性にも着目することにより、重要な特徴点のみを抽出可能なアルゴリズムを考案した。

  • 超高精細動画像向け画像圧縮LSI構成法の研究

    2010  

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     本研究では、次世代の高臨場感動画像通信・放送サービス実現のコアとなる、超高精細(7680×4320画素)動画像圧縮を方式仕様、アルゴリズム、LSIアーキテクチャの3つの視点から評価・検討を行い、5~10年先のLSI製造技術(10~20nm)を想定した場合における、LSI実現可能性、最適アルゴリズム・アーキテクチャ構成を明確化する事を目的に取り組んできている。 具体的には、動き予測処理、モード選択などH.264に用いられている技術に加えて、現在標準化がすすめられているH.265/HEVCで検討されている16×16を超える大きなブロックを用いたスーパーマクロブロック、適応型の内挿フィルター、インループフィルターなどに注力し、高精細画像を対処として、高画質かつ低演算量なアルゴリズムの検討を進めた。 その結果、整数画素精度動き予測処理においては、アーキテクチャおよび回路レベルの最適化により、Propagate Partial SADやSADツリーの低ハードウェア化を可能な見通しを得た。本成果は、IEICEの英文誌に採択された。また、スーパーマクロブロックに関しては、コンテンツベースのモード選択手法を考案し、適応型の内装フィルターに関しては、処理の1パス化により演算量を大きく削減可能な手法を考案し、それぞれ国際会議等の成果を発信した。 これらの成果は、適宜、関連企業との議論を行い成果の実用化を検討するとともに、H.265/HEVCなどに関しては、国際標準化への提案も模索した。

  • 超高精細動画像向け画像圧縮LSI構成法の研究

    2009   黄 異青

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    メディア処理SoCの主要課題として、プロジェクト当初より取り組んできているH.264エンコーダLSIのさらなる低消費電力化を図るため、エンコーダ処理を各要素に切り分け、それぞれに対し低演算量化・低消費電力化が可能なハードウェアアルゴリズム構成法、LSIアーキテクチャ構成法の検討を進めた。H.264エンコーダの中で特に大きな演算量を占め、電力消費の主な要因となっている処理は、IME(整数画素精度動き予測処理)、FME(少数画素精度動き予測処理)、Inter/Intraモード選択処理の3つとなっており、90%以上の演算量/電力を占めている。特にこれらの低演算量化に注力し、あらゆる視点に立った提案評価をおこなってきた。IMEでは、算術解析、理論解析(レート歪理論など)により、テキスチャーと予測誤差の関係、高周波信号と可変ブロック処理や参照フレーム数の関係、差分絶対値和とエッジの分布との関係などを明確化し、それらに基づく、画像コンテンツによる初期演算打ち切り手法や、ブロック中のエッジ分布に基づく動的な探索範囲アルゴリズムなどを考案し、画質を落とすことなく30%-60%の演算量を削減可能な事を明らかにした。さらにこれらのエンコーダLSIへの組込み方法を明確にした。また、FMEに関しては、主要モジュールであるアダマール変換器に対し、ハードウェア再利用、ノイズ解析に基づく中間データのビット打ち切り、SATD処理のビット幅削減、SATD生成のためのCSA回路、クロックゲーティングなどの手法を提案した。評価により、画質を落とすことなく12~32%の電力を削減できる見通しを得た。さらに、Interモードに関しては、17個のモード選択処理が必要なInterモードに対して、均一な画像に対するモードスキップ処理や空間的・時間的解析に基づく早期判断処理手法などを提案し、画質を落とすことなく33%-66%の演算量削減を図った。

  • 高性能動画像通信処理用SoC技術の研究

    2007  

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    本特定課題プロジェクトのテーマである「高性能動画像通信処理用SoC技術」の確立を目指し、動画像圧縮SoC、無線通信処理SoCの2つの分野を中心に検討を行った。動画像圧縮SoCでは、最先端の動画圧縮国際標準であるH.264/AVCを対象とし、低電力並びに高性能(フルハイビジョン画像)を両立可能なエンコーダLSIの実現を目指し検討を進めた。特に多くの演算量を必要とする整数画素精度動き予測処理に対しては、周波数解析、背景解析、動きの特徴解析などにより余分な処理を低減可能なハードウェア向きアルゴリズム手法を考案した。また、ハード量削減が可能な差分絶対値和演算アーキテクチャや演算回路などを考案し、従来例と比較し優位性を確認した。さらに、通信路でエラーが生じた場合も画質を落とすことなく通信が可能となる新たなエラーコンシールメント手法を考案した。また、こられを発展させ、将来の放送応用を含め大きな市場が期待されるスーパーHDTV(7680x4320 at 60fps)を対象とした検討に着手した。無線通信処理SoCに関しては、ハイビジョンクラスの動画像通信が可能となる700Mbpsクラスの高スループットかつ高信頼を達成可能なベースバンド処理アーキテクチャの検討を進めた。最先端の誤り訂正処理であるLDPCと最先端の無線通信処理であるOFDM UWBを組み合わせた評価用ハードウェアシミュレータを構築し、その評価に基づくLSIアーキテクチャを考案した。さらには、UMC 0.13um CMOS(5mm角)のプロセス技術を用いLSIの第一次試作を行った。以上の取り組みは、相乗効果を出すため、現在推進中のグローバルCOEプログラム(アンビエントSoC教育研究の国際拠点)、CRESTや知的クラスタプロジェクトなどと密にリンクを取りながら推進した。

  • セキュア画像圧縮LSI技術の研究

    2005  

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    動画メディアは、TV電話、ビデオレター、ネットワークカメラ(監視用・介護用)など、ホームネットワーク上においても幅広く流通し始めており、セキュリティおよびプライバシーの観点から、そのセキュア化は、極めて重要となってきている。本研究課題では、動画像圧縮手法として最も幅広く用いられているMPEGコーデックに焦点を絞り、セキュア化のアルゴリズム検討を行った。MPEG符号データのうち、DC係数およびAC係数に対する暗号手法として、それぞれDCEA(DC Coefficient Encryption Algorithm)法、Event Shuffle法を考案した。DCEAは、MPEG符号の中で最も重要なDC係数に対し、シャッフルとDEC暗号の組み合わせによりセキュア化を図る手法であり、Event Shuffleは、AC係数に対しVLC処理する際に、イベントレベルでシャッフルすることにより符号化効率を落とさずセキュア化が可能となる手法である。評価により、符号量やハードウェアのオーバーヘッドを極力抑えた中で動画像を効率よく保護できることを確認した。本成果は、IEICE Trans. Fundamentals(2006年1月)等に採択された。また、独自低電力画像圧縮方式に基づくハードウェア化の検討や、次世代の画像圧縮方式として、普及が望まれるH.264エンコーダーのハードウェア化の検討に着手し、LSI開発を行った。H.264の動き予測処理エンジンに関する成果は、ISSCC2006等に採択された。さらに暗号LSI実現の際に重要となる実装攻撃対処法への検討にも着手した。両者の成果を効果的に融合させて、今後、独自画像圧縮方式及びH.264のセキュアLSI化の実現へと発展させていく予定である。

  • ユビキタス情報処理端末用システムLSI構成法に関する研究

    2004  

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    本プロジェクトのテーマであるユビキタス情報処理用システムLSI構成法の確立を目指し、暗号処理用SoC、ネットワーク処理用SoC画像処理用SoCの3つの応用分野に対し検討を行った。暗号処理SoCでは、考案した多ビット乗算器構成法に基づき、TSMC0.18umを用いたRSA暗号LSI、およびローム0.35umを用いた楕円暗号LSIの試作(2品種)を行った。以上の取り組みを通じて世界最高レベルの暗号コアが得られることを実証評価した。また、新たなターゲットとして、今後の市場拡大が見込まれるストリーム暗号の検討に着手し、様々な実装攻撃を評価するための環境を構築し、新たなストリーム暗号の実現に向けた基本検討を開始した。ネットワーク処理SoCに関しては、既存FPGAデバイスを用いて,最適FEC処理を実現する環境適応型通信処理システムを構築した。また、次世代の符号化方式として注目を集めているLDPF符号のハードウェアを検討した。画像処理SoCでは、国際標準MPEG4準拠で計算量が少なく符号量が増加しない暗号化方式を開発。独自の動画圧縮では動きの大きい領域について動き補償をする方式を提案し、動き補償を従来の5倍以上高速化するアルゴリズムを開発した。以上の取り組みは、北九州・福岡地域で展開されている知的クラスタプロジェクトと密にリンクを取りながら推進した。

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Syllabus

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Committee Memberships

  • 2018
    -
     

    SISA Technical Program Committee Member 2018

  • 2017
    -
     

    SISA Technical Program Committee Member 2017

  • 2016
    -
    2017

    電子情報通信学会英文論文誌A(小特集号) 編集委員

  • 2016
    -
     

    SISA Technical Program Committee Member 2016

  • 2015
    -
    2016

    Asia-Pacific Signal and Information Processing Association (APSIPA): Distinguished Lecturers

  • 2014
    -
    2016

    画像電子学会 財務理事

  • 2015
    -
     

    Asia-Pacific Signal and Information Processing Association (APSIPA): Technical Committee Past Chair

  • 2015
    -
     

    SISA Technical Program Committee Member 2015

  • 2015
    -
     

    GlobalSIP Technical Program Committee Member 2015

  • 2014
    -
     

    VLSI-DAT Technical Program Committee Member 2013-2014

  • 2014
    -
     

    SISA Technical Program Committee Member 2014

  • 2014
    -
     

    ISIPS Technical Program Committee Member 2014

  • 2014
    -
     

    ASPIPA ASCTechnical Program Committee Co-Chairs 2014

  • 2013
    -
    2014

    Asia-Pacific Signal and Information Processing Association (APSIPA): Technical Committee Chair

  • 2013
    -
     

    APSIPA ASC Technical Program Committee Co-Chairs 2013

  • 2013
    -
     

    ASICON Technical Program Committee Member

  • 2013
    -
     

    SISA Technical Program Committee Member 2013

  • 2012
    -
     

    IEEE SiPS Program Committee Member 2012

  • 2012
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    電子情報通信学会スマートインフォメディアシステム研究会 専門委員

  • 2011
    -
    2012

    Asia-Pacific Signal and Information Processing Association (APSIPA): Technical Committee Secretary

  • 2006
    -
    2011

    電子情報通信学会信号処理研究会 専門委員

  • 2010
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    電子情報通信学会英文論文誌C(小特集号) 編集委員

  • 2005
    -
    2010

    電子情報通信学会集積回路研究会 専門委員

  • 2009
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    電子情報通信学会機能集積情報システム研究会 専門委員

  • 2009
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    International Symposium on Intelligent Signal Processing and Communication Systetms (ISPACS): Technical Program Committee

  • 2009
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    International Conference on Multimedia &amp; Expo (ICME): Technical Program Committee

  • 2009
    -
     

    Asia-Pacific Signal and Information Processing Association (APSIPA): Techinical Committee member

  • 2008
    -
    2009

    Workshop on Synthesis andn System Integration of Mixed Information Technologies (SASIMI): Technical Program Commitee

  • 2008
    -
    2009

    IEEE Asian Solid-State Circuits Conference (ASSCC): Technical Program Commitee

  • 2007
    -
    2009

    システムLSIワークショップ 実行委員

  • 2007
    -
    2008

    電子情報通信学会英文論文誌C(小特集号) 編集幹事

  • 2007
    -
    2008

    電子情報通信学会英文論文誌A(小特集号) 編集委員

  • 2007
    -
    2008

    電子情報通信学会英文論文誌C(小特集号) 編集委員

  • 2007
    -
    2008

    電子情報通信学会総合大会実行委員

  • 2007
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    Jornal of Ubiquitous Convergence Technology Editor

  • 2007
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    International Conference on Field-Programmable Technology Organizing commitiee (publication chair)

  • 2006
     
     

    ASP-DAC: Technical Program Commitee

  • 2004
    -
    2006

    IEEE ISCAS Review Commitee Member

  • 2004
    -
    2005

    (社)電子情報産業協会 SoC・SiPソフトウェア専門委員会 幹事

  • 2004
    -
    2005

    電子情報通信学会英文論文誌A(小特集号) 編集委員

  • 2004
     
     

    IEEE APCCAS Technical Progam Commitiee

  • 2001
    -
    2004

    電子情報通信学会英文論文誌C 編集委員

  • 2002
    -
    2003

    (社)電子情報産業協会システムLSI技術専門委員会 幹事

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