YANAGISAWA, Masao

写真a

Affiliation

Faculty of Science and Engineering, School of Fundamental Science and Engineering

Job title

Professor

Homepage URL

http://www.yanagi.cs.waseda.ac.jp/

Concurrent Post 【 display / non-display

  • Faculty of Science and Engineering   Graduate School of Fundamental Science and Engineering

Research Institute 【 display / non-display

  • 2020
    -
    2022

    理工学術院総合研究所   兼任研究員

Education 【 display / non-display

  •  
    -
    1986

    Waseda University   Graduate School, Division of Science and Engineering  

  •  
    -
    1981

    Waseda University   Faculty of Science and Engineering  

Degree 【 display / non-display

  • Doctor of Engineering

Research Experience 【 display / non-display

  • 1998
    -
     

    Waseda University, Professor

  • 1991
    -
    1998

    Waseda University, Associate Professor

  • 1994
     
     

    Passau University, Germany, Visiting Professor

  • 1987
    -
    1991

    Takushoku University, Associate Professor

  • 1986
    -
    1987

    University of California at Berkeley, Researcher

Professional Memberships 【 display / non-display

  •  
     
     

    OR

  •  
     
     

    ACM:Association for Computing Machinery

  •  
     
     

    IEEE:The Institute of Electrical and Electronics Engineers,Inc.

  •  
     
     

    IPSJ

  •  
     
     

    IEICE

 

Research Areas 【 display / non-display

  • Life, health and medical informatics

  • Computer system

  • Control and system engineering

  • Control and system engineering

Research Interests 【 display / non-display

  • Electron Devices and Apparatus Engineering,System Engineering,Computer Science, Bio-informatics,Computer-Aided Design

Papers 【 display / non-display

  • A loop structure optimization targeting high-level synthesis of fast number theoretic transform

    Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa

    Proceedings - International Symposium on Quality Electronic Design, ISQED   2018-   106 - 111  2018.05  [Refereed]

     View Summary

    Multiplication with a large number of digits is heavily used when processing data encrypted by a fully homomorphic encryption, which is a bottleneck in computation time. An algorithm utilizing fast number theoretic transform (FNTT) is known as a high-speed multiplication algorithm and the further speeding up is expected by implementing the FNTT process on an FPGA. A high-level synthesis tool enables efficient hardware implementation even for FNTT with a large number of points. In this paper, we propose a methodology for optimizing the loop structure included in a software description of FNTT so that the performance of the synthesized FNTT processor can be maximized. The loop structure optimization is considered in terms of loop flattening and trip count reduction. We implement a 65,536-point FNTT processor with the loop structure optimization on an FPGA, and demonstrate that it can be executed 6.9 times faster than the execution on a CPU.

    DOI

  • A stayed location estimation method for sparse GPS positioning information based on positioning accuracy and short-time cluster removal

    Sae Iwata, Tomoyuki Nitta, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E101A ( 5 ) 831 - 843  2018.05  [Refereed]

     View Summary

    Cell phones with GPS function as well as GPS loggers are widely used and users' geographic information can be easily obtained. However, still battery consumption in these mobile devices is main concern and then obtaining GPS positioning data so frequently is not allowed. In this paper, a stayed location estimation method for sparse GPS positioning information is proposed. After generating initial clusters from a sequence of measured positions, the e ective radius is set for every cluster based on positioning accuracy and the clusters are merged e ectively using it. After that, short-time clusters are removed temporarily but measured positions included in them are not removed. Then the clusters are merged again, taking all the measured positions into consideration. This process is performed twice, in other words, two-stage short-time cluster removal is performed, and finally accurate stayed location estimation is realized even when the GPS positioning interval is five minutes or more. Experiments demonstrate that the total distance error between the estimated stayed location and the true stayed location is reduced by more than 33% and also the proposed method much improves F1 measure compared to conventional state-of-the-art methods.

    DOI

  • A hardware-Trojan classification method utilizing boundary net structures

    Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa

    2018 IEEE International Conference on Consumer Electronics, ICCE 2018   2018-   1 - 4  2018.03  [Refereed]

     View Summary

    Recently, cybersecurity has become a serious concern for us. For example, the threats of hardware Trojans (malfunctions inserted into hardware devices) have appeared. Since hardware vendors often outsource parts of their hardware products to third-party vendors, the risk of hardware-Trojan insertion has been increased. Especially in the hardware design step, malicious vendors have a chance to insert hardware Trojans easily. In this paper, we propose a hardware-Trojan classification method utilizing boundary net structures. To begin with, we use a machine-learning-based hardware-Trojan detection method and classify the nets in a given netlist into a set of normal nets and that of Trojan nets. Based on the classification, we investigate the nets around the boundary between normal nets and Trojan nets and extract the features of the nets identified to be normal nets or Trojan nets mistakenly. Finally, using the classification results of machine-learning-based hardware-Trojan detection and the extracted features of the boundary nets, we classify the nets in a given netlist into a set of normal nets and that of Trojan nets again. The experimental results demonstrate that our method outperforms an existing machine-learning-based hardware-Trojan detection method in terms of true positive rate.

    DOI

  • Road-illuminance level inference across road networks based on Bayesian analysis

    Siya Bao, Masao Yanagisawa, Nozomu Togawa

    2018 IEEE International Conference on Consumer Electronics, ICCE 2018   2018-   1 - 6  2018.03  [Refereed]

     View Summary

    This paper proposes a road-illuminance level inference method based on the naive Bayesian analysis. We investigate quantities and types of road lights and landmarks with a large set of roads in real environments and reorganize them into two safety classes, safe or unsafe, with seven road attributes. Then we carry out data learning using three types of datasets according to different groups of the road attributes. Experimental results demonstrate that the proposed method successfully classifies a set of roads with seven attributes into safe ones and unsafe ones with the accuracy of more than 85%, which is superior to other machine-learning based methods and a manual-based method.

    DOI

  • A low cost and high speed CSD-based symmetric transpose block FIR implementation

    Jinghao Ye, Youhua Shi, Nozomu Togawa, Masao Yanagisawa

    Proceedings of International Conference on ASIC   2017-   311 - 314  2018.01  [Refereed]

     View Summary

    In this paper, a low cost and high speed CSD-based symmetric transpose block FIR design was proposed for low cost digital signal processing. First, the existing area-efficient CSD-based multiplier was optimized by considering the reusability and the symmetry of coefficients for area reduction. Second, the position of the input register was changed for high speed transpose block FIR processing in which half of the number of required multipliers can be saved. When compared with the existing block FIR designs, the proposed FIR design can increase the data rate from 238.66 MHz to 373.13 MHz while saving 10.89% area and 21.30% energy consumption as well.

    DOI

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Books and Other Publications 【 display / non-display

  • 最新VLSIの開発設計とCAD(共著)

    ミマツデータシステム  1994

Awards 【 display / non-display

  • 電気通信普及財団賞

    2011.03  

  • 海洋調査技術学会技術賞

    2008  

  • Best Paper Award, Asia South Pacific Design Automation Conference

    1995  

  • 安藤博記念学術奨励賞

    1990  

  • 丹羽記念賞

    1988  

Research Projects 【 display / non-display

  • Development of Education-Microprocessor for Computer Engineering and VLSI Engineering.

  • 柔軟性の高いLSIレイアウト設計手法に関する研究

    奨励研究(A)

  • 柔軟性の高いLSIレイアウト設計手法に関する研究

    奨励研究(A)

  • Development of Educational Microprocessors for Computer Science Education

  • Development of Curriculums for Education of VLSI System Design.

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Presentations 【 display / non-display

  • Suspicious Timing Error prediction with In-Cycle Clock Gating

    Presentation date: 2013.03

  • Scan-Based Attack Against DES Cryptosystems Using Scan Signatures

    Presentation date: 2012.12

  • Weighted Adders with Selector Logics for Super-resolution and Its FPGA-based Evaluation

    Presentation date: 2012.12

  • State Dependent Scan Flip-Flop with Key-Based Configuration against Scan-Based Side Channel Attack on RSA Circuit

    Presentation date: 2012.12

  • Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating

    Presentation date: 2012.11

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Specific Research 【 display / non-display

  • 表面筋電信号用ユーザ・インタフェースを用いた手指部の動作のVR空間での実現

    2020  

     View Summary

    本研究では、まず、表面筋電図および筋電位信号と人間の動作を表すような各種センサに対して機械学習を用いた回帰分析を行い,高精度かつ連続的な手指動作推定を行った.当研究室では、すでに、手指部の筋電情報に基づいたユーザ・インタフェースを実現するために、筋電測定用の乾式電極を用いたウェアラブルグローブ型電極を製作している。このウェアラブルグローブ型電極を用いて、手指部の動作をVR空間において実現している。つぎに、本研究では,筋電位信号のリアルタイム通信における通信手法を構築した.提案した通信方法では要件として基準となるサンプリング周波数 1kHz を満たし,かつ、高い信頼性を達成している.ここではOSCを用いてUDPの速度と拡張性を確保した.また RUDP の手法を提案し,高い信頼性を確保した.以上の結果から筋電位信号のリアルタイム通信として利用でき、手指部の動作をVR空間で実現できることを示した.

  • 表面筋電信号用ユーザ・インタフェースを用いた手指部の動作のVR空間での実現

    2019  

     View Summary

    本研究室では、すでに、手指部の筋電情報に基づいたユーザ・インタフェースを実現するために、筋電測定用の乾式電極を用いたウェアラブルグローブ型電極を製作している。このウェアラブルグローブ型電極を用いて、手指部の動作をVR空間において実現することを本研究の目的とした。そのために、(1) ノイズ・フィルタの開発、(2) 採用すべき特徴量の抽出、(3) 採用すべき識別器の選択、(4) 同被験者・異被験者間でデータによる識別精度の比較・改良、(5) タッピングにピッチ動作等を加えた際の識別方法の構築、(6) リアルタイム処理に向けたデータ処理環境の構築、(7) VR空間への適用、に関して順次研究を進めた。

  • 手指内在筋の表面筋電信号用ユーザ・インターフェースならびに動作識別手法の開発

    2018  

     View Summary

    The motion of the finger is made up of a combination of forearm part (extrinsic) muscles and hand part (intrinsic) muscles.  We have created a wearable fingerless glove controller to sense sEMG (surface Electromyography) from intrinsic muscles using dry electrodes.  Recognition of air-tapping gesture with a sensor attached to wearable fingerless glove controller is a challenging problem.  In this study, we focused on motion recognition of air-tapping and performed motion recognition using CNN and evaluated its ac-curacy.  As a result, the accuracy in intra-subject identification was 85.05%.  Also, experiments are currently being conducted in anticipation of character input in VR space.  Character input experiment in VR space was carried out using sEMG wearable fingerless glove controller, as a primitive experiment of the use of sEMG glove in VR space.  Based on the results, we discussed the efficiency of character input using sEMG glove in VR space.  

  • 侵襲に頑健な集積回路の設計および実装に関する研究

    2018  

     View Summary

    To deal with the reliability issue caused by soft errors, a low power soft error hardened latch (SHC) design using Schmitt-Trigger-based C-element is proposed for reliable low power applications in this research.  The total number of transistors of the proposed SHC latch is only increased by 2 when compared to the conventional unhardened C2MOS latch, while up to 82.96% power reduction can be achieved when compared to the existing soft error tolerant HiPeR design.  When soft errors occur in the internal nodes of the proposed SHC, it can be filtered inside and will not cause the output Q to be upset.  Moreover, in case of soft errors occurring and affecting the output, the proposed SHC latch can recover to the correct state as fast as the existing works while they usually introduce about 2X area overhead as large as the proposed SHC, which clearly shows the effectiveness of the proposed low cost SHC design. 

  • 高速かつ低電力なソフトエラー耐性をもつラッチの設計

    2017  

     View Summary

    As semiconductor technology continues scaling down, the reliability issue has become much more critical than ever before.  Unlike traditional hard-errors caused by permanent physical damage which can’t be recovered in field, soft errors are caused by radiation or voltage/current fluctuations that lead to transient changes on internal node states, thus they can be viewed as temporary errors.  However, due to the unpredictable occurrence of soft errors, it is desirable to develop soft error tolerant designs.  For this reason, soft error tolerant design techniques have gained great research interest.  In this research, low-power soft error tolerant SHC latch is proposed using C-elements.  SHC latch and existing soft error tolerant latch are implemented and evaluated by spice simulator.  80.52% power reduction at maximum is achieved by SHC latch compared with HiPeR latch.  66.04% delay reduction at maximum is achieved by improved SHC latch compared with FERST latch. 

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Syllabus 【 display / non-display

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