Details of a Researcher - YANAGISAWA, Masao

写真a

YANAGISAWA, Masao

Affiliation

Faculty of Science and Engineering, School of Fundamental Science and Engineering

Job title

Professor

Homepage URL

http://www.yanagi.cs.waseda.ac.jp/

Concurrent Post

Faculty of Science and Engineering Graduate School of Fundamental Science and Engineering

Research Institute

2020

-

2022

理工学術院総合研究所兼任研究員

Education

　

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1986

Waseda University Graduate School, Division of Science and Engineering
　

-

1981

Waseda University Faculty of Science and Engineering

Degree

Doctor of Engineering

Research Experience

1998

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Waseda University, Professor
1991

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1998

Waseda University, Associate Professor
1994

　

　

Passau University, Germany, Visiting Professor
1987

-

1991

Takushoku University, Associate Professor
1986

-

1987

University of California at Berkeley, Researcher

Professional Memberships

　

　

　

OR
　

　

　

ACM:Association for Computing Machinery
　

　

　

IEEE:The Institute of Electrical and Electronics Engineers,Inc.
　

　

　

IPSJ
　

　

　

IEICE

Research Areas

Life, health and medical informatics
Control and system engineering
Computer system
Control and system engineering

Research Interests

Electron Devices and Apparatus Engineering,System Engineering,Computer Science, Bio-informatics,Computer-Aided Design

Papers

A loop structure optimization targeting high-level synthesis of fast number theoretic transform

Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa

Proceedings - International Symposium on Quality Electronic Design, ISQED 2018- 106 - 111 2018.05 [Refereed]

　View Summary

Multiplication with a large number of digits is heavily used when processing data encrypted by a fully homomorphic encryption, which is a bottleneck in computation time. An algorithm utilizing fast number theoretic transform (FNTT) is known as a high-speed multiplication algorithm and the further speeding up is expected by implementing the FNTT process on an FPGA. A high-level synthesis tool enables efficient hardware implementation even for FNTT with a large number of points. In this paper, we propose a methodology for optimizing the loop structure included in a software description of FNTT so that the performance of the synthesized FNTT processor can be maximized. The loop structure optimization is considered in terms of loop flattening and trip count reduction. We implement a 65,536-point FNTT processor with the loop structure optimization on an FPGA, and demonstrate that it can be executed 6.9 times faster than the execution on a CPU.

DOI
A stayed location estimation method for sparse GPS positioning information based on positioning accuracy and short-time cluster removal

Sae Iwata, Tomoyuki Nitta, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E101A ( 5 ) 831 - 843 2018.05 [Refereed]

　View Summary

Cell phones with GPS function as well as GPS loggers are widely used and users' geographic information can be easily obtained. However, still battery consumption in these mobile devices is main concern and then obtaining GPS positioning data so frequently is not allowed. In this paper, a stayed location estimation method for sparse GPS positioning information is proposed. After generating initial clusters from a sequence of measured positions, the e ective radius is set for every cluster based on positioning accuracy and the clusters are merged e ectively using it. After that, short-time clusters are removed temporarily but measured positions included in them are not removed. Then the clusters are merged again, taking all the measured positions into consideration. This process is performed twice, in other words, two-stage short-time cluster removal is performed, and finally accurate stayed location estimation is realized even when the GPS positioning interval is five minutes or more. Experiments demonstrate that the total distance error between the estimated stayed location and the true stayed location is reduced by more than 33% and also the proposed method much improves F1 measure compared to conventional state-of-the-art methods.

DOI
A hardware-Trojan classification method utilizing boundary net structures

Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa

2018 IEEE International Conference on Consumer Electronics, ICCE 2018 2018- 1 - 4 2018.03 [Refereed]

　View Summary

Recently, cybersecurity has become a serious concern for us. For example, the threats of hardware Trojans (malfunctions inserted into hardware devices) have appeared. Since hardware vendors often outsource parts of their hardware products to third-party vendors, the risk of hardware-Trojan insertion has been increased. Especially in the hardware design step, malicious vendors have a chance to insert hardware Trojans easily. In this paper, we propose a hardware-Trojan classification method utilizing boundary net structures. To begin with, we use a machine-learning-based hardware-Trojan detection method and classify the nets in a given netlist into a set of normal nets and that of Trojan nets. Based on the classification, we investigate the nets around the boundary between normal nets and Trojan nets and extract the features of the nets identified to be normal nets or Trojan nets mistakenly. Finally, using the classification results of machine-learning-based hardware-Trojan detection and the extracted features of the boundary nets, we classify the nets in a given netlist into a set of normal nets and that of Trojan nets again. The experimental results demonstrate that our method outperforms an existing machine-learning-based hardware-Trojan detection method in terms of true positive rate.

DOI
Road-illuminance level inference across road networks based on Bayesian analysis

Siya Bao, Masao Yanagisawa, Nozomu Togawa

2018 IEEE International Conference on Consumer Electronics, ICCE 2018 2018- 1 - 6 2018.03 [Refereed]

　View Summary

This paper proposes a road-illuminance level inference method based on the naive Bayesian analysis. We investigate quantities and types of road lights and landmarks with a large set of roads in real environments and reorganize them into two safety classes, safe or unsafe, with seven road attributes. Then we carry out data learning using three types of datasets according to different groups of the road attributes. Experimental results demonstrate that the proposed method successfully classifies a set of roads with seven attributes into safe ones and unsafe ones with the accuracy of more than 85%, which is superior to other machine-learning based methods and a manual-based method.

DOI
A low cost and high speed CSD-based symmetric transpose block FIR implementation

Jinghao Ye, Youhua Shi, Nozomu Togawa, Masao Yanagisawa

Proceedings of International Conference on ASIC 2017- 311 - 314 2018.01 [Refereed]

　View Summary

In this paper, a low cost and high speed CSD-based symmetric transpose block FIR design was proposed for low cost digital signal processing. First, the existing area-efficient CSD-based multiplier was optimized by considering the reusability and the symmetry of coefficients for area reduction. Second, the position of the input register was changed for high speed transpose block FIR processing in which half of the number of required multipliers can be saved. When compared with the existing block FIR designs, the proposed FIR design can increase the data rate from 238.66 MHz to 373.13 MHz while saving 10.89% area and 21.30% energy consumption as well.

DOI
Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems

Daiki Asai, Masao Yanagisawa, Nozomu Togawa

Proceedings of International Conference on ASIC 2017- 64 - 67 2018.01 [Refereed]

　View Summary

In this paper, we propose a floorplan-driven highlevel synthesis algorithm utilizing both volatile and non-volatile registers for hybrid energy-harvesting systems. In our algorithm, we firstly introduce an idea of safety line candidates. Based on them, we perform safety-line (SL) scheduling so that every operation does not cross the safety line candidates and then perform volatile/non-volatile register binding so that all the data crossing the safety line candidates are stored into non-violate registers. We can safely restore all the data and re-start the circuit operation from every safety line candidate, even if the power shut-off occurs while running the circuit. Experimental results show that our algorithm reduces average latency by 30.76% and the average energy consumption by 24.94% compared to the naive algorithm when sufficient energy is given (normal mode). Experimental results also show that our algorithm reduces average latency by 30.58% compared to the naive algorithm by reducing rollback execution if a small amount of energy is given (energy-harvesting mode).

DOI
Soft error tolerant latch designs with low power consumption (invited paper)

Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi

Proceedings of International Conference on ASIC 2017- 52 - 55 2018.01 [Refereed]

　View Summary

As semiconductor technology continues scaling down, the reliability issue has become much more critical than ever before. Unlike traditional hard-errors caused by permanent physical damage which can't be recovered in field, soft errors are caused by radiation or voltage/current fluctuations that lead to transient changes on internal node states, thus they can be viewed as temporary errors. However, due to the unpredictable occurrence of soft errors, it is desirable to develop soft error tolerant designs. For this reason, soft error tolerant design techniques have gained great research interest. In this paper, we will explain the soft error mechanism and then review the existing soft error tolerant design techniques with particular emphasis on SEH family because they can achieve low power consumption and small performance overhead as well.

DOI
An Ising model mapping to solve rectangle packing problem.

Kotaro Terada, Daisuke Oku, Sho Kanamaru, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa

2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 16-19, 2018 1 - 4 2018 [Refereed]

DOI
Scan-based Side-channel Attack against HMAC-SHA-256 Circuits Based on Isolating Bit-transition Groups Using Scan Signatures.

Daisuke Oku, Masao Yanagisawa, Nozomu Togawa

IPSJ Trans. System LSI Design Methodology 11 2018 [Refereed]

DOI DOI2
A Relaxed Bit-Write-Reducing and Error-Correcting Code for Non-Volatile Memories.

Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa

IEICE Transactions 101-A ( 7 ) 1045 - 1052 2018 [Refereed]

DOI
A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element.

Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi

IEICE Transactions 101-A ( 7 ) 1025 - 1034 2018 [Refereed]

　View Summary

Copyright © 2018 The Institute of Electronics, Information and Communication Engineers. To deal with the reliability issue caused by soft errors, this paper proposed a low power soft error hardened latch (SHC) design using a novel Schmitt-Trigger-based C-element for reliable low power applications. Unlike state-of-the-art soft error tolerant latches that are usually based on hardware redundancy with large area overhead and high power consumption, the proposed SHC latch is implemented through double-sampling and node-checking using a novel Schmitt-Trigger-based C-element, which can help to reduce the area overhead and the corresponding power consumption as well. The evaluation results show that the total number of transistors of the proposed SHC latch is only increased by 2 when compared to the conventional unhardened C2MOS latch, while up to 20.35% and 82.96% power reduction can be achieved when compared to the conventional un-hardened C2MOS latch and the existing soft error tolerant HiPeR design, respectively.

DOI
Extension and Performance/Accuracy Formulation for Optimal GeAr-Based Approximate Adder Designs.

Ken Hayamizu, Nozomu Togawa, Masao Yanagisawa, Youhua Shi

IEICE Transactions 101-A ( 7 ) 1014 - 1024 2018 [Refereed]

　View Summary

Copyright © 2018 The Institute of Electronics, Information and Communication Engineers. Approximate computing is a promising solution for future energy-efficient designs because it can provide great improvements in performance, area and/or energy consumption over traditional exact-computing designs for non-critical error-tolerant applications. However, the most challenging issue in designing approximate circuits is how to guarantee the pre-specified computation accuracy while achieving energy reduction and performance improvement. To address this problem, this paper starts from the state-of-the-art general approximate adder model (GeAr) and extends it for more possible approximate design candidates by relaxing the design restrictions. And then a maximum-error-distance-based performance/accuracy formulation, which can be used to select the performance/energy-accuracy optimal design from the extended design space, is proposed. Our evaluation results show the effectiveness of the proposed method in terms of area overhead, performance, energy consumption, and computation accuracy.

DOI
Stochastic Number Duplicators Based on Bit Re-Arrangement Using Randomized Bit Streams.

Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa

IEICE Transactions 101-A ( 7 ) 1002 - 1013 2018 [Refereed]

DOI
A bitwidth-aware high-level synthesis algorithm using operation chainings for tiled-DR architectures

Kotaro Terada, Masao Yanagisawa, Nozomu Togawa

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E100A ( 12 ) 2911 - 2924 2017.12 [Refereed]

　View Summary

As application hardware designs and implementations in a short term are required, high-level synthesis is more and more essential EDA technique nowadays. In deep-submicron era, interconnection delays are not negligible even in high-level synthesis thus distributed-register and - controller architectures (DR architectures) have been proposed in order to cope with this problem. It is also profitable to take data-bitwidth into account in high-level synthesis. In this paper, we propose a bitwidth-aware high-level synthesis algorithm using operation chainings targeting Tiled-DR architectures. Our proposed algorithm optimizes bitwidths of functional units and utilizes the vacant tiles by adding some extra functional units to realize effective operation chainings to generate high performance circuits without increasing the total area. Experimental results show that our proposed algorithm reduces the overall latency by up to 47% comparedtothe conventional approach without area overheads by eliminating unnecessary bitwidths and adding efficient extra FUs for Tiled-DR architectures.

DOI
A safe and comprehensive route finding algorithm for pedestrians based on lighting and landmark conditions

Siya Bao, Tomoyuki Nitta, Masao Yanagisawa, Nozomu Togawa

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E100A ( 11 ) 2439 - 2450 2017.11 [Refereed]

　View Summary

In this paper, we propose a safe and comprehensive route finding algorithm for pedestrians based on lighting and landmark conditions. Safety and comprehensiveness can be predicted by the five possible indicators: (1) lighting conditions, (2) landmark visibility, (3) landmark effectiveness, (4) turning counts along a route, and (5) road widths. We first investigate impacts of these five indicators on pedestrians' perceptions on safety and comprehensiveness during route findings. After that, a route finding algorithm is proposed for pedestrians. In the algorithm, we design the score based on the indicators (1), (2), (3), and (5) above and also introduce a turning count reduction strategy for the indicator (4). Thus we find out a safe and comprehensive route through them. In particular, we design daytime score and nighttime score differently and find out an appropriate route depending on the time periods. Experimental simulation results demonstrate that the proposed algorithm obtains higher scores compared to several existing algorithms. We also demonstrate that the proposed algorithm is able to find out safe and comprehensive routes for pedestrians in real environments in accordance with questionnaire results.

DOI
A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation

Koki Igawa, Masao Yanagisawa, Nozomu Togawa

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E100A ( 7 ) 1439 - 1451 2017.07 [Refereed]

　View Summary

In this paper, we propose a floorplan aware high-level synthesis algorithm with body biasing for delay variation compensation, which minimizes the average leakage energy of manufactured chips. In order to realize floorplan-aware high-level synthesis, we utilize huddle-based distributed register architecture (HDR architecture). HDR architecture divides the chip area into small partitions called a huddle and we can control a body bias voltage for every huddle. During high-level synthesis, we iteratively obtain expected leakage energy for every huddle when applying a body bias voltage. A huddle with smaller expected leakage energy contributes to reducing expected leakage energy of the entire circuit more but can increase the latency. We assign control-data flow graph (CDFG) nodes in non-critical paths to the huddles with larger expected leakage energy and those in critical paths to the huddles with smaller expected leakage energy. We expect to minimize the entire leakage energy in a manufactured chip without increasing its latency. Experimental results show that our algorithm reduces the average leakage energy by up to 39.7% without latency and yield degradation compared with typical-case design with body biasing.

DOI
A Hardware-Trojan Classification Method Using Machine Learning at Gate-Level Netlists Based on Trojan Features

Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E100A ( 7 ) 1427 - 1438 2017.07 [Refereed]

　View Summary

Due to the increase of outsourcing by IC vendors, we face a serious risk that malicious third-party vendors insert hardware Trojans very easily into their IC products. However, detecting hardware Trojans is very difficult because today's ICs are huge and complex. In this paper, we propose a hardware-Trojan classification method for gate-level netlists to identify hardware-Trojan infected nets (or Trojan nets) using a support vector machine (SVM) or a neural network (NN). At first, we extract the five hardware-Trojan features from each net in a netlist. These feature values are complicated so that we cannot give the simple and fixed threshold values to them. Hence we secondly represent them to be a five-dimensional vector and learn them by using SVM or NN. Finally, we can successfully classify all the nets in an unknown netlist into Trojan ones and normal ones based on the learned classifiers. We have applied our machine-learning based hardware-Trojan classification method to Trust-HUB benchmarks. The results demonstrate that our method increases the true positive rate compared to the existing state-of-the-art results in most of the cases. In some cases, our method can achieve the true positive rate of 100%, which shows that all the Trojan nets in an unknown netlist are completely detected by our method.

DOI
Efficient Multiplexer Networks for Field-Data Extractors and Their Evaluations

Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E100A ( 4 ) 1015 - 1028 2017.04 [Refereed]

　View Summary

As seen in stream data processing, it is necessary to extract a particular data field from bulk data, where we can use a field-data extractor. Particularly, an (M, N)-field-data extractor reads out any consecutive N bytes from an M-byte register by connecting its input/output using multiplexers (MUXs). However, the number of required MUXs increases too much as the input/output byte widths increase. It is known that partitioning a MUX network leads to reducing the number of MUXs. In this paper, we firstly pick up a multi-layered MUX network, which is generated by repeatedly partitioning a MUX network into a collection of single layered MUX networks. We show that the multi-layered MUX network is equivalent to the barrel shifter from which redundant MUXs and wires are removed, and we prove that the number of required MUXs becomes the smallest among MUX-network-partitioning based field-data extractors. Next, we propose a rotator-based MUX network for a field-data extractor, which is based on reading out a particular data in an input register to a rotator. The byte width of the rotator is the same as its output register and hence we no longer require any extra wires nor MUXs. By rotating the input data appropriately, we can finally have a right-ordered data into an output register. Experimental results show that a multi-layered MUX network reduces the number of required gates to construct a field-data extractor by up to 97.0% compared with the one using a naive approach and its delay becomes 1.8 ns-2.3 ns. A rotator-based MUX network with a control circuit also reduces the number of required gates to construct a field-data extractor by up to 97.3% compared with the one using a naive approach and its delay becomes 2.1 ns-2.9 ns.

DOI
An Evaluation of Hand-Force Prediction Using Artificial Neural-Network Regression Models of Surface EMG Signals for Handwear Devices.

Array,Ryohei Koyama, Masao Yanagisawa

J. Sensors 2017 3980906:1-3980906:12 2017 [Refereed]
Trojan-Net Feature Extraction and Its Application to Hardware-Trojan Detection for Gate-Level Netlists Using Random Forest.

Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa

IEICE Transactions 100-A ( 12 ) 2857 - 2868 2017 [Refereed]

DOI
A thermal-aware high-level synthesis algorithm for RDR architectures through binding and allocation

Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E96-A ( 1 ) 312 - 321 2013

　View Summary

With process technology scaling, a heat problem in ICs is becoming a serious issue. Since high temperature adversely impacts on reliability, design costs, and leakage power, it is necessary to incorporate thermal-aware synthesis into IC design flows. In particular, hot spots are serious concerns where a chip is locally too much heated and reducing the peak temperature inside a chip is very important. On the other hand, increasing the average interconnect delays is also becoming a serious issue. By using RDR architectures (Regular-Distributed-Register architectures), the interconnect delays can be easily estimated and their influence can be much reduced even in high-level synthesis. In this paper, we propose a thermal-aware high-level synthesis algorithm for RDR architectures. The RDR architecture divides the entire chip into islands and each island has uniform area. Our algorithm balances the energy consumption among islands through re-binding to functional units. By allocating some new additional functional units to vacant areas on islands, our algorithm further balances the energy consumption among islands and thus reduces the peak temperature. Experimental results demonstrate that our algorithm reduces the peak temperature by up to 9.1% compared with the conventional approach. Copyright © 2013 The Institute of Electronics, Information and Communication Engineers.

DOI
Scan-Based Attack on AES through Round Registers and Its Countermeasure

Youhua Shi, Nozomu Togawa, Masao Yanagisawa

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E95A ( 12 ) 2338 - 2346 2012.12

　View Summary

Scan-based side channel attack on hardware implementations of cryptographic algorithms has shown its great security threat. Unlike existing scan-based attacks, in our work we observed that instead of the secret-related-registers, some non-secret registers also carry the potential of being misused to help a hacker to retrieve secret keys. In this paper, we first present a scan-based side channel attack method on AES by making use of the round counter registers, which are not paid attention to in previous works, to show the potential security threat in designs with scan chains. And then we discussed the issues of secure DFT requirements and proposed a secure scan scheme to preserve all the advantages and simplicities of traditional scan test, while significantly improve the security with ignorable design overhead, for crypto hardware implementations.

DOI
AUV navigation around jacket structures I: relative localization based on multi-sensor fusion

Toshihiro Maki, Hayato Mizushima, Tamaki Ura, Takashi Sakamaki, Masao Yanagisawa

JOURNAL OF MARINE SCIENCE AND TECHNOLOGY 17 ( 3 ) 330 - 339 2012.09

　View Summary

Underwater jacket structures or support legs of on-water platforms, such as ports and oil rigs, need to be periodically inspected for maintenance, environmental monitoring, and security reasons. Autonomous underwater vehicles (AUVs) can potentially make these tasks more inexpensive and reliable compared to conventional methods that involve the use of divers and remotely operated vehicles. This paper proposes a robust and practical self-localization method for an underwater vehicle navigating around jacket structures, where the performance of conventional acoustic positioning suffers from multipath degradation. The key idea is to stochastically update the vehicle's horizontal position and heading relative to the structures using two types of perceptional sensors, sonar and camera, assuming that the configuration of the structure is known. The performance of the method was verified with tank experiments using a jacket mock-up and the AUV Tri-Dog 1.

DOI
A Locality-Aware Hybrid NoC Configuration Algorithm Utilizing the Communication Volume among IP Cores

Seungju Lee, Masao Yanagisawa, Nozomu Togawa

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E95A ( 9 ) 1538 - 1549 2012.09

　View Summary

Network-on-chip (NoC) architectures have emerged as a promising solution to the lack of scalability in multi-processor systems-on-chips (MPSoCs). With the explosive growth in the usage of multimedia applications, it is expected that NoC serves as a multimedia server supporting multi-class services. In this paper, we propose a configuration algorithm for a hybrid bus-NoC architecture together with simulation results. Our target architecture is a hybrid bus-NoC architecture, called busmesh NoC, which is a generalized version of a hybrid NoC with local buses. In our BMNoC configuration algorithm, cores which have a heavy communication volume between them are mapped in a cluster node (CN) and connected by a local bus. CNs can have communication with each other via edge switches (ESes) and mesh routers (MRs). With this hierarchical communication network, our proposed algorithm can improve the latency as compared with conventional methods. Several realistic applications applied to our algorithm illustrate the better performance than earlier studies and feasibility of our proposed algorithm.

DOI
Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 20 ( 1 ) 176 - 181 2012.01

　View Summary

Scan technology carries the potential risk of being misused as a "side channel" to leak out the secrets of crypto cores. The existing scan-based attacks could be viewed as one kind of differential cryptanalysis, which takes advantages of scan chains to observe the bit changes between pairs of chosen plaintexts so as to identify the secret keys. To address such a design/test challenge, this paper proposes a robust secure scan structure design for crypto cores as a countermeasure against scan-based attacks to maintain high security without compromising the testability.

DOI
Integrating wearable sensor technology into project-management process

Koji Ara, Tomoaki Akitomi, Nobuo Sato, Kunio Takahashi, Hideyuki Maeda, Kazuo Yano, Masao Yanagisawa

Journal of Information Processing 20 ( 2 ) 406 - 418 2012

　View Summary

A sensor-based project management process, which uses continuous sensing data of face-to-face communication, was developed for integration into current project management processes. To establish a practical process, a sensing system was applied in two software-development projects involving 123 and 65 employees, respectively, to analyze the relation between work performance and behavioral patterns and investigate the use of sensor data. It was found that a factor defined as "communication richness," which refers to the amount of communication, correlates with employee performance (job evaluation) and was common in both projects, while other factors, such as "workload," were found in just one of the projects. Developers' quality of development (low bug occurrence) was also investigated in one of the projects and "communication richness" was found as a factor of high development quality. As a result of this analysis, we propose a four-step sensor-based project management process, which consists of analysis, monitoring, inspection, and action, and evaluated its effectiveness. Through monitoring, it was estimated that some "unplanned" events, such as changing specifications and problem solving during a project, could be systematically identified. Cohesion of a network was systematically increased using a recommendation of communication, called WorkX, which involves micro rotating of discussion members based on network topology. © 2012 Information Processing Society of Japan.

DOI
A fastweighted adder by reducing partial product for reconstruction in super-resolution

Hiromine Yoshihara, Masao Yanagisawa, Nozomu Togawa

IPSJ Transactions on System LSI Design Methodology 5 96 - 105 2012

　View Summary

In recent years, it is quite necessary to convert conventional low-resolution images to high-resolution ones at low cost. Super-resolution is a technique to remove the noise of observed images and restore its high frequencies. We focus on reconstruction-based super-resolution. Reconstruction requires large computation cost since it requires many images. In this paper, we propose a fast weighted adder for reconstruction-based super-resolution. From the viewpoint of reducing partial products, we propose two approaches to speed up a weighted adder. First, we use selector logics to halve its partial products. Second, we propose a weights-range limit method utilizing negative term. By applying our proposed approaches to a weighted adder, we can reduce carry propagations and our weighted adder can be designed by a fast circuit as compared to conventional ones. Experimental evaluations demonstrate that our weighted adder reduces its delay time by a maximum of 25.29% and its area to a maximum of 1/3, compared to conventional implementations. © 2012 Information Processing Society of Japan.

DOI
Energy-efficient high-level synthesis for HDR architectures

Shin-Ya Abe, Masao Yanagisawa, Nozomu Togawa

IPSJ Transactions on System LSI Design Methodology 5 106 - 117 2012

　View Summary

As battery runtime and overheating problems for portable devices become unignorable, energy-aware LSI design is strongly required. Moreover, an interconnection delay should be explicitly considered there because it exceeds a gate delay as the semiconductor devices are downsized. We must take account of energy efficiency and interconnection delays even in high-level synthesis. In this paper, we first propose a huddle-based distributed-register architecture (HDR architecture), an island-based distributed-register architecture for multi-cycle interconnect communications where we can develop several energy-saving techniques. Next, we propose an energy-efficient high-level synthesis algorithm for HDR architectures focusing on multiple supply voltages. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, a huddle, which is composed of functional units, registers, controller, and level converters, are very naturally generated using floorplanning results. By assigning high supply voltage to critical huddles and low supply voltage to non-critical huddles, we can finally have energy-efficient floorplan-aware high-level synthesis. Experimental results show that our algorithm achieves 45% energy-saving compared with the conventional distributed-register architectures and conventional algorithms. © 2012 Information Processing Society of Japan.

DOI
MH4 : multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures

Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa

IEICE ELECTRONICS EXPRESS 9 ( 17 ) 1414 - 1422 2012

　View Summary

In this paper, we propose multiple-supply-voltages aware high-level synthesis algorithm for HDR architectures which realizes high-speed and high-efficient circuits. We propose three new techniques: virtual area estimation, virtual area adaptation, and floorplanning-directed huddling, and integrate them into our HDR architecture synthesis algorithm. Virtual area estimation/adaptation effectively estimates a huddle area by gradually reducing it during iterations, which improves the convergence of our algorithm. Floorplanning-directed huddling determines huddle composition very effectively by performing floorplanning and functional unit assignment inside huddles simultaneously. Experimental results show that our algorithm achieves about 29% run-time-saving compared with the conventional algorithms, and obtains a solution which cannot be obtained by our original algorithm even if a very tight clock constraint is given.

DOI
Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint

Mikiko Sode Tanaka, Nozomu Togawa, Masao Yanagisawa, Satoshi Goto

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E94A ( 12 ) 2482 - 2489 2011.12

　View Summary

With the progress of process technology in recent years, low voltage power supplies have become quite predominant. With this, the voltage margin has decreased and therefore the on-chip decoupling capacitance optimization that satisfies the voltage drop constraint becomes more important. In addition, the reduction of the on-chip decoupling capacitance area will reduce the chip area and, therefore, manufacturing costs. Hence, we propose an algorithm that satisfies the voltage drop constraint and at the same time, minimizes the total on-chip decoupling capacitance area. The proposed algorithm uses the idea of the network algorithm where the path which has the most influence on voltage drop is found. Voltage drop is improved by adding the on-chip capacitance to the node on the path. The proposed algorithm is efficient and effectively adds the on-chip capacitance to the greatest influence on the voltage drop. Experimental results demonstrate that, with the proposed algorithm, real size power/ground network could be optimized in just a few minutes which are quite practical. Compared with the conventional algorithm, we confirmed that the total on-chip decoupling capacitance area of the power/ground network was reducible by about 40 similar to 50%.

DOI
2基のハイドロフォンアレイを用いたマッコウクジラの集団潜水行動への考察

廣津良, 裏環, 小島淳一, 杉松治美, Rajendar Bahl, 柳澤政生

日本音響学会誌 67巻 ( 11号 ) 499 - 509 2011.10

DOI
Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint

Mikiko Sode Tanaka, Nozomu Togawa, Masao Yanagisawa, Satoshi Goto

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E94A ( 4 ) 1082 - 1090 2011.04

　View Summary

With the process technological progress in recent years, low voltage power supplies have become quite predominant. With this, the voltage margin has decreased and therefore the power/ground design that satisfies the voltage drop constraint becomes more important. In addition, the reduction of the power/ground total wiring area and the number of layers will reduce manufacturing and designing costs. So, we propose an algorithm that satisfies the voltage drop constraint and at the same time, minimizes the power/ground total wiring area. The proposed algorithm uses the idea of a network algorithm [I] where the edge which has the most influence on voltage drop is found. Voltage drop is improved by changing the resistance of the edge. The proposed algorithm is efficient and effectively updates the edge with the greatest influence on the voltage drop. From experimental results, compared with the conventional algorithm, we confirmed that the total wiring area of the power/ground was reducible by about 1/3. Also, the experimental data shows that the proposed algorithm satisfies the voltage drop constraint in the data whereas the conventional algorithm cannot.

DOI
エッジ情報を用いたAngular イントラ予測モード高速決定手法

徳満健太, 蝶野慶一, 先崎健太, 仙田裕三, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会総合大会 2011.03
スクラッチパッドメモリとコード配置最適化による低エネルギーASIP合成手法

嶋田吉倫, 史又華, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 VLD2010-120 25 - 30 2011.03
柔軟な置換ポリシをもつ2階層キャッシュの正確で高速なシミュレーション手法

多和田雅師, 柳澤政生, 大附辰夫, 戸川望

電子情報通信学会VLSI設計技術研究会 VLD2010-118 13 - 18 2011.03
SASEBO-GIIを使用したAESに対するスキャンベース攻撃の実装実験

奈良竜太, 小寺博和, 柳澤政生, 大附辰夫, 戸川望

2011年暗号と情報セキュリティシンポジウム(SCIS2011) 1D1-2 1 - 8 2011.01
A fast selector-based subtract-multiplication unit and its application to butterfly unit

Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa

IPSJ Transactions on System LSI Design Methodology 4 60 - 69 2011

　View Summary

Large-scale network and multimedia application LSIs include application specific arithmetic units. A multiply-accumulator unit or a MAC unit which is one of these optimized units arranges partial products and decreases carry propagations. However, there is no method similar to MAC to execute "subtractmultiplication". In this paper, we propose a high-speed subtract-multiplication unit that decreases latency of a subtract operation by bit-level transformation using selector logics. By using bit-level transformation, its partial products are calculated directly. The proposed subtract-multiplication units can be applied to any types of systems using subtract-multiplications and a butterfly operation in FFT is one of their suitable applications. We apply them effectively to Radix- 2 butterfly units and Radix-4 butterfly units. Experimental results show that our proposed operation units using selector logics improves the performance by up to 13.92%, compared to a conventional approach. © 2011 Information Processing Society of Japan.

DOI
Scan vulnerability in elliptic curve cryptosystems

Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IPSJ Transactions on System LSI Design Methodology 4 47 - 59 2011

　View Summary

A scan-path test is one of the most important testing techniques, but it can be used as a side-channel attack against a cryptography circuit. Scan-based attacks are techniques to decipher a secret key using scanned data obtained from a cryptography circuit. Public-key cryptography, such as RSA and elliptic curve cryptosystem (ECC), is extensively used but conventional scan-based attacks cannot be applied to it, because it has a complicated algorithm as well as a complicated architecture. This paper proposes a scan-based attack which enables us to decipher a secret key in ECC. The proposed method is based on detecting intermediate values calculated in ECC. We focus on a 1-bit sequence which is specific to some intermediate values. By monitoring the 1-bit sequence in the scan path, we can find out the register position specific to the intermediate value in it and we can know whether this intermediate value is calculated or not in the target ECC circuit. By using several intermediate values, we can decipher a secret key. The experimental results demonstrate that a secret key in a practical ECC circuit can be deciphered using 29 points over the elliptic curve E within 40 seconds. © 2011 Information Processing Society of Japan.

DOI
Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures

Ryuta Nara, Kei Satoh, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E93A ( 12 ) 2481 - 2489 2010.12

　View Summary

Scan based side channel attacks retrieve a secret key in a cryptography circuit by analyzing scanned data Since they must be considerable threats to a cryptosystem LSI we have to protect cryptography circuits from them RSA is one of the most important cryptography algorithms because it effectively realizes a public key cryptography system RSA is extensively used but conventional scan based side channel attacks cannot be applied to it because It has a complicated algorithm This paper proposes a scan based side channel attack which enables us to retrieve a secret key in an RSA circuit The proposed method is based on detecting intermediate values calculated in an RSA circuit We focus on a I bit time sequence which is specific to some intermediate values By monitoring the I bit time sequence in the scan path we can find out the register position specific to the intermediate value and we can know whether this intermediate value is calculated or not in the target RSA circuit We can retrieve a secret key one bit by one bit from MSB to LSB The experimental results demonstrate that a 1 024 bit secret key used in the target RSA circuit can be retrieved using 30 2 input messages within 98 3 seconds and its 2 048 bit secret key can be retrieved using, 34 4 input within 634 0 seconds

DOI
VLSI Implementation of a Fast Intra Prediction Algorithm for H.264/AVC Encoding

Youhua Shi, Kenta Tokumitsu, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEEE APCCAS 2010 1139 - 1142 2010.12

DOI
A Fast Selector-Based Subtract-Multiplication Unit and its Application to Radix-2 Butterfly Unit

Youhei Tsukamoto, Masao. Yanagisawa, Tatsuo. ohtsuki, Nozomu. Togawa

IEEE APCCAS 2010 1083 - 1086 2010.12

DOI
Busmesh NoC: A Novel NoC Architecture Comprised of Bus-based Connection and Global Mesh Routers

SeungJu Lee, Masao.Yanagisawa, Tatsuo. Ohtsuki, Nozomu. Togawa

IEEE APCCAS 2010 712 - 715 2010.12

DOI
FIFOをキャッシュ置換えポリシとする正確なキャッシュ構成シミュレーションの高速化

多和田雅師, 柳澤政生, 大附辰夫, 戸川望

電子情報通信学会デザインガイア2010 VLD 2010-64 55 - 60 2010.11
A Throughput-aware BusMesh NoC Configuration Algorithm Utilizing the Communication Rate between IP Cores

SeungJu Lee, Masao Yanagisawak, Tatsuo Ohtsuki, Nozomu Togawa

The 16th Workshop on Synthesis and System Integration of Mixed Information Technologies 96 - 101 2010.10
RSA暗号に対するスキャンベース攻撃の評価実験

奈良竜太, 柳澤政生, 大附辰夫, 戸川望

電子情報通信学会ソサイエティ大会 68 2010.09
Constant-scan-based attack and its countermeasure for crypto hardware implementations

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

情報処理学会DAシンポジウム2010 75 - 80 2010.09
RDRアーキテクチャを対象としたフォールトセキュア高位合成手法

田中翔, 柳澤政生, 大附辰夫, 戸川望

情報処理学会DAシンポジウム2010 69 - 74 2010.09
FIFOとPLRUをキャッシュ置換ポリシとする高速なキャッシュ構成シミュレーション手法

多和田雅師, 柳澤政生, 大附辰夫, 戸川望

情報処理学会DAシンポジウム2010 63 - 68 2010.09
組み込みアプリケーションを対象とした2階層キャッシュメモリにおけるキャッシュ/バス構成最適化手法

渡辺信太, 戸川望, 柳澤政生, 大附辰夫

情報処理学会DAシンポジウム2010 57 - 62 2010.09
Improved Launch for Higher TDF Coverage With Fewer Test Patterns

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 29 ( 8 ) 1294 - 1299 2010.08

　View Summary

Due to the limitations of scan structure, the second vector in transition delay test is usually applied either by shift operation or by functional launch, which possibly results in unsatisfying transition delay fault (TDF) coverage. To overcome such a limitation for higher TDF coverage, a novel improved launch delay test technique that combines the pros of launch-on-shift and launch-on-capture tests is introduced in this paper. The proposed method can achieve near perfect TDF coverage with fewer test patterns without the need for a global fast scan enable signal. Experimental results on ISCAS89 and ITC99 benchmark circuits are included to show the effectiveness of the proposed method.

DOI
携帯電話GPSの測位誤差測定に基づく道路標識とランドマークを用いた位置特定システムの改良

田口真史, 児島伴幸, 柳澤政生, 大附辰夫, 戸川望

マルチメディア,分散,協調とモバイルシンポジウム(DICOMO2010)論文集 968 - 975 2010.07
MANETにおけるSIPサーバレスシステム

下坂知輝, 戸川望, 柳澤政生, 大附辰夫

マルチメディア,分散,協調とモバイルシンポジウム(DICOMO2010)論文集 1919 - 1927 2010.07
一般化レジスタ分散アーキテクチャを対象とした高位合成手法とその評価

大智輝, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 VLD2010-1 19 - 24 2010.05
State-dependent Changeable Scan Architecture against Scan-based Side Channel Attacks

Ryuta Nara, Hiroshi Atobe, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

ISCAS 2010 1867 - 1870 2010.05

DOI
Performance-driven High-level Synthesis with Floorplan for GDR Architectures and its Evaluation

Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

ISCAS 2010 921 - 924 2010.05

DOI
RSA暗号に対するスキャンベース攻撃

奈良竜太, 佐藤圭, 戸川望, 柳澤政生, 大附辰夫

第23回回路とシステム軽井沢ワークショップ 197 - 202 2010.04
道路標識とランドマークを用いた歩行者位置特定システムと実地調査による評価

児島伴幸, 山根和也, 柳澤政生, 大附辰夫, 戸川望

情報処理学会論文誌 Vol. 51 ( No.3 ) 899 - 913 2010.03

CiNii
常時着用型センサ"ビジネス顕微鏡"による組織変革

荒宏視, 佐藤信夫, 矢野和男, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 Vol.109 ( No.462 ) 43 - 47 2010.03
歩行者の現在地認識に基づく道路標識とランドマークを用いた位置特定システムの改良とシミュレーション評価

児島伴幸, 柳澤政生, 大附辰夫

電子情報通信学会ITS研究会 Vol.109 ( No.414 ) 153 - 158 2010.02
Localization of sperm whales in a group using clicks received at two separated short baseline arrays

Ryo Hirotsu, Masao Yanagisawa, Tamaki Ura, Masao Sakata, Harumi Sugimatsu, Junichi Kojima, Rajendar Bahl

JOURNAL OF THE ACOUSTICAL SOCIETY OF AMERICA 127 ( 1 ) 133 - 147 2010.01

　View Summary

In this paper, a sperm whale click analysis scheme is proposed in order to calculate the position of individual sperm whales in a group using data received at two arrays deployed near the surface. The proposed method mainly consists of two parts: short baseline (SBL) with classification and long baseline (LBL) with class matching. In SBL with classification, a click is automatically detected, and its direction of arrival is calculated. The clicks are then classified based on their direction vectors. The class data are then sent together with direction data and matched to the other array's class data. LBL with class matching is used for localization. The classification algorithm can be used to estimate the number of whales clicking and to list potential candidates for LBL matching. As a result, the proposed method is able to localize the positions of the whales in a group. The performance of the proposed method is evaluated using data recorded off Ogasawara islands with two arrays near the surface. The three-dimensional underwater trajectories of six sperm whales are extracted to demonstrate the capability of the proposed method. (C) 2010 Acoustical Society of America. [DOI: 10.1121/1.3268593]

DOI
部分マッチングを考慮しMISO構造に対応した専用演算器合成手法

橋本識弘, 戸川望, 柳澤政生

電子情報通信学会VLSI設計技術研究会 Vol.109 ( No.393 ) 89 - 94 2010.01
Scan-Based Attack against Elliptic Curve Cryptosystems

Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEEE 15th Asia and South Pacific Design Automation Conference (ASP-DAC 2010) 407 - 412 2010.01

DOI
複数のグループを持つ無線アドホックネットワークにおける衝突回避型マルチキャストプロトコル

竹内博是, 戸川望, 柳澤政生

電子情報通信学会AN研究会 Vol.109 ( No.381 ) 95 - 100 2010.01
アドホックネットワークにおけるクラスタの接続性とクラスタヘッドの負荷分散を考慮したルーティング

板橋裕介, 戸川望, 柳澤政生

電子情報通信学会AN研究会 Vol.109 ( No.381 ) 85 - 90 2010.01
X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E92A ( 12 ) 3119 - 3127 2009.12

　View Summary

This paper presents a novel X-handling technique, which removes the effect of unknowns on compacted test response with maximal compaction ratio. The proposed method combines with the current X-tolerant compactors and inserts masking cells on scan paths to selectively mask X's. By doing this, the number of unknown responses in each scan-out cycle could be reduced to a reasonable level such that the target X-tolerant compactor would tolerate with guaranteed possible error detection, It guarantees no test loss due to the effect of X's, and achieves the maximal compaction that the target response compactor could provide as well. Moreover, because the masking cells are only inserted on the scan paths, it has no performance degradation of the designs. Experimental results demonstrate the effectiveness of the proposed method.

DOI
2階層キャッシュメモリにおけるシミュレーションベースのバス幅最適化手法

渡辺信太, 戸川望, 柳澤政生

電子情報通信学会VLSI設計技術研究会 Vol.109 ( No.315 ) 43 - 48 2009.12
組み込みアプリケーションを対象とした2階層ユニファイドキャッシュのシミュレーション手法

小林優太, 戸川望, 柳澤政生

電子情報通信学会VLSI設計技術研究会 Vol.109 ( No.315 ) 37 - 42 2009.12
A Scan-Based Attack Based on Discriminators for AES Cryptosystems

Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E92A ( 12 ) 3229 - 3237 2009.12

　View Summary

A scan chain is one of the most important testing techniques, but it can be used as side-channel attacks against a cryptography LSI. We focus on scan-based attacks, in which scan chains are targeted for side-channel attacks. The conventional scan-based attacks only consider the scan chain composed of only the registers in a cryptography circuit. However, a cryptography LSI usually uses many circuits such as memories, micro processors and other circuits. This means that the conventional attacks cannot be applied to the practical scan chain composed of various types of registers. In this paper, a scan-based attack which enables to decipher the secret key in an AES cryptography LSI composed of an AES circuit and other circuits is proposed. By focusing on bit pattern of the specific register and monitoring its change, Our scan-based attack eliminates the influence of registers included in other circuits than AES. Our attack does not depend on scan chain architecture, and it can decipher practical AES cryptography LSIs.

DOI
Design-for-Secure- Test for Crypto Cores

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEEE International Test Conference (ITC) 2009.11

DOI
セレクタ論理を用いた高速な差積演算器の設計とバタフライ演算への応用

塚本洋平, 戸川望, 柳澤政生

電子情報通信学会SIP研究会 Vol.109 ( No.226 ) 101 - 106 2009.10
ディジタルメディア向け動的再構成型プロセッサFE-GAへのDFGマッピングとその自動化手法

田村亮, 戸川望, 柳澤政生, 大附辰夫, 佐藤真琴

電子情報通信学会VLSI設計技術研究会 Vol.109 ( No.201 ) 57 - 62 2009.09
IEEE802.11nに対応した高効率列処理演算器による高スループットイレギュラーLDPC復号器の実装と評価

長島諒侑, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 Vol.109 ( No.201 ) 51 - 56 2009.09
Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2(n))

Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E92A ( 9 ) 2304 - 2317 2009.09

　View Summary

Modular multiplication is the most dominant arithmetic operation in elliptic curve cryptography (ECC), that is a type of public-key cryptography. Montgomery multiplier is commonly used to compute the modular multiplications and requires scalability because the bit length of operands varies depending on its security level. In addition, ECC is performed in GF(P) or GF(2(n)), and unified architecture for multipliers in GF(P) and GF(2(n)) is required. However, in previous works, changing frequency is necessary to deal with delay-time difference between GF(P) and GF(2(n)) multipliers because the critical path of the GF(P) multiplier is longer. This paper proposes unified dual-radix architecture for scalable Montgomery multiplications in GF(P) and GF(2(n)). This proposed architecture unifies four parallel radix-2(16) multipliers in GF(P) and a radix-2(64) multiplier in GF(2(n)) into a single unit. Applying lower radix to GF(P) multiplier shortens its critical path and makes it possible to compute the operands in the two fields using the same multiplier at the same frequency so that clock dividers to deal with the delay-time difference are not required. Moreover, parallel architecture in GF(P) reduces the clock cycles increased by dual-radix approach. Consequently, the proposed architecture achieves to compute a GF(P) 256-bit Montgomery multiplication in 0.28 mu s. The implementation result shows that the area of the proposal is almost the same as that of previous works: 39 kgates.

DOI
楕円曲線暗号に対するスキャンベース攻撃

奈良竜太, 戸川望, 柳澤政生, 大附辰夫

DAシンポジウム2009 Vol.2009 ( No.7 ) 197 - 202 2009.08
道路標識とランドマークを用いた歩行者位置特定システムと実地調査による評価

児島伴幸, 山根和也, 戸川望, 柳澤政生, 大附辰夫

マルチメディア,分散,協調とモバイルシンポジウム(DICOMO2009) 457 - 466 2009.07

CiNii
ビットレベル処理を考慮したセレクタ帰着型重み付き加算器

原智昭, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 Vol.109 ( No.34 ) 7 - 12 2009.05
Handling More X’s Using Current X-Tolerant Compactors with Maximal Compaction

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEEE European Test Symposium (ETS) 2009.05
一般化レジスタ分散アーキテクチャを対象としたフロアプラン指向高位合成手法

大智輝, 戸川望, 柳澤政生, 大附辰夫

第22回回路とシステム軽井沢ワークショップ 438 - 443 2009.04

CiNii
Odd-Even Turn Modelを対象としたNoCの負荷分散による遅延時間削減手法

脇田慎吾, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 Vol.108 ( No.478 ) 153 - 158 2009.03

　View Summary

It is necessary to suppress the average delay to low when the packet is forwarded from a source node to the destination node in Network-on-Chip (NoC) for the quality maintenance of the communication between nodes. Adaptive routing used in NoC is composed of routing function that selects route candidates and selection function that decides the candidate which minimizes the communication delay for the distribution of traffic to the used route. Currently, the odd-even turn model has been used as the most popular method for routing function. However, due to that odd-even turn model doesn't consider the load distribution when conducting route selection, the use of the channel on which the load has been concentrated might not be avoided and the delay might grow as a result. Thus, in this paper we propose an approach for both traffic decentralization and delay reduction. The proposed approach introduces a concept of restricted area, which contains the region concentrating traffic by the feature of the route selection method of odd-even turn model and limits the use of channels in the restricted area.

CiNii
連携処理を考慮したネットワークプロセッサへの処理割り当て手法

齊藤啓太, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 Vol.108 ( No.478 ) 147 - 152 2009.03
命令メモリアクセス数削減に基づく低エネルギーASIP合成手法

小林優太, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 Vol.108 ( No.414 ) 147 - 152 2009.01
組み込みシステム向けMPSoCのためのマルチレイヤ構造をとるバスアーキテクチャ最適化手法

吉田陽信, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 Vol.108 ( No.414 ) 141 - 146 2009.01
アプリケーションプロセッサのための高速かつ最適なパイプライン構成を持つSIMD演算ユニット合成手法

渡辺隆行, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 Vol.108 ( No.414 ) 99 - 104 2009.01
フロアプランを考慮した高位合成のための高速なモジュール配置手法

佐藤亘, 大智輝, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 Vol.108 ( No.412 ) 93 - 98 2009.01
高速移動体のためのNEMOを用いた高速ハンドオフ手法

田中敦樹, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会NS研究会 Vol.108 ( No.359 ) 89 - 94 2008.12
ルータの負荷分散と制御パケット数削減を目的としたエニーキャスト経路選択手法

横田雅之, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会NS研究会 Vol.108 ( No.359 ) 13 - 18 2008.12
組み込みシステムの2階層キャッシュとスクラッチパッドメモリのシミュレーション手法

東條信明, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 Vol.108 ( No.298 ) 97 - 102 2008.11
周辺回路を含むAES-LSIへのスキャンベース攻撃

奈良竜太, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 Vol.108 ( No.298 ) 49 - 53 2008.11
MANETにおけるGPSの位置情報を用いたハイブリッド型ルーティングプロトコル

三浦俊祐, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会AN研究会 Vol.108 ( No.251 ) 17 - 22 2008.10
ビットレベル式変形によるセレクタ帰着型バタフライ演算器の設計と評価

名村健, 戸川望, 柳澤政生, 大附辰夫, 外村元伸

電子情報通信学会VLSI設計技術研究会 Vol.108 ( No.224 ) 31 - 36 2008.09
ディジタルメディア向け動的再構成型プロセッサFE-GAへのFFTマッピングとその自動化手法

田村亮, 本間雅行, 戸川望, 柳澤政生, 大附辰夫, 佐藤真琴

電子情報通信学会VLSI設計技術研究会 Vol.108 ( No.224 ) 13 - 18 2008.09
再構成型プロセッサFE-GAへのデータフローグラフマッピング手法

本間雅行, 田村亮, 戸川望, 柳澤政生, 大附辰夫, 佐藤真琴

電子情報通信学会VLSI設計技術研究会 Vol.108 ( No.224 ) 7 - 12 2008.09
Classification of Sperm Whale Clicks and Triangulation for Real-Time Localization with SBL Arrays

Ryo Hirotsu, Tamaki Ura, Junichi Kojima, Harumi Sugimatsu, Rajendar Bahl, Masao Yanagisawa

Proc. of OCEANS' 08 IEEE/MTS Quebec Canada 2008.09

DOI
歩行者ナビゲーションにおける道路標識を用いた位置特定システムのための撮影状況に依存した認識度調査

児島伴幸, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会ITS研究会 Vol.108 ( No.171 ) 37 - 42 2008.07
屋内環境におけるユーザの経路嗜好調査とこれに基づく経路探索手法

山岸敬弘, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会ITS研究会 Vol.108 ( No.171 ) 31 - 36 2008.07
道路ネットワーク分割に基づく高速エリア略地図生成手法

松本和也, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会ITS研究会 Vol.108 ( No.171 ) 25 - 30 2008.07
セレクタ論理を用いたバタフライ演算器の設計

名村健, 戸川望, 柳澤政生, 大附辰夫, 外村元伸

電子情報通信学会VLSI設計技術研究会 Vol.108 ( No.22 ) 25 - 30 2008.05
アプリケーションプロセッサのL1キャッシュ最適化手法

東條信明, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会第21回回路とシステム軽井沢ワークショップ 243 - 248 2008.04
Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures

A. Ohchi, S. Kohara, N. Togawa, M. Yanagisawa, T. Ohtsuki

VLSI-DAT 2008 164 - 167 2008.04

DOI
応用指向型動的再構成可能ネットワークプロセッサアーキテクチャとその最適化手法

大田元則, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 Vol.107 ( No.508 ) 47 - 52 2008.03
命令メモリビット幅削減に基づく低エネルギーASIP合成手法

小原俊逸, 史又華, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 Vol.107 ( No.506 ) 25 - 30 2008.03
光パケット交換ネットワークにおける波長割当の公平性

原真吾, 石川栄治, 徐蘇鋼, 田中良明, 柳澤政生

電子情報通信学会総合大会 2008 2008.03
広域ネットワークにおけるノード探索アルゴリズム

岡田陽士朗, ザニケエフマラット, 田中良明, 柳澤政生

電子情報通信学会総合大会 2008 2008.03
A secure test technique for pipelined advanced encryption standard

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E91D ( 3 ) 776 - 780 2008.03

　View Summary

In this paper, we presented a Design-for-Secure-Test (DFST) technique for pipelined AES to guarantee both the security and the test quality during testing. Unlike previous works, the proposed method can keep all the secrets inside and provide high test quality and fault diagnosis ability as well. Furthermore, the proposed DFST technique can significantly reduce test application time, test data volume, and test generation effort as additional benefits.

DOI
応用指向型動的再構成可能ネットワークプロセッサアーキテクチャとその最適化手法

大田元則, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 VLD2007-164 47 - 52 2008.03
命令メモリビット幅削減に基づく低エネルギーASIP合成手法

小原俊逸, 史又華, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 VLD2007-141 25 - 30 2008.03
LAMR : アドホックネットワークにおける負荷分散を考慮したマルチパスルーティング

清水悠司, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会ネットワークシステム研究会 NS2007-129 51 - 56 2008.01
MAPドメイン間移動のためのハンドオフ時間とパケットロスの削減手法

田中敦樹, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会ネットワークシステム研究会 NS2007-127 41 - 46 2008.01
エニーキャストにおけるルータの負荷に基づく経路選択手法

横田雅之, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会ネットワークシステム研究会 NS2007-121 13 - 18 2008.01
Scalable Unified Dual-Radix Architecture for Montgomery Multiplication in GF(P) and GF(2n)

Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

ASP-DAC 2008 697 - 702 2008.01
GECOM: Test Data Compression Combined with All Unknown Response Masking

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

ASP-DAC 2008 577 - 582 2008.01
アプリケーションプロセッサのカーネル記述自動生成手法

日浦敏宏, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 VLD2007-132 83 - 88 2008.01
アプリケーションプロセッサのL1データキャッシュ最適化手法

東條信明, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 VLD2007-131 77 - 82 2008.01
レジスタ分散型アーキテクチャを対象とした高位合成のためのマルチプレクサ削減手法

遠藤哲弥, 大智輝, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 VLD2007-119 7 - 12 2008.01
Classification of Sperm Whale Clicks for Real-Time Localization with Triangulation

Ryo Hirotsu, Tamaki Ura, Junichi Kojima, Harumi Sugimatsu, Masao Sakata, Rajendar Bahl, Masao Yanagisawa

17th Biennial Conference on the Biology of Marine Mammals 2007.11
歩行者向けデフォルメ地図生成ハードウェアエンジンの設計

荒幡明, 奈良竜太, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 VLD2007-99 61 - 66 2007.11
列処理演算法に着目したマルチレート対応イレギュラーLDPC符号復号器

今井優太, 清水一範, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会リコンフィギャラブルシステム研究会 RECONF2007-46 19 - 24 2007.11
AESにおける合成体SubBytes向けパワーマスキング乗算回路の設計

川畑伸幸, 奈良竜太, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 VLD2007-88 37 - 42 2007.11
SIMD プロセッサコアの面積/遅延見積もり手法

山崎大輔, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

情報処理学会組込みシステムシンポジウム2007 2007 233 - 240 2007.10

CiNii
応用指向動的再構成なネットワークプロセッサ設計手法

大田元則, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

情報処理学会組込みシステムシンポジウム2007 141 - 150 2007.10
楕円曲線暗号用SIMD型MSD乗算器の設計

奈良竜太, 清水一範, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

情報処理学会組込みシステムシンポジウム2007 90 - 99 2007.10
CoDaMa: An XML-based Framework to Manipulate Control Data Flow Graphs

Shunitsu Kohara, Shi Youhua, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proc. of SASIMI2007 545 - 549 2007.10
A Network Processor Synthesis System for Task-Chaining Network Applications

Youhua Shi, Keishi Nakayama, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proc. of SASIMI2007 369 - 374 2007.10
Autonomous recognition of bubble plumes for navigation of underwater robots in active shallow vent areas

Hayato Mizushima, Toshihiro Maki, Tamaki Ura, Takashi Sakamaki, Hayato Kondo, Masao Yanagisawa

Oceans '07 Vancouver ポスターセッション 2007.10
歩行者ナビゲーションにおける携帯電話カメラ機能とランドマークを利用した位置補正手法

本多聖人, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会ITS研究会 ITS 2007-29 33 - 38 2007.09
歩行者ナビゲーションにおけるGPS誤差補正のための道路標識による現在位置測位手法

大平英貴, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会ITS研究会 ITS 2007-28 27 - 32 2007.09
移動体を対象としたアプリケーションとデータサイズによる階層型Network Mobilityの負荷分散方式

月木英治, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会ITS研究会 Vol.2007 65 - 70 2007.09
進路方向によって異なる混雑度を考慮した旅行時間算出手法

大高宏介, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会ITS研究会 ITS 2007-19 15 - 20 2007.09
パラメトリック連鎖解析の検出力推定のためのMCMCによる遺伝情報サンプリング

萩原紘史, 中村好宏, 高橋篤, 柳澤政生, 鎌谷直之

日本人類遺伝学会第52回大会ポスターセッション 2007.09
ケース・コントロール関連解析におけるハプロタイプ頻度推定

後藤海, 高橋篤, 柳澤政生, 鎌谷直之

日本人類遺伝学会第52回大会ポスターセッション 2007.09
GF(2m)上のSIMD型MSD乗算器を用いた楕円曲線暗号回路の実装

奈良竜太, 清水一範, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

情報処理学会DAシンポジウム2007 221 - 226 2007.08
アプリケーションに特化した動的再構成可能なネットワークプロセッサ

大田元則, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

情報処理学会DAシンポジウム2007 37 - 42 2007.08
HW/SW協調合成におけるASIPの面積/遅延見積もり手法

山崎大輔, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

情報処理学会DAシンポジウム2007 31 - 36 2007.08
Floorplan-aware High-Level Synthesis for Distributed/Shared-Register Architectures

Akira Ohchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

ITC-CSCC'07 1049 - 1050 2007.07
An Area-Efficient GF(2m) MSD Multiplier Based on an MSB Multiplier for Elliptic Curve LSI

Ryuta Nara, Kazunori Shimizu, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

ITC-CSCC'07 36 - 37 2007.07
GF(2n)及びGF(P)におけるスケーラブル双基数ユニファイド型モンゴメリ乗算器

谷村和幸, 奈良竜太, 小原俊逸, 史又華, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 VLD 2007-42 ( 103 ) 43 - 48 2007.06

　View Summary

Modular multiplication is the dominant arithmetic operation in elliptic curve cryptography (ECC), which is one of public-key cryptographies. Montgomery multiplication is commonly used as a technique for modular multiplication and required scalability since the bit length of operands varies depending on the security levels. ECC is performed in GF(P) of GF(2^n), and scalable unified architectures are proposed in previous works. However, changing frequency or dual-radix architecture is necessary to deal with delay-time difference between GF(P) and GF(2^n) parts of the multiplier because the critical path of GF(P) hardware is longer. This paper proposes an algorithm and architecture for a scalable and dual-radix unified Montgomery multiplier in GF(P) and GF(2^n). The proposed architecture unifies 4 parallelized radix-2^16 multipliers in GF(P) and a radix-2^64 multiplier in GF(2^n) into a single unit. Applying lower radix to GF(P) hardware shortens its critical path and allows to compute the numbers in the two fields using a same multiplier. Moreover, parallelized architecture in GF(P) reduces the clock cycles increased by dual-radix approach, achieving the fastest scalable unified Montgomery multiplier yet reported.

CiNii
再構成型プロセッサFE-GAへのフィルタマッピングとその自動化手法

本間雅行, 戸川望, 柳澤政生, 大附辰夫, 佐藤真琴

電子情報通信学会VLSI設計技術研究会 VLD 2007-28 67 - 72 2007.06
Design for Secure Test -- A Case Study on Pipelined Advanced Encryption Standard

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proc. of ISCAS2007 49 - 152 2007.05
楕円曲線暗号に適したGF(2m)上のSIMD型MSD乗算器の設計

奈良竜太, 清水一範, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 VLD 2007-11 ( 32 ) 25 - 29 2007.05

　View Summary

Originally elliptic curve cryptosystem (ECC) hardware are often required to operate variable key length. Digit-serial multipliers for ECC enable the hardware to accelerale the finite field operation. However, the lack of flexibility of digit-serial multipliers is major challenge for building the ecc hardware which operates variable key length. In this paper, we propose a SIMD MSD multiplier based on variable GF(2^m) for ECC. Adjusting the parallellizm of the SIMD MSD multiplier according to the field length enables us to accelarate the ecc scalar multiplication throughput. The proposed multiplier operates 5 types of field length which are recommended by NIST, where 2 multiplications can be operated simultaneously for the small field length. Implementation results show that the proposed multiplier reduces the hardware area by up to 1/3 compared to the same throughput. while achieving up to about 2 times multiplication throughput compared to the conventional multipliers for the variable field length.

CiNii
GF(2n)上のMSB乗算器をベースにした楕円曲線暗号LSI向けMSD乗算器の実装

奈良竜太, 小原俊逸, 清水一範, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会回路とシステム軽井沢ワークショップ 355 - 360 2007.04
モバイルユーザの目的地への方向性を考慮した楕円領域検索手法

山本隆之, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会ITS研究会 ITS 2006-94 25 - 30 2007.03
エニーキャスト通信におけるサーバ処理時間を考慮した経路選択手法

楊夏, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会ネットワークシステム研究会 NS 2006-231 381 - 386 2007.03
携帯電話向けMPEG-A Photo Playerのメタデータ生成システムのハードウェア化に関する一考察

元橋雅人, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 VLD 2006-145 31 - 36 2007.03
アプリケーションプロセッサ向けデータキャッシュ構成最適化システムとその評価

堀内一央, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 VLD 2006-122 19 - 24 2007.03
SIMD型プロセッサコア最適化設計のための多重ループに対応したSIMD命令合成手法

中島裕貴, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 VLD 2006-121 13 - 18 2007.03
SIMD型プロセッサコアを対象としたハードウェア/ソフトウェア分割フレームワーク

大東真崇, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 VLD 2006-120 7 - 12 2007.03
SIMD型プロセッサコア設計におけるプロセッシングユニット最適化手法

繁田裕之, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 VLD 2006-119 1 - 6 2007.03
無線センサネットワークにおけるエネルギー消費削減のためのクラスタリング手法

廣瀬文昭, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会ネットワークシステム研究会 NS 2006-165 41 - 46 2007.03
XMLをベースとしたCDFGマニピュレーションフレームワーク:CoDaMa

小原俊逸, 史又華, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 Vol.VLD 2006-97 19 - 24 2007.01
楕円曲線暗号向けGF(2m)上のDigit-Serial乗算器の設計

奈良竜太, 小原俊逸, 清水一範, 戸川望, 池永剛, 柳澤政生, 後藤敏, 大附辰夫

電子情報通信学会VLSI設計技術研究会 Vol.VLD 2006-89 25 - 30 2007.01
アプリケーションプロセッサのフォワーディングユニット最適化手法

日浦敏宏, 小原俊逸, 史又華, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 Vol.VLD 2006-80 49 - 54 2006.11
動的再構成可能なマルチレート対応LDPC符号複号器の実装

今井優太, 清水一範, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会リコンフィギャラブルシステム Vol.RECONF 2006-43 35 - 40 2006.11
MPEG-4形式符号化/複合化に対応したDSP組み込み向け専用演算器の設計

古宇田朋史, 小原俊逸, 史又華, 戸川望, 柳澤政生, 大附辰夫

組込みシステムシンポジウム2006 Vol.2006 70 - 78 2006.10
歩行者ナビゲーションにおける微小画面での視認性とユーザの迷いにくさを考慮した略地図生成手法

二宮直也, 戸川望, 柳澤政生, 大附辰夫

第26回高度交通システム研究発表会 (EICE Technical Report ITS) 2006-34 53 - 58 2006.09
屋内用歩行者ナビゲーションにおける歩行者の嗜好を反映させる経路探索手法

荒井亨, 戸川望, 柳澤政生, 大附辰夫

第26回高度交通システム研究発表会 (IEICE Technical Report ITS) 2006-34 47 - 52 2006.09
屋内向け歩行者ナビゲーションにおけるユーザの嗜好性と混雑状況を考慮した目的地決定手法

小林和馬, 戸川望, 柳澤政生, 大附辰夫

第26回高度交通システム研究発表会 (IEICE Technical Report ITS) 2006-34 41 - 45 2006.09
車車間・路車間通信技術を用いた車線別の渋滞情報の検出手法

大高宏介, 戸川望, 柳澤政生, 大附辰夫

第26回高度交通システム研究発表会 (IEICE Technical Report ITS) 2006-34 19 - 24 2006.09
自己組織化マップを用いた複数MRI画像からの腫瘍自動抽出 -高速化アルゴリズムの検討-

細田順一, 上村幸司, 小畠隆行, 生駒洋子, 安藤裕, 鎌田正, 溝江純悦, 辻井博彦, 柳澤政生, 内山明彦, 外山比南子

第25回日本医用画像工学会大会ポスターセッション 2006.07
レジスタ分散・共有併用型アーキテクチャを対象としたフロアプランを考慮した高位合成手法

大智輝, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

情報処理学会DAシンポジウム2006 Vol.2006 175 - 180 2006.07
連携処理を考慮したネットワークプロセッサ合成システム

中山敬史, 戸川望, 柳澤政生, 大附辰夫

情報処理学会DAシンポジウム2006 Vol.2006 61 - 66 2006.07
H.264/AVC符号化向けDSPにおける動き予測演算器の設計

高橋豊和, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会回路とシステム Vol.CAS10 13 - 19 2006.06
HW/SW協調合成におけるアプリケーションプロセッサの面積/遅延見積もり手法

山崎大輔, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会回路とシステム Vol.CAS1 1 - 6 2006.06
SIMD型プロセッサコアの自動合成のためのパイプライン演算ユニット生成手法

栗原輝, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

情報処理学会論文誌 Vol.47 ( No.6 ) 1594 - 1607 2006.06
Analysis of Sperm Whale Click by MUSIC Algorithm

Ryou Hirotsu, Tamaki Ura, Rajendar Bahl, Masao Yanagisawa

Proc OCEANS’06 Singapore 2006.05
Analysis of Sperm Whale Click by MUSIC Algorithm

Ryou Hirotsu, Tamaki Ura, Rajendar Bahl, Masao Yanagisawa

Proc OCEANS’06 Singapore 2006.05
A Pipelined Functional Unit Generation Method in HW/SW Cosynthesis System for SIMD Processor Cores

Shunitsu Kohara, Akira Kurihara, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proc. of SASIMI2006 287 - 294 2006.04
アプリケーションプロセッサのデータキャッシュ構成最適化手法

堀内一央, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会回路とシステム軽井沢ワークショップ 583 - 588 2006.04
A Pipelined Functional Unit Generation Method in HW/SW Cosynthesis System for SIMD Processor Cores

Shunitsu Kohara, Akira Kurihara, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proc. of SASIMI2006 287 - 294 2006.04
歩行者向け地図情報配信システムにおける道路交通標識を用いた位置特定手法

中口智史, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会ITS研究会 2006.03
SIMD型プロセッサコアの自動合成におけるパイプライン構成最適化手法

栗原輝, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 Vol.VLD115 43 - 48 2006.03
動的フローに対応したネットワークプロセッサの改良とその評価

田淵英孝, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 Vol.VLD112 25 - 30 2006.03
設計ナビゲーション機構を有するシステムLSI設計のためのHW/SW分割システム

小島洋平, 戸川望, 橘昌良, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 Vol.VLD111 19 - 24 2006.03
高速移動体のためのハンドオフメッセージ数を最小化した高速ハンドオフ手法

伊藤光司, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会情報ネットワーク研究会 Vol.IN222 389 - 394 2006.03
事後確率最大化規範と波形認識によるPETを用いた脳内糖代謝詳細画像の作成

山口純, 木村裕一, 長縄美香, 内山明彦, 柳澤政生

電子情報通信学会医用画像研究会 13 - 16 2006.01
FCSCAN: An Efficient Multiscan-based Test Compression Technique for Test Cost Reduction

Youha Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki

Proc. of ASP-DAC 2006 653 - 658 2006.01
An Interface-Circuit Synthesis Method with Configurable Processor Core in IP-Based SoC Designs

Shunitsu Kohara, Naoki Tomono, Junpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proc. of ASP-DAC 2006 594 - 599 2006.01
A fast elliptic curve cryptosystem LSI embedding word-based montgomery multiplier

Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Transactions on Electronics E89-C ( 3 ) 243 - 249 2006

　View Summary

Elliptic curve cryptosystems are expected to be a next standard of public-key cryptosystems. A security level of elliptic curve cryptosystems depends on a difficulty of a discrete logarithm problem on elliptic curves. The security level of a elliptic curve cryptosystem which has a public-key of 160-bit is equivalent to that of a RSA system which has a public-key of 1024-bit. We propose an elliptic curve cryptosystem LSI architecture embedding word-based Montgomery multipliers. A Montgomery multiplication is an efficient method for a finite field multiplication. We can design a scalable architecture for an elliptic curve cryptosystem by selecting structure of word-based Montgomery multipliers. Experimental results demonstrate effectiveness and efficiency of the proposed architecture. In the hardware evaluation using 0.18 μ m CMOS library, the high-speed design using 126 Kgates with 20 × 8-bit multipliers achieved operation times of 3.6 ms for a 160-bit point multiplication. Copyright © 2006 The Institute of Electronics, Information and Communication Engineers.

DOI
Noninvasive Tonometry of Intraocular Pressure over a Closed Eyelid

M.Nakai, I.Yoshizawa, A.Fujita, S.Takeda, K.Yanasima, A.Uchiyama, M.Yanagisawa

The 12th International Conference On Biomedical Engineering 2005.12
重回帰分析による1次式によるインダクタンスを考慮した配線遅延の見積り

鈴木康成, マルタディナタアンワル, 戸川望, 柳澤政生, 大附辰夫

情報処理学会システムLSI設計技術研究会 Vol.SLDM122 109 - 114 2005.12
レジスタ分散・共有アーキテクチャを対象としたフロアプラン指向高位合成手法

大智輝, 戸川望, 柳澤政生, 大附辰夫

情報処理学会システムLSI設計技術研究会 Vol.SLDM122 73 - 78 2005.12
Volume DAtaをリアルタイム変形処理できる手術シミュレータにおける肝区域分けの実現

瀧本崇博, 鈴木直樹, 服部麻木, 鈴木薫之, 林部充宏, 大竹義人, 中田典生, 小林進, 柳澤政生

第14回日本コンピュータ外科学会大会第15回コンピュータ支援画像診断学会大会合同論文集 255 - 256 2005.11
振動を用いた瞼の上から測定可能な無侵襲眼圧計の開発

中井真琴, 吉澤周, 藤田明宏, 武田朴, 簗島謙次, 内山明彦, 柳澤政生

第41回日本眼光学学会第20回眼科ME学会合同学会総会 48 2005.09
画像処理向けシステムLSI設計における設計ナビゲーションを考慮したHW/SW分割システム

小島洋平, 戸川望, 橘昌良, 柳澤政生, 大附辰夫

情報処理学会DAシンポジウム2005 Vol.2005 25 - 30 2005.08
SIMD型プロセッサコアの自動合成におけるパイプライン演算ユニット生成手法

栗原輝, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

情報処理学会DAシンポジウム2005 Vol.2005 19 - 24 2005.08
自己組織化マップを用いた複数MRI画像からの腫瘍自動抽出法の開発

細田順一, 上村幸司, 小畠隆行, 生駒洋子, 安藤裕, 鎌田正, 神立進, 溝江純悦, 辻井博彦, 柳澤政生, 内山明彦

第24回日本医用画像工学会大会ポスターセッション 2005.07
A SIMD instruction set and functional unit synthesis algorithm with SIMD operation decomposition

N Togawa, K Tachikake, Y Miyaoka, M Yanagisawa, T Ohtsuki

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E88D ( 7 ) 1340 - 1349 2005.07

　View Summary

This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algorithm. Given an initial assembly code and a timing constraint, the proposed algorithm synthesizes an area-optimized processor core with optimal SIMD functional units. It also synthesizes a SIMD instruction set. The input initial assembly code is assumed to run on a full-resource SIMD processor (virtual processor) which has all the possible SIMD functional units. In our algorithm, we introduce the SIMD operation decomposition and apply it to the initial assembly code and the full-resource SIMD processor. By gradually reducing SIMD operations or decomposing SIMD operations, we can finally find a processor core with small area under the given timing constraint. The promising experimental results are also shown.

DOI
Sub-operation Parallelism Optimization in SIMD Processor Synthesis and Its Experimental Evaluations

Nozomu Togawa, Hideki Kawazu, Jumpei UchiDA, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. on Fundamentals. Vol.E88-A ( No.4 ) 876 - 884 2005.04

DOI
IP再利用を考慮したシステムLSI設計におけるインタフェース回路生成システム

小原俊逸, 友野直紀, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会回路とシステム軽井沢ワークショップ 581 - 586 2005.04
SIMD型プロセッサコア向けHW/SW協調合成システムにおけるパイプライン演算ユニット生成手法

栗原輝, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会回路とシステム軽井沢ワークショップ 575 - 580 2005.04
A Selective Care Bits Coding Method for Test DAta Compression

Youha Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki

電子情報通信学会回路とシステム軽井沢ワークショップ 241 - 246 2005.04
インダクタンスを考慮した配線遅延の近似式による見積もり

鈴木康成, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会回路とシステム軽井沢ワークショップ 1 - 6 2005.04
クラスタリングを用いたPET神経受容体画像の画質改善

矢野純一, 木村裕一, 柳澤政生, 内山明彦

第44回日本生体医工学会大会ポスターセッション 438 2005.04
自己組織化マップを用いた複数MRI画像からの腫瘍自動抽出

細田順一, 上村幸司, 小畠隆行, 生駒洋子, 鎌田正, 神立進, 溝江純悦, 辻井博彦, 柳澤政生, 内山明彦

第44回日本生体医工学会大会ポスターセッション 430 2005.04
volume data を扱うことのできる手術シミュレーションシステムの開発 - 肝臓モデルにおける切開・切離, 摘出機能の実現

瀧本崇博, 服部麻木, 鈴木薫之, 林部充宏, 大竹義人, 小林進, 柳澤政生, 内山明彦

第44回日本生体医工学会大会ポスターセッション 353 2005.04
Sub-operation parallelism optimization in SIMD processor core synthesis

H Kawazu, J Uchida, Y Miyaoka, N Togawa, M Yanagisawa, T Ohtsuki

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E88A ( 4 ) 876 - 884 2005.04

　View Summary

A b-bit SIMD functional unit has n k-bit sub-functional units in itself, where b = k x n. It can execute n-parallel k-bit operations. However, all the b-bit functional units in a processor core do not necessarily execute n-parallel operations. Depending on an application program, some of them just execute n/2-parallel operations or even n/4-parallel operations. This means that we can modify a b-bit SIMD functional unit so that it has n/2 k-bit sub-functional units or n/4 k-bit sub-functional units. The number of k-bit sub-functional units in a SIMD functional unit is called sub-operation parallelism. We incorporate a sub-operation parallelism optimization algorithm into SIMD functional unit optimization. Our proposed algorithm gradually reduces sub-operation parallelism of a SIMD functional unit while the timing constraint of execution time satisfied. Thereby, we can finally find a processor core with small area under the given timing constraint. We expect that we can obtain processor core configurations of smaller area in the same timing constraint rather than a conventional system. The promising experimental results are also shown.

DOI
動的フローに適応したネットワークプロセッサ設計とその評価

細田宗一郎, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 Vol.VLD150 79 - 84 2005.03
面積制約を考慮したマルチスレッドプロセッサの合成手法

麻生雄一, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 Vol.VLD142 31 - 36 2005.03
ネットワークプロセッサ合成システムの改良とその評価

升本英行, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 Vol.VLD141 25 - 30 2005.03
ワードベースモンゴメリ乗算器を搭載した高速楕円曲線暗号LSI

内田純平, 奈良竜太, 宮岡祐一郎, 戸川望, 柳沢政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 Vol.VLD125 5 - 10 2005.03
A Processor Core Synthesis System in IP-based SoC Design

Naoki Tomono, Shuitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proc. of ASP-DAC 2005 Vol.1 286 - 291 2005.01
A SIMD instruction set and functional unit synthesis algorithm with SIMD operation decomposition

Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Transactions on Information and Systems E88-D ( 7 ) 1340 - 1349 2005

　View Summary

This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algorithm. Given an initial assembly code and a timing constraint, the proposed algorithm synthesizes an area-optimized processor core with optimal SIMD functional units. It also synthesizes a SIMD instruction set. The input initial assembly code is assumed to run on a full-resource SIMD processor (virtual processor) which has all the possible SIMD functional units. In our algorithm, we introduce the SIMD operation decomposition and apply it to the initial assembly code and the full-resource SIMD processor. By gradually reducing SIMD operations or decomposing SIMD operations, we can finally find a processor core with small area under the given timing constraint. The promising experimental results are also shown. Copyright © 2005 The Institute of Electronics, Information and Communication Engineers.

DOI
FPGAによる海洋生物のための音声解析システムの実装

清水友樹, バール・ラジェンダール, 坂田雅雄, 浦環, 柳澤政生

電子情報通信学会VLSI設計技術研究会 Vol.VLD113 19 - 24 2005.01
A Processor Core Synthesis System in IP-based SoC Design

Naoki Tomono, Shuitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proc. of ASP-DAC 2005 Vol.1 286 - 291 2005.01
A new correction for multiple comparisons in genome-wide case-control association studies based on haplotypes and diplotype configurations

Shogo Fujii, Toshimasa Yamazaki, Masao Yanagisawa, Yozo Ohnishi, Yusuke Nakamura, Naoyuki Kamatani

The 13th Takeda Science Foundation Symposium on Bioscience ポスターセッション 74 2004.12
A Selective Scan Chain Reconfiguration through Run-Length Coding for Test Data Compression and Scan Power Reduction

Youhua Shi, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. on Fundamentals Vol.E87-A ( No.12 ) 3208 - 3215 2004.12
A Hybrid Dictionary Test Data Compression for Multiscan-Based Designs

Youhua Shi, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. on Fundamentals Vol.E87-A ( No.12 ) 3193 - 3199 2004.12
High-Level Power Optimization Based on thread Partitioning

Junpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. on Fundamentals Vol.E87-A ( No.12 ) 3075 - 3082 2004.12
FPGA-Based Reconfigurable Adaptive FEC

Kazunori Shimizu, Junpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. on Fundamentals Vol.E87-A ( No.12 ) 3036 - 3046 2004.12
A new correction for multiple comparisons in genome-wide case-control association studies based on haplotypes and diplotype configurations

Shogo Fujii, Toshimasa Yamazaki, Masao Yanagisawa, Yozo Ohnishi, Yusuke Nakamura, Naoyuki Kamatani

The 13th Takeda Science Foundation Symposium on Bioscience ポスターセッション 74 2004.12
レジスタ分散型アーキテクチャを対象とするフロアプランを考慮した高位合成手法

田中真, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会VLSI設計技術研究会 Vol.VLD82 127 - 132 2004.12
A Selective Scan Chain Reconfiguration through Run-Length Coding for Test Data Compression and Scan Power Reduction

Youhua Shi, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. on Fundamentals Vol.E87-A ( No.12 ) 3208 - 3215 2004.12
A Hybrid Dictionary Test Data Compression for Multiscan-Based Designs

Youhua Shi, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. on Fundamentals Vol.E87-A ( No.12 ) 3193 - 3199 2004.12
High-Level Power Optimization Based on thread Partitioning

Junpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. on Fundamentals Vol.E87-A ( No.12 ) 3075 - 3082 2004.12
FPGA-Based Reconfigurable Adaptive FEC

Kazunori Shimizu, Junpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. on Fundamentals Vol.E87-A ( No.12 ) 3036 - 3046 2004.12
A statistical clustering method for classifying the Invader assay genotyping data

Shuichi Takitoh, Shogo Fujii, Yoichi Mase, Naoyuki Kamatani, Toshimasa Yamazaki, Yozo Ohnishi, Yusuke Nakamura, Masao Yanagisawa

The American Society of Human Genetics 54th Annual Meeting ABSTRACTS ポスターセッション 511 2004.10
A sub-operation parallelism optimization algorithm in HW/SW partitioning for SIMD processor cores

Hideki Kawazu, Junpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proc. of SASIMI2004 483 - 490 2004.10
A statistical clustering method for classifying the Invader assay genotyping data

Shuichi Takitoh, Shogo Fujii, Yoichi Mase, Naoyuki Kamatani, Toshimasa Yamazaki, Yozo Ohnishi, Yusuke Nakamura, Masao Yanagisawa

The American Society of Human Genetics 54th Annual Meeting ABSTRACTS ポスターセッション 511 2004.10
A sub-operation parallelism optimization algorithm in HW/SW partitioning for SIMD processor cores

Hideki Kawazu, Junpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proc. of SASIMI2004 483 - 490 2004.10
Invader Assay法の出力結果の自動クラスタリング手法-最短距離法を初期値としたMCMCによる手法

間瀬洋一, 瀧藤修一, 藤井省吾, 鎌谷直之, 山崎敏正, 大西洋三, 中村祐輔, 柳澤政生

2004.10
フロアプランとタイミング制約に基づくレジスタ間データ転送を考慮した高位合成手法

田中真, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

情報処理学会DAシンポジウム2004 Vol.2004 ( No.8 ) 283 - 288 2004.07
IP再利用を考慮したシステムLSIにおけるプロセッサコア合成システム

友野直紀, 小原俊逸, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

情報処理学会DAシンポジウム2004 Vol.2004 ( No.8 ) 19 - 24 2004.07
A Hardware/Software Cosynthesis Algorithm for Processors with Heterogeneous Datapaths

Yuichiro Miyaoka, Nozomu Togawa, Masao yanagisawa, Tatsuo Ohtsuki

IEICE Trans. on Fundamentals Vol.E87-A ( No.4 ) 830 - 836 2004.04
SIMD型プロセッサコア向けHW/SW分割における内部演算並列度最適化手法

川津秀樹, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫

電子情報通信学会回路とシステム軽井沢ワークショップ 579 - 584 2004.04
A Hardware/Software Cosynthesis Algorithm for Processors with Heterogeneous Datapaths

Yuichiro Miyaoka, Nozomu Togawa, Masao yanagisawa, Tatsuo Ohtsuki

IEICE Trans. on Fundamentals Vol.E87-A ( No.4 ) 830 - 836 2004.04
携帯機器を対象としたJava動的コンパイラにおけるプロファイリングシステム

情報処理学会研究報告 2004-MBL-28 2004.03
ネットワークプロセッサ合成システム

電子情報通信学会技術報告 VLD2003-145 2004.03
HW/SW分割システムにおける仮想IP類推手法

電子情報通信学会技術報告 VLD2003-151 2004.03
面積制約を考慮したCAMプロセッサ最適化手法

電子情報通信学会技術報告 VLD2003-152 2004.03
インターリーブを考慮したReconfigurable Adaptive FEC

電子情報通信学会技術報告 VLD2003-151 2004.03
Packed SIMD型命令を持つプロセッサ合成システムのためのリターゲッタブルコンパイラ

電子情報通信学会技術報告 VLD2003-157 2004.03
An efficient algorithm/architecture codesign for image encoders

J Choi, N Togawa, T Ikenaga, S Goto, M Yanagisawa, T Ohtsuki

2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS 469 - 472 2004

　View Summary

We describe the optimization of a complex video encoder systems based on target architecture. We implemented the MPEG-4 encoder using hardware/software codesign approach, mapped together based on a target architecture. We proposed a target architecture template and an optimization methodology. In our design flow, we searched for a bottleneck module constraining the system. After investigating the computational complexity, quality, and the simplicity of algorithms, we chose the best algorithm for hardware implementation, and then mapped the selected algorithm onto the hardware with different architecture, what does the best architecture for the algorithm and which is the best architecture of components. We chose one of the architectures meet the constraints and also made tradeoffs among speed, chip area, and memory bandwidth for different architecture. The proposed system architecture was used to reduce the design decisions and iterations, provided flexible and scalable systems. The evaluations resulted in effective optimization of the motion estimation module and better tradeoffs that optimized the overall system.
Reducing test data volume for multiscan-based designs through single/sequence mixed encoding

Y Shi, S Kimura, N Togawa, M Yanagisawa, T Ohtsuki

2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS 445 - 448 2004

　View Summary

This paper presents a new test data compression technique for multiscan-based designs through dictionary-based encoding on the single or sequences scan-inputs. In spite of its simplicity, it achieves significant reduction in test data volume. Unlike some previous approaches on test data compression, our approach eliminates the need for additional synchronization and handshaking between the CUT and the ATE, so it is especially suitable to be integrated in a low cost test scheme for SoC test In addition in contrast to previous dictionary-based coding techniques, even for the CUT with a small number of scan chains, the proposed approach can achieve satisfied reduction in test data volume. Experimental results showed the proposed test scheme works particularly well for the large ISCAS'89 benchmarks.
Alternative run-length coding through scan chain reconfiguration for joint minimization of test data volume and power consumption in scan test

Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the Asian Test Symposium 432 - 437 2004

　View Summary

Test data volume and scan power are two major concerns in SoC test. In this paper we present an alternative run-length coding method through scan chain reconfiguration to reduce both test data volume and scan-in power consumption. The proposed method analyzes the compatibility of the internal scan cells for a given test set and then divides the scan cells into compatible classes. To extract the compatible scan cells we apply a heuristic algorithm by solving the graph coloring problem
and then a simple greedy algorithm is used to configure the scan chain for the minimization of scan power. Experimental results for the larger IS-CAS'89 benchmarks show that the proposed approach leads to highly reduced test data volume with significant power savings during scan test.

DOI
Experimental evaluation of high-level energy optimization based on thread partitioning

J Uchida, Y Miyaoka, N Togawa, M Yanagisawa, T Ohtsuki

PROCEEDINGS OF THE 2004 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1 AND 2 Vol.1 161 - 164 2004

　View Summary

This paper presents a thread partitioning algorithm for high-level synthesis systems which generate low energy circuits. In the algorithm, we partitions a thread into two sub-threads, one of which has RF and the other does not have RE The partitioned sub-threads need to be synchronized with each other to keep the data dependency of the original thread. Since the partitioned sub-threads have waiting time for synchronization, gated clocks can be applied to each sub-thread. We achieve 33% energy reduction when we apply our proposed algorithm to a JPEG encoder.
A reconfigurable adaptive FEC system for reliable wireless communications

K Shimizu, N Togawa, T Ikenaga, M Yanagisawa, S Goto, T Ohtsuki

PROCEEDINGS OF THE 2004 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1 AND 2 Vol.1 13 - 16 2004

　View Summary

This paper proposes a reconfigurable adaptive FEC system. For adaptive FEC schemes, we can implement an FEC decoder which is optimal for error correction capability t by taking the number of operations into consideration. Reconfiguring the optimal FEC decoder dynamically for each t allows us to maximize the throughput of each decoder within a limited hardware resource. Our system can reduce packet dropping rate more efficiently than conventional fixed hardware systems for a reliable transport protocol.
プロセッサにおける配線の再構成可能性の利用について

電子情報通信学会技術報告 VLD2003-114 2004.01
A Thread Partitioning Algorithm in Low Power High-Level Synthesis

Proc. of ASP-DAC 2004 2004.01
A Cosynthesis Algorithm for Application Specific Processors with Heterogeneous Datapaths

Proc. of ASP-DAC 2004 2004.01
Instruction Set and Functional Unit Synthesis for SIMD Processor Cores

Proc. of ASP-DAC 2004 2004.01
An efficient algorithm/architecture codesign for image encoders

J Choi, N Togawa, T Ikenaga, S Goto, M Yanagisawa, T Ohtsuki

2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS 469 - 472 2004

　View Summary

We describe the optimization of a complex video encoder systems based on target architecture. We implemented the MPEG-4 encoder using hardware/software codesign approach, mapped together based on a target architecture. We proposed a target architecture template and an optimization methodology. In our design flow, we searched for a bottleneck module constraining the system. After investigating the computational complexity, quality, and the simplicity of algorithms, we chose the best algorithm for hardware implementation, and then mapped the selected algorithm onto the hardware with different architecture, what does the best architecture for the algorithm and which is the best architecture of components. We chose one of the architectures meet the constraints and also made tradeoffs among speed, chip area, and memory bandwidth for different architecture. The proposed system architecture was used to reduce the design decisions and iterations, provided flexible and scalable systems. The evaluations resulted in effective optimization of the motion estimation module and better tradeoffs that optimized the overall system.
Reducing test data volume for multiscan-based designs through single/sequence mixed encoding

Y Shi, S Kimura, N Togawa, M Yanagisawa, T Ohtsuki

2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS 445 - 448 2004

　View Summary

This paper presents a new test data compression technique for multiscan-based designs through dictionary-based encoding on the single or sequences scan-inputs. In spite of its simplicity, it achieves significant reduction in test data volume. Unlike some previous approaches on test data compression, our approach eliminates the need for additional synchronization and handshaking between the CUT and the ATE, so it is especially suitable to be integrated in a low cost test scheme for SoC test In addition in contrast to previous dictionary-based coding techniques, even for the CUT with a small number of scan chains, the proposed approach can achieve satisfied reduction in test data volume. Experimental results showed the proposed test scheme works particularly well for the large ISCAS'89 benchmarks.
Alternative Run-Length.Coding through scan chain reconfiguration for joint minimization of test data volume and power consumption in scan test

YH Shi, S Kimura, N Togawa, M Yanagisawa, T Ohtsuki

13TH ASIAN TEST SYMPOSIUM, PROCEEDINGS 432 - 437 2004

　View Summary

Test data volume and scan power are two Major concerns in SoC test. In this paper we present an alternative run-length coding method through scan chain reconfiguration to reduce both test data volume and scan-in power consumption. The proposed method analyzes the compatibility of the internal scan cells for a given test set and then divides the scan cells into compatible classes. To extract the compatible scan cells we apply a heuristic algorithm by solving the graph coloring problem; and then a simple greedy algorithm is used to configure the scan chain for the minimization of scan power Experimental results for the larger ISCAS'89 benchmarks show that the proposed approach leads to highly reduced test data volume with significant power savings during scan test.

DOI
Experimental evaluation of high-level energy optimization based on thread partitioning

J Uchida, Y Miyaoka, N Togawa, M Yanagisawa, T Ohtsuki

PROCEEDINGS OF THE 2004 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1 AND 2 Vol.1 161 - 164 2004

　View Summary

This paper presents a thread partitioning algorithm for high-level synthesis systems which generate low energy circuits. In the algorithm, we partitions a thread into two sub-threads, one of which has RF and the other does not have RE The partitioned sub-threads need to be synchronized with each other to keep the data dependency of the original thread. Since the partitioned sub-threads have waiting time for synchronization, gated clocks can be applied to each sub-thread. We achieve 33% energy reduction when we apply our proposed algorithm to a JPEG encoder.
A reconfigurable adaptive FEC system for reliable wireless communications

K Shimizu, N Togawa, T Ikenaga, M Yanagisawa, S Goto, T Ohtsuki

PROCEEDINGS OF THE 2004 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1 AND 2 Vol.1 13 - 16 2004

　View Summary

This paper proposes a reconfigurable adaptive FEC system. For adaptive FEC schemes, we can implement an FEC decoder which is optimal for error correction capability t by taking the number of operations into consideration. Reconfiguring the optimal FEC decoder dynamically for each t allows us to maximize the throughput of each decoder within a limited hardware resource. Our system can reduce packet dropping rate more efficiently than conventional fixed hardware systems for a reliable transport protocol.
A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation

IEICE Trans. on Fundamentals Vol.E86-A, No.12 2003.12
A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions

IEICE Trans. on Fundamentals Vol.E86-A, No.12 2003.12
Real-time identification and tracking of Sperm whales in a multi-whale scenario

15th Marine Mammal Conf. 2003.12
A Parallel Algorithm of GENEHUNTER on Multi-Processors

The American Journal of Human Genetics Vol.73, No. 5 2003.11
ldlight:A Fast Haplotype Inference Algorithm for Large-Scale Unphased Diploid Genotype Data based on EM Algorithm and Graph Theoretical Data Structure

The American Journal of Human Genetics Vol.73, No.5 2003.11
プロセッサにおける配線の再構成可能性の利用について

第7回システムLSIワークショップ 2003.11
面積制約を考慮したCAMプロセッサ向けハードウェア/ソフトウェア協調設計手法

電子情報通信学会技術報告 VLD2003-89 2003.11
PGAを用いたReconfigurable Adaptive FECの実装と評価

電子情報通信学会技術報告 DSP2003-138 2003.10
公共空間におけるハンドオフ時間短縮を考慮したBluetoothネットワークの手順に関する一検討

電子情報通信学会技術報告 CQ2003-57 2003.09
分岐距離による再送手法選択式マルチキャスト

電子情報通信学会技術報告 CQ2003-58 2003.09
ハプロタイプ推定手法、推定装置、プログラム

特許番号2003-327943 2003.09
動的再構成可能システムによるAdaptive FECの実装

情報処理学会DAシンポジウム2003論文集 2003.07
畳み込み機構をもつFPGAのマッピング能力について

情報処理学会DAシンポジウム2003論文集 2003.07
冗長記述を利用したVHDLへの透かし埋め込み手法

情報処理学会DAシンポジウム2003論文集 2003.07
VDEC IPプロジェクトの成果とその利用について 1.プロセッサコアIP

情報処理学会DAシンポジウム2003論文集 2003.07
システムLSIをにおける定性的側面を考慮したハードウェア/ソフトウェア分割システム

情報処理学会DAシンポジウム2003論文集 2003.07
An Instruction-Set Simulator Generator for SIMD Processor Cores

Proc. of SASIMI2003 2003.04
不規則なデータパスを持つプロセッサのハードウェア/ソフトウェア協調合成手法

電子情報通信学会回路とシステム軽井沢ワークショップ論文集 2003.04
ネットワークスイッチング処理を対象としたCAMプロセッサ自動合成システム

電子情報通信学会回路とシステム軽井沢ワークショップ論文集 2003.04
高位合成システムにおけるスレッド分割を用いた低消費電力化手法

電子情報通信学会技術報告 VLD2002-221, pp.7-12 2003.03
SIMD型プロセッサコア向けHW/SW分割におけるSIMD型演算最適化手法

電子情報通信学会技術報告 VLD2002-222, pp.13-18 2003.03
閾値検索機能付きCAMプロセッサの最適化手法

電子情報通信学会技術報告 VLD2002-223, pp.19-24 2003.03
ldlight:A Fast Haplotype Inference Algorithm for Large-Scale Unphased Diploid Genotype Data based on EM Algorithm and Graph Theoretical Data Structure

The American Society of Human Genetics 2003
A Parallel Algorithm of GENEHUNTER on Multi-Processors

The American Society of Human Genetics 2003
A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories

IEICE Trans. on Fundamentals Vol.E86-A, No.5, pp.1082--1092 2003
An Instruction-Set Simulator Generator for SIMD Processor Cores

Proc. of SASIMI2003 pp.160--167 2003
A hardware/software partitioning algorithm for SIMD processor cores

Proc. of ASP-DAC 2003 /, 135-140 2003
A hardware/software partitioning algorithm for SIMD processor cores

Proc. of ASP-DAC 2003 pp.135--140 2003.01
MPEG-4コアプロファイル符号に対応した専用演算器を持つDSP

電子情報通信学会技術報告 VLD2002-134, pp.25-30 2003.01
ハードウェアIPの応答時間を考慮したプロセッサ合成システム

電子情報通信学会技術報告 VLD2002-136, pp.37-42 2003.01
ハードウェアIPの応答時間を考慮したプロセッサコアのハードウェア/ソフトウェア分割手法

電子情報通信学会技術報告 VLD2002-135, pp.31-36 2003.01
ldlight:A Fast Haplotype Inference Algorithm for Large-Scale Unphased Diploid Genotype Data based on EM Algorithm and Graph Theoretical Data Structure

The American Society of Human Genetics 2003
A Parallel Algorithm of GENEHUNTER on Multi-Processors

The American Society of Human Genetics 2003
A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories

IEICE Trans. on Fundamentals Vol.E86-A, No.5, pp.1082--1092 2003
An Instruction-Set Simulator Generator for SIMD Processor Cores

Proc. of SASIMI2003 pp.160--167 2003
A hardware/software partitioning algorithm for SIMD processor cores

Proc. of ASP-DAC 2003 pp.135--140 2003
An algorithm and a flexible architecture for fast block-matching motion estimation

IEICE Trans. on Fundamentals Vol.E85-A,No.12,pp.2603--2611 2002.12
A high-level energy-optimizing algorithm for system VLSIs with Gated Clocks

IEICE Trans. on Fundamentals Vol.E85-A,No12,pp.2655--2666 2002.12
閾値検索を持つCAMプロセッサの自動合成システム

電子情報通信学会技術報告 VLD2002-113, pp.187-192 2002.11
動的再構成可能システムによるプロトコルブースタの実装

電子情報通信学会技術報告 VLD2002-103, pp.127-132 2002.11
A Software/Hardware Codesign for MPEG Encoder

FIT2002 2002.09
仮想IP類推機構を有する動画像処理向けシステムVLSIのためのハードウェア/ソフトウェア分割システム

情報処理学会DAシンポジウム2002論文集 pp.173--178 2002.07
Packed SIMD型命令を持つプロセッサを対象としたハードウェア/ソフトウェア協調合成システムのための並列化コンパイル手法

電子情報通信学会技術報告 CAS2002-38, pp.79-84 2002.06
Packed SIMD型命令を持った画像処理プロセッサのためのハードウェア/ソフトウェア分割手法

電子情報通信学会技術報告 CAS2002-39, pp.85-90 2002.06
System-level Function and Architecture Codesign for Optimization of MPEG Encoder

ITC-CSCC'02 2002.06
Packed SIMD型命令を持つプロセッサを対象としたハードウェア/ソフトウェア協調合成システムのためのハードウェアユニット生成手法

情報処理学会論文誌 Vol.43,No.5,pp.1191-1201 2002.05
ディジタル信号処理向けプロセッサのためのシミュレータ生成手法

情報処理学会論文誌 Vol.43,No.5,pp.1202--1213 2002.05
High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks

IEICE Trans. on Fundamentals Vol.E85-A, No.4, pp.827-834 2002.04
DSPプロセッサコアのハードウェア/ソフトウェア協調合成システムのための演算語長縮小化手法

電子情報通信学会回路とシステム軽井沢ワークショップ論文集 pp.429-434 2002.04
Packed SIMD型演算器を持つディジタル信号処理プロセッサのためのリターゲッタブルシミュレータ生成手法

電子情報通信学会技術報告 VLD2001-162, pp.17-24 2002.03
IP再利用を考慮した動画像処理システムVLSI向けハードウェア/ソフトウェア分割設計支援システム

電子情報通信学会技術報告 VLD2001-164, pp.33-40 2002.03
制御処理ハードウェア高位合成のためのコントロールデータフローグラフ変形手法

電子情報通信学会技術報告 VLD2001-165, pp.41-48 2002.03
An algorithm of hardware unit generation for processor core synthesis with pasked SIMD type instructions

Proc. of APCCAS 2002 /, 2002

DOI
A high-level energy-optimizing algorithm for system VLSIs with Gated Clocks

IEICE Trans. on Fundamentals E85-A/12, 2655-2666 2002
An algorithm and a flexible architecture for fast block-matching motion estimation

IEICE Trans. on Fundamentals E85-A/12, 2603-2611 2002
A Software/Hardware Codesign for MPEG Encoder

FIT 2002 /, 2002
System-level Function and Architecture Codesign for Optimization of MPEG Encoder

ITC-CSCC'02 /, 2002
High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks

IEICE Trans. on Fundamentals E85-A/4, 827-834 2002
VLSI Architecture for a Flexible Motion Estimation with Parameters

ASP-DAC/VLSI Design 2002 /, 452-457 2002

DOI
システムVLSIのための高位面積/遅延/消費電力見積りに基づく低消費電力指向高位合成手法

電子情報通信学会技術報告 VLD2001-144, pp.93-100 2002.01
ロジック入力用レベルシフトコンパレータ設計考察

電子回路研究会技術報告 ETC-02-16, pp.13-17 2002.01
VLSI Architecture for a Flexible Motion Estimation with Parameters

Proc. ASP-DAC 2002 pp.452-457 2002.01

DOI
An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions

Y. Miyaoka, J. Choi, N. Togawa, M. Yanagisawa, T. Ohtsuki

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS 1 171 - 176 2002

　View Summary

The authors consider the synthesis of a processor core with SIMD instructions by a hardware/software cosynthesis system. The system is required to configure functional units executing SIMD instructions and obtain the area and delay of the functional units to evaluate the synthesized processor core. This paper proposes a hardware unit generation algorithm for a hardware/software cosynthesis system of processors with SIMD instructions. Given a set of instructions to be executed by a hardware unit and constraints for area and delay of the hardware unit, the proposed algorithm extracts a set of subfunctions to be required by the hardware unit and generates more than one architecture candidates for the hardware unit. The algorithm also outputs the estimated area and delay of each of the generated hardware units. The execution time of the proposed algorithm is very short and thus it can be easily incorporated into the processor core synthesis system. Experimental results demonstrate effectiveness and efficiency of the algorithm.

DOI
An algorithm of hardware unit generation for processor core synthesis with pasked SIMD type instructions

Proc. of Int. Conf. on Computer-Aided Design 2002

DOI
A high-level energy-optimizing algorithm for system VLSIs with Gated Clocks

IEICE Trans. on Fundamentals Vol.E85-A, No.12, pp.2655--266 2002
An algorithm and a flexible architecture for fast block-matching motion estimation

IEICE Trans. on Fundamentals Vol.E85-A,No.12, pp.2603--2611 2002
A Software/Hardware Codesign for MPEG Encoder

FIT2002 2002
System-level Function and Architecture Codesign for Optimization of MPEG Encoder

ITC-CSCC'02 2002
ディジタル信号処理向けプロセッサのためのシミュレータ生成手法

情報処理学会論文誌 43/5, 1202-1213 2002
Packed SIMD型命令を持つプロセッサを対象としたハードウェア/ソフトウェア協調合成システムのためのハードウェアユニット生成手法

情報処理学会論文誌 43/5, 1191-1201 2002
メモリとのインターフェース仕様を考慮した演算語長縮小に基づくプロセッサコアのハードウェア/ソフトウェア協調合成システム

電子情報通信学会技術報告 vol.VLD2001-11, pp.127-132 2001.11
Area and Delay Estimation in Hardware/Software Cosynthesis for Digital Signal Processor Cores

IEICE Trans. on Fundamentals vol.E84-A, No.11, pp.2639--264 2001.11
A New Hardware/Software Partitioning Algorithm for DSP Processor Cores with Two Types of Register Files

IEICE Trans. on Fundamentals vol.E84-A, No.11, pp.2802-2807 2001.11
ディジタル信号処理向けプロセッサのためのシミュレータ生成手法

情報処理学会DAシンポジウム2001論文集 pp.137-142 2001.07
Packed SIMD型命令を持つプロセッサを対象としたハードウェア/ソフトウェア協調合成システムのためのハードウェアユニット生成手法

情報処理学会DAシンポジウム2001論文集 pp.223-228 2001.07
ディジタル信号処理向けプロセッサコアのPacked SIMD型ハードウェア生成手法

電子情報通信学会技術報告 vol.VLD2001-2, pp.7-14 2001.05
An Area/Time Optimizing Algorithm in High-Level Synthesis of Control-Based Hardwares

IEICE Trans. on Fundamentals vol.E84-A, No.5, pp.1166-1176 2001.05
Gated Clockによる低消費電力化システムVLSIの高位面積/遅延/消費電力見積もり

回路とシステム軽井沢ワークショップ論文集 pp.591-596 2001.04
ソフトIPのための保護アルゴリズム

回路とシステム軽井沢ワークショップ論文集 pp.411-416 2001.04
A Hardware/Software Cosynthesis System for CAM Processors

Proc. of Synthesis and System Integration of Mixed Technologies (SASIMI2001) pp.37-44 2001.04
システムLSIを対象としたハードウェア/ソフトウェア分割システム

電子情報通信学会VLSI設計技術研究会技術報告 vol.VLD2000, no.140, pp.37-42 2001.03
画像処理を対象としたPacked SIMD型命令セットを持つプロセッサのハードウェア/ソフトウェア協調合成システムにおける並列化Cコンパイラ

電子情報通信学会VLSI設計技術研究会技術報告 vol.VLD2000,no.139, pp.31-36 2001.03
制御処理ハードウェアの高位合成システムにおける面積/遅延見積もり手法

情報処理学会システムLSI設計技術研究会研究報告 vol.SLDM2001, no.100, pp.25-32 2001.02
RC等価回路に基づくクロストーク低減配線手法

情報処理学会システムLSI設計技術研究会研究報告 vol.SLDM2001, no.100, pp.17-24 2001.02
Area/Delay Estimation for Digital Signal Processor Cores

Proc. of ASP-DAC 2001 pp.156-161 2001.01

DOI
A New Hardware/Software Partitioning Algorithm for DSP Processor Cores with Two Types of Register Files

IEICE Trans. On Fundamentals E84-A/11, 2802-2807 2001
Area and Delay Estimation in Hardware/Software Cosynthesis for Digital Signal Processor Cores

IEICE Trans. on Fundamentals E84-A/11, 2639-2647 2001
An Area/Time Optimizing Algorithm in High-Level Synthesis of Control-Based Hardwares

IEICE Trans. on Fundamentals E84-A/5, 1166-1176 2001
A Hardware/Software Cosynthesis System for CAM Processors

Proc. SASIMI 2001 /, 37-44 2001
Area/Delay Estimation for Digital Signal Processor Cores

Proc. of ASP-DAC 2001 /,156-161 2001

DOI
発見的算法と分枝限定法を用いた計算時間予測に基づくリソースバインディング手法

電子情報通信学会VLSI設計技術研究会技術報告 vol.VLD2000, no.119, pp.17-24 2001.01
FPGAを用いた動的再構成可能システムを対象とするスケジューリング手法

電子情報通信学会VLSI設計技術研究会技術報告 vol.VLD-2000, no.115, pp.33-40 2001.01
パラメータ付けされた動的再構成可能システムとその応用

電子情報通信学会VLSI設計技術研究会技術報告 vol.VLD-2000, no.114, pp.25-32 2001.01
Area/Delay Estimation for Digital Signal Processor Cores

Proc. of ASP-DAC 2001 pp.156-161 2001.01

DOI
A Hardware/Software Partitioning Algorithm for Digital Signal Processor Cores with Two Types of Register Files

Proc. IEEE Asia-Pacific Conf. on Circuits and Systems (APCCAS2000) pp.544-547 2000.12
CAM Processor Synthesis Based on Behavioral Descriptions

IEICE Trans. Fundamentals vol.E83-A, no.12, pp.2464-2473 2000.12
A Hardware/Software Partitioning Algorithm for Digital Signal Processor Cores with Two Types of Register Files

Proc. IEEE Asia-Pacific Conf. on Circuits and Systems (APCCAS2000) pp.544-547 2000.12
CAM Processor Synthesis Based on Behavioral Descriptions

IEICE Trans. Fundamentals vol.E83-A, no.12, pp.2464-2473 2000.12
CAMプロセッサを対象とするハードウェア/ソフトウェア協調合成システム

電子情報通信学会VLSI設計技術研究会技術報告 vol.2000, no.84, pp.89-94 2000.11
機能メモリを使用したプロセッサの面積/遅延見積り手法

電子情報通信学会VLSI設計技術研究会技術報告 vol.2000, no.83, pp.83-88 2000.11
制御処理ハードウェアの高位合成のための高速な面積/時間最適化アルゴリズム

情報処理学会DAシンポジウム2000論文集 pp.27-32 2000.07
A High Performance Embedded Wavelet Video Coder

IEICE Trans. Fundamentals vol.E83-A, no.6, pp.979-986 2000.06
A High Performance Embedded Wavelet Video Coder

IEICE Trans. Fundamentals vol.E83-A, no.6, pp.979-986 2000.06
A Behavioral Synthesis System for Processors with Content Addressable Memories

Proc. Synthesis and System Integration of Mixed Technologies (SASIMI2000) pp.56-63 2000.04
システムVLSIの動作合成におけるレイアウト面積・遅延見積もり手法

第13回回路とシステム(軽井沢)ワークショップ論文集 pp.125-130 2000.04
A Behavioral Synthesis System for Processors with Content Addressable Memories

Proc. Synthesis and System Integration of Mixed Technologies (SASIMI2000) pp.56-63 2000.04
歩行者を対象とした地図データ配信システムにおける専用プロセッサの設計と評価

電子情報通信学会VLSI設計技術研究会技術報告 VLD99-267, pp.15-22 2000.03
FPGAを用いた動的再構成可能システムと暗号化アルゴリズム

電子情報通信学会VLSI設計技術研究会技術報告 VLD99-109, pp.7-14 2000.03
A Hardware/Software Cosynthesis System for Digital Signal Processor Cores with Two Types of Register Files

IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences E83-A; 3 2000.03
CAM Processor Synthesis Based on Behavioral Descriptions

IEICE Trans. Fundamentals E83-A/12,2464-2473 2000
A Hardware/Software Partitioning Algorithm for Digital Signal Processor Cores with Two Types of Register Files

Proc. IEEE Asia-Pacific Conf. on Circuits and Systems(APCCAS2000) /,544-547 2000
A High Performance Embedded Wavelet Video Coder

IEICE Trans. Fundamentals E83-A/6,979-986 2000
A Behavioral Synthesis System for Processors with Content Addressable Memories

Proc. Synthesis and System Integration of Mixed Technologies(SASIMI2000) /,56-63 2000
A Hardware/Software Cosynthesis System for Digital Signal Processor Cores with Two Types of Register Files

IEICE Transactions on Fundamentals of Electronics,Communications and Computer Sciences E 83-A/3,442-451 2000
An area/time optimizing algorithm in high-level synthesis for control-based hardwares

Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC /,309-312 309 - 312 2000

　View Summary

This paper proposes an area/time optimizing algorithm in high-level synthesis for control-based hardwares. Given a call graph whose node corresponds to a control flow of an application program, the algorithm generates a set of state-transition graphs which represents the input call graph under area and timing constraint. In the algorithm, first state-transition graphs which satisfy only timing constraint are generated and second they are transformed so that they can satisfy area constraint. Since the algorithm is directly applied to control-flow graphs, it can deal with control flows such as bit-wise processes and conditional branches. Further, the algorithm synthesizes more than one hardware architecture candidates from a single call graph for an application program. Designers of an application program can select several good hardware architectures among candidates depending on multiple design criteria. Experimental results for several control-based hardwares demonstrate effectiveness and efficiency of the algorithm. © 2000 IEEE.

DOI
An Area/Time Optimizing Algorithm in High-Level Synthesis for Control-Based Hardwares

Proc. of ASP-DAC 2000 pp.309-312 2000.01
2種類のレジスタファイルを持つディジタル信号処理向けプロセッサのハードウェア/ソフトウェア分割手法

電子情報通信学会VLSI設計技術研究会技術報告 VLD99-76, pp.9-16 1999.11
ディジタル信号処理向けプロセッサコアの面積/遅延見積り手法

電子情報通信学会VLSI設計技術研究会技術報告 VLD99-75, pp.1-8 1999.11
A Hardware/Software Cosynthesis System for Digital Signal Processor Cores

IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences E82-A; 11, pp.2325-2337 1999.11
制御処理ハードウェアの高位合成システムのための面積/時間最適化アルゴリズム

電子情報通信学会VLSI設計技術研究会技術報告 VLD99-66, pp.15-22 1999.09
A Simultaneous Placement and Global Routing Alogorithm for FPGAs with Power Optimization

Journal of Circuits, Systems, and Computers 9; 1&2, pp.99-112 1999.09

DOI
Fast Motion Esitimation Scheme for Video Coding Using Feature Vector Matching and Motion Vector's Correlations

Journal of Circuits, Systems, and Computers 9; 1&2, pp.67-82 1999.09

DOI
制御処理を主体としたハードウェア記述生成手法

情報処理学会DAシンポジウム'99論文集 pp.195-200 1999.07
制御処理を主体としたハードウェアを対象とする高位合成システムとその適用

情報処理学会DAシンポジウム'99論文集 pp.189-194 1999.07
2種類のレジスタファイルを持ったディジタル信号処理向けプロセッサのハードウェア/ソフトウェア協調合成システム

電子情報通信学会回路とシステム(軽井沢)ワークショップ論文集 pp.115-120 1999.04
分枝限定に基づく最適解を保証するリソースバインディング手法

情報処理学会論文誌 40; 4, pp.1565-1577 1999.04
FPGAを用いた動的再構成可能システムとその応用

電子情報通信学会VLSI設計技術研究会 98;143,pp.17-24 1999.03
A Depth-Constrained Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Structured LUTs

IEICE Trans. on Fundamentals E82-A;3,pp.473-482 1999.03
2種類のレジスタファイルを持ったディジタル信号処理向けプロセッサのハードウェア/ソフトウェア協調合成システムとその並列化コンパイラ

電子情報通信学会フォールトトレラントシステム研究会 98;132,pp.71-78 1999.02
A Hardware/Software Cosynthesis System for Digital Signal Processor

IEICE Transactions on Fundamentals of Electronics,Communications and Computer Sciences E 82-A/11,2325-2337 1999
A Simultaneous Placement and Global Routing Algorithm for FPGAs with Power Optimization

Journal of Circuits,System,and Computers 9/1 & 2,99-112 1999

DOI
Fast Motion Estimation Scheme for Video Coding Using Feature Vector Matching and Motion Vector's Correlations

Journal of Circuits,Systems, and Computers 9/1 & 2,67-82 1999

DOI
An Optimal Binding Algorithm in High -level Synthesis System for Digital Signal Processing

Transaction of Information Processing Society of Japan 40/4,1565-1577 1999
A Depth-Constrained Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Structured LUTs

Transaction of Institute of Electronics, Information, and Communication Engineers E82-A/3,473-482 1999
A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing

Proceedings of Asia and South Pacific Design Automation Conference /,335-338 1999
A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing

Proc. ASP-DAC'99 pp.335-338 1999.01
分枝限定に基づく最適解を保証するリソースバインディング手法

情報処理学会論文誌 40/4,1565-1577 1999
FPGAのマクロブロックを対象とした配置概略配線同時処理手法

電子情報通信学会VLSI設計技術研究会 98;115,pp.123-130 1998.12
A High-Level Synthesis System for Digital Signal Processing Based on Data-Flow Graph Enumeration

IEICE Trans. on Fundamentals E81-A;12,pp.2563-2575 1998.12
A Simultaneous Placement and Global Routing Algorithm for FPGAs with Power Optimization

Proc. APCCAS'98 pp.125-128 1998.11
機能メモリを使用したプロセッサを対象とするハードウェア/ソフトウェア協調合成システム

電子情報通信学会コンピュータシステム研究会 98;85,pp.31-38 1998.09
Maple-opt: A Performance-Oriented Simultaneous Technology Mapping,Placement, and Global Routing Algorithm for FPGA's

IEEE Trans. on CAD of IC and Systems 17;9,pp.803-818 1998.09

DOI
最適解を保証するリソースバインディング手法

情報処理学会DAシンポジウム'98論文集 pp.245-250 1998.07
A Fast Scheduling Algorithm Based on Gradual Time-Frame Reduction for Datapath Synthesis

IEICE Trans. on Fundamentals E81-A;6,pp.1231-1241 1998.06
分布定数回路の遅延感度解析に基づくクロック配線最適化手法

情報処理学会設計自動化研究会 88;4,pp.21-28 1998.05
An FPGA Layout Reconfiguration Algorithm Based on Global Routes for Engineering Changes in System Design Specifications

IEICE Trans. on Fundamentals E81-A;5,pp.873-884 1998.05
ツリー状に接続されたLUTを対象とした深さ制約付きテクノロジーマッピング手法

電子情報通信学会回路とシステム(軽井沢)ワークショップ論文集 pp.343-348 1998.04
パイプラインプロセッサのハードウェア記述自動生成手法

電子情報通信学会VLSI設計技術研究会 97;117,pp.33-40 1998.03
ディジタル信号処理向けプロセッサの自動合成システムにおける並列化コンパイラ

電子情報通信学会VLSI設計技術研究会 97;116,pp.25-32 1998.03
ディジタル信号処理向けプロセッサのハードウェア/ソフトウェア協調合成システム

電子情報通信学会VLSI設計技術研究会 97;115,pp.17-24 1998.03
An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays

Proc. ASP-DAC'98 pp.519-526 1998.02
A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs

Proc. ASP-DAC'98 pp.265-274 1998.02
A High-Level Synthesis System for Digital Signal Processing Based on Data-Flow Graph Enumeration

Transaction of Institute of Electronics, Information, and Communication Engineers E81-A/12,2563-2575 1998
A Simultaneous Placement anf Global Routing Algorithm for FPGAs with Power Optimization

Proceedings of Asia-Pacific Conference on Circuits and Systems /,125-128 1998
Maple-opt : A Performance-Oriented Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGA's

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17/9,803-818 1998

DOI
A Fast Scheduling Algorithm Based on Gradual Time-Frame Reduction for Datapath Synthesis

Transaction of Institute of Electronics, Information, and Communication Engineers E81-A/6,1231-1241 1998
An FPGA Layout Reconfiguration Algorithm Based on Global Routes for Engineering Changes in System Design Specifications

Transaction of Institute of Electronics, Information and Communication Engineers E81-A/5,873-884 1998
An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays

Proceedings of Asia and South Pacific Design Automation Conference /,519-526 1998
A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs

Proceedings of Asia and South Pacific Design Automation Conference /,265-274 1998
ツリー構造を持つ論理ブロックを対象としたテクノロジマッピング手法

電子情報通信学会VLSI設計技術研究会 97;104,pp.29-36 1997.12
VDEC用ライブラリの開発とそれを利用したVLSI設計事例

第1回システムLSI琵琶湖ワークショップ pp.383-387 1997.11
連想メモリを搭載したハードウェアエンジンによる故障回路並列故障シミュレーションの高速化手法

情報処理学会設計自動化研究会 97;103,pp.81-88 1997.10
Fast Scheduling and Allocation Algorithms for Entropy CODEC

IEICE Trans. on Information and Systems E80-D;10,pp.982-992 1997.10
A Performance-Oriented Simultaneous Placement and Global Routing Algorithm for Transport-Processing FPGAs

IEICE Trans. on Fundamentals E80-A;10,pp.1795-1806 1997.10
ディジタル信号処理を対象とした高位合成システムにおける高速なスケジューリングアルゴリズム

情報処理学会DAシンポジウム'97論文集 pp.167-172 1997.07
商用ツールを利用したLSI設計用ライブラリの開発

情報処理学会DAシンポジウム'97論文集 pp.25-30 1997.07
スケッチレイアウトシステムにおけるBGAパッケージ配線手法

回路実装学会誌 12;4,pp.241-246 1997.07

DOI
FPGAを対象とした低消費電力指向配置・概略配線同時処理手法

電子情報通信学会VLSI設計技術研究会 97;42,pp.191-198 1997.06
システム設計仕様の部分的変更を実現する概略配線径路を考慮したFPGA向けレイアウト再構成手法

電子情報通信学会回路とシステム軽井沢ワークショップ論文集 pp.187-192 1997.04
スケッチレイアウトシステムにおけるBGAパッケージ配線手法

電子情報通信学会VLSI設計技術研究会 VLD96;106 1997.03
接続コストの最小化を目的とした高速アロケーション手法

電子情報通信学会VLSI設計技術研究会 VLD96;96 1997.03
A Circuit Partitioning Algorithm with Path Delay Constraints for Multi-FPGA Systems

電子情報通信学会英文論文誌 E80-A;3 1997.03
Fast Scheduling and Allocation Algorithms for Entropy CODEC

Transaction of Institute of Electronics, Information and Communication Engineers E80-D/10,982-992 1997
A Performance-Oriented Simultaneous Placement and Global Routing Algorithm for Transport-Processing FPGAs

Transaction of Institute of Electronics, Information and Communication Engineers E80-A/10,1795-1806 1997
A BGA Package Routing Algorithm on Sketch Layout System

The Journal of Japan Institute for Interconnecting and Packaging Electronic Circuits 12/4,241-246 1997

DOI
A Circuit Partition Algorithm with Path Delay Constraints for Multi-FPGA Systems

Transaction of Institute of Electronics, Information, and Communication Engineers E80-A/3,494-505 1997
A Simultaneous Placement and Global Ronting Algorithm with Path Length Constraints for Transport-Processing FPGAs

Proceedings of Asia and South Pacific Design Automation Conference /,569-578 1997
A Simultaneous Placement and Global Routing Algorithm with Path Length Constraints for Transport-Processing FPGAs

Proc. of ASP-DAC'97 1997.01
スケッチレイアウトシステムにおけるBGAパッケージ配線手法

回路実装学会誌 12/4,241-246 1997

DOI
Dharmaアーキテクチャに基づくFPGAチップの試作

マイクロエレクロトニクス研究開発機構第15回研究交流会 1996.12
Simultaneous Placement and Global Routing for Transport-Processing FPGA Layout

電子情報通信学会英文論文誌 E79-A;12 1996.12
Scheduling and Allocation Algorithm for Entropy CODEC

Proc. of SASIMI'96 1996.11
A Performance-Oriented Circuit Partitioning Algorithm with Logic-Block Replication for Multi-FPGA Systems

Proc. of APCCAS'96 1996.11
パス長制約を考慮した通信処理用FPGA向け配置・概略配線同時処理手法

電子情報通信学会VLSI設計技術研究会 VLD96;56 1996.10
スケッチレイアウトシステムにおける配線可能性検証手法

回路実装学会誌 11;6 1996.09

DOI
柔軟性の高いレイアウトシステムのためのデータ表現方式

回路実装学会誌 11;6 1996.09

DOI
高位合成システムを用いた画像符号化アルゴリズムのハードウェア合成手法

情報処理学会DAシンポジウム'96論文集 1996.08
データパス設計を対象とした高位合成システム

情報処理学会DAシンポジウム'96論文集 1996.08
通信処理用FPGAを対象とした配置・概略配線同時処理手法

情報処理学会設計自動化研究会 DA96;51 1996.05
プリント配線板を対象とした二層均等化スペーシング手法

情報処理学会設計自動化研究会 DA96;51 1996.05
パス遅延制約を考慮したマルチFPGA用回路分割手法

電子情報通信学会回路とシステム軽井沢ワークショップ論文集 1996.04
イタレーション間データ依存制約を考慮したパイプライン化DSPスケジューリング手法

電子情報通信学会VLSI設計技術研究会 VLD95;134 1996.03
条件分岐構造を持つコントロールデータフローグラフの時間制約スケジューリング手法

電子情報通信学会VLSI設計技術研究会 VLD95;133 1996.03
A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints

電子情報通信学会英文論文誌 E79-A;3 1996.03
エントロピーCODECの高位合成手法

情報処理学会設計自動化研究会 DA96;16 1996.02
Simultaneous Placement and Global Ronting for Transport-Processing FPGA Layout

Transaction of Institute of Electronics, Information, and Communication Engineers E79-A/12,2140-2150 1996
Scheduling and Alloeation Algorithm for Entropy CODEC

Proceedings of SASIMI'96 /,149-154 1996
A Performance-Oriented Circuit Partitioning Algorithm with Logic-Block Replication for Mults-FPGA Systems

Proceedings of Asia-Pacific Conference on Circuits and Systems /,294-297 1996
A Rontability Cheeking Method in Sketch Layout System

The Journal of Japan Institute for Interconnecting and Packaging Electronic Circuits 11/6,416-422 1996

DOI
A Data Representing Method for Flexible Layout Systems

The Journal of Japan Institute for Interconnecting and Packaging Electronic Circuits 11/6,408-415 1996

DOI
A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints

Transaction of Institute of Electronics, Information, and Communication Engineers E79-A/3,321-329 1996
スケッチレイアウトシステムにおける配線可能検証手法

回路実装学会誌 11/6,416-422 1996

DOI
柔軟性の高いレイアウトシステムのためのデータ表現方式

回路実装学会誌 11/6,408-415 1996

DOI
A CAM-Based Parallel Fault, Simulation Algorithm with Minimal Storage Size

電子情報通信学会英文論文誌 E78-A;12 1995.12
A Circuit Partitioning Algorithm with Replication Capability for Multi-FPGA Systems

電子情報通信学会英文論文誌 E78-A;12 1995.12
パイプライン化DSPのデータパス・スケジューリング手法-動作記述からSFL記述の自動合成

第7回パルテノン研究会 1995.11
リソースアロケーションを考慮したデータパス・スケジューリング手法

電子情報通信学会VLSI設計技術研究会 VLD95;97 1995.10
動作記述からのデータフローグラフ生成手法

電子情報通信学会VLSI設計技術研究会 VLD95;96 1995.10
ASP-DAC'95 Best Paper Award

1995.08
Maple-opt: A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Performance Optimization

Proc. of ASP-DAC'95 1995.08
A CAM Based Parallel Fault Simulation Algorithm with Minimal Storage Size

Proc. of SASIMI'95 1995.08
I/Oピン数最小化を目的とした回路分割手法

Proc. of FPGA/PLD Design Conference 1995.07
マルチFPGAを対象とした階層的回路分割手法

電子情報通信学会回路とシステム研究会 VLD95;40 1995.06
Maple-opt: パス遅延制約を考慮したFPGA用テクノロジーマッピング・配置・概略配線同時処理手法

電子情報通信学会軽井沢ワークショップ論文集 1995.04
Maple-opt : A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with performance Optimization

Proceedings of Asia and South Pacific Design Automation Conference /,319-327 1995
A CAM Based Parallel Fault Simulation Algorithm with Minimal Storage Size

Proceedings of SASIMI '95 /,136-143 1995
A Circuit Patitioning Algorithm with Replication Capability for Multi-FPGA Systems

Transaction of Institute of Electronics, Information, and Communication Engineers E78-A/12,1765-1776 1995
A CAM-Based Parallel Fault Simulation Algorithm with Minimal Storage Size

Transaction of Institute of Electronics, Information, and Communication Engineers E78-A/12,1755-1764 1995
Maple : A Simultaneous technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays

Transaction of Institute of Electronics, Information, and Communication Engineers E77-A/12,2028-2038 1994
Maple : A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays (jointly worked)

Transaction of Institute of Electronics, Information, and Communication Engineers E77-A/12,2028-2038 1994
A Top-Down Hierarchical Routing Algorithm for FPGAs with Long-Lines

Transaction of Information Processing Society of Japan 35/12,2785-2796 1994
Maple : A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays (jointly worked)

Proceedings of Asia-Pacific Conference on Circuits and Systems /,554-559 1994
Maple : A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays (jointly worked)

Proceedings of International Conference on Computer-Aided Design /,156-163 1994
A Simultaneous Placement and Global Routing Algorithm for FPGAs (jointly worked)

Proceedings of International Symposium on Circuits and Systems 1/,482-485 1994
WA Timing-Driven Simultaneous Placement and Global Routing Algorithm for Field-Programmable Gate Arrays

Transaction of Information Processing Society of Japan 35/5,934-944 1994
A Simultaneous Placement and Global Routing Algorithm for Symmetric FPGAs (jointly worked)

Proceedings of International Workshop on Field-Programmable Gate Arrays 8/, 1994
ロングラインに対応した階層的FPGA配線手法(共著)

情報処理学会論文誌 35/12,2785-2796 1994
パス長制約を考慮したFPGA配置概略配線同時処理手法 (共著)

情報処理学会論文誌 35/5,934-944 1994
A Simultaneous Placement and Global Routing Algorithm for Field-Programmable Gate Arrays (jointly worked)

Proceedings of International Conference on VLSI and CAD /,205-210 1993
A Top-Down Hierarchical Global and Detailed Routing Algorithm for Field-Programmable Gate Arrays

Transaction of Institute of Electronics, Information, and Communication Engineers J76-A/9,1312-1321 1993
Chip Compaction Method with Automatic Jog Insertion

Transaction of Institute of Electronics, Information, and Communication Engineers J76-A/7,968-978 1993
Optimal Constraint Graph Generation Algorithm for Layout Compaction Using Enhanced Plane-Sweep MEthod (jointly worked)

Transaction of Institute of Electronics, Information, and Communication Engineers E76-A/4,507-512 1993
A Multi-Layer Gridless Routing Method Based on Line-Expansion Algorithm

Transaction of Institute of Electronics, Information, and Communication Engineers J76-A/3,410-420 1993
A Computer NetworkCharacterization in terms of Partial k-trees

Memoirs of the School of Science & Engineering, Waseda University /56,75-86 1993
FPGAを対象とした階層的概略詳細配線手法 (共著)

電子情報通信学会論文誌A J76-A/9,1312-1321 1993
ジョグ挿入を伴ったチップコンパクション手法(共著)

電子情報通信学会論文誌A J76-A/7,968-978 1993
線分展開法を拡張した多層グリッドレス配線手法(共著)

電子情報通信学会論文誌A J76-A/3,410-420 1993
A CAM-Based Hardware Implementation of the Improved Line Search Algorithm

Transaction of Institute of Electronics, Information, and Communication Engineers J75-A/12,1837-1848 1992
A Line-and Rectangle-Expansion Routing Algorithm for Multi-Layer Interconnection (jointly worked)

Proceedings of Asia-Pacific Conference on Circuits and Systems /,356-361 1992
Top-Down Hierarchical Global and Detailed Routing Algorithm for Field-Programmable Gate Arrays (jointly worked)

Proceedings of Asia-Pacific Conference on Circuits and Systems /,340-345 1992
An Efficient Spacing Method for Macro-Cell Layouts (jointly worked)

Proceedings of Asia-Pacific Conference on Circuits and Systems /,283-288 1992
An Optimal Chip Compaction Method Based on Shortest Path Algorithm with Automatic Jog Insertion (jointly worked)

Proceedings of International Conference on Computer-Aided Design /,162-165 1992
改良線分探索法の連想プロセッサを用いた一実装手法(共著)

電子情報通信学会論文誌A J75-A/12,1837-1848 1992
A VLSI Geometrical Design Rule Verification Acceleroted by CAM-Based Hardware Engine

TRANSACTION OF INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS Oct-74 1991
A Hardware System for Interactive Routing with Reroute Feect Index Function

JOURNAL OF JAPAN INSTITUTE OF PRINTED CIRCUITE 5月2日 1990

DOI
再配線評価指標算出機能をもった対話型配線ハードウェアシステム

プリント回路学会誌「サーキットテクノロジ」 5月2日 1990

DOI
An Improved Line Search Algorithm

TRANSACTION OF INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS Feb-72 1989
A Fast Intelligent Channel Spacer with Automatic Jog Insertion and Via Reduction

TRANSACTION OF INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS Feb-72 1989
A Fast Minimum Width/Space Verification Algorithm Based on an Enhanced Plane-Sweep Method.

TRANSACTION OF INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS Feb-72 1989
A Minimum Bend Path Algorithm Based on a Tile Plane

TRANSACTION OF INFORMATION PROCESSING SOCIETY OF JAPAN Feb-30 1989
線分探索法の改良とその評価

電子情報通信学会論文誌 Feb-72 1989
ビア削除を伴った高速多機能チャンネルスペーサ

電子情報通信学会論文誌 Feb-72 1989
拡張平面掃引法に基づく最小幅/間隔検証手法

電子情報通信学会論文誌 Feb-72 1989
タイル平面に基づく最小曲がり径路探索アルゴリズム

情報処理学会論文誌 Feb-30 1989
Application of computational geometry to VLSI layout pattern design.

INTEGRATION the VLSI journal 2005/3/4 1987
Gridless Routers-Two-Layer Routing Methods without Using Grid Graph-

TRANSACTION OF INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS May-69 1986
グリッドレス・ルーター格子を用いない二層配線径路探索手法-

電子通信学会論文誌 May-69 1986
Minimum Partitioning of Rectilinear Regions

TRANSACTION OF INFORMATION PROCESSING SOCIETY OF JAPAN 5月24日 1983
An Algorithm for Resizing Polygonal Regions and Its Applications to LSI Mask Pattern Design

TRANSACTION OF INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS Dec-66 1983
複合長方形領域の最小分割

情報処理学会論文誌 5月24日 1983
図形整形アルゴリズムとそのLSIパターン設計への応用

電子情報通信学会論文誌 Dec-66 1983
A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories

IEICE Trans. on Fundamentals Vol.E86-A

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Books and Other Publications

最新VLSIの開発設計とCAD(共著)

ミマツデータシステム 1994

Awards

電気通信普及財団賞

2011.03
海洋調査技術学会技術賞

2008
Best Paper Award, Asia South Pacific Design Automation Conference

1995
安藤博記念学術奨励賞

1990
丹羽記念賞

1988

Research Projects

Development of Education-Microprocessor for Computer Engineering and VLSI Engineering.
柔軟性の高いLSIレイアウト設計手法に関する研究

科学研究費助成事業(早稲田大学) 科学研究費助成事業(奨励研究(A))
柔軟性の高いLSIレイアウト設計手法に関する研究

科学研究費助成事業(早稲田大学) 科学研究費助成事業(奨励研究(A))
Development of Educational Microprocessors for Computer Science Education
Development of Curriculums for Education of VLSI System Design.
An FPGA System for Digital Signal Processing and CAD tools
Development of AUV for Whale following
Reconfigurable LSI Systems for Statistical Genetic Algorithms
Development of autonomous acoustic observation system using click sounds emitted by small cetacean and field experiments
Bioinformatics in silico by the Unification of Symobols and Patterns
Design Methods for Crypto LSI Implementations and Testing
故障利用攻撃を検出できる耐タンパー暗号回路設計に関する研究

科学研究費助成事業(早稲田大学) 科学研究費助成事業(基盤研究(C))
ロバスト超低電圧回路設計技術に関する研究

科学研究費助成事業(早稲田大学) 科学研究費助成事業(基盤研究(C))
Synthesis tools for Adaptive Devices
Genome Analysis
SoC Design and CAD

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Presentations

Suspicious Timing Error prediction with In-Cycle Clock Gating

Presentation date： 2013.03
Scan-Based Attack Against DES Cryptosystems Using Scan Signatures

Presentation date： 2012.12
Weighted Adders with Selector Logics for Super-resolution and Its FPGA-based Evaluation

Presentation date： 2012.12
State Dependent Scan Flip-Flop with Key-Based Configuration against Scan-Based Side Channel Attack on RSA Circuit

Presentation date： 2012.12
Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating

Presentation date： 2012.11
Dynamically Changeable Architecture against Scan-Based Side Channel, Attack Using State Dependent Scan Flip-Flop on RSA Circuit

Presentation date： 2012.11
2コアプロセッサを対象とする正確で高速なヘテロL1キャッシュシミュレーション

Presentation date： 2012.08
HDRアーキテクチャを対象としたクロックゲーティングを用いた低電力高位合成手法

Presentation date： 2012.08
動的複数電源電圧およびフロアプラン統合化アーキテクチャを対象とした低電力化高位合成手法

Presentation date： 2012.08
キャッシュ構成の高速シミュレーションを利用した不揮発メモリによる二階層キャッシュ構成の評価

Presentation date： 2012.08
温度特性を考慮したRDRアーキテクチャ向け高位合成手法

Presentation date： 2012.08
State Dependent Scan Flip Flopを用いたRSA暗号回路へのセキュアスキャンアーキテクチャの実装

Presentation date： 2012.08
クロックグリッチを利用した故障攻撃に対するカウンタを用いた耐タンパAES暗号回路

Presentation date： 2012.08
高集積かつ高周波な回路に対応した複数電源電圧指向の高位合成手法

Presentation date： 2012.07
複数のキャッシュ構成を同時に表現するデータ構造とこれを用いた高速で正確な2コアキャッシュシミュレーション

Presentation date： 2012.07
センサネットワーク低消費電力化のためのS-MACプロトコルduty cycle最適化手法

Presentation date： 2012.07
空間認知を利用した歩行者のための屋内ナビゲーションシステム設計

Presentation date： 2012.07
可視グラフによる屋内環境モデル化に基づく屋内環境向けナビゲーションシステム

Presentation date： 2012.07
State Dependent Scan Flip Flopを用いたRSA暗号回路へのセキュアスキャンアーキテクチャの実装

Presentation date： 2012.07
An Energy-efficient High-level Synthesis Algorithm for Huddle-based Distributed-Register architectures

Presentation date： 2012.05
HDRアーキテクチャを対象とした高速かつ効率的な複数電源電圧指向の高位合成手法

Presentation date： 2012.05
2コアプロセッサL1キャッシュ構成の正確で高速なシミュレーション手法

Presentation date： 2012.03
RDRアーキテクチャを対象とした部分2重化フォールトセキュア高位合成手法

Presentation date： 2012.03
セレクタ論理を利用した高速補間演算器設計

Presentation date： 2012.03
スキャンシグネチャを利用したTriple DESに対するスキャンベース攻撃の実装実験

Presentation date： 2012.02
スキャンシグネチャを用いたTriple DESに対するスキャンベース攻撃手法

Presentation date： 2011.11
スキャンチェイン構造に依存しないDESに対するスキャンベース攻撃手法

Presentation date： 2011.10
HDRアーキテクチャを対象とした複数電源電圧指向の低電力化高位合成手法

Presentation date： 2011.10
2コアプロセッサアーキテクチャを対象とする正確なキャッシュ構成シミュレーションの高速化に対する一考察

Presentation date： 2011.09
共有バス方式とバスマトリクス方式を用いたネットワークプロセッサのバス競合の性能比較評価

Presentation date： 2011.09
動きベクトルを考慮した遅延オーバーヘッドのないハードウェア向き適応的並列補間手法

Presentation date： 2011.09
セレクタ論理帰着型重み付き加算器を用いた超解像処理と比較実験

Presentation date： 2011.09
複数電源電圧および複数サイクルレジスタ間通信指向の低電力化高位合成手法

Presentation date： 2011.08
屋内環境モデル化と柔軟な歩行経路生成手法

Presentation date： 2011.07
歩行者ナビゲーションのための屋内環境での空間認知

Presentation date： 2011.07
セレクタ論理帰着型重み付き加算器を用いた超解像処理

Presentation date： 2011.05

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Specific Research

手指動作解析手法ならびに瞳孔情報解析手法に関する研究

2021

　View Summary

本研究では，筋電位信号から手指動作を時系列的に推定が可能な手法として，LSTM を用いた手法を提案した．更にその手法を用いて，クラウドコンピューティングを用いた手指動作のリアルタイム推定システムを提案した．提案したシステムは，およそ400ms遅延で，予測周波数50Hzで稼働させる事が可能である．また，瞳孔は交感神経や副交感神経を総称する交感神経系による精神的な影響を強く受ける.瞳孔径の変化を測定することによって, その人の感じていることを推定することが可能である.特定条件下での瞳孔径変化に関する原因を明らかにすることを目的として. 3種類の実験を行い, 結果に対して有意差検定を用いることで一定の考察にたどり着くことが出来た. 
表面筋電信号用ユーザ・インタフェースを用いた手指部の動作のVR空間での実現

2020

　View Summary

本研究では、まず、表面筋電図および筋電位信号と人間の動作を表すような各種センサに対して機械学習を用いた回帰分析を行い，高精度かつ連続的な手指動作推定を行った．当研究室では、すでに、手指部の筋電情報に基づいたユーザ・インタフェースを実現するために、筋電測定用の乾式電極を用いたウェアラブルグローブ型電極を製作している。このウェアラブルグローブ型電極を用いて、手指部の動作をVR空間において実現している。つぎに、本研究では，筋電位信号のリアルタイム通信における通信手法を構築した．提案した通信方法では要件として基準となるサンプリング周波数 1kHz を満たし，かつ、高い信頼性を達成している．ここではOSCを用いてUDPの速度と拡張性を確保した．また RUDP の手法を提案し，高い信頼性を確保した．以上の結果から筋電位信号のリアルタイム通信として利用でき、手指部の動作をVR空間で実現できることを示した．
表面筋電信号用ユーザ・インタフェースを用いた手指部の動作のVR空間での実現

2019

　View Summary

本研究室では、すでに、手指部の筋電情報に基づいたユーザ・インタフェースを実現するために、筋電測定用の乾式電極を用いたウェアラブルグローブ型電極を製作している。このウェアラブルグローブ型電極を用いて、手指部の動作をVR空間において実現することを本研究の目的とした。そのために、(1) ノイズ・フィルタの開発、(2) 採用すべき特徴量の抽出、(3) 採用すべき識別器の選択、(4) 同被験者・異被験者間でデータによる識別精度の比較・改良、(5) タッピングにピッチ動作等を加えた際の識別方法の構築、(6) リアルタイム処理に向けたデータ処理環境の構築、(7) VR空間への適用、に関して順次研究を進めた。
手指内在筋の表面筋電信号用ユーザ・インターフェースならびに動作識別手法の開発

2018

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The motion of the ﬁnger is made up of a combination of forearm part (extrinsic) muscles and hand part (intrinsic) muscles.  We have created a wearable ﬁngerless glove controller to sense sEMG (surface Electromyography) from intrinsic muscles using dry electrodes.  Recognition of air-tapping gesture with a sensor attached to wearable ﬁngerless glove controller is a challenging problem.  In this study, we focused on motion recognition of air-tapping and performed motion recognition using CNN and evaluated its ac-curacy.  As a result, the accuracy in intra-subject identiﬁcation was 85.05%.  Also, experiments are currently being conducted in anticipation of character input in VR space.  Character input experiment in VR space was carried out using sEMG wearable ﬁngerless glove controller, as a primitive experiment of the use of sEMG glove in VR space.  Based on the results, we discussed the eﬃciency of character input using sEMG glove in VR space.  
侵襲に頑健な集積回路の設計および実装に関する研究

2018

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To deal with the reliability issue caused by soft errors, a low power soft error hardened latch (SHC) design using Schmitt-Trigger-based C-element is proposed for reliable low power applications in this research.  The total number of transistors of the proposed SHC latch is only increased by 2 when compared to the conventional unhardened C2MOS latch, while up to 82.96% power reduction can be achieved when compared to the existing soft error tolerant HiPeR design.  When soft errors occur in the internal nodes of the proposed SHC, it can be ﬁltered inside and will not cause the output Q to be upset.  Moreover, in case of soft errors occurring and aﬀecting the output, the proposed SHC latch can recover to the correct state as fast as the existing works while they usually introduce about 2X area overhead as large as the proposed SHC, which clearly shows the eﬀectiveness of the proposed low cost SHC design. 
高速かつ低電力なソフトエラー耐性をもつラッチの設計

2017

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As semiconductor technology continues scaling down, the reliability issue has become much more critical than ever before.  Unlike traditional hard-errors caused by permanent physical damage which can’t be recovered in field, soft errors are caused by radiation or voltage/current fluctuations that lead to transient changes on internal node states, thus they can be viewed as temporary errors.  However, due to the unpredictable occurrence of soft errors, it is desirable to develop soft error tolerant designs.  For this reason, soft error tolerant design techniques have gained great research interest.  In this research, low-power soft error tolerant SHC latch is proposed using C-elements.  SHC latch and existing soft error tolerant latch are implemented and evaluated by spice simulator.  80.52% power reduction at maximum is achieved by SHC latch compared with HiPeR latch.  66.04% delay reduction at maximum is achieved by improved SHC latch compared with FERST latch. 
複合的なセンサによる人体動作解析システムに関する研究

2014 史　又華

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　筋主体の人体動作解析システムを構築するための基礎研究として，筋硬度計，および超音波エラストグラフィを用いて等張性収縮時，等尺性収縮時の筋硬度の変化を測定し，肘関節角度や負荷と，筋硬度との相関性を求めた．本研究では，骨格筋の主に上腕二頭筋に狙いを絞り，筋繊維と並行に三点，筋硬度測定位置を定め，等張性収縮時の各々の筋硬度の違いを調べた．この実験により，等張性収縮時，肘関節角度に応じて，肩から肘の間で最も筋硬度が高い位置が移動する現象を定量的に確認した．これにより，上腕二頭筋の複数位置の筋硬度測定値と，等張性収縮時の肘関節角度との相関性が高いことが分かり，筋硬度からの肘関節角度推定の実現性を示した．
ＦＰＧＡを用いた遺伝統計学アルゴリズムのハードウェア設計

2006

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ヒトゲノムのDNAの全塩基配列を解読する構造解析は終わり、ゲノムの解析作業は構造解析により得られたDNA塩基配列から遺伝子の働きを解読する機能解析に移行している。機能解析の中でも、遺伝子情報からSNP（スニップ）やマイクロサテライトといった多型情報を得て、これを基にハプロタイプやディプロタイプを遺伝統計学アルゴリズムによって求め解析し、病気等の原因となっている遺伝子を特定することは、将来行われるであろうテーラーメイド医療に必須である。遺伝統計学アルゴリズムとしては連鎖不平衡解析が有力であり、EMアルゴリズムに基づく方法、MCMC法、Pooled DNA法が知られている。しかし、これらのアルゴリズムはいずれも膨大な時間を要するものであり、ソフトウェアによる改善だけでは実用的なものを開発するのは難しい状況である。本研究では、FPGAを用いることによって、遺伝統計学アルゴリズムを高速に実行するハードウェアシステムを構築することを主たる目的とする。このために、まず、FPGA、遺伝統計学アルゴリズム、および、ＣＡＤ技術に関する調査を行った。その後、アプリケーションプロセッサのデータキャッシュ構成最適化手法、SIMD型プロセッサコアの自動合成のためのパイプライン演算ユニット生成手法、HW/SW協調合成におけるアプリケーションプロセッサの面積/遅延見積もり手法、レジスタ分散・共有併用型アーキテクチャを対象としたフロアプランを考慮した高位合成手法、動的再構成可能なマルチレート対応LDPC符号複号器の実装、アプリケーションプロセッサのフォワーディングユニット最適化手法、XMLをベースとしたCDFGマニピュレーションフレームワーク：CoDaMaなどに関する研究を行い、その研究成果を学会において発表した。また、FPGAを用いたハードウェア・アーキテクチャの詳細の検討およびシミュレーションにより検証を行った。
携帯情報機器を対象とした楕円曲線暗号LSIの試作と自動合成システムに関する研究

2005

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本研究では、携帯情報機器に搭載することを前提として、楕円曲線暗号に特化したアーキテクチャを考案し、回路試作することを主たる目的として研究を行った。主な研究成果を以下に示す。１．暗号技術による安全性に着目した上で、ワードベースモンゴメリ乗算器を設計し、それを搭載した楕円曲線暗号LSIアーキテクチャを提案した。ワードベースモンゴメリ乗算器のワード幅、個数の構成を変更可能な160ビット楕円曲線暗号LSIアーキテクチャを提案し、計算機上に実装することで評価した。この乗算器が20個の構成で回路面積は126Kゲートであり、174MHz で動作させた場合、160ビットの暗号化を3.6msで実行可能である。既存研究との比較では、同程度の回路面積の楕円曲線暗号LSIと比較して、処理時間を16％削減できることを示した。２．メディア処理LSIの高性能化に着目した上で、スレッド分割アルゴリズムとスレッドに対するGated Clockを用いた低消費電力化手法を提案した。スレッド分割を適用する前の回路と比較して、スレッド分割を適用した回路の平均待機状態を増やすことで、待機状態にあるサブスレッドに対しGated Clockを適用し、効果的な消費電力削減を実現している。提案手法を評価するため、画像処理アプリケーションとしてJPEGエンコーダを実装し、提案アルゴリズムを適用した場合としない場合とで、各モジュールとJPEGエンコーダの消費電力と消費エネルギを比較した。提案手法では、スレッドに対するGated Clockを適用しているため、Gated Clock制御回路の面積オーバーヘッドは小さく、増加を3％までに抑えている。消費電力の大きなレジスタファイルをスレッド内に生成するスレッド分割アルゴリズムを適用することで、消費電力を最大で48％削減し、JPEGエンコーダの消費エネルギを33％削減できることを示した。
遺伝統計学アルゴリズムを高速実行する再構成可能LSIシステムの開発

2004

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本研究では，複数の遺伝統計学アルゴリズムを高速に実行するLSIを搭載したシステムを構築することを主たる目的とする．このために本年度は昨年度に引き続き，まず，遺伝統計学アルゴリズム，再構成可能LSI，および，ＣＡＤ技術に関する調査を行った．その後、SIMD型プロセッサコア向けHW/SW分割における内部演算並列度最適化手法、IP再利用を考慮したシステムLSIにおけるプロセッサコア合成システム、消費電力最適化をめざしたスレッド分割手法、フロアプランとタイミング制約に基づくレジスタ間データ転送を考慮した高位合成手法、レジスタ分散型アーキテクチャを対象とするフロアプランを考慮した高位合成手法、ランレングス符号化を利用したスキャンチェイン再構成手法、マルチスキャンを対象としたテストデータ圧縮手法、Invader Assay法の出力結果の自動クラスタリング手法-最短距離法を初期値としたMCMCによる手法、ゲノムワイドなcase-control association studiesにおける多重比較手法などに関する研究を行い、その研究成果を学会において発表した。また、再構成可能LSI用アーキテクチャの詳細の検討およびシミュレーションにより検証を行った．来年度はさらに研究を発展させてゆく。
動的再構成可能LSIによる柔軟性の高いシステムの開発

2002

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　本研究では，動的再構成可能LSIを用いた柔軟性の高い優れたデジタル信号処理システムを構築するために有効なＦＰＧＡの設計および製作，ならびに，その専用のＣＡＤ（計算機支援設計）ツールの開発を行った．研究成果を以下にまとめる．　１．動的再構成可能LSIシステムとＣＡＤの開発：動的再構成可能LSIシステムをパラメタライズすることにより自動合成する手法を提案するとともに，そのシステムを対象としたスケジューリング手法を提案し，これらの有効性を示した．　２．ハードウェア/ソフトウェア協調合成ＣＡＤツールの開発：２種類のレジスタファイルを持ったディジタル信号処理向けプロセッサのハードウェア/ソフトウェア協調合成手法の開発を行った．ここでは特に，ハードウェア/ソフトウェア分割手法，面積/遅延見積り手法，並列Ｃコンパイラの開発を行った．また，連想メモリ（ＣＡＭ）を対象としたハードウェア/ソフトウェア協調合成手法の開発を行った．　３．高位合成ＣＡＤツールの開発：制御処理を主体としたハードウェアを対象とした高位合成ＣＡＤ手法の開発を行った．ここでは特に，面積/遅延見積り手法，面積/遅延見積り最適化手法，合成時間に制約を与えたときに最良のリソースバインディング結果を与える手法の開発を重点的に行った．　４．レイアウト手法の開発：合成の最終工程であるレイアウト設計を対象として，上流レベルから面積/遅延を見積る手法，クロストークを考慮した手法を開発した．　５. ＦＰＧＡ応用：応用例として，動画像符号化アルゴリズムの高速化を考察した．
デジタル信号処理プロセッサを対象とした高位合成手法

2000

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　本研究では、昨年度に引き続きハードウェア／ソフトウェア協調合成手法、ならびに、高位合成手法に焦点をあてて研究を行った。以下では、それぞれについて概要を示す。１．ハードウェア／ソフトウェア協調合成手法　ディジタル信号処理用プロセッサを対象としたハードウェア／ソフトウェア協調合成アルゴリズムに関する研究を行った。ハードウェア／ソフトウェア協調合成とは、システムＶＬＳＩ全体において、ハードウェアとして実現する部分とソフトウェアとして実現する部分を決定する問題であり、システムＶＬＳＩ全体の性能、ひいては、このようなシステムＶＬＳＩを包含する機器（例えば情報携帯端末等）の価格、面積、性能を決定するものである。本研究で想定するプロセッサは、内部にアドレッシングユニット、ハードウェアルーピング機構、ハーバードアーキテクチャ等に代表される専用ハードウェアユニットを持ち、これらをどのように設計し有機的に組み合わせていくか、がプロセッサ性能を引き出す鍵となる。一昨年度より、このテーマの研究を行っており、本年度は、ディジタル信号処理プロセッサコアを対象としたアルゴリズムにおける、プロセッサコアの面積・遅延見積り手法、ハードウェア／ソフトウェア分割手法、並列化Ｃコンパイラを提案し、その有効性を示した。また、システムレベルにおける協調合成アルゴリズムを提案した。２．高位合成手法　ディジタル信号処理のハードウェアは通常、複雑なデータパスによって実現される。本研究室では、Ｃ言語のサブセットによって記述された動作記述を入力とし、レジスタトランスファ（ＲＴ：状態遷移図）レベルのハードウェア記述（ＨＤＬ: Hardware Description Language）を合成する高位合成システムを提案している。本年度は、与えたれた時間の中で最適な解を求めるリソースバインディング手法を提案し、その有効性を示した。これは、ヒューリスティックな手法と分枝限定法を組み合わせたものである。また、制御処理を主体とするハードウェアを対象とした高位合成システムの開発を行った。これは、画像符号化・復号化、プロトコル処理、あるいは、暗号処理といった、ビット処理もしくは条件分岐処理から構成されるアプリケーションプログラムをターゲットとしている。本年度は、面積・遅延を見積もる手法、ならびに、面積・時間最適化手法を提案し、その有効性を示した。
デジタル信号処理プロセッサを対象とした高位合成手法

1999

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　本研究では、ハードウェア／ソフトウェア協調合成手法、ならびに、高位合成手法に焦点をあてて研究を行った。以下では、それぞれについて概要を示す。１．ハードウェア／ソフトウェア協調合成手法　ディジタル信号処理用プロセッサを対象としたハードウェア／ソフトウェア協調合成アルゴリズムに関する研究を行った。ハードウェア／ソフトウェア協調合成とは、システムＶＬＳＩ全体において、ハードウェアとして実現する部分とソフトウェアとして実現する部分を決定する問題であり、システムＶＬＳＩ全体の性能、ひいては、このようなシステムＶＬＳＩを包含する機器（例えば情報携帯端末等）の価格、面積、性能を決定するものである。本研究で想定するプロセッサは、内部にアドレッシングユニット、ハードウェアルーピング機構、ハーバードアーキテクチャ等に代表される専用ハードウェアユニットを持ち、これらをどのように設計し有機的に組み合わせていくか、がプロセッサ性能を引き出す鍵となる。昨年度より、このテーマの研究を行い、ディジタルプロセッサコアを対象としたアルゴリズムの基本戦略を構築した。本年度は２種類のレジスタを持った協調合成アルゴリズムに拡張するとともに、そのために必要となる、プロセッサコアの面積・遅延見積り手法、ならびに、ハードウェア／ソフトウェア分割手法を提案し、その有効性を示した。２．高位合成手法　ディジタル信号処理のハードウェアは通常、複雑なデータパスによって実現される。本研究室では、Ｃ言語のサブセットによって記述された動作記述を入力とし、レジスタトランスファ（ＲＴ：状態遷移図）レベルのハードウェア記述（ＨＤＬ: Hardware Description Language）を合成する高位合成システムを提案している。本年度は、このシステムの構成要素の１つとなる、最適解を保証するリソースバインディング手法を提案し、その有効性を示した。また、制御処理を主体とするハードウェアを対象とした高位合成システムの開発を行った。これは、画像符号化・復号化、プロトコル処理、あるいは、暗号処理といった、ビット処理もしくは条件分岐処理から構成されるアプリケーションプログラムをターゲットとしている。本研究では、このシステムの基本的戦略をたてるとともに、ハードウェア記述の自動生成手法、ならびに、面積・時間最適化手法を提案し、その有効性を示した。
デジタル信号処理用FPGAおよび専用CADツールの開発

1998

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デジタル信号処理を目的としたFPGAを用いた回路設計は、以下に示す4つの段階的な設計工程に基づいて行われている。本研究では、この4つの各設計工程にFPGAボードの製作を加えた、5つの研究テーマに関して研究を行った。(1) ハードウェア／ソフトウェア協調合成では、従来、提案していた1種類のレジスタの使用を前提としたアルゴリズムを、2種類のレジスタを持った協調合成アルゴリズムに拡張するとともに、そのための並列化コンパイラを提案・構築した。これにより、演算精度を保った状態で、レイアウト面積の削減を実現することを示した。(2) 高位合成では、データフローグラフ列挙アルゴリズム、高速スケジューリング・アルゴリズム、ならびに、最適解を保証したリソースバインディングアルゴリズムを提案した。(3) 論理合成では、深さの制約値ｄが与えられたときに、論理の深さをｄに抑え、かつ、論理ブロック数を最小化する発見的なテクノロジーマッピング・アルゴリズムを構築した。(4) レイアウトでは、消費電力の低減を目的とした配置と概略配線アルゴリズムし、配線混雑度および実行時間は10％程度増加するが、約10％の消費電力を削減可能であることを示した。また、FPGAのマクロブロックを考慮して配置と概略配線を行うアルゴリズムの構築を行い、この有効性を示した。さらに、レイアウト再構成手法を提案し、追加されるＬＵＴの割合が20％以下ならば、提案手法が有効でることを示した。(5) FPGAボードの製作では、ディジタル信号処理アプリケーションの高速実行を目的とした動的再構成可能システムであるマルチFPGAボードを考案し、製作を行った。応用例として、JPEGエンコーダを実装した結果、計算機によるソフトウェア処理に比較して2倍の処理速度を達成した。この研究成果は日本工業新聞の取材を受け、新聞に掲載された。以上の研究成果により、デジタル信号処理用FPGAのためのCADツールの開発およびFPGAボードの製作ができ、当初の研究の目的をほぼ、はたすことができた。

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Syllabus

Master's Thesis (Department of Computer Science and Communications Engineering)

Graduate School of Fundamental Science and Engineering

2022 full year
Master's Thesis (Department of Electronic and Physical Systems)

Graduate School of Fundamental Science and Engineering

2022 full year
IoT System Design

Graduate School of Fundamental Science and Engineering

2022 spring semester
Seminar on Wireless Communication Circuit Technologies D

Graduate School of Fundamental Science and Engineering

2022 fall semester
Seminar on Wireless Communication Circuit Technologies C

Graduate School of Fundamental Science and Engineering

2022 spring semester
Seminar on Wireless Communication Circuit Technologies B

Graduate School of Fundamental Science and Engineering

2022 fall semester
Seminar on Wireless Communication Circuit Technologies A

Graduate School of Fundamental Science and Engineering

2022 spring semester
Seminar on Integrated System Design D

Graduate School of Fundamental Science and Engineering

2022 fall semester
Seminar on Integrated System Design C

Graduate School of Fundamental Science and Engineering

2022 spring semester
Seminar on Integrated System Design B

Graduate School of Fundamental Science and Engineering

2022 fall semester
Seminar on Integrated System Design A

Graduate School of Fundamental Science and Engineering

2022 spring semester
Seminar on High-level Verification Technologies D

Graduate School of Fundamental Science and Engineering

2022 fall semester
Seminar on High-level Verification Technologies C

Graduate School of Fundamental Science and Engineering

2022 spring semester
Seminar on High-level Verification Technologies B

Graduate School of Fundamental Science and Engineering

2022 fall semester
Seminar on High-level Verification Technologies A

Graduate School of Fundamental Science and Engineering

2022 spring semester
Seminar on Design and Analysis Systems D

Graduate School of Fundamental Science and Engineering

2022 fall semester
Seminar on Design and Analysis Systems C

Graduate School of Fundamental Science and Engineering

2022 spring semester
Seminar on Design and Analysis Systems B

Graduate School of Fundamental Science and Engineering

2022 fall semester
Seminar on Design and Analysis Systems A

Graduate School of Fundamental Science and Engineering

2022 spring semester
Computer-Aided Design

Graduate School of Fundamental Science and Engineering

2022 fall quarter
Research on Wireless Communication Circuit Technologies

Graduate School of Fundamental Science and Engineering

2022 full year
Research on Integrated System Design

Graduate School of Fundamental Science and Engineering

2022 full year
Research on High-level Verification Technologies

Graduate School of Fundamental Science and Engineering

2022 full year
Research on Design and Analysis Systems

Graduate School of Fundamental Science and Engineering

2022 full year
Computer-Aided Design

Graduate School of Fundamental Science and Engineering

2022 fall quarter
Research on Design and Analysis Systems

Graduate School of Fundamental Science and Engineering

2022 full year
Seminar on Design and Analysis Systems D

Graduate School of Fundamental Science and Engineering

2022 fall semester
Seminar on Design and Analysis Systems C

Graduate School of Fundamental Science and Engineering

2022 spring semester
Seminar on Design and Analysis Systems B

Graduate School of Fundamental Science and Engineering

2022 fall semester
Seminar on Design and Analysis Systems A

Graduate School of Fundamental Science and Engineering

2022 spring semester
Research on Design and Analysis Systems

Graduate School of Fundamental Science and Engineering

2022 full year
Seminar on Integrated System Design D

Graduate School of Fundamental Science and Engineering

2022 fall semester
Seminar on Integrated System Design C

Graduate School of Fundamental Science and Engineering

2022 spring semester
Seminar on Integrated System Design B

Graduate School of Fundamental Science and Engineering

2022 fall semester
Seminar on Integrated System Design A

Graduate School of Fundamental Science and Engineering

2022 spring semester
Seminar on Design and Analysis Systems D

Graduate School of Fundamental Science and Engineering

2022 fall semester
Seminar on Design and Analysis Systems C

Graduate School of Fundamental Science and Engineering

2022 spring semester
Seminar on Design and Analysis Systems B

Graduate School of Fundamental Science and Engineering

2022 fall semester
Seminar on Design and Analysis Systems A

Graduate School of Fundamental Science and Engineering

2022 spring semester
Research on Integrated System Design

Graduate School of Fundamental Science and Engineering

2022 full year
Research on Design and Analysis Systems

Graduate School of Fundamental Science and Engineering

2022 full year
Master's Thesis (Department of Computer Science and Communications Engineering)

Graduate School of Fundamental Science and Engineering

2022 full year
Master's Thesis (Department of Electronic and Physical Systems)

Graduate School of Fundamental Science and Engineering

2022 full year
Special Seminar B in Computer Science and Communications Engineering

Graduate School of Fundamental Science and Engineering

2022 fall semester
Special Seminar A in Computer Science and Communications Engineering

Graduate School of Fundamental Science and Engineering

2022 spring semester
Research on Design and Analysis Systems

Graduate School of Fundamental Science and Engineering

2022 full year
Research on Wireless Communication Circuit Technologies

Graduate School of Fundamental Science and Engineering

2022 full year
Research on Integrated System Design

Graduate School of Fundamental Science and Engineering

2022 full year
Research on High-level Verification Technologies

Graduate School of Fundamental Science and Engineering

2022 full year
Research on Design and Analysis Systems

Graduate School of Fundamental Science and Engineering

2022 full year
Research on Design and Analysis Systems

Graduate School of Fundamental Science and Engineering

2022 full year
Seminar on Design and Analysis Systems D

Graduate School of Fundamental Science and Engineering

2022 fall semester
Seminar on Design and Analysis Systems C

Graduate School of Fundamental Science and Engineering

2022 spring semester
Seminar on Design and Analysis Systems B

Graduate School of Fundamental Science and Engineering

2022 fall semester
Seminar on Design and Analysis Systems A

Graduate School of Fundamental Science and Engineering

2022 spring semester
IoT System Design

Graduate School of Creative Science and Engineering

2022 spring semester
IoT System Design

Graduate School of Advanced Science and Engineering

2022 spring semester
Electronic and Physical Systems Laboratory A

School of Fundamental Science and Engineering

2022 fall semester
Electronic and Physical Systems Practice B [S Grade]

School of Fundamental Science and Engineering

2022 fall semester
Electronic and Physical Systems Practice B

School of Fundamental Science and Engineering

2022 fall semester
Logic Circuits [S Grade]

School of Fundamental Science and Engineering

2022 spring semester
Logic Circuits

School of Fundamental Science and Engineering

2022 spring semester
Mathematical Foundations of Computation [S Grade]

School of Fundamental Science and Engineering

2022 spring semester
Mathematical Foundations of Computation

School of Fundamental Science and Engineering

2022 spring semester
Electronic and Physical Systems Practice A [S Grade]

School of Fundamental Science and Engineering

2022 spring semester
Electronic and Physical Systems Practice A

School of Fundamental Science and Engineering

2022 spring semester
Introduction to Electronic and Physical Systems [S Grade]

School of Fundamental Science and Engineering

2022 an intensive course(spring)
Introduction to Electronic and Physical Systems

School of Fundamental Science and Engineering

2022 an intensive course(spring)
Introduction to Electronic and physical systems [S Grade]

School of Fundamental Science and Engineering

2022 spring semester
Introduction to Electronic and physical systems

School of Fundamental Science and Engineering

2022 spring semester
Special Seminar on Electronic and Physical Systems

School of Fundamental Science and Engineering

2022 fall semester
Electronic and Physical Systems Laboratory C [S Grade]

School of Fundamental Science and Engineering

2022 fall semester
Electronic and Physical Systems Laboratory C

School of Fundamental Science and Engineering

2022 fall semester
Electronic and Physical Systems Laboratory B [S Grade]

School of Fundamental Science and Engineering

2022 spring semester
Electronic and Physical Systems Laboratory B

School of Fundamental Science and Engineering

2022 spring semester
IoT System Design

School of Fundamental Science and Engineering

2022 spring semester
Computer-Aided Design

School of Fundamental Science and Engineering

2022 fall quarter
IoT System Design

School of Fundamental Science and Engineering

2022 spring semester
LSI Architecture

School of Fundamental Science and Engineering

2022 spring quarter
Bachelor Thesis B [S Grade]

School of Fundamental Science and Engineering

2022 fall semester
Bachelor Thesis B

School of Fundamental Science and Engineering

2022 spring semester
Bachelor Thesis B

School of Fundamental Science and Engineering

2022 fall semester
Bachelor Thesis A [S Grade]

School of Fundamental Science and Engineering

2022 fall semester
Bachelor Thesis A [S Grade]

School of Fundamental Science and Engineering

2022 spring semester
Bachelor Thesis A

School of Fundamental Science and Engineering

2022 fall semester
Bachelor Thesis A

School of Fundamental Science and Engineering

2022 spring semester
Electronic and Physical Systems Laboratory A [S Grade]

School of Fundamental Science and Engineering

2022 fall semester
Computer-Aided Design

School of Fundamental Science and Engineering

2022 fall quarter
IoT System Design

School of Fundamental Science and Engineering

2022 spring semester
Research Project D

School of Fundamental Science and Engineering

2022 spring semester
Research Project A

School of Fundamental Science and Engineering

2022 fall semester
Research Project C

School of Fundamental Science and Engineering

2022 fall semester
Research Project C

School of Fundamental Science and Engineering

2022 fall semester
Research Project B

School of Fundamental Science and Engineering

2022 spring semester
Research Project B

School of Fundamental Science and Engineering

2022 spring semester
Physical Electronics Laboratory B

School of Fundamental Science and Engineering

2022 spring quarter
Physical Electronics Seminar B

School of Fundamental Science and Engineering

2022 spring quarter
Physical Electronics Laboratory A

School of Fundamental Science and Engineering

2022 winter quarter
Physical Electronics Seminar A

School of Fundamental Science and Engineering

2022 winter quarter

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