Updated on 2023/02/01

写真a

 
KASAHARA, Hironori
 
Scopus Paper Info  
Paper Count: 0  Citation Count: 0  h-index: 5

Citation count denotes the number of citations in papers published for a particular year.

Affiliation
Faculty of Science and Engineering, School of Fundamental Science and Engineering
Job title
Professor
Homepage URL
http://www.kasahara.cs.waseda.ac.jp/kasahara.html.ja

Concurrent Post

  • Faculty of Science and Engineering   Graduate School of Fundamental Science and Engineering

  • Affiliated organization   Global Education Center

Research Institute

  • 2022
    -
    2024

    Waseda Research Institute for Science and Engineering   Concurrent Researcher

Education

  • 1982.04
    -
    1985.03

    Waseda University   Graduate School of Science and Engineering   Department of Electrical Engineering  

    Doctor of Engineeting

  • 1980.04
    -
    1982.03

    Waseda University   Graduate School of Science and Engineering Master Course   Department of Electrical Engineering  

    Master of Enginnering

  • 1976.04
    -
    1980.03

    Waseda University   School of Science and Engineering   Department of Electrical Engineering  

    Bachelor of engineering

Degree

  • 早稲田大学　電気工学（計算機システム）   工学博士

  • Doctor Engineering

Research Experience

  • 2017.01
    -
    Now

    IEEE   Fellow

  • 2010.01
    -
    Now

    IEEE Computer Society   Golden Core Member

  • 2004.04
    -
    Now

    Waseda University   Advanced Multicore Processor Research Institute   Director

  • 1997.04
    -
    Now

    Waseda University   Department of Computer Science and Engineering   Professor

  • 2020.06
    -
    2024.06

    Engineering Academy of Japan   Director

  • 2019.05
    -
    2023.05

    COCN (Council on Competitiveness-Nippon)   Board Member

  • 2020.04
    -
    2022.09

    Waseda University   Senior Executive Vice President (Research Promotion)

  • 2019.06
    -
    2021.05

    Japan Universities Association for Computer Education   Standing director

  • 2018.11
    -
    2020.03

    Waseda University   Senior Executive Vice President (Research and Information System Promotion)

  • 2017.01
    -
    2019.12

    IEEE Computer Society   Strategic Planning Committee Chair

  • 2018.01
    -
    2018.12

    IEEE   Technical Activity Board Member

  • 2018.01
    -
    2018.12

    IEEE Computer Society   Board of Governors Chair

  • 2018.01
    -
    2018.12

    IEEE Computer Society   President

  • 2017
    -
    　

    日本学術会議連携会員

  • 2017
    -
    　

    日本工学アカデミー会員

  • 2015
    -
    　

    情報処理学会フェロー

  • 2009.01
    -
    2014.12

    IEEE Computer Society   Board of Governors

  • 1988.04
    -
    1997.03

    Waseda University   Department of Electrical, Electronics, and Computer Engineering   Associate Professor

  • 1989.03
    -
    1990.03

    Univ. of Illinois at Urbana-Champaign   Center for Supercomputing R & D   Visiting Research Scholar

  • 1986.04
    -
    1988.03

    Waseda Univerrsity   Department of electrical Engineering   Assistant Professor

  • 1985.09
    -
    1986.03

    The Japan Society for the Promotion of Science (JSPS)   The First Special Resarch Fellow (PD)

  • 1985.07
    -
    1985.12

    University of California at Berkeley   Department of Electrical Engineering and Computer Science   Visiting Scholar

  • 1983.04
    -
    1985.03

    Waseda University   Department of Electrical Engineering   Research Associate

  • 2017.06
    -
    2025.03

    The Okawa Foundation for Information and Telecommunications (The Okawa Foundation)   Councilor

  • 2018.06
    -
    2024.06

    The Okawa Foundation for Information and Telecommunications (The Okawa Foundation)   Ohkawa Award Selection Committee Member

  • 2021.01
    -
    2022.09

    Research Innovation Center, Waseda University   General Manager

  • 2018.11
    -
    2022.09

    Research Organization for Open Innovation Strategy, Waseda University   Chairperson

  • 2018.11
    -
    2022.09

    Waseda Shibuya Senior High School   Representative Director

  • 2018.11
    -
    2022.09

    Waseda Junior and Senior High School   Member of Board of Directors and Councilor

  • 2021.04
    -
    2021.10

    IEEE Computer Society   Election Committee Member

  • 2020.09
    -
    2020.12

    Research Innovation Center, Waseda University   Head of Intellectual Property and Research Collaboration Support Section

  • 2019.06
    -
    2020.12

    Research Innovation Center, Waseda University   Director

  • 2012.01
    -
    2020.09

    IEEE Computer Society   Multicore STC (Special Technical Community) Chair

  • 2019.01
    -
    2019.12

    IEEE Computer Society   Nomination Committee Chair

  • 2019.01
    -
    2019.12

    IEEE Computer Society   Past President

  • 2017.01
    -
    2019.12

    IEEE Computer Society   Executive Committee Member

  • 2018.11
    -
    2019.05

    Research Collaboration and Promotion Center, Waseda University   Director

  • 2018.01
    -
    2018.12

    IEEE Computer Society   Executive Committee Chair

  • 2017.01
    -
    2017.12

    IEEE Computer Society   President Elect

  • 2017
    -
    　

    Professional member of the IEEE-Eta Kappa Nu(IEEE-HKN)

  • 2010.04
    -
    2013.03

    Egypt Japan University of Science and Technology - EJUST   Invited Professor

  • 2011.04
    -
    2011.09

    The University of Tokyo   Deoartment of Computer Science   Part-time Lecturer

  • 1993.01
    -
    1993.03

    Kyushu University   Graduate School of Science and Engineering   Part-time Lecturer

  • 1982.04
    -
    1985.03

    Waseda Univerrsity   Department of Electrical Engineering, Graduate School of Science and Engineering   Ph.D. Student   Ph.D.

  • 1980.04
    -
    1982.03

    Waseda University   Department of Electrical Engineering, Graduate School of Sciece and Engineering   Master Course Student   Master of Engineering

  • 1976.04
    -
    1980.03

    Waseda University   Department of Electirical Engineering   Undergraduate Student   BSEE

▼display all

Professional Memberships

  • 2020.06
    -
    Now

    The Engineering Academy of Japan, Director

  • 2019.01
    -
    Now

    COCN Board Member

  • 2017.11
    -
    Now

    IEEE Eta Kappa Nu Professional member,

  • 2017.05
    -
    Now

    The Engineering Academy of Japan Inc.(EAJ)

  • 2017.04
    -
    Now

    Science Council of Japan Member

  • 2017.01
    -
    Now

    IEEE Fellow

  • 2017.01
    -
    Now

    The Okawa Foundation for Information and Telecommunications

  • 2016.02
    -
    Now

    IEEE Senior Member,

  • 2015.06
    -
    Now

    IPSJ Fellow

  • 1987.04
    -
    Now

    ACM

  • 1986.01
    -
    Now

    IEEE Professional member

  • 1983.01
    -
    Now

    The Robotics Society of Japan

  • 1982.06
    -
    Now

    IEEE Computer Society

  • 1982.06
    -
    Now

    Japan Society for Simulation Technology

  • 1982.04
    -
    Now

    The Institute of Electronics, Information and Communication Engineers

  • 1982.01
    -
    Now

    IEEE

  • 1981.04
    -
    Now

    Information Processing Society of Japan

  • 2018.01
    -
    2018.12

    IEEE Computer Society President

  • 1980.04
    -
    　

    Institute of Electrical Engineers of Japan

▼display all

 

Research Areas

  • Computer system

Research Interests

  • Parallel Processing, Parallelizing Compiler, Multicore Processor, Green Computing, Computer Science

Papers

  • Parallelizing Factory Automation Ladder Programs by OSCAR Automatic Parallelizing Compiler

    Tohma Kawasumi, Tsumura Yuta, Hiroki Mikami, Tomoya Yoshikawa, Takero Hosomi, Shingo Oidate, Keiji Kimura, Hironori Kasahara

    Proc. of the 35th International Workshop on Languages and Compilers for Parallel Computing (LCPC2022)    2022.10

  • Parallelism Analysis of Ladder Programs by OSCAR Automatic Parallelizing Compiler

    Yuta TSUMURA, Tohma KAWASUMI, Hiroki MIKAMI, Daiki KAWAKAMI, Takero HOSOMI, Shingo OIDATE, Keiji KIMURA, Hironori KASAHARA

    IPSJ SIG Technical Report   ( 53 )  2022.03

  • LocalMapping Parallelization and CPU Allocation Method on ORB-SLAM3

    Kazuki YAMAMOTO, Takugo OSAKABE, Honoka KOIKE, Tohma KAWASUMI, Kazuki FUJITA, Toshiaki KITAMURA, Akihiro KAWASHIMA, Akira NODOMI, Sadahiro KIMURA, Keiji KIMURA, Hironori KASAHARA

    IEICE Technical Report   121 ( 425, CPSY2021-58 ) 79 - 74  2022.03

  • Trends in Parallelization Techniques for Embedded Systems

    Keiji Kimura, Dan Umeda, Hironori Kasahara

      66 ( 1 ) 2 - 7  2022.01

  • Parallelizing Compiler Translation Validation Using Happens-Before and Task-Set

    Jixin Han, Tomofumi Yuki, Michelle Mills Strout, Dan Umeda, Hironori Kasahara, Keiji Kimura

    2021 Ninth International Symposium on Computing and Networking Workshops (CANDARW)     87 - 93  2021.11  [Refereed]

    DOI

  • OSCAR Parallelizing and Power Reducing Compiler and API for Heterogeneous Multicores : (Invited Paper)

    Hironori Kasahara, Keiji Kimura, Toshiaki Kitamura, Hiroki Mikami, Kazutaka Morita, Kazuki Fujita, Kazuki Yamamoto, Tohma Kawasumi

    2021 IEEE/ACM SC'21 Workshop on Programming Environments for Heterogeneous Computing (PEHC)     10 - 19  2021.11

    Authorship：Lead author

    DOI

  • Performance Evaluation of OSCAR Multi-target Automatic Parallelizing Compiler on Intel, AMD, Arm and RISC-V Multicores

    Birk Martin Magnussen, Tohma Kawasumi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara

       2021.10  [Refereed]

  • Engineering Education in the Age of Autonomous Machines

    Shaoshan Liu, Jean-Luc Gaudiot, Hironori Kasahara

    IEEE Computer   54 ( 4 ) 66 - 69  2021.04  [Refereed]

  • Automatic Parallelization of MATLAB/Simulink Applications Using OSCAR Compiler

    Ryo Koyama, Yuta Tsumura, Toma Kawasumi, Yuya Nakada, Dan Umeda, Keiji Kimura, Hironori Kasahara

    Information Processing Society of Japan, Special Interest Group on System Architecture (ARC236@ETNET2021)    2021.03

  • Parallelization and Vectorization of SpMM for Sparse Neural Network

    Yuta Tadokoro, Keiji Kimura, Hironori Kasahara

    Information Processing Society of Japan, Special Interest Group on System Architecture (ARC236@ETNET2021)    2021.03

  • Waseda University Venture Creation and Expectations for 'Lab to Market'

    Hironori Kasahara

    STE Relay Column : Narratives 130, Research Organization for Open Innovation Strategy, Science, Technology and Entreprenership Research Factory    2021.03

  • Computer Education in the Age of COVID-19

    Jean-Luc Gaudiot, Hironori Kasahara

    Computer, January 2020, IEEE Computer Society   53 ( 10 ) 114 - 118  2020.10  [Refereed]

  • Local Memory Mapping of Multicore Processors on an Automatic Parallelizing Compiler

    Yoshitake Oki, Yuto Abe, Kazuki Yamamoto, Kohei Yamamoto, Tomoya Shirakawa, Akimasa Yoshida, Keiji Kimura, Hironori Kasahara

    IEICE Transaction on Electronics Special Section on “Low-Power and High-Speed Chips”   E103-C ( 3 ) 98 - 109  2020.03  [Refereed]

  • Compiler Software Coherent Control for Embedded High Performance Multicore

    Boma A. Adhi, Tomoya Kashimata, Ken Takahashi, Keiji Kimura, Hironori Kasahara

    IEICE Transaction on Electronics Special Section on “Low-Power and High-Speed Chips”   E103-C ( 3 ) 85 - 97  2020.03  [Refereed]

  • Consideration of Accelerator Cost Estimation Method in Multi-Target Automatic Parallelizing Compiler

    Kazuki Yamamoto, Kazuki Fujita, Tomoya Kashimata, Ken Takahashi, Boma A. Adhi, Toshiaki Kitamura, Akihiro Kawashima, Akira Nodomi, Yuji Mori, Keiji Kimura, Hironori Kasahara

    Information Processing Society of Japan, Special Interest Group on System Architecture (ARC232@ETNET2020)    2020.02

  • Automatic Vector-Parallelization by Collaboration of Oscar Automatic Parallelizing Compiler and NEC Vectorizing Compiler

    Yuta Tadokoro, Hiroki Mikami, Takeo Hosomi, Keiji Kimura, Hironori Kasahara

    Information Processing Society of Japan, Special Interest Group on System Architecture (ARC232@ETNET2020)    2020.02

  • Extensions of OSCAR Compiler for Parallelizing C++ Programs

    Toma Kawasumi, Tilman Priesner, Masato Noguchi, Jixin Han, Hiroki Mikami, Takahiro Miyajima, Keishiro Tanaka, Keiji Kimura, Hironori Kasahara

    Information Processing Society of Japan, Special Interest Group on System Architecture (ARC232@ETNET2020)    2020.02

  • Automatically Parallelizing Compiler Cooperative OSCAR Vector Multicore

    Keiji Kimura, Kazuki Fujita, Kazuki Yamamoto, Tomoya Kashimata, Toshiaki Kitamura, Hironori Kasahara

    International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems    2020.02

  • Aiming for World Level Research Promotion Considering Safety and Environment

    Hironori Kasahara

    Waseda Univ. Environmental Safety Center "Environment 40th anniversary edition "     3 - 3  2019.11  [Invited]

  • Cascaded DMA Controller for Speedup of Indirect Memory Access in Irregular Applications

    Tomoya Kashimata, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara

    9th Workshop on Irregular Applications: Architectures and Algorithms (IA3 2019)    2019.11  [Refereed]

  • Fast and Highly Optimizing Separate Compilation for Automatic Parallelization

    Tohma Kawasumi, Ryota Tamura, Yuya Asada, Jixin Han, Hiroki Mikami, Keiji Kimura, Hironori Kasahara

    The 2019 International Conference on High Performance Computing & Simulation (HPCS 2019)    2019.07  [Refereed]

  • 2018 CS PRESIDENT’S MESSAGE --Collaboration for the Future--

    Hironori Kasahara

    Computer, January 2019, IEEE Computer Society   ( 1-19 ) 72 - 76  2019.03  [Refereed]  [Invited]

  • Speedup of indirect load by DMA cascading

    Tomoya Kashimata, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara

    Information Processing Society of Japan(2018-ARC-234)    2019.01

  • Software Cache Coherent Control by Parallelizing Compiler

    Boma A. Adhi, Masayoshi Mase, Yuhei Hosokawa, Yohei Kishimoto, Taisuke Onishi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara

    Lecture Notes in Computer Science   LNCS 11403. Springer, 2019   17 - 25  2019.01  [Refereed]

  • NPC: 15th IFIP International Conference Network and Parallel Computing

    Feng Zhang, Jidong Zhai, Marc Snir, Hai Jin, Hironori Kasahara, Mateo Valero

    Lecture Notes in Computer Science   11276 ( LNCS )  2018.11

  • IEEE Division VIII Delegate/Director Candidates

    Hironori Kasahara

    Computer, IEEE Computer Society   50 ( 8 ) 94 - 95  2018.07

  • Development of Compilation Flow and Evaluation of OSCAR Vector Multicore Architecture

    Ken Takahashi, Satoshi Karino, Kazuki Miyamoto, Takumi Kawata, Tomoya Kashimata, Tetsuya Makita, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara

    The 80th National Conversion of Information Processing Society of Japan    2018.03

  • FPGA implementation of OSCAR Vector Accelerator

    Tomoya Kashimata, Boma A. Adhi, Satoshi Karino, Kazuki Miyamoto, Takumi Kawata, Ken Takahashi, Tetsuya Makita, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara

    The 80th National Conversion of Information Processing Society of Japan    2018.03

  • Automatic parallelizing and vectorizing compiler framework for OSCAR vector multicore processor.

    Kazuki Miyamoto, Tetsuya Makita, Ken Takahashi, Tomoya Kashimata, Takumi Kawada, Satoshi Karino, Toshiaki Kitamura, Keiji Kimura, Hironori kasahara

    Information Processing Society of Japan, Special Interest Group on System Architecture (ARC222@ETNET2018)    2018.03

  • Satisfaction and Sustainability

    Hironori Kasahara

    Computer IEEE Computer Society   51   4 - 6  2018.01  [Refereed]  [Invited]

  • Automatic Local Memory Management Using Hierarchical Adjustable Block for Multicores and Its Performance Evaluation

    Tomoya Shirakawa, Yuto abe, Yoshitake Ooki, Akimasa Yoshida, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2017-ARC-220 (DesignGaia2017)    2017.11

  • IEEE President-Elect Candidates Address Computer Society Concerns

    Hironori Kasahara

    Computer, IEEE Computer Society   50 ( 8 ) 96 - 100  2017.08

  • Multicore Cache Coherence Control by a Parallelizing Compiler

    Hironori Kasahara, Keiji Kimura, Boma A. Adhi, Yuhei Hosokawa, Yohei Kishimoto, Masayoshi Mase

    IEEE COMPSAC 2017 (The 41th IEEE Computer Society International Conference on Computers, Software & Applications)    2017.07  [Refereed]

  • Message from the CAP 2017 Organizing Committee

    Cristina Seceleanu, Hironori Kasahara, Tiberiu Seceleanu

    2017 IEEE 41st Annual Computer Software and Applications Conference (COMPSAC)    2017.07

    DOI

  • Hierarchical Interconnection Network Extension for Gen 5 Simulator Considering Large Scale Systems

    Tatsuya Onoguchi, Ayane Hayashi, Katsuyuki Utaka, Yuichi Matsushima, Keiji Kimura, Hironori Kasahara

    Information Processing Society of Japan, Special Interest Group on System Architecture (ARC217@ETNET2017)    2017.03

  • Parallel Processing of Automobile Real-time Control on Multicore System with Multiple Clusters

    Jin Miyata, Mamoru Shimaoka, Hiroki Mikami, Hirofumi Nishi, Hitoshi Suzuki, Keiji Kimura, Hironori Kasahara

    Information Processing Society of Japan, Special Interest Group on System Architecture (ARC217@ETNET2017)    2017.03

  • Code Generating Method with Profile Feedback for Reducing Compilation Time of Automatic Parallelizing Compiler

    Rina Fujino, Jixin Han, Mamoru Shimaoka, Hiroki Mikami, Takahiro Miyajima, Moriyuki Takamura, Keiji Kimura, Hironori Kasahara

    Information Processing Society of Japan, Special Interest Group on System Architecture (ARC217@ETNET2017)    2017.03

  • Automatic Local Memory Management for Multicores Having Global Address Space

    Kouhei Yamamoto, Tomoya Shirakawa, Yoshitake Oki, Akimasa Yoshida, Keiji Kimura, Hironori Kasahara

    LANGUAGES AND COMPILERS FOR PARALLEL COMPUTING, LCPC 2016   10136   282 - 296  2017  [Refereed]

    　View Summary

    Embedded multicore processors for hard real-time applications like automobile engine control require the usage of local memory on each processor core to precisely meet the real-time deadline constraints, since cache memory cannot satisfy the deadline requirements due to cache misses. To utilize local memory, programmers or compilers need to explicitly manage data movement and data replacement for local memory considering the limited size. However, such management is extremely difficult and time consuming for programmers. This paper proposes an automatic local memory management method by compilers through (i) multi-dimensional data decomposition techniques to fit working sets onto limited size local memory (ii) suitable block management structures, called Adjustable Blocks, to create application specific fixed size data transfer blocks (iii) multi-dimensional templates to preserve the original multi-dimensional representations of the decomposed multi-dimensional data that are mapped onto one-dimensional Adjustable Blocks (iv) block replacement policies from liveness analysis of the decomposed data, and (v) code size reduction schemes to generate shorter codes. The proposed local memory management method is implemented on the OSCAR multi-grain and multi-platform compiler and evaluated on the Renesas RP2 8 core embedded homogeneous multicore processor equipped with local and shared memory. Evaluations on 5 programs including multimedia and scientific applications show promising results. For instance, speedups on 8 cores compared to single core execution using off-chip shared memory on an AAC encoder program, a MPEG2 encoder program, Tomcatv, and Swim are improved from 7.14 to 20.12, 1.97 to 7.59, 5.73 to 7.38, and 7.40 to 11.30, respectively, when using local memory with the proposed method. These evaluations indicate the usefulness and the validity of the proposed local memory management method on real embedded multicore processors.

    DOI

    Scopus

    2
    Citation
    (Scopus)

  • Kasahara Voted 2017 Computer Society President-Elect

    Hironori Kasahara, Jean Luc Gaudiot

    Computer, IEEE Computer Society   49 ( 12 ) 90 - 92  2016.12

    DOI

  • Architecture Design for the Environmental Monitoring System over the Winter Season

    Koichiro Yamashita, Takahisa Suzuki, Hongchun Li, Chen Ao, Yi Xu, Jun Tian, Keiji Kimura, Hironori Kasahara

    Proceedings of the 14th ACM International Symposium on Mobility Management and Wireless Access     27 - 34  2016.11

    DOI

    Scopus

    2
    Citation
    (Scopus)

  • Reducing parallelizing compilation time by removing redundant analysis

    Jixin Han, Rina Fujino, Ryota Tamura, Mamoru Shimaoka, Hiroki Mikami, Moriyuki Takamura, Sachio Kamiya, Kazuhiko Suzuki, Takahiro Miyajima, Keiji Kimura, Hironori Kasahara

    SEPS 2016 - Proceedings of the 3rd International Workshop on Software Engineering for Parallel Systems, co-located with SPLASH 2016     1 - 9  2016.10  [Refereed]

    　View Summary

    Parallelizing compilers employing powerful compiler optimizations are essential tools to fully exploit performance from today's computer systems. These optimizations are supported by both highly sophisticated program analysis techniques and aggressive program restructuring techniques. However, the compilation time for such powerful compilers becomes larger and larger for real commercial application due to these strong program analysis techniques. In this paper, we propose a compilation time reduction technique for parallelizing compilers. The basic idea of the proposed technique is based on an observation that parallelizing compilers apply multiple program analysis passes and restructuring passes to a source program but all program analysis passes do not have to be applied to the whole source program. Thus, there is an opportunity for compilation time reduction by removing redundant program analysis. We describe the removing redundant program analysis techniques considering the inter-procedural propagation of analysis update information in this paper. We implement the proposed technique into OSCAR automatically multigrain parallelizing compiler. We then evaluate the proposed technique by using three proprietary large scale programs. The proposed technique can remove 37.7% of program analysis time on average for basic analysis includes def-use analysis and dependence calculation, and 51.7% for pointer analysis, respectively.

    DOI

    Scopus

    2
    Citation
    (Scopus)

  • A Compilation Framework for Multicores having Vector Accelerators using LLVM

    Akira Maruoka, Yuya Mushu, Satoshi Karino, Takashi Mochiyama, Toshiaki Kitamura, Sachio Kamiya, Moriyuki Takamura, Keiji Kimura, Hironori Kasahara

    Summer United Workshops on Parallel, Distributed and Cooperative Processing, Technical Report of IPSJ,Vol.2016-ARC-221 No.4    2016.08

  • Multigrain Parallelization of Program for Medical Image Filtering

    Mariko Okumura, Tomoyuki Shibasaki, Kohei Kuwajima, Hiroki Mikami, Keiji Kimura, Kohei Kadoshita, Keiichi Nakano, Hironori Kasahara

    Technical Report of IPSJ, 2016-HPC-153    2016.03

  • Automatic Multigrain Parallel Processing for 3D Noise Reduction Using OSCAR Compiler

    Tomoyuki Shibasaki, Kohei Kuwajima, Mariko Okumura, Hiroki Mikami, Keiji Kimura, Kohei Kadoshita, Keiichi Nakano, Hironori Kasahara

    Technical Report of IPSJ, 2016-HPC-153    2016.03

  • The parallelism abstraction method with a data conversion at analysis in a OSCAR compiler

    Naoto Kageura, Tamami Wake, Ji Xin Han, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2016-HPC-153    2016.03

  • Multigrain Parallelization Using Profile Information of Embedded Applications Generated by Model-based Development Tools on Multicore Processors

    Dan Umeda, Takahiro Suzuki, Hiroki Mikami, Keiji Kimura, Hironori Kasahara

    Trans. of IPSJ   57 ( 2 ) 1 - 12  2016.02  [Refereed]

  • Coarse grain task parallelization of earthquake simulator GMS using OSCAR compiler on various Cc-NUMA servers

    Mamoru Shimaoka, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)   9519   238 - 253  2016  [Refereed]

    　View Summary

    This paper proposes coarse grain task parallelization for a earthquake simulation program using Finite Difference Method to solve the wave equations in 3-D heterogeneous structure or the Ground Motion Simulator (GMS) on various cc-NUMA servers using IBM, Intel and Fujitsu multicore processors. The GMS has been developed by the National Research Institute for Earth Science and Disaster Prevention (NIED) in Japan. Earthquake wave propagation simulations are important numerical applications to save lives through damage predictions of residential areas by earthquakes. Parallel processing with strong scaling has been required to precisely calculate the simulations quickly. The proposed method uses the OSCAR compiler for exploiting coarse grain task parallelism efficiently to get scalable speed-ups with strong scaling. The OSCAR compiler can analyze data dependence and control dependence among coarse grain tasks, such as subroutines, loops and basic blocks. Moreover, locality optimizations considering the boundary calculations of FDM and a new static scheduler that enables more efficient task schedulings on cc-NUMA servers are presented. The performance evaluation shows 110 times speed-up using 128 cores against the sequential execution on a POWER7 based 128 cores cc-NUMA server Hitachi SR16000 VM1, 37.2 times speed-up using 64 cores against the sequential execution on a Xeon E7-8830 based 64 cores cc-NUMA server BS2000, 19.8 times speed-up using 32 cores against the sequential execution on a Xeon X7560 based 32 cores cc-NUMA server HA8000/RS440, 99.3 times speed-up using 128 cores against the sequential execution on a SPARC64 VII based 256 cores cc-NUMA server Fujitsu M9000, 9.42 times speed-up using 12 cores against the sequential execution on a POWER8 based 12 cores cc-NUMA server Power System S812L.

    DOI

    Scopus

  • Multigrain parallelization for model-based design applications using the OSCAR compiler

    Dan Umeda, Takahiro Suzuki, Hiroki Mikami, Keiji Kimura, Hironori Kasahara

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)   9519   125 - 139  2016  [Refereed]

    　View Summary

    Model-based design is a very popular software development method for developing a wide variety of embedded applications such as automotive systems, aircraft systems, and medical systems. Model-based design tools like MATLAB/Simulink typically allow engineers to graphically build models consisting of connected blocks for the purpose of reducing development time. These tools also support automatic C code generation from models with a special tool such as Embedded Coder to map models onto various kinds of embedded CPUs. Since embedded systems require real-time processing, the use of multi-core CPUs poses more opportunities for accelerating program execution to satisfy the real-time constraints. While prior approaches exploit parallelism among blocks by inspecting MATLAB/Simulink models, this may lose an opportunity for fully exploiting parallelism of the whole program because models potentially have parallelism within a block. To unlock this limitation, this paper presents an automatic parallelization technique for auto-generated C code developed by MATLAB/Simulink with Embedded Coder. Specifically, this work (1) exploits multi-level parallelism including inter-block and intra-block parallelism by analyzing the auto-generated C code, and (2) performs static scheduling to reduce dynamic overheads as much as possible. Also, this paper proposes an automatic profiling framework for the auto-generated code for enhancing static scheduling, which leads to improving the performance of MATLAB/Simulink applications. Performance evaluation shows 4.21 times speedup with six processor cores on Intel Xeon X5670 and 3.38 times speedup with four processor cores on ARM Cortex-A15 compared with uniprocessor execution for a road tracking application.

    DOI

    Scopus

    8
    Citation
    (Scopus)

  • Multicore Local Memory Management Scheme using Data Multidimensional Aligned Decomposition

    Kohei Yamamoto, Tomoya Shirakawa, Akimasa Yoshida, Keiji Kimura, Hironori Kasahara

    Information Processing Society of Japan, Special Interest Group on Embedded Systems(SIGEMB) Vol.2016-ARC-218No.10 Vol.2016-SLDM174No    2016.01

  • Android video processing system combined with automatically parallelized and power optimized code by OSCAR compiler

    Bui Duc Binh, Tomohiro Hirano, Hiroki Mikami, Hideo Yamamoto, Keiji Kimura, Hironori Kasahara

    Journal of Information Processing   24 ( 3 ) 504 - 511  2016  [Refereed]

    　View Summary

    The emergence of multi-core processors in smart devices promises higher performance and low power consumption. The parallelization of applications enables us to improve their performance. However, simultaneously utilizing many cores would drastically drain the device battery life. This paper shows a demonstration system of realtime video processing combined with power reduction controlled by the OSCAR automatic parallelization compiler on ODROID-X2, an open Android development platform based on Samsung Exynos4412 Prime with 4 ARM Cortext- A9 cores. In this paper, we exploited the DVFS framework, core partitioning, and profiling technique and OSCAR parallelization - power control algorithm to reduce the total consumption in a real-time video application. The demonstration results show that it can cut power consumption by 42.8% for MPEG-2 Decoder application and 59.8% for Optical Flow application by using 3 cores in both applications.

    DOI

    Scopus

  • Accelerating Multicore Architecture Simulation Using Application Profile

    Keiji Kimura, Gakuho Taguchi, Hironori Kasahara

    2016 IEEE 10TH INTERNATIONAL SYMPOSIUM ON EMBEDDED MULTICORE/MANY-CORE SYSTEMS-ON-CHIP (MCSOC)     177 - 184  2016  [Refereed]

    　View Summary

    Architecture simulators play an important role in exploring frontiers in the early stages of the architecture design. However, the execution time of simulators increases with an increase the number of cores. The sampling simulation technique that was originally proposed to simulate single-core processors is a promising approach to reduce simulation time. Two main hurdles for multi/many-core are preparing sampling points and thread skewing at functional simulation time. This paper proposes a very simple and low-error sampling-based acceleration technique for multi/many-core simulators. For a parallelized application, an iteration of a large loop including a parallelizable program part, is defined as a sampling unit. We apply X-means method to a profile result of the collection of iterations derived from a real machine to form clusters of those iterations. Multiple iterations are exploited as sampling points from these clusters. We execute the simulation along the sampling points and calculate the number of total execution cycles. Results from a 16-core simulation show that our proposed simulation technique gives us a maximum of 443x speedup with a 0.52% error and 218x speedup with 1.50% error on an average.

    DOI

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    2
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  • Annotatable systrace: An extended linux ftrace for tracing a parallelized program

    Daichi Fukui, Mamoru Shimaoka, Hiroki Mikami, Dominic Hillenbrand, Hideo Yamamoto, Keiji Kimura, Hironori Kasahara

    SEPS 2015 - Proceedings of the 2nd International Workshop on Software Engineering for Parallel Systems     21 - 25  2015.10  [Refereed]

    　View Summary

    Investigation of the runtime behavior is one of the most important processes for performance tuning on a computer system. Profiling tools have been widely used to detect hot-spots in a program. In addition to them, tracing tools produce valuable information especially from parallelized programs, such as thread scheduling, barrier synchronizations, context switching, thread migration, and jitter by interrupts. Users can optimize a runtime system and hardware configuration in addition to a program itself by utilizing the attained information. However, existing tools provide information per process or per function. Finer information like task-or loop-granularity should be required to understand the program behavior more precisely. This paper has proposed a tracing tool, Annotatable Systrace, to investigate runtime execution behavior of a parallelized program based on an extended Linux ftrace. The Annotatable Systrace can add arbitrary annotations in a trace of a target program. The proposed tool exploits traces from 183.equake, 179.art, and mpeg2enc on Intel Xeon X7560 and ARMv7 as an evaluation. The evaluation shows that the tool enables us to observe load imbalance along with the program execution. It can also generate a trace with the inserted annotations even on a 32-core machine. The overhead of one annotation on Intel Xeon is 1.07 us and the one on ARMv7 is 4.44 us, respectively.

    DOI

    Scopus

    3
    Citation
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  • Nominees for Computer Society Officers and Board of Governors Positions in 2016

    Jean-Luc Gaudiot, Hironori Kasahara

    IEEE Computer Society Computer     96 - 97  2015.08  [Invited]

  • Evaluation of Parallelization of video decoding on Intel and ARM Multicore

    Tamami Wake, Shuhei Iizuka, Hiroki Mikami, Keiji Kimura, Hironori Kasahara

    Information Processing Society of Japan, Special Interest Group on Embedded Systems(SIGEMB)    2015.03

  • Dynamic Scheduling Algorithm for Automatically Parallelized and Power Reduced Applications on Multicore Systems

    Takashi Goto, Kohei Muto, Tomohiro Hirano, Hiroki Mikami, Uichiro Takahashi(Fujitsu, Sakae Inoue(Fujitsu, Keiji Kimura, Hironori Kasahara

    Information Processing Society of Japan, Special Interest Group on Embedded Systems(SIGEMB)    2015.03

  • Power Reduction of Real-time Dynamic Image Processing on Haswell Multicore Using OSCAR Compiler

    Shuhei Iizuka, Hideo Yamamoto, Tomohiro Hirano, Youhei Kishimoto, Takashi Goto, Hiroki Mikami, Keiji Kimura, Hironori Kasahara

    Information Processing Society of Japan, Special Interest Group on Embedded Systems(SIGEMB)    2015.03

  • What Will 2022 Look Like? The IEEE CS 2022 Report

    Hasan Alkhatib, Paolo Faraboschi, Eitan Frachtenberg, Hironori Kasahara, Danny Lange, Phil Laplante, Arif Merchant, Dejan Milojicic, Karsten Schwan

    COMPUTER   48 ( 3 ) 68 - 76  2015.03  [Refereed]

    　View Summary

    Over the last two years, nine IEEE Computer Society tech leaders collaborated to identify important industry advances that promise to change the world by 2022. The 23 technologies provide new insights into the emergence of "seamless intelligence."

  • Evaluation of Automatic Power Reduction with OSCAR Compiler on Intel Haswell and ARM Cortex-A9 Multicores

    Tomohiro Hirano, Hideo Yamamoto, Shuhei Iizuka, Kohei Muto, Takashi Goto, Tamami Wake, Hiroki Mikami, Moriyuki Takamura, Keiji Kimura, Hironori Kasahara

    LANGUAGES AND COMPILERS FOR PARALLEL COMPUTING (LCPC 2014)   8967   239 - 252  2015  [Refereed]

    　View Summary

    Reducing power dissipation without performance degradation is one of the most important issues for all computing systems, such as supercomputers, cloud servers, desktop PCs, medical systems, smartphones and wearable devices. Exploiting parallelism, careful frequency-and-voltage control and clock-and-power-gating control for multicore/manycore systems are promising to attain performance improvements and reducing power dissipation. However, the hand parallelization and power reduction of application programs are very difficult and time-consuming. The OSCAR automatic parallelization compiler has been developed to overcome these problems by realizing automatic low-power control in addition to the parallelization. This paper evaluates performance of the low-power control technology of the OSCAR compiler on Intel Haswell and ARM multicore platforms. The evaluations show that the power consumption is reduced to 2/5 using 3 cores on the Intel Haswell multicore for the H. 264 decoder and 1/3 for Optical Flow on 3 cores with the power control compared with 3 cores without power control. On the ARM Cortex-A9 using 3 cores, the power control reduces power consumption to 1/2 with the H. 264 decoder and 1/3 with Optical Flow. These show that the OSCAR multi-platform compiler allows us to reduce the power consumption on Intel and ARM multicores.

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  • Evaluation of Software Cashe Coherency Cotrol Scheme by an Automatic Parallelizing Compiler

    Yohei Kishimoto, Masayoshi Mase, Keiji Kimura, Hironori Kasahara

    IPSJ SIG Technical Report Vol.2014-ARC-213 No.19    2014.12

  • Power Reduction of H.264/AVC Decoder on Android Multicore Using OSCAR Compiler

    Shuhei Iizuka, Hideo Yamamoto, Tomohiro Hirano, Takashi Goto, Hiroki Mikami, Uichiro Takahashi, Sakae Yamamoto, Moriyuki Takamura, Keiji Kimura, Hironori Kasahara

    IPSJ SIG Technical Report Vol.2014-ARC-204    2014.10

  • Expectation for Green Computing and Smart Grid

    Hironori Kasahara

    Technical Journal "Smart Grid", Special Issue `New Technologies for Smart Grid'     2 - 2  2014.10  [Refereed]  [Invited]

  • Prospect of Green Computing

    Keiji Kimura, Hironori Kasahara

    Technical Journal "Smart Grid", Special Issue `New Technologies for Smart Grid   55 ( 14 ) 3 - 8  2014.10  [Refereed]

  • Parallel Hashtable Building Using Serialization Based on Inter-Thread Pipes

    Makoto Nakayama, Kenichi Yamazaki(Shibaura, Institute of Technology, Satoshi Tanaka(NTT DOCOMO, Hironori Kasahara

    The IEICE Transactions on Information and Systems   Vol. J97-D(10) ( 10 ) 1541 - 1552  2014.10  [Refereed]

    J-GLOBAL

  • Automatic Parallelization of Designed Engine Control C Codes by MATLAB/Simulink

    Dan Umeda, Youhei Kanehagi, Hiroki Mikami, Akihiro Hayashi, Mituhiro Tani, DENSO, Yuji Mori, DENSO, Keiji Kimura, Hironori Kasahara

    Journal of Embedded System Symposium   55 ( 8 ) 1817 - 1829  2014.08  [Refereed]

    CiNii

  • Tracing method of a parallelized program using Linux ftrace on a multicore processor

    Daichi Fukui, Mamoru Shimaoka, Hiroki Mikami, Dominic Hillenbrand, Keiji Kimura, Hironori Kasahara

    Summer United Workshops on Parallel, Distributed and Cooperative Processing, Technical Report of IPSJ,Vol.2014-ARC-211 No.6    2014.07

  • Android Demonstration System of Automatic Parallelization and Power Optimization by OSCAR Compiler

    Bui Duc Binh, Tomohiro Hirano, Hiroki Mikami, Dominic Hillenbrand, Keiji Kimura, Hironori Kasahara

    Summer United Workshops on Parallel, Distributed and Cooperative Processing, Technical Report of IPSJ,Vol.2014-ARC-211 No.6    2014.07

  • Automatic Parallelization of Small Point FFT on Multicore Processor

    Yuuki Furuyama, Hiroki Mikami, Keiji Kimura, Hironori Kasahara

    IPSJ SIG Technical Report Vol.2013-ARC-201   113 ( 474 ) 15 - 22  2014.03

    　View Summary

    Fast Fourier Transorm (FFT) is one of the most frequently used algorihtms in many applications including digital signal processing and image processing to compute Descrite Fourier Transform (DFT). Although small size FFT programs must be used in baseband signal processing such as LTE and so on, it's difficult to use special hardwares like DSPs for computing such a small problem because of their relatively large data transfer and control overhead. This paper proposes an automatic parallelization method to generate parallelized programs with low overhead for small size FFTs suited for shared memory multicore processor by applying cache optimization to avoide false sharing between cores. The proposed method has been implemented in OSCAR automatic parallelizing compiler, parallelized small point FFT programs from 32 points to 256 points and evaluated them on RP2 multicore processor having 8 SH-4A cores. It achieved 1.97 times speedup on 2 SH-4A cores and 3.9 times speedup on 4 SH-4A cores in a 256 points FFT program. In addition to the FFT programs, the proposed approach is applied to Fast Hadamard Transform (FHT) which has similar computation to the FFT. The results are 1.91 times speedup on 2 SH-4A cores and 3.32 times speedup on 4 SH-4A cores. It shows effectiveness of the proposed method and easiness of applying the method to many kinds of programs.

    CiNii

  • A Latency Reduction Technique for IDS by Allocating Decomposed Signature on Multi-core

    Shohei Yamada, Keiji Kimura, Hironori Kasahara

    IPSJ SIG Technical Report Vol.2013-ARC-201    2014.03

  • A Parallelizing Compiler Cooperative Acceleration Technique of Multicore Architecture Simulation using a Statistical Method

    Gakuho Taguchi, Keiji Kimura, Hironori Kasahara

    IPSJ SIG Technical Report    2014.03

  • Multicore Technologies Realizing Low-power Computing

    Keiji Kimura, Hironori Kasahara

    The Journal of Electronics, Information and Communication Engineers   97 ( 2 ) 133 - 139  2014.02  [Refereed]

    CiNii

  • OSCAR Compiler Controlled Multicore Power Reduction on Android Platform

    Hideo Yamamoto, Tomohiro Hirano, Kohei Muto, Hiroki Mikami, Takashi Goto, Dominic Hillenbrand, Moriyuki Takamura, Keiji Kimura, Hironori Kasahara

    LANGUAGES AND COMPILERS FOR PARALLEL COMPUTING, LCPC 2013   8664   155 - 168  2014  [Refereed]

    　View Summary

    In recent years, smart devices are transitioning from single core processors to multicore processors to satisfy the growing demands of higher performance and lower power consumption. However, power consumption of multicore processors is increasing, as usage of smart devices become more intense. This situation is one of the most fundamental and important obstacle that the mobile device industries face, to extend the battery life of smart devices. This paper evaluates the power reduction control by the OSCAR Automatic Parallelizing Compiler on an Android platform with the newly developed precise power measurement environment on the ODROID-X2, a development platform with the Samsung Exynos4412 Prime, which consists of 4 ARM Cortex-A9 cores. The OSCAR Compiler enables automatic exploitation of multigrain parallelism within a sequential program, and automatically generates a parallelized code with the OSCAR Multi-Platform API power reduction directives for the purpose of DVFS (Dynamic Voltage and Frequency Scaling), clock gating, and power gating. The paper also introduces a newly developed micro second order pseudo clock gating method to reduce power consumption using WFI (Wait For Interrupt). By inserting GPIO (General Purpose Input Output) control functions into programs, signals appear on the power waveform indicating the point of where the GPIO control was inserted and provides a precise power measurement of the specified program area. The results of the power evaluation for real-time Mpeg2 Decoder show 86.7% power reduction, namely from 2.79[W] to 0.37[W] and for real-time Optical Flow show 86.5% power reduction, namely from 2.23[W] to 0.36[W] on 3 core execution.

    DOI

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    2
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  • Parallelization of Tree-to-TLV Serialization

    Makoto Nakayama, Kenichi Yamazaki, Satoshi Tanaka, Hironori Kasahara

    2014 IEEE INTERNATIONAL PERFORMANCE COMPUTING AND COMMUNICATIONS CONFERENCE (IPCCC)    2014  [Refereed]

    　View Summary

    A serializer/deserializer (SerDe) is necessary to serialize a data object into a byte array and to deserialize in reverse direction. A SerDe that is used worldwide and runs quickly is the Protocol Buffer (ProtoBuf), which serializes a tree-structured data object into the Type-Length-Value (TLV) format. Acceleration of SerDe processing is beneficial because SerDes are used in various fields. This paper proposes a new method that accelerates the tree-to-TLV serialization through 2-way parallel processing called "parallelized serialization" and "parallelization with streaming". Experimental results show that parallelized serialization with 4 worker threads achieves a 1.97 fold shorter serialization time than when using a single worker thread, and the combination of 2-way parallel processing achieves a 2.11 fold shorter output time than that for ProtoBuf when 4 worker threads, FileOutputStream and trees of 10,080 container nodes are used.

  • Profile-Based Automatic Parallelization for Android 2D Rendering by Using OSCAR Compiler

    Takashi Goto, Kohei Muto, Hideo Yamamoto, Tomohiro Hirano, Hiroki Mikami, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, Vol.2013-ARC-207 No.12    2013.12

  • New SerDe Featured by Precompression Using Knowledge of Redundant Subtrees

    Makoto Nakayama, Kenichi Yamazaki(Shibaura, Institute of Technology, Satoshi Tanaka(NTT DOCOMO, Hironori Kasahara

    The IEICE Transactions on Information and Systems   Vol. J96-D(10) ( Vol. J96-D(10) ) 2089 - 2100  2013.10  [Refereed]

    CiNii

  • An Evaluation of Hardware Barrier Synchronization Mechanism Considering Hierarchical Processor Grouping using OSCAR API Standard Translator

    Akihiro Kawashima, Youhei Kanehagi, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara

    Summer United Workshops on Parallel, Distributed and Cooperative Processing, Technical Report of IPSJ, Vol.2013-ARC-206 No.16    2013.08

  • Automatic Power Control on Multicore Android Devices

    Tomohiro Hirano, Hideo Yamamoto, Kohei Muto, Hiroki Mikami, Takashi Goto, Dominic Hillenbrand, Keiji Kimura, Hironori Kasahara

    Summer United Workshops on Parallel, Distributed and Cooperative Processing, Technical Report of IPSJ, Vol.2013-ARC-206 No.23    2013.08

  • Automatic Parallelization of Hand Written Automotive Engine Control Codes Using OSCAR Compiler

    Dan Umeda, Yohei Kanehagi, Hiroki Mikami, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara

    17th Workshop on Compilers for Parallel Computing (CPC2013), Lyon, France    2013.07  [Refereed]

  • OSCAR API v2.1: Extensions for an Advanced Accelerator Control Scheme to a Low-Power Multicore API

    Keiji Kimura, Cecilia Gonzáles-Álvarez, Akihiro Hayashi, Hiroki Mikami, Mamoru Shimaoka, Jun Shirako, Hironori Kasahara

    17th Workshop on Compilers for Parallel Computing (CPC2013), Lyon, France    2013.07  [Refereed]

  • Enhancing the Performance of a Multiplayer Game by Using a Parallelizing Compiler

    Yasir I. M. Al-Dosary, Yuki Furuyama, Dominic Hillenbrand, Keiji Kimura, Hironori Kasahara, Seinosuke Narita

    Technical Report of IPSJ    2013.04  [Refereed]

    　View Summary

    Video Games have been a very popular form of digital entertainment in recent years. They have been delivered in state of the art technologies that include multi-core processors that are known to be the leading contributor in enhancing the performance of computer applications. Since parallel programming is a difficult technology to implement, that field in Video Games is still rich with areas for advancements. This paper investigates performance enhancement in Video Games when using parallelizing compilers and the difficulties involved in achieving that. This experiment conducts several stages in attempting to parallelize a well-renowned sequentially written Video Game called ioquake3. First, the Game is profiled for discovering bottlenecks, then examined by hand on how much parallelism could be extracted from those bottlenecks, and what sort of hazards exist in delivering a parallel-friendly version of ioquake3. Then, the Game code is rewritten into a hazard-free version while also modified to comply with the Parallelizable-C rules, which crucially aid parallelizing compilers in extracting parallelism. Next, the program is compiled using a parallelizing compiler called OSCAR (Optimally Scheduled Advanced Multiprocessor) to produce a parallel version of ioquake3. Finally, the performance of the newly produced parallel version of ioquake3 on a Multi-core platform is analyzed.
    The following is found: (1) the parallelized game by the compiler from the revised sequential program of the game is found to achieve a 5.1 faster performance at 8-threads than original one on an IBM Power 5+ machine that is equipped with 8-cores, and (2) hazards are caused by thread contentions over globally shared data, and as well as thread private data, and (3) AI driven players are represented very similarly to Human players inside ioquake3 engine, which gives an estimation of the costs for parallelizing Human driven sessions, and (4) 70% of the costs of the experiment is spent in analyzing ioquake3 code, 30% in implementing the changes in the code.

  • An Investigation of Parallelization and Evaluation on Commercial Multi-core Smart Device

    Hideo Yamamoto, Takashi Goto, Tomohiro Hirano, Kouhei Muto, Hiroki Mikami, Dominic Hillenbrand, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, Vol. 2013-OS-124 No. 000310    2013.02

  • Languages and Compilers for Parallel Computing: 25th International Workshop, LCPC 2012, Tokyo, Japan, September 11-13, 2012, Revised Selected Papers

    Hironori Kasahara, Keiji Kimura

    Lecture Notes in Computer Science   7760  2013

  • Evaluation of power consumption at execution of multiple automatically parallelized and power controlled media applications on the RP2 low-power multicore

    Hiroki Mikami, Shumpei Kitaki, Masayoshi Mase, Akihiro Hayashi, Mamoru Shimaoka, Keiji Kimura, Masato Edahiro, Hironori Kasahara

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)   7146   31 - 45  2013  [Refereed]

    　View Summary

    This paper evaluates an automatic power reduction scheme of OSCAR automatic parallelizing compiler having power reduction control capability when multiple media applications parallelized by the OSCAR compiler are executed simultaneously on RP2, a 8-core multicore processor developed by Renesas Electronics, Hitachi, and Waseda University. OSCAR compiler enables the hierarchical multigrain parallel processing and power reduction control using DVFS (Dynamic Voltage and Frequency Scaling), clock gating and power gating for each processor core using the OSCAR multi-platform API. The RP2 has eight SH4A processor cores, each of which has power control mechanisms such as DVFS, clock gating and power gating. First, multiple applications with relatively light computational load are executed simultaneously on the RP2. The average power consumption of power controlled eight AAC encoder programs, each of which was executed on one processor, was reduced by 47%, (to 1.01W), against one AAC encoder execution on one processor (from 1.89W) without power control. Second, when multiple intermediate computational load applications are executed, the power consumptions of an AAC encoder executed on four processors with the power reduction control was reduced by 57% (to 0.84W) against an AAC encoder execution on one processor (from 1.95W). Power consumptions of one MPEG2 decoder on four processors with power reduction control was reduced by 49% (to 1.01W) against one MPEG2 decoder execution on one processor (from 1.99W). Finally, when a combination of a high computational load application program and an intermediate computational load application program are executed simultaneously, the consumed power reduced by 21% by using twice number of cores for each application. This paper confirmed parallel processing and power reduction by OSCAR compiler are efficient for multiple application executions. In execution of multiple light computational load applications, power consumption increases only 12% for one application. Parallel processing being applied to intermediate computational load applications, power consumption of executing one application on one processor core (1.49W) is almost same power consumption of two applications on eight processor cores (1.46W). © 2013 Springer-Verlag.

    DOI

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  • Parallelization of Automobile Engine Control Software on Multicore Processor

    Youhei Kanehagi, Dan Umeda, Hiroki Mikami, Akihiro Hayashi, Mitsuo Sawada(TOYOTA, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, Vol.2013-ARC-203 No.2    2013.01

  • An Acceleration Technique of Many-core Architecture Simulation with Parallelized Applications by Statistical Technique

    Yoichi Abe, Gakuho Taguchi, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, Vol.2012-ARC-203 N0.13    2013.01

  • A Parallelizing Compiler Cooperative Multicore Architecture Simulator with Changeover Mechanism of Simulation Modes

    Gakuho Taguchi, Yoichi Abe, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, Vol.2012-ARC-203 N0.14    2013.01

  • Automatic Design Exploration Framework for Multicores with Reconfigurable Accelerators

    Cecilia Gonzalez-Alvarez, Haruku Ishikawa, Akihiro Hayashi, Daniel Jimenez-Gonzalez, Carlos Alvarez, Keiji Kimura, Hironori Kasahara

    7th Workshop on Reconfigurable Computing (WRC) 2013, held in conjuction with HiPEAC conference 2013, Berlin    2013.01  [Refereed]

  • Automatic Parallelization, Performance Predictability and Power Control for Mobile-Applications

    Dominic Hillenbrand, Akihiro Hayashi, Hideo Yamamoto, Keiji Kimura, Hironori Kasahara

    2013 IEEE COOL CHIPS XVI (COOL CHIPS)    2013  [Refereed]

    　View Summary

    Currently few mobile applications exploit the power- and performance capabilities of multi-core architectures. As the number of cores increases, the challenges become more pressing. We picked three challenges: application parallelization, performance-predictability/portability and power control for mobile devices. We tackled the challenges with our auto-parallelizing compiler and operating system enhancements.

  • Parallelization of Automotive Engine Control Software On Embedded Multi-core Processor Using OSCAR Compiler

    Yohei Kanehagi, Dan Umeda, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara

    2013 IEEE COOL CHIPS XVI (COOL CHIPS)    2013  [Refereed]

  • Reconciling application power control and operating systems for optimal power and performance

    Dominic Hillenbrand, Yuuki Furuyama, Akihiro Hayashi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara

    2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC 2013    2013  [Refereed]

    　View Summary

    In the age of dark silicon on-chip power control is a necessity. Upcoming and state of the art embedded- and cloud computer system-on-chips (SoCs) already provide interfaces for fine grained power control. Sometimes both: core- and interconnect-voltage and frequency can be scaled for example. To further reduce power consumption SoCs often have specialized accelerators. Due to the rising specialization of hard- and software general purpose operating systems require changes to exploit the power saving opportunities provided by the hardware. However, they lack detailed hardware- and application-level-information. Application-level power control in turn is still very uncommon and difficult to realize. Now a days vendors of mobile devices are forced to tweak and patch system-level software to enhance the power efficiency of each individual product. This manual process is time consuming and must be re-iterated for each new product. In this paper we explore the opportunities and challenges of automatic application- level power control using compilers. © 2013 IEEE.

    DOI

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  • Dynamic Profiling and Feedback Framework for Reduce-side Join

    Makoto Nakayama, Kenichi Yamazaki, Satoshi Tanaka, Hironori Kasahara

    2013 IEEE 16TH INTERNATIONAL CONFERENCE ON COMPUTATIONAL SCIENCE AND ENGINEERING (CSE 2013)     1255 - 1262  2013  [Refereed]

    　View Summary

    MapReduce has become popular and Reduce-side join is one of the most important application of MapReduce. Data skew, in which the data load assigned to each Reduce task fluctuates task by task, increases the MapReduce job completion time. This paper proposes a dynamic profiling and feedback framework that works on a MapReduce cluster. The framework allows programmers to build their own algorithm to address data skew on Reduce-side join based on their specific knowledge and/or requirements. This paper also proposes an estimation method which makes our framework adapt to a wide range of MapReduce cluster sizes. This paper presents two example algorithms to address data skew using the estimation method, and the experimental results shows up to 2.59 times speed-up of join completion time on a cluster with 50 servers and highly skewed input data.

    DOI

    Scopus

  • Automatic parallelization with OSCAR API Analyzer: a cross-platform performance evaluation

    Cecilia Gonzalez-Alvarez, Youhei Kanehagi, Kosei Takemoto, Yohei Kishimoto, Kohei Muto, Hiroki Mikami, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, Vol.2012-ARC-202HPC137 No.10    2012.12

  • Automatic Parallelization of Ground Motion Simulator

    Mamoru Shimaoka, Hiroki Mikami, Akihiro Hayashi, Yasutaka Wada, Keiji Kimura, Hidekazu Morita, HITACHI, Kunio Uchiyama, HITACHI, Hironori Kasahara

    Technical Report of IPSJ, Vol.2012-ARC-202HPC137 No.11    2012.12

  • Opportunities and Challenges of Application-Power Control in the Age of Dark Silicon

    Dominic Hillenbrand, Yuuki Furuyama, Akihiro Hayashi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, Vol.2012-ARC-202HPC137 No.26    2012.12

  • Parallelization of Basic Engine Controll Software Model on Multicore Processor

    Dan Umeda, Youhei Kanehagi, Hiroki Mikami, Akihiro Hayashi, Mituhiro Tani, DENSO, Yuji Mori, DENSO, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, Vol.2012-ARC-201 No.22    2012.08

  • Realization of 1 Watt Web Service with RP-X Low-power Multicore Processor

    Yuuki Furuyama, Mamoru Shimaoka, Hiroki Mikami, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, Vol.2012-ARC-201 No.24    2012.08

  • Low Power Consumption Multicore Technology for Green Computing

    Hironori Kasahara

    Tokugicon Patent Office Society, Japan Patent Office   265   31 - 42  2012.05  [Refereed]

  • A Definition of Parallelizable C by JISX0180:2011 "Framework of establishing coding guidelines for embedded system development" (to appear)

    Keiji Kimura, Masayoshi Mase, Hironori Kasahara

    ETNET2012    2012.03

  • Inlining Analysis of Exception Flow and Fast Method Dispatch on Automatic Parallelization of Java

    Keiichi Tabata, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, Vol. 2012-ARC-199, No. 9    2012.03

  • An Examination of Accelerating Many-core Architecture Simulation for Parallelized Media Applications

    Yoichi Abe, Ryo Ishizuka, Ryota Daigo, Gakuho Taguchi, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, Vol. 2012-ARC-199, No. 3    2012.03

  • OSCAR Parallelizing Compiler and API for Real-time Low Power Heterogeneous Multicores

    Akihiro Hayashi, Mamoru Shimaoka, Hiroki Mikami, Masayoshi Mase, Yasutaka Wada, Jun Shirako, Keiji Kimura, Hironori Kasahara

    16th Workshop on Compilers for Parallel Computing(CPC2012), Padova, Italy    2012.01  [Refereed]

  • Enhancing the Performance of a Multiplayer Game by Using a Parallelizing Compiler

    Yasir I. M. Al-Dosary, Keiji Kimura, Hironori Kasahara, Seinosuke Narita

    2012 17TH INTERNATIONAL CONFERENCE ON COMPUTER GAMES (CGAMES)     67 - 75  2012  [Refereed]

    　View Summary

    Video Games have been a very popular form of digital entertainment in recent years. They have been delivered in state of the art technologies that include multi-core processors that are known to be the leading contributor in enhancing the performance of computer applications. Since parallel programming is a difficult technology to implement, that field in Video Games is still rich with areas for advancements. This paper investigates performance enhancement in Video Games when using parallelizing compilers and the difficulties involved in achieving that. This experiment conducts several stages in attempting to parallelize a well-renowned sequentially written Video Game called ioquake3. First, the Game is profiled for discovering bottlenecks, then examined by hand on how much parallelism could be extracted from those bottlenecks, and what sort of hazards exist in delivering a parallel-friendly version of ioquake3. Then, the Game code is rewritten into a hazard-free version while also modified to comply with the Parallelizable-C rules, which crucially aid parallelizing compilers in extracting parallelism. Next, the program is compiled using a parallelizing compiler called OSCAR (Optimally Scheduled Advanced Multiprocessor) to produce a parallel version of ioquake3. Finally, the performance of the newly produced parallel version of ioquake3 on a Multi-core platform is analyzed.
    The following is found: (1) the parallelized game by the compiler from the revised sequential program of the game is found to achieve a 5.1 faster performance at 8-threads than original one on an IBM Power 5+ machine that is equipped with 8-cores, and (2) hazards are caused by thread contentions over globally shared data, and as well as thread private data, and (3) AI driven players are represented very similarly to Human players inside ioquake3 engine, which gives an estimation of the costs for parallelizing Human driven sessions, and (4) 70% of the costs of the experiment is spent in analyzing ioquake3 code, 30% in implementing the changes in the code.

  • Automatic Parallelization of Dose Calculation Engine for A Particle Therapy on SMP Servers

    Akihiro Hayashi, Takuji Matsumoto, Hiroki Mikami, Keiji Kimura, Keiji Yamamoto, Hironori Saki, Yasuyuki Takatani, Hironori Kasahara

    Technical Report of IPSJ, Vol.2011-ARC189HPC132-2    2011.11

  • Parallelizing Compiler Framework and API for Heterogeneous Multicores

    Akihiro Hayashi, Yasutaka Wada, Takeshi Watanabe, Takeshi Sekiguchi, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara

    IPSJ Transactions on Advanced Computing Systems   5   68 - 79  2011.11  [Refereed]

  • An Evaluation of An Acceleration Technique of Many Core Architecture Simulator Considering Science Technology Calculation Program Structure

    Ryo Ishizuka, Yoichi Abe, Ryota Daigo, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, Vol.2011-ARC-196-14    2011.07

  • Examination of Parallelization by CUDA in SPEC benchmark program

    Yuki Taira, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, Vol.2011-HPC-130-16    2011.07

  • Hiding I/O overheads with Parallelizing Compiler for Media Applications

    Akihiro Hayashi, Takeshi Sekiguchi, Masayoshi Mase, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

    Techinical Report of IPSJ, Vol.2011-ARC-195OS117-14   2011 ( 14 ) 1 - 7  2011.04

    CiNii

  • A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core

    Osamu Nishii, Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima

    IEICE TRANSACTIONS ON ELECTRONICS   E94C ( 4 ) 663 - 669  2011.04  [Refereed]

    　View Summary

    We built a 12.4 mm x 12.4 mm, 45-nm CMOS, chip that integrates eight 648-MHz general purpose cores, two matrix processor (MX-2) cores, four flexible engine (FE) cores and media IP (VPU5) to establish heterogeneous multi-core chip architecture. The general purpose core had its IPC (instructions per cycle) performance enhanced by adding 32-bit instructions to the existing 16-bit fixed-length instruction set and executing up to two 32-bit instructions per cycle. Considering these five-to-seven years of embedded LSI and increasing trend of access-master within LSI, we predict that the memory usage of single core will not exceed 32-bit physical area (i.e. 4 GB), but chip-total memory usage will exceed 4 GB. Based on this prediction, the physical address was expanded from 32-bit to 40-bit. The fabricated chip was tested and a parallel operation of eight general purpose cores and four FE cores and eight data transfer units (DTU) is obtained on AAC (Advanced Audio Coding) encode processing.

    DOI

    Scopus

  • Evaluation of Power Consumption by Executing Media Applications on Low-power Multicore RP2

    Hiroki Mikami, Shumpei Kitaki, Takafumi Sato, Masayoshi Mase, Keiji Kimura, Kazuhisa Ishizaka, Junji Sakai, Masato Edahiro, Hironori Kasahara

    Technical Report of IPSJ, 2011-ARC-194-1    2011.03

  • A parallelizing compiler cooperative heterogeneous multicore processor architecture

    Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)   6760   215 - 233  2011  [Refereed]

    　View Summary

    Heterogeneous multicore architectures, integrating several kinds of accelerator cores in addition to general purpose processor cores, have been attracting much attention to realize high performance with low power consumption. To attain effective high performance, high application software productivity, and low power consumption on heterogeneous multicores, cooperation between an architecture and a parallelizing compiler is important. This paper proposes a compiler cooperative heterogeneous multicore architecture and parallelizing compilation scheme for it. Performance of the proposed scheme is evaluated on the heterogeneous multicore integrating Hitachi and Renesas' SH4A processor cores and Hitachi's FE-GA accelerator cores, using an MP3 encoder. The heterogeneous multicore gives us 14.34 times speedup with two SH4As and two FE-GAs, and 26.05 times speedup with four SH4As and four FE-GAs against sequential execution with a single SH4A. The cooperation between the heterogeneous multicore architecture and the parallelizing compiler enables to achieve high performance in a short development period. © 2011 Springer-Verlag Berlin Heidelberg.

    DOI

  • Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-Time Heterogeneous Multicores

    Akihiro Hayashi, Yasutaka Wada, Takeshi Watanabe, Takeshi Sekiguchi, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara

    LANGUAGES AND COMPILERS FOR PARALLEL COMPUTING   6548   184 - 198  2011  [Refereed]

    　View Summary

    Heterogeneous multicores have been attracting much attention to attain high performance keeping power consumption low in wide spread of areas. However, heterogeneous multicores force programmers very difficult programming. The long application program development period lowers product competitiveness. In order to overcome such a situation, this paper proposes a compilation framework which bridges a gap between programmers and heterogeneous multicores. In particular, this paper describes the compilation framework based on OSCAR compiler. It realizes coarse grain task parallel processing, data transfer using a DMA controller, power reduction control from user programs with DVFS and clock gating on various heterogeneous multicores from different vendors. This paper also evaluates processing performance and the power reduction by the proposed framework on a newly developed 15 core heterogeneous multicore chip named RP-X integrating 8 general purpose processor cores and 3 types of accelerator cores which was developed by Renesas Electronics, Hitachi, Tokyo Institute of Technology and Waseda University. The framework attains speedups up to 32x for an optical flow program with eight general purpose processor cores and four DRP(Dynamically Reconfigurable Processor) accelerator cores against sequential execution by a single processor core and 80% of power reduction for the real-time AAC encoding.

  • A parallelizing compiler cooperative heterogeneous multicore processor architecture

    Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)   6760   215 - 233  2011  [Refereed]

    　View Summary

    Heterogeneous multicore architectures, integrating several kinds of accelerator cores in addition to general purpose processor cores, have been attracting much attention to realize high performance with low power consumption. To attain effective high performance, high application software productivity, and low power consumption on heterogeneous multicores, cooperation between an architecture and a parallelizing compiler is important. This paper proposes a compiler cooperative heterogeneous multicore architecture and parallelizing compilation scheme for it. Performance of the proposed scheme is evaluated on the heterogeneous multicore integrating Hitachi and Renesas' SH4A processor cores and Hitachi's FE-GA accelerator cores, using an MP3 encoder. The heterogeneous multicore gives us 14.34 times speedup with two SH4As and two FE-GAs, and 26.05 times speedup with four SH4As and four FE-GAs against sequential execution with a single SH4A. The cooperation between the heterogeneous multicore architecture and the parallelizing compiler enables to achieve high performance in a short development period. © 2011 Springer-Verlag Berlin Heidelberg.

    DOI

  • Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-Time Heterogeneous Multicores

    Akihiro Hayashi, Yasutaka Wada, Takeshi Watanabe, Takeshi Sekiguchi, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara

    LANGUAGES AND COMPILERS FOR PARALLEL COMPUTING   6548   184 - 198  2011  [Refereed]

    　View Summary

    Heterogeneous multicores have been attracting much attention to attain high performance keeping power consumption low in wide spread of areas. However, heterogeneous multicores force programmers very difficult programming. The long application program development period lowers product competitiveness. In order to overcome such a situation, this paper proposes a compilation framework which bridges a gap between programmers and heterogeneous multicores. In particular, this paper describes the compilation framework based on OSCAR compiler. It realizes coarse grain task parallel processing, data transfer using a DMA controller, power reduction control from user programs with DVFS and clock gating on various heterogeneous multicores from different vendors. This paper also evaluates processing performance and the power reduction by the proposed framework on a newly developed 15 core heterogeneous multicore chip named RP-X integrating 8 general purpose processor cores and 3 types of accelerator cores which was developed by Renesas Electronics, Hitachi, Tokyo Institute of Technology and Waseda University. The framework attains speedups up to 32x for an optical flow program with eight general purpose processor cores and four DRP(Dynamically Reconfigurable Processor) accelerator cores against sequential execution by a single processor core and 80% of power reduction for the real-time AAC encoding.

  • Evaluation of Parallelizable C Programs by the OSCAR API Standard Translator

    Takuya Sato, Hiroki Mikami, Akihiro Hayashi, Masayoshi Mase, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2010-ARC-191-2   2010 ( 2 ) 1 - 6  2010.10

    CiNii

  • Performance of Power Reduction Scheme by a Compiler on Heterogeneous Multicore for Consumer Electronics "RP-X"

    Yasutaka Wada, Akihiro Hayashi, Takeshi Watanabe, Takeshi Sekiguchi, Masahiro Mase, Jun Shirako, Keiji Kimura, Masayuki Ito, Jun Hasegawa, Makoto Sato, Tohru Nojiri, Kunio Uchiyama, Hironori Kasahara

    Technical Report of IPSJ, 2010-ARC-190-8(SWoPP2010)    2010.08

  • A Compiler Framework for Heterogeneous Multicores for Consumer Electronics

    Akihiro Hayashi, Yasutaka Wada, Takeshi Watanabe, Takeshi Sekiguchi, Masahiro Mase, Keiji Kimura, Masayuki Ito, Jun Hasegawa, Makoto Sato, Tohru Nojiri, Kunio Uchiyama, Hironori Kasahara

    Technical Report of IPSJ, 2010-ARC-190-7(SWoPP2010)    2010.08

  • An Acceleration Technique of Many Core Architecture Simulator Considering Program Structure

    Ryo Ishizuka, Toshiya Ootomo, Ryouta Daigo, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2010-ARC-190-20    2010.07

  • Parallelizable C and Its Performance on Low Power High Performance Multicore Processors

    Masayoshi Mase, Yuto Onozaki, Keiji Kimura, Hironori Kasahara

    15th Workshop on Compilers for Parallel Computing 2010    2010.07  [Refereed]

  • Parallelizing Compiler Directed Software Coherence

    Masayoshi Mase, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2010-ARC-189-7   2010 ( 7 ) 1 - 10  2010.04

    CiNii

  • Processing Performance of Automatically Parallelized Applications on Embedded Multicore with Running Multiple Applications

    Takamichi Miyamoto, Masayoshi Mase, Keiji Kimura, Kazuhisa Ishizaka, Junji Sakai, Masato Edahiro, Hironori Kasahara

    Technical Report of IPSJ   2010-ARC-188 ( 9 )  2010.03

  • Hierarchical Parallel Processing of H.264/AVC Encoder on an Multicore Processeor

    Hiroki Mikami, Takamichi Miyamoto, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJVol.2010-ARC-187 No.22 Vol.2010-EMB-15 No.22    2010.01

  • OSCAR API for Real-Time Low-Power Multicores and Its Performance on Multicores and SMP Servers

    Keiji Kimura, Masayoshi Mase, Hiroki Mikami, Takamichi Miyamoto, Jun Shirako, Hironori Kasahara

    LANGUAGES AND COMPILERS FOR PARALLEL COMPUTING   5898   188 - 202  2010  [Refereed]

    　View Summary

    OSCAR (Optimally Scheduled Advanced Multiprocessor) API has been designed for real-time embedded low-power multicores to generate parallel programs for various multicores from different vendors by using the OSCAR parallelizing compiler. The OSCAR API has been developed by Waseda University in collaboration with Fujitsu Laboratory, Hitachi, NEC, Panasonic, Renesas Technology, and Toshiba in an METI/NEDO project entitled "Multicore Technology for Realtime Consumer Electronics." By using the OSCAR API as an interface between the OSCAR compiler and backend compilers, the OSCAR compiler enables hierarchical multigrain parallel processing with memory optimization under capacity restriction for cache memory, local memory, distributed shared memory, and on-chip/off-chip shared memory; data transfer using a DMA controller; and power reduction control using DVFS (Dynamic Voltage and Frequency Scaling), clock gating, and power gating for various embedded multicores. In addition, a parallelized program automatically generated by the OSCAR, compiler with OSCAR API can be compiled by the ordinary OpenMP compilers since the OSCAR API is designed on a subset of the OpenMP. This paper describes the OSCAR API and its compatibility with the OSCAR compiler by showing code examples. Performance evaluations of the OSCAR compiler and the OSCAR. API are carried out using an IBM Power5+ workstation, an IBM Power6 high-end SMP server, and a newly developed consumer electronics multicore chip RP2 by Renesas, Hitachi and Waseda. From the results of scalability evaluation, it is found that on an average, the OSCAR compiler with the OSCAR API can exploit 5.8 times speedup over the sequential execution on the Power5+ workstation with eight cores and 2.9 times speedup on RP2 with four cores, respectively. In addition, the OSCAR compiler can accelerate an IBM XL Fortran compiler up to 3.3 times on the Power6 SMP server. Due to low-power optimization on RP2, the OSCAR compiler with the OSCAR API achieves a maximum power reduction of 84% in the real-time execution mode.

  • Research and Development of Advanced Low Power Computer (Multicore/Manycore)Hardware and Software

    Hironori Kasahara

    EWE   ( 51 )  2009.11

    Authorship：Lead author

  • Element-Sensitive Pointer Analysis for Automatic Parallelization

    Masayoshi Mase, Keiji Kimura, Hironori Kasahara, Yuta murata

    IPSJ-SIGPRO    2009.10

  • Roles of Parallelizing Compilers for Low Power Manycores”, Panel: "What do compiler optimizations mean for many-cores?"

    Hironori Kasahara

    The 22nd International Workshop on Languages and Compilers for Parallel Computing (LCPC09)    2009.10  [Refereed]

  • 太陽電池で駆動できる低消費電力マルチコアプロセッサとソフトウェア

    笠原博徳

    Waseda University DCC Industry and Academia Cooperation Forum    2009.09  [Refereed]

  • Automatic Parallelization of Parallelizable C Programs on Multicore Processors

    Masayoshi Mase, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2009-ARC-184-15(SWoPP2009)    2009.08

  • Compiler Technology and API for Multi-Core

    Hironori Kasahara, Jun Shirako

    The IEEE Computer Society 2009 Vail Computer Elements Workshop    2009.06  [Refereed]

  • Parallelizing Compiler and API for Low Power Multicores

    Hironori Kasahara

    LSI and Systems Workshop 2009    2009.05  [Refereed]

  • 低消費電力マルチコアのための並列化コンパイラ及びAPI

    笠原 博徳

    LSIとシステムのワークショップ2009「エネルギーと環境のためのLSIとシステム」    2009.05  [Refereed]

  • マルチコア上でのOSCAR APIを用いた並列化コンパイラによる低消費電力化手法

    中川亮, 間瀬正啓, 白子準, 木村啓二, 笠原博徳

    SACSIS2009 - 先進的計算基盤システムシンポジウム    2009.05  [Refereed]

  • A Power Reduction Scheme for Parallelizing Compiler Using OSCAR API on Multicore Processors

    Ryo Nakagawa, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara

    Symposium on Advanced Computing Systems and Infrastructures (SACSIS 2009)    2009.05  [Refereed]

  • 組み込みマルチコアが開く新市場とそれを支える並列コンパイラ技術の最前線

    笠原 博徳

    組み込みプロセッサ&プラットホーム・ワークショップ2009    2009.04  [Refereed]

  • New Markets Opened by Embedded Multicores and Forefront of Parallelizing Compiler Technology

    Hironori Kasahara

    Embedded Processor and Platform Workshop 2009    2009.04  [Refereed]

  • OSCAR Parallelizing Compiler and API for Low Power High Performance Multicores

    Hironori Kasahara

    The 11th International Specialist Meeting on The Next generation Models on Climate Change and Sustainability for Adavanced High-performance Computing Facilities (Climate Meeting 2009)    2009.03  [Refereed]

  • 低消費電力マルチコアプロセッサとソフトウェア技術

    笠原 博徳

    早稲田大学技術説明会    2009.03  [Refereed]

  • Low Power Multicores Processor and Software Technologies

    Hironori Kasahara

    Waseda University Technical Presentation Meeting    2009.03  [Refereed]

  • Performance Evaluation of Minimum Execution Time Multiprocessor Scheduling Algorithms Using Standard Task Graph Set Ver3 Consider Parallelism of Task Graphs and Deviation of Task Execution Time

    Mamoru Shimaoka, Kazuhiro Imaizumi, Fumiyo Takano, Keiji Kimura, Hironori Kasahara

    Technical Report of IEICE   2009 ( 14 ) 127 - 132  2009.02

    　View Summary

    This paper proposes the "Standard Task Graph Set Ver3" (STG Ver3) to evaluate performance of heuristic and optimization algorithms for the minimum execution time multiprocessor scheduling problem. The minimum execution time multiprocessor scheduling problem is known as a strong NP-hard combinational optimization problem to the public. The STG Ver2 was created by random task execution times and random predecessors. In addition, the STG Ver3 considers parallelism of task graphs and deviation of task execution times to let us understand characteristics of algrithms. This paper describes evaluation results by applying the STG Ver3 to several algorithms. Performance evaluation show that DF/IHS can give us optimal solutions for 87.25%, and PDF/IHS 92.25% within 600 seconds.

    CiNii

  • Parallel and Concurrent Search for Fast AND/OR Tree Search on Multicore Processors

    Fumiyo Takano, Yoshitaka Maekawa, Hironori Kasahara

    Proc. of the IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN 2009)    2009.02  [Refereed]

  • 組込マルチコア用並列化コンパイラとAPIについて

    笠原 博徳

    トロン協会    2009.02  [Refereed]

  • Parallelizing Compiler and API for Embedded Multi-cores

    Hironori Kasahara

    TRON Association    2009.02  [Refereed]

  • 並列度・タスク実行時間の偏りを考慮した標準タスクグラフセットSTG Ver3を用いたスケジューリングアルゴリズムの評価

    島岡護, 今泉和浩, 鷹野芙美代, 木村啓二, 笠原博徳

    第119回 ハイパフォーマンスコンピューティング研究会    2009.02  [Refereed]

  • Performance Evaluation of Minimum Execution Time Multiprocessor Scheduling Algorithms Using Standard Task Graph Set Ver3 Consider Parallelism of Task Graphs and Deviation of Task Execution Time

    Mamoru Shimaoka, Kazuhiro Imaizumi, Fumiyo Takano, Keiji Kimura, Hironori Kasahara

    Technical Report of IEICE    2009.02  [Refereed]

  • A Power Saving Scheme on Multicore Processors Using OSCAR API

    Ryo Nakagawa, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara

    THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD2008/145)    2009.01

  • Local Memory Management Scheme by a Compiler for Multicore Processor

    Taku Momozono, Hirofumi Nakano, Masayoshi Mase, Keiji Kimura, Hironori Kasahara

    THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD2008/141)    2009.01

  • Performance Evaluation of Parallelizing Compiler Cooperated Heterogeneous Multicore Architecture Using Media Applications

    Teruo Kamiyama, Yasutaka Wada, Akihiro Hayashi, Masayoshi Mase, Hirofumi Nakano, Takeshi Watanabe, Keiji Kimura, Hironori Kasahara

    THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD2008/140)    2009.01

  • Performance of OSCAR Multigrain Parallelizing Compiler on Multicore Processors

    Hiroki Mikami, Jun Shirako, Masayoshi Mase, Takamichi Miyamoto, Hirofumi Nakano, Fumiyo Takano, Akihiro Hayashi, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

    Proc. of 14th Workshop on Compilers for Parallel Computing(CPC 2009)    2009.01  [Refereed]

  • マルチコア上でのOSCAR API を用いた低消費電力化手法

    中川亮, 間瀬正啓, 白子準, 木村啓二, 笠原博徳

    社団法人 電子情報通信学会, 信学技報, ICD2008-145    2009.01  [Refereed]

  • A Power Saving Scheme on Multicore Processors Using OSCAR API

    Ryo Nakagawa, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara

    THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD2008/145)    2009.01  [Refereed]

  • マルチコアのためのコンパイラにおけるローカルメモリ管理手法

    桃園拓, 中野啓史, 間瀬正啓, 木村啓二, 笠原博徳

    社団法人 電子情報通信学会, 信学技報, ICD2008-141    2009.01  [Refereed]

  • Local Memory Management Scheme by a Compiler for Multicore Processor

    Taku Momozono, Hirofumi Nakano, Masayoshi Mase, Keiji Kimura, Hironori Kasahara

    THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD2008/141)    2009.01  [Refereed]

  • メディアアプリケーションを用いた並列化コンパイラ協調型ヘテロジニアスマルチコアアーキテクチャのシミュレーション評価

    神山輝壮, 和田康孝, 林明宏, 間瀬正啓, 中野啓史, 渡辺岳志, 木村啓二, 笠原博徳

    社団法人 電子情報通信学会, 信学技報, ICD2008-140    2009.01  [Refereed]

  • Performance Evaluation of Parallelizing Compiler Cooperated Heterogeneous Multicore Architecture Using Media Applications

    Teruo Kamiyama, Yasutaka Wada, Akihiro Hayashi, Masayoshi Mase, Hirofumi Nakano, Takeshi Watanabe, Keiji Kimura, Hironori Kasahara

    THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD2008/140)    2009.01  [Refereed]

  • Multiple-paths Search with Concurrent Thread Scheduling for Fast AND/OR Tree Search

    Fumiyo Takano, Yoshitaka Maekawa, Hironori Kasahara

    CISIS: 2009 INTERNATIONAL CONFERENCE ON COMPLEX, INTELLIGENT AND SOFTWARE INTENSIVE SYSTEMS, VOLS 1 AND 2     51 - +  2009  [Refereed]

    　View Summary

    This paper proposes a fast AND/OR tree search algorithm using a multiple-paths concurrent search method. Conventional heuristic AND/OR tree search algorithms expand nodes in only a descending order of heuristic evaluation values. However, since the evaluation values are heuristic, a solution node group sometimes includes nodes with lower evaluation values. The tree which has a solution node group including nodes with lower evaluation values requires a long time to be solved by the conventional algorithms. The proposed algorithm. allows us to search paths including nodes with lower evaluation values and paths including nodes with higher evaluation values concurrently For searching various paths concurrently, the proposed algorithm uses pseudo-threads and a pseudo-thread scheduler managed by a user program with low overhead compared with the OS thread management. The pseudo-thread scheduler can weight the amount of search on each path and schedule the pseudo-threads. The proposed algorithm car, solve trees which have solutions including nodes with lower evaluation values also quickly. For performance evaluation, the proposed algorithm was applied to a tsume-shogi (Japanese chess problem) solver as a typical AND/OR tree search problem. In tsume-shogi, players can reuse captured pieces. Performance evaluation results on 385 problems show that the proposed algorithm is 1.67 times faster on the average than the previous algorithm df-pn.

  • 情報家電用マルチコア並列化APIを生成する自動並列化コンパイラによる並列化の評価

    宮本孝道, 浅香沙織, 見神広紀, 間瀬正啓, 木村啓二, 笠原博徳

    情報処理学会論文誌 コンピューティングシステム   1 ( 3 ) 83 - 95  2008.12  [Refereed]

    CiNii

  • An Evaluation of Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API

    Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Keiji Kimura, Hironori Kasahara

    IPSJ Transactions on Advanced Computing Systems   1 ( 3 ) 83 - 95  2008.12  [Refereed]

    CiNii

  • Panel Discussions: Japanese Challenges for Multicore -Low Power High Performance Multicores,Compiler and API-

    Hironori Kasahara

    Intel Higher Education Program 2008 Asia Academic Forum    2008.10  [Refereed]

  • 低炭素社会実現のためのマルチコア・テクノロジーと利用技術への挑戦

    笠原 博徳

    IBM HPCフォーラム 2008    2008.09  [Refereed]

  • Multicore Technologies for Realization of Low-carbon Society and Challenge for Utilization Technologies

    Hironori Kasahara

    IBM HPC Forum 2008    2008.09  [Refereed]

  • An Eight Core - Eight-RAM SoC Delivers 8.6GMIPS and 33.6GFLOPS at 600MHz (1/2)

    Hironori Kasahara

    Microprocessor Forum Japan 2008    2008.07  [Refereed]

  • 8.6GMIPS/33.6GFLOPSを実現する8コア/8RAM内蔵SoC (1/2)

    笠原 博徳

    マイクロプロセッサ・フォーラム・ジャパン2008    2008.07  [Refereed]

  • Low Power High Performance Multicores Technology

    Hironori Kasahara

    JAPAN ASSOCIATION for HEAT PIPE Seminar    2008.07  [Refereed]

  • 低消費電力・高性能マルチコア技術

    笠原 博徳

    日本ヒートパイプ協会 第27回総会・講演会    2008.07  [Refereed]

  • Parallelizing Compiler Cooperative Heterogeneous Multicore

    Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

    Proc. of Workshop on Software and Hardware Challenges of Manycore Platforms (SHCMP 2008)    2008.06  [Refereed]

  • Parallelization of MP3 Encoder using Static Scheduling on a Heterogeneous Multicore

    Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara

    Trans. of IPSJ on Computing Systems   1 ( 1 ) 105 - 119  2008.06  [Refereed]

    CiNii

  • ヘテロジニアスマルチコア上でのスタティックスケジューリングを用いたMP3エンコーダの並列化

    和田 康孝, 林 明宏, 益浦 健, 白子 準, 中野 啓史, 鹿野 裕明, 木村啓二, 笠原博徳

    情報処理学会論文誌コンピューティングシステム   1 ( 1 ) 105 - 119  2008.06  [Refereed]

  • OSCAR Low Power High Performance Multicore and Parallelizing Compiler

    Hironori Kasahara

    Nokia, Finland    2008.06  [Refereed]

  • Compiler and API for Low Power High Performance Multicores

    Hironori Kasahara

    8th International Forum on Application-Specific Multi-Processor SoC (MpSoc '08)    2008.06  [Refereed]

  • An Evaluation of Barrier Synchronization Mechanism Considering Hierarchical Processor Grouping

    Kaito Yamada, Masayoshi Mase, Jun Shirako, Keiji Kimura, Masayuki Ito, Toshihiro Hattori, Hiroyuki Mizuno, Kunio Uchiyama, Hironori Kasahara

    Technical Report of IPSJ   108 ( 28 ) 19 - 24  2008.05

    　View Summary

    In order to use a large number of processor cores in a chip, hierarchical coarse grain task parallel processing, which exploits whole program parallelism by analyzing hierarchical coarse grain task parallelism inside loops and subroutines, has been proposed and implemented in OSCAR automatic parallelizing compiler. This hierarchical coarse grain task parallel processing defines processor groups hierarchically and logically, and assigns hierarchical coarse grain tasks to each processor group. A light-weight and scalable barrier synchronization mechanism considering hierarchical processor grouping, which supports hierarchical coarse grain task parallel processing, is developed and implemented into RP2 multicore processor having eight SH4A cores with support by NEDO "Multicore Technology for Realtime Consumer Electronics". This barrier mechanism is proposed and evaluated in this paper. The evaluation using AAC encoder program by 8 cores shows our barrier mechanism achieves 16% better performance than software barrier.

    CiNii

  • Automatic Parallelization of Restricted C Programs using Pointer Analysis

    Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Yuta Murata, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ   108 ( 28 ) 69 - 74  2008.05

    　View Summary

    This paper describes a restriction on pointer usage in C language for parallelism extraction by an automatic parallelizing compiler. By rewriting programs to satisfy the restriction, automatic parallelization using flow-sensitive, context-sensitive pointer analysis on an 8 cores SMP server achieved 3.80 times speedup for SPEC2000 art, 6.17 times speedup for SPEC2006 lbm and 5.14 times speedup for MediaBench mpeg2enc against the sequential execution, respectively.

    CiNii

  • OSCAR Multigrain Parallelizing Compiler for High Performance Low Power Multicores

    Hironori Kasahara

    The 14th Workshop on Compiler Techniques for High-Performance Computing(CTHPC2008)    2008.05  [Refereed]

  • OSCAR Multigrain Parallelizing Compiler for High Performance Low Power Multicores

    Hironori Kasahara

    Industrial Technology Research Institute, Hosted by Dr. Cheng    2008.05  [Refereed]

  • Embedded Multi-cores Advanced Parallelizing Compiler Technologies

    Hironori Kasahara

    11th Embedded Systems Expo    2008.05  [Refereed]

  • 組込みマルチコア最先端並列化コンパイラ技術

    笠原 博徳

    第11回組込みシステム開発技術展(ESEC) 専門セミナー    2008.05  [Refereed]

  • An Evaluation of Barrier Synchronization Mechanism Considering Hierarchical Processor Grouping

    Kaito Yamada, Masayoshi Mase, Jun Shirako, Keiji Kimura, Masayuki Ito, Toshihiro Hattori, Hiroyuki Mizuno, Kunio Uchiyama, Hironori Kasahara

    Technical Report of IPSJ, 2008    2008.05  [Refereed]

  • 階層グルーピング対応バリア同期機構の評価

    山田 海斗, 間瀬 正啓, 白子 準, 木村 啓二, 伊藤 雅之, 服部 俊洋, 水野 弘之, 内山 邦男, 笠原 博徳

    第170回 計算機アーキテクチャ研究会    2008.05  [Refereed]

  • Automatic Parallelization of Restricted C Programs using Pointer Analysis

    Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Yuta Murata, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2008    2008.05  [Refereed]

  • ポインタ解析を用いた制約付きCプログラムの自動並列化

    間瀬正啓, 馬場大介, 長山晴美, 村田雄太, 木村啓二, 笠原博徳

    第170回 計算機アーキテクチャ研究会    2008.05  [Refereed]

  • Parallelization of Multimedia Applications by Compiler on Multicores for Consumer Electronics

    Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Keiji Kimura, Hironori Kasahara

    Symposium on Advanced Computing Systems and Infrastructures (SACSIS 2008)    2008.05  [Refereed]

  • 情報家電用マルチコア上におけるマルチメディア処理のコンパイラによる並列化

    宮本孝道, 浅香沙織, 見神広紀, 間瀬正啓, 木村啓二, 笠原博徳

    SACSIS2008 - 先進的計算基盤システムシンポジウム    2008.05  [Refereed]

  • Heterogeneous multi-core architecture that enables 54x AAC-LC stereo encoding

    Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   43 ( 4 ) 902 - 910  2008.04  [Refereed]

    　View Summary

    This paper describes a heterogeneous multi-core processor (HMCP) architecture that integrates general-purpose processors (CPUs) and accelerators (ACCs) to achieve exceptional performance as well as low-power consumption for the SoCs of embedded systems. The memory architectures of CPUs and ACCs were unified to improve programming and compiling efficiency. Advanced audio codec-low complexity (AAC-LC) stereo audio encoding was parallelized on a heterogeneous multi-core having homogeneous processor cores and dynamically reconfigurable processor (DRP) ACC cores in a preliminary evaluation of the HMCP architecture. The performance evaluation revealed that 54x AAC encoding was achieved on the chip with two CPUs at 600 MHz and two DRPs at 300 MHz, which achieved encoding of an entire CD within 1-2 min.

    DOI

    Scopus

    16
    Citation
    (Scopus)

  • An 8 CPU SoC with Independent Power-off Control of CPUs and Multicore Software Debug Function

    Yutaka Yoshida, Masayuki Ito, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Toshihiro Hattori, Jun Sakiyama, Masashi Takada, Kunio Uchiyama, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara

    Proc. of IEEE Cool Chips XI: Symposium on Low-Power and High-Speed Chips 2008    2008.04  [Refereed]

  • Panel Discussions: Multi-Core and Many-Core: the 5 to 10 Year View

    Hironori Kasahara

    IEEE Symposium on Low-Power and High-Speed Chips COOLChips XI    2008.04  [Refereed]

  • Multicore Compiler for Low Power High Performance Embedded Computing

    Hironori Kasahara

    IEEE Symposium on Low-Power and High-Speed Chips COOLChips XI, Yokohama, Japan    2008.04  [Refereed]

  • Power-aware compiler controllable chip multiprocessor

    Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

    IEICE TRANSACTIONS ON ELECTRONICS   E91C ( 4 ) 432 - 439  2008.04  [Refereed]

    　View Summary

    A power-aware compiler controllable chip multiprocessor (CMP) is presented and its performance and power consumption are evaluated with the optimally scheduled advanced multiprocessor (OSCAR) parallelizing compiler. The CMP is equipped with power control registers that change clock frequency and power supply voltage to functional units including processor cores, memories, and an interconnection network. The OSCAR compiler carries out coarse-grain task parallelization of programs and reduces power consumption using architectural power control support and the compiler's power saving scheme. The performance evaluation shows that MPEG-2 encoding on the proposed CMP with four CPUs results in 82.6% power reduction in real-time execution mode with a deadline constraint on its sequential execution time. Furthermore, MP3 encoding on a heterogeneous CMP with four CPUs and four accelerators results in 53.9% power reduction at 21.1-fold speed-up in performance against its sequential execution in the fastest execution mode.

    DOI

    Scopus

    1
    Citation
    (Scopus)

  • 情報家電用マルチコア・プロセッサ

    笠原博徳

    電気学会誌   128 ( 3 ) 172 - 175  2008.03  [Refereed]

  • Multicore Processors for Consumer Electronics

    Hironori Kasahara

    The Journal of IEE of Japan   128 ( 3 ) 172 - 175  2008.03  [Refereed]

  • A Multigrain Parallelizing Compiler with Power Control for Multicore Processors

    Hironori Kasahara

    Intel Headquarter, Hosted by Dr. Peng Tu    2008.02  [Refereed]

  • A Multigrain Parallelizing Compiler with Power Control for Multicore Processors

    Hironori Kasahara

    Google Headquarter, Hosted by Dr. Shih-wei Liao    2008.02  [Refereed]

  • Performance evaluation of compiler controlled power saving scheme

    Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofurni Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

    HIGH-PERFORMANCE COMPUTING   4759   480 - 493  2008  [Refereed]

    　View Summary

    Multicore processors, or chip multiprocessors, which allow us to realize low power consumption, high effective performance, good cost performance and short hardware/software development period, are attracting much attention. In order to achieve full potential of multicore processors, cooperation with a parallelizing compiler is very important. The latest compiler extracts multilevel parallelism, such as coarse grain task parallelism, loop parallelism and near fine grain parallelism, to keep parallel execution efficiency high. It also controls voltage and clock frequency of processors carefully to reduce energy consumption during execution of an application program. This paper evaluates performance of compiler controlled power saving scheme which has been implemented in OSCAR multigrain parallelizing compiler. The developed power saving scheme realizes voltage/frequency control and power shutdown of each processor core during coarse grain task parallel processing. In performance evaluation, when static power is assumed as one-tenth of dynamic power, OSCAR compiler with the power saving scheme achieved 61.2 percent energy reduction for SPEC CFP95 applu without performance degradation on 4 processors and 87.4 percent energy reduction for mpeg2encode, 88.1 percent energy reduction for SPEC CFP95 tomcatv and 84.6 percent energy reduction for applu with real-time deadline constraint on 4 processors.

  • Language extensions in support of compiler parallelization

    Jun Shirako, Hironori Kasahara, Vivek Sarkar

    LANGUAGES AND COMPILERS FOR PARALLEL COMPUTING   5234   78 - +  2008  [Refereed]

    　View Summary

    In this paper, we propose an approach to automatic compiler parallelization based on language extensions that is applicable to a broader range of program structures and application domains than in past work. As a complement to ongoing work on high productivity languages for explicit parallelism, the basic idea in this paper is to make sequential languages more amenable to compiler parallelization by adding enforceable declarations and annotations. Specifically, we propose the addition of annotations and declarations related to multidimensional arrays, points, regions, array views, parameter intents, array and object privatization, pure methods, absence of exceptions, and gather/reduce computations. In many cases, these extensions are also motivated by best practices in software engineering, and can also contribute to performance improvements in sequential code. A detailed case study of the Java Grande Forum benchmark suite illustrates the obstacles to compiler parallelization in current object-oriented languages, and shows that the extensions proposed in this paper can be effective in enabling compiler parallelization. The results in this paper motivate future work on building an automatically parallelizing compiler for the language extensions proposed in this paper.

  • Advanced Parallelizing Compiler Technology for High Performance Low Power Multicores

    Hironori Kasahara

    VDEC Refresh Seminar    2008.01  [Refereed]

  • 高性能低消費電力マルチコアのための最先端並列化コンパイラ技術

    笠原 博徳

    VDECリフレッシュ・セミナー    2008.01  [Refereed]

  • Software-cooperative power-efficient heterogeneous multi-core for media processing

    Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

    2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2     712 - +  2008  [Refereed]

    　View Summary

    A heterogeneous multi-core processor (HMCP) architecture, which integrates general purpose processors (CPU) and accelerators (ACC) to achieve high-performance as well as low-power consumption with the support of a parallelizing compiler, was developed. The evaluation was performed using an MP3 audio encoder on a simulator that accurately models the HMCP, It showed that 16-frame encoding on the HMCP with four CPUs and four ACCs yielded 24.5-fold speed-up of performance against sequential execution on one CPU. Furthermore, power saving by the compiler reduced energy consumption of the encoding to 0.17 J, namely, by 28.4%.

  • Performance evaluation of compiler controlled power saving scheme

    Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofurni Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

    HIGH-PERFORMANCE COMPUTING   4759   480 - 493  2008  [Refereed]

    　View Summary

    Multicore processors, or chip multiprocessors, which allow us to realize low power consumption, high effective performance, good cost performance and short hardware/software development period, are attracting much attention. In order to achieve full potential of multicore processors, cooperation with a parallelizing compiler is very important. The latest compiler extracts multilevel parallelism, such as coarse grain task parallelism, loop parallelism and near fine grain parallelism, to keep parallel execution efficiency high. It also controls voltage and clock frequency of processors carefully to reduce energy consumption during execution of an application program. This paper evaluates performance of compiler controlled power saving scheme which has been implemented in OSCAR multigrain parallelizing compiler. The developed power saving scheme realizes voltage/frequency control and power shutdown of each processor core during coarse grain task parallel processing. In performance evaluation, when static power is assumed as one-tenth of dynamic power, OSCAR compiler with the power saving scheme achieved 61.2 percent energy reduction for SPEC CFP95 applu without performance degradation on 4 processors and 87.4 percent energy reduction for mpeg2encode, 88.1 percent energy reduction for SPEC CFP95 tomcatv and 84.6 percent energy reduction for applu with real-time deadline constraint on 4 processors.

  • An 8640 MIPS SoC with independent power-off control of 8 CPUs and 8 RAMs by an automatic parallelizing compiler

    Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Masaki Ito, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara

    Digest of Technical Papers - IEEE International Solid-State Circuits Conference   51   81 - 598  2008  [Refereed]

    　View Summary

    A 104.8mm2 90nm CMOS 600MHz SoC integrates 8 processor cores and 8 user RAMs in 17 separate power domains and delivers 33.6GFLOPS. An automatic parallelizing compiler assigns tasks to each CPU and controls its power mode including power supply in accordance with its processing load and status. The compiler also uses barrier registers to achieve fast and accurate CPU synchronization. ©2008 IEEE.

    DOI

    Scopus

    36
    Citation
    (Scopus)

  • Language extensions in support of compiler parallelization

    Jun Shirako, Hironori Kasahara, Vivek Sarkar

    LANGUAGES AND COMPILERS FOR PARALLEL COMPUTING   5234   78 - +  2008  [Refereed]

    　View Summary

    In this paper, we propose an approach to automatic compiler parallelization based on language extensions that is applicable to a broader range of program structures and application domains than in past work. As a complement to ongoing work on high productivity languages for explicit parallelism, the basic idea in this paper is to make sequential languages more amenable to compiler parallelization by adding enforceable declarations and annotations. Specifically, we propose the addition of annotations and declarations related to multidimensional arrays, points, regions, array views, parameter intents, array and object privatization, pure methods, absence of exceptions, and gather/reduce computations. In many cases, these extensions are also motivated by best practices in software engineering, and can also contribute to performance improvements in sequential code. A detailed case study of the Java Grande Forum benchmark suite illustrates the obstacles to compiler parallelization in current object-oriented languages, and shows that the extensions proposed in this paper can be effective in enabling compiler parallelization. The results in this paper motivate future work on building an automatically parallelizing compiler for the language extensions proposed in this paper.

  • Power Reduction Controll for Multicores in OSCAR Multigrain Parallelizing Compiler

    Jun Shirako, Keiji Kimura, Hironori Kasahara

    ISOCC: 2008 INTERNATIONAL SOC DESIGN CONFERENCE, VOLS 1-3     50 - 55  2008  [Refereed]

    　View Summary

    Multicore processors have become mainstream computer architecture to go beyond the performance and power efficiency limits of single-core processors. To achieve low power consumption and high performance on multicores, parallelizing compilers take on an important role. This paper describes the performance of a compiler-based power reduction scheme cooperating with OSCAR multigrain parallelizing compiler on a newly developed 8-way SH4A low power multicore chip for consumer electronics, which supports DVFS (Dynamic Voltage and Frequency Scaling) and Clock/Power Gating. Using hardware parameters and parallelized program information, OSCAR compiler determines suitable voltage and frequency of each active processor core and appropriate schedule of clock gating and power gating. Performance experiments shows the compiler reduces consumed power by 88.3%, namely from 5.68 W to 0.67 W, for real-time secure AAC Encoding and 73.5%, namely from 5.73 W to 1.52 W, for real-time MPEG2 Decoding on 8 core execution.

  • Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API

    Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Yasutaka Wada, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara

    PROCEEDINGS OF THE 2008 INTERNATIONAL SYMPOSIUM ON PARALLEL AND DISTRIBUTED PROCESSING WITH APPLICATIONS     600 - 607  2008  [Refereed]

    　View Summary

    Multicore processors have been adopted for consumer electronics like portable electronics, mobile phones, car navigation systems, digital TVs and games to obtain high performance with low power consumption. The OSCAR automatic parallelizing compiler has been developed to utilize these multicores easily. Also, a new Consumer Electronics Multicore Application Program Interface (API) to use the OSCAR compiler with native sequential compilers for various kinds of multicores from different vendors has been developed in NEDO (New Energy and Industrial Technology Development Organization) "Multicore Technology for Realtime Consumer Electronics" project with Japanese 6 IT companies. This paper evaluates the parallel processing performance of multimedia applications using this API by the OSCAR compiler on the FR1000 4 VLIW cores multicore processor developed by Fujitsu Ltd, and the RP1 4 SH-4A cores multicore processor jointly-developed by Renesas Technology Corp., Hitachi Ltd. and Waseda University. As the results, the parallel codes generated by the OSCAR compiler using the API give us 3.27 times speedup on average using 4 cores against 1 core on the FR1000 multicore, and 3.31 times speedup on average using 4 cores against 1 core on the RP1 multicore.

    DOI

    Scopus

    6
    Citation
    (Scopus)

  • Parallelization for Multimedia Processing on Multicore Processors

    Takamichi Miyamoto, Kei Tamura, Hiroaki Tano, Hiroki Mikami, Saori Asaka, Masayoshi Mase, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2007-ARC-175-05 (DesignGaia2007)   2007 ( 115 ) 77 - 82  2007.11

    　View Summary

    Multicore processors have attracted much attention to handle the increase of power consumption, the slowdown of improvement of processor clock speed, and the increase of hardware/software developing period. Also, speeding up multimedia applications is required with the progress of the consumer electronics devices like mobile phones, digital TV and games. This paper describes parallelization methods of multimedia applications on the multicore processors. Especially in this paper, MPEG2 encoding and MPEG2 decoding are selected as examples of video sequence processing, MP3 encoding is selected as an example of audio processing, JPEG 2000 encoding is selected as an example of picture processing. OSCAR multigrain parallelizing compiler parallelizes these media applications using newly developed multicore API. This paper evaluates parallel processing performances of these multimedia applications on the FR1000 multicore processor developed by Fujitsu Ltd, and the RP1 multicore processor jointly-developed by Waseda University, Renesas Technology Corp. and Hitachi Ltd.

    CiNii

  • マルチコアプロセッサ上でのマルチメディア処理の並列化

    宮本孝道, 田村圭, 田野裕秋, 見神広紀, 浅香沙織, 間瀬正啓, 木村啓二, 笠原博徳

    情報処理学会研究会報告2007-ARC-175-15(デザインガイア2007)    2007.11  [Refereed]

  • Parallelization for Multimedia Processing on Multicore Processors

    Takamichi Miyamoto, Kei Tamura, Hiroaki Tano, Hiroki Mikami, Saori Asaka, Masayoshi Mase, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2007-ARC-175-05 (DesignGaia2007)    2007.11  [Refereed]

  • Multigrain Parallelization of Restricted C Programs on SMP Servers and Low Power Multicores

    M. Mase, D. Baba, H. Nagayama, H. Tano, T. Masuura, T. Miyamoto, J. Shirako, H. Nakano, K. Kimura, H. Kasahara

    The 20th International Workshop on Languages and Compilers for Parallel Computing (LCPC2007)    2007.10  [Refereed]

  • Low Power High Performance Multicores and Compiler Technology

    Hironori Kasahara

    The 5th Technology Link in W.T.L.O - For International Research Center in Collaboration of Industry and Academia    2007.10  [Refereed]

  • 低消費電力・高性能マルチコアとコンパイラ技術

    笠原 博徳

    第5回Technology Link in W.T.L.O 〜 産学連携における国際化拠点の構築に向けて 〜    2007.10  [Refereed]

  • 情報家電用マルチコアSMP実行モードにおける制約付きCプログラムのマルチグレイン並列化

    間瀬正啓, 馬場大介, 長山晴美, 田野裕秋, 益浦健, 宮本孝道, 白子準, 中野啓史, 木村啓二, 笠原博徳

    情報家電用マルチコアSMP実行モードにおける制約付きCプログラムのマルチグレイン並列化    2007.10  [Refereed]

  • A Multi-core Parallelizing Compiler for Low-Power High-Performance Computing

    Hironori Kasahara

    Colloquium Electrical and Computer Engineering, Computer and Information Technology Institute, Computer Science, and Dean of Engineering, Duncan Hall, Rice University, Hosted by Prof. Vivek Sarkar    2007.10  [Refereed]

  • How is specifically multicore programming different from traditional parallel computing?", Panel Discussion on "How is specifically multicore programming different from traditional parallel computing?

    Hironori Kasahara

    The 20th International Workshop on Languages and Compilers for Parallel Computing (LCPC2007), University of Illinois at Urbana-Champaign    2007.10  [Refereed]

  • 情報家電用マルチコアSMP実行モードにおける制約付きCプログラムのマルチグレイン並列化

    間瀬正啓, 馬場大介, 長山晴美, 田野裕秋, 益浦健, 宮本孝道, 白子準, 中野啓史, 木村啓二, 笠原博徳

    組込みシステムシンポジウム2007    2007.10  [Refereed]

  • Multigrain Parallelization of Restricted C Programs in SMP Execution Mode of a Multicore for Consumer Electronics

    Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Hiroaki Tano, Takeshi Masuura, Takamichi Miyamoto, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara

    Embedded Systems Symposium 2007 (ESS 2007)    2007.10  [Refereed]

  • Multicore Innovation

    Hironori Kasahara

    Waseda Univ. 125 th & Faculty of Science and Engineering 100th Anniversary Symposium "Innovative Information, Electronics, and Optical technology"    2007.09  [Refereed]

  • マルチコア・イノベーション

    笠原 博徳

    早稲田大学125周年・理工学部100周年記念シンポジウム “イノベーティブ情報・電子・光技術”    2007.09  [Refereed]

  • Compiler Control Power Saving for Heterogeneous Multicore Processor

    Akihiro Hayashi, Taketo Iyoku, Ryo Nakagawa, Shigeru Matsumoto, Kaito Yamada, Naoto Oshiyama, Jun Shirako, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2007-ARC-174-18(SWoPP2007)   2007 ( 79 ) 103 - 108  2007.08

    　View Summary

    Multicore processors are getting introduced for performance improvement and reduction of power dissipation in various IT fields, such as consumer electronics, PCs, servers and super-computers. Especially, heterogeneous multicores have attracted much attention in consumer electronics to achieve higher performance per watt. In order to satisfy the demand for the high performance, low power dissipation and high software productivity, Parallelizing compilers for both parallelization and Frequency and Voltage control are required. This paper describes the evaluation results of compiler control power saving for a heterogeneous multicore processor which integrates upto 4 general purpose embedded processor Renesas SH4As and 4 accelerator core like dynamically reconfigureable processors Hitachi FE-GAs. Performance evaluation shows the heterogeneous multicore gave us 24.32 times speed up against sequential processing and 28.43% energy savings for MP3 encoding program without performance degradation.

    CiNii

  • A Hierarchical Coarse Grain Task Static Scheduling Scheme on a Heterogeneous Multicore

    Yasutaka Wada, Akihiro Hayashi, Taketo Iyoku, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2007-ARC-174-17(SWoPP2007)   2007 ( 79 ) 97 - 102  2007.08

    　View Summary

    This paper proposes a static scheduling scheme for hierarchical coarse grain task parallel processing on a heterogeneous multicore processor. A heterogeneous multicore processor integrates not only general purpose processors but also accelerators like dynamically reconfigurable processors (DRPs) or digital signal processors (DSPs). Effective usage of these accelerators allows us to get high performance and low power consumption at the same time. In the proposed scheme, the compiler extracts parallelism using coarse grain parallel processing and assigns tasks considering characteristics of each core to minimize the execution time of an application. Performance of the proposed scheme is evaluated on a heterogeneous multicore processor using MP3 encoder. Hetero-geneous configurations give us 12.64 times speedup with two SH4As and two DRPs and 24.48 times speedup with four SH4As and four DRPs against sequential execution with one SH4A core.

    CiNii

  • Evaluation of Heterogeneous Multicore Architecture with AAC-LC Stereo Encoding

    Hiroaki Shikano, Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Masafumi Onouchi, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

    THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD2007-71)   107 ( 195 ) 11 - 16  2007.08

    　View Summary

    This paper describes a heterogeneous multi-core processor (HMCP) architecture which integrates general purpose processors (CPU) and accelerators (ACC) to achieve high-performance as well as low-power consumption for SoCs of embedded systems. Memory architecture of CPUs and ACCs were unified to improve programming and compiling efficiency. For preliminary evaluation of the HMCP architecture, AAC-LC stereo audio encoding is parallelized on a heterogeneous multi-core having homogeneous processor cores and dynamic reconfigurable processor (DRP) accelerator cores. The performance evaluation shows that 54x AAC encoding is achieved on the chip with two CPUs at 600MHz and two DRPs at 300MHz, which realizes encoding of a whole CD in 1-2 minutes.

    CiNii

  • ヘテロジニアスマルチコア上でのコンパイラによる低消費電力制御

    林明宏, 伊能健人, 中川亮, 松本繁, 山田海斗, 押山直人, 白子準, 和田康孝, 中野啓史, 鹿野裕明, 木村啓二, 笠原博徳

    情報処理学会研究会報告2007-ARC-174-18(SWoPP2007)    2007.08  [Refereed]

  • ヘテロジニアスマルチコア上での階層的粗粒度タスクスタティックスケジューリング手法

    和田康孝, 林明宏, 伊能健人, 白子準, 中野啓史, 鹿野裕明, 木村啓二, 笠原博徳

    情報処理学会研究会報告2007-ARC-174-17(SWoPP2007)    2007.08  [Refereed]

  • 54倍速AACエンコードを実現するヘテロジニアスマルチコアアーキテクチャの検討

    鹿野裕明, 伊藤雅樹, 戸高貴司, 津野田賢伸, 兒玉征之, 小野内雅文, 内山邦男, 小高俊彦, 亀井達也, 永濱 衛, 草桶 学, 新田祐介, 和田康孝, 木村啓二, 笠原博徳

    社団法人 電子情報通信学会, 信学技報, ICD2007-71   107 ( 195 ) 11 - 16  2007.08  [Refereed]

  • A Hierarchical Coarse Grain Task Static Scheduling Scheme on a Heterogeneous Multicore

    Yasutaka Wada, Akihiro Hayashi, Taketo Iyoku, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2007-ARC-174-17(SWoPP2007)    2007.08  [Refereed]

  • Evaluation of Heterogeneous Multicore Architecture with AAC-LC Stereo Encoding

    Hiroaki Shikano, Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Masafumi Onouchi, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

    THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD2007-71)   107 ( 195 ) 11 - 16  2007.08  [Refereed]

  • 最先端の組み込みマルチコア用コンパイラ技術

    笠原 博徳

    DAシンポジウム2007 - システムLSI設計技術とDA -    2007.08  [Refereed]

  • Advanced Parallelizing Compiler Technologies for Embedded Multi-cores

    Hironori Kasahara

    DA Symposiumu 2007    2007.08  [Refereed]

  • Mutligrain Parallel Processing in SMP Execution Mode on a Multicore for Consumer Electronics

    Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Hiroaki Tano, Takeshi Masuura, Takamichi Miyamoto, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Tatsuya Kamei, Toshihiro Hattori, Atsushi Hasegawa, Makoto Sato, Masaki Ito, Toshihiko Odaka, Hironori Kasahara

    Technical Report of IPSJ, 2007-ARC-173-05    2007.05

  • MP3エンコーダを用いたOSCARヘテロジニアスチップマルチプロセッサの性能評価

    鹿野裕明, 鈴木裕貴, 和田康孝, 白子準, 木村啓二, 笠原博徳

    情報処理学会論文誌   48 ( SIG8(ACS18) ) 141 - 152  2007.05  [Refereed]

  • 独立に周波数制御可能な 4320MIPS、SMP/AMP対応 4プロセッサLSIの開発

    早瀬 清, 吉田 裕, 亀井達也, 芝原真一, 西井 修, 服部俊洋, 長谷川 淳, 高田雅士, 入江直彦, 内山邦男, 小高俊彦, 高田 究, 木村啓二, 笠原博徳

    情報処理学会研究会報告2007-ARC-173-06(第165回 計算機アーキテクチャ研究会)    2007.05  [Refereed]

  • 情報家電用マルチコアSMP実行モードにおけるマルチグレイン並列処理

    間瀬正啓, 馬場大介, 長山晴美, 田野裕秋, 益浦健, 深津幸 二, 宮本孝道, 白子準, 中野啓史, 木村啓二, 亀井達也, 服部俊洋, 長谷川淳, 佐藤真琴, 伊藤雅樹, 内山 邦男, 小高俊彦, 笠原博徳

    情報処理学会研究会報告2007-ARC-173-05(第165回 計算機アーキテクチャ研究会)    2007.05  [Refereed]

  • Performance Evaluation of MP3 Audio Encoder on OSCAR Heterogeneous Chip Multicore Processor

    Hiroaki Shikano, Yuki Suzuki, Yasutaka Wada, Jun Shirako, Keiji Kimura, Hironori Kasahara

    Trans. of IPSJ   48 ( SIG8(ACS18) ) 141 - 152  2007.05  [Refereed]

    　View Summary

    This paper evaluates a heterogeneous chip multi-processor (HCMP) and its scheduling scheme. The HCMP possesses different types of processing elements (PEs) such as CPUs as general-purpose processors, as well as digital signal processors or dynamic reconfigurable processors (DRPs) as specific-purpose processors. The HCMP realizes higher performance and lower power consumption than conventional single-core processors or even homogeneous multi-core processors in some specific applications such as media processing with low operating frequency supplied. In this paper, the performance of the HCMP is analyzed by studying parallelizing scheme and power control scheme of an MP3 audio encoding program and by scheduling the program onto the HCMP using these two schemes. As a result, it is observed an HCMP, consisting of two CPUs and four DRPs, outperforms a single-core processor with one CPU by a speed-up factor of 18.4. It is also obtained that the estimated energy on the HCMP with a power control results in as much as 80.0% reduction.

    CiNii

  • Mutligrain Parallel Processing in SMP Execution Mode on a Multicore for Consumer Electronics

    Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Hiroaki Tano, Takeshi Masuura, Takamichi Miyamoto, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Tatsuya Kamei, Toshihiro Hattori, Atsushi Hasegawa, Makoto Sato, Masaki Ito, Toshihiko Odaka, Hironori Kasahara

    Technical Report of IPSJ, 2007-ARC-173-05    2007.05  [Refereed]

  • A Local Memory Management Scheme in Multigrain Parallelizing Compiler

    Tsuyoshi Miura, Tomohiro Tagawa, Yusuke Muramatsu, Akinori Ikemi, Masahiro Nakagawa, Hirofumi Nakano, Jun Shirako, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2007-ARC-172/HPC-109-11   2007 ( 17 ) 61 - 66  2007.03

    　View Summary

    Multicore systems have been attracting much attention for performance, low power consumption and short hardware/software development period. To take the full advantage of multiprocessor systems, parallelizing compilers serve important roles. On multicore processor, a memory wall caused by the speed gap between processor core and memory is also serious problem. Therefore, it is important for performance improvement to use fast memolies like cache and local memory nearby a processor effectively. This paper proposes a local memory management scheme for coarse grain task parallel processing. In the evaluation using SPeC 95fp tomcatv, the proposed scheme using 8 processors achieved 19.6 times speedup against the sequantial execution without the proposed scheme on the OSCAR multicore processor by the effective use of local memories.

    CiNii

  • マルチグレイン並列化コンパイラにおけるローカルメモリ管理手法

    三浦 剛, 田川友博, 村松裕介, 池見明紀, 中川正洋, 中野啓史, 白子 準, 木村啓二, 笠原博徳

    情報処理学会研究会報告2007-ARC-109/HPC-109-11 (HOKKE2007)    2007.03  [Refereed]

  • A Local Memory Management Scheme in Multigrain Parallelizing Compiler

    Tsuyoshi Miura, Tomohiro Tagawa, Yusuke Muramatsu, Akinori Ikemi, Masahiro Nakagawa, Hirofumi Nakano, Jun Shirako, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2007-ARC-172/HPC-109-11    2007.03  [Refereed]

  • Power-aware compiler controllable chip multiprocessor

    Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

    Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT     427  2007  [Refereed]

    DOI

    Scopus

    1
    Citation
    (Scopus)

  • Automatic Parallelization for Multimedia Applications on Multicore Processors

    Takamichi Miyamoto, Saori Asaka, Nobuhito Kamakura, Hiromasa Yamauchi, Masayoshi Mase, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2007-ARC-171-13   2007 ( 4 ) 69 - 74  2007.01

    　View Summary

    Multicore processors have attracted much attention to handle the increase of power consumption along with the increase of integration degree of semiconductor devices, the slowdown of improvement of processor clocks, and the increase of hardware/software developing period. Also, speeding up multimedia applications is required with the progress of the consumer electronics like mobile phones, digital TV and games. This paper describes parallelization methods of multimedia applications on the multicore processors. Especially in this paper, MPEG2 encoding and MPEG2 decoding are selected as examples of video sequence processing, MP3 encoding is selected as an example of audio processing, JPEG 2000 encoding is selected as an example of picture processing. OSCAR multigrain parallelizing compiler automatically parallelizes these media applications. This paper evaluates parallel processing performances of these multimedia applications on the OSCAR multicore processor, and the IBM p5 550Q Power5+ 8 processors SMP server. On the OSCAR multicore processor, the parallel execution with the proposed method of managing local memory and optimizing data transfer using 4 processors, gives us 3.81 times speedup for MPEG2 encoding, 3.04 times speedup for MPEG2 decoding, 3.09 times speedup for MP3 encoding, 3.79 times speedup for JPEG 2000 encoding against the sequential execution. On the IBM p5 550Q Power5+ 8 processors server, the parallel execution using 8 processors gives us 5.19 times speedup for MPEG2 encoding, 5.12 times speedup for MPEG2 decoding, 3.69 times speedup for MP3 encoding, 4.32 times speedup for JPEG 2000 encoding against the sequential execution.

    CiNii

  • マルチコア上でのマルチメディアアプリケーションの自動並列化

    宮本孝道, 浅香沙織, 鎌倉信仁, 山内宏真, 間瀬正啓, 白子準, 中野啓史, 木村啓二, 笠原博徳

    情報処理学会研究会報告2006-ARC-171-13    2007.01  [Refereed]

  • Automatic Parallelization for Multimedia Applications on Multicore Processors

    Takamichi Miyamoto, Saori Asaka, Nobuhito Kamakura, Hiromasa Yamauchi, Masayoshi Mase, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2007-ARC-171-13    2007.01  [Refereed]

  • A 4320MIPS four-processor core SMP/AMP with individually managed clock frequency for low power consumption

    Yutaka Yoshida, Tatsuya Kamei, Kiyoshi Hayase, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara

    Digest of Technical Papers - IEEE International Solid-State Circuits Conference     95 - 590  2007  [Refereed]

    　View Summary

    A 4320MIPS four-core SoC that supports both SMP and AMP for embedded applications is designed in 90nm CMOS. Each processor-core can be operated with a different frequency dynamically including clock stop, while keeping data cache coherency, to maintain maximum processing performance and to reduce average operating power. The 97.6mm2 die achieves a floating-point performance of 16.8GFLOPS. © 2007 IEEE.

    DOI

    Scopus

    26
    Citation
    (Scopus)

  • A 4320MIPS four-processor core SMP/AMP with individually managed clock frequency for low power consumption

    Yutaka Yoshida, Tatsuya Kamei, Kiyoshi Hayase, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara

    Digest of Technical Papers - IEEE International Solid-State Circuits Conference     95 - 590  2007

    　View Summary

    A 4320MIPS four-core SoC that supports both SMP and AMP for embedded applications is designed in 90nm CMOS. Each processor-core can be operated with a different frequency dynamically including clock stop, while keeping data cache coherency, to maintain maximum processing performance and to reduce average operating power. The 97.6mm2 die achieves a floating-point performance of 16.8GFLOPS. © 2007 IEEE.

    DOI

    Scopus

    26
    Citation
    (Scopus)

  • A 4320MIPS four-processor core SMP/AMP with individually managed clock frequency for low power consumption

    Yutaka Yoshida, Tatsuya Kamei, Kiyoshi Hayase, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara

    Digest of Technical Papers - IEEE International Solid-State Circuits Conference     95 - 590  2007  [Refereed]

    　View Summary

    A 4320MIPS four-core SoC that supports both SMP and AMP for embedded applications is designed in 90nm CMOS. Each processor-core can be operated with a different frequency dynamically including clock stop, while keeping data cache coherency, to maintain maximum processing performance and to reduce average operating power. The 97.6mm2 die achieves a floating-point performance of 16.8GFLOPS. © 2007 IEEE.

    DOI

    Scopus

    26
    Citation
    (Scopus)

  • Heterogeneous multiprocessor on a chip which enables 54x AAC-LC stereo encoding

    Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Hiroshi Tanaka, Tomoyuki Kodama, Hiroaki Shikano, Masafumi Onouchi, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

    2007 Symposium on VLSI Circuits, Digest of Technical Papers     18 - 19  2007  [Refereed]

    　View Summary

    A heterogeneous multiprocessor on a chip has been designed and implemented. It consists of 2 CPUs and 2 DRPs (Dynamic Reconfigurable Processors). The design of DRP was intended to achieve high-performance in a small area to be integrated on a SoC for embedded systems. Memory architecture of CPUs and DRPs were unified to improve programming and compiling efficiency. 54x AAC-LC stereo encoding has been enabled with 2 DRPs at 300MHz and 2 CPUs at 600MHz.

  • Automatic Parallelization of Restricted C Programs in OSCAR Compiler

    Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Hiroaki Tano, Takeshi Masuura, Koji Fukatsu, Takamichi Miyamoto, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2006-ARC-170-01 (DesignGaia2006)   2006 ( 127 ) 1 - 6  2006.11

    　View Summary

    Along with the popularization of multiprocessors and multicore architectures, automatic parallelizing compiler, which can realize high effective performance and low power comsumption, becomes more and more important in various areas from high performance computing to embedded computing. OSCAR compiler realizes multigrain automatic parallelization, which can exploit parallelism and data locality from the whole of the program. This paper describes C language support in OSCAR compiler. For rapid support of C language, restricted C language is proposed. In the preliminary performance evaluation of automatic parallelization using following media applications as MPEG2 encode, MP3 encode, and AAC encode, Susan (smoothing) derived from MiBench, and Art from SPEC2000, OSCAR compiler achieved 7.49 times speed up in maximum for susan (smoothing) against sequential execution on IBM p5 550 server having 8 processors, and 3.75 times speed up in maximum for susan (smoothing) too against sequential execution on Sun Ultra80 workstation having 4 processors.

    CiNii

  • Performance of OSCAR Multigrain Parallelizing Compiler on SMP Servers and Embedded Multicore

    Jun Shirako, Tomohiro Tagawa, Tsuyoshi Miura, Takamichi Miyamoto, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2006-ARC-170-02 (DesignGaia2006)   2006 ( 127 ) 7 - 12  2006.11

    　View Summary

    Currently, multiprocessor systems, especially multicore processors, are attracting much attention for performance, low power consumption and short hardware/software development period. To take the full advantage of multiprocessor systems, parallelizing compilers serve important roles. This paper describes the execution performance of OSCAR multigrain parallelizing compiler using coarse grain task parallelization and near fine grain parallelization in addition to loop parallelization, on the latest SMP servers and a SMP embedded multicore. The OSCAR compiler has realized the automatic determination of parallelizing layer, which decides the suitable number of processors and parallelizing technique for each nested part of the program, and global cache memory optimization over loops and coarse grain tasks. In the performance evaluation using 10 SPEC CFP95 benchmark programs and 4 SPEC CFP2000, OSCAR compiler gave us 2.74 times speedup compared with IBM XL Fortran compiler 10.1 on IBM p5 550Q Power5+8 processors server, 4.82 times speedup compared with IBM XL Fortran compiler 8.1 on IBM pSeries690 Power4 24 processors server. OSCAR compiler can be also applied for NEC/ARM MPCore ARMv6 4 processors low power embedded multicore, using subset of OpenMP libraries and g77 compiler. In the evaluation using SPEC CFP95 benchmarks with reduced data sets, OSCAR compiler achieved 4.08 times speedup for tomcatv, 3.90 times speedup for swim, 2.21 times speedup for su2cor, 3.53 times speedup for hydro2d, 3.85 times speedup for mgrid, 3.62 times speedup for applu and 3.20 times speedup for turb3d against the sequential execution.

    CiNii

  • SMPサーバ及び組込み用マルチコア上でのOSCARマルチグレイン自動並列化コンパイラの性能

    白子準, 田川友博, 三浦剛, 宮本孝道, 中野啓史, 木村啓二, 笠原博徳

    情報処理学会研究会報告2006-ARC-170-02(デザインガイア2006)    2006.11  [Refereed]

  • OSCARコンパイラにおける制約付きCプログラムの自動並列化

    間瀬正啓, 馬場大介, 長山晴美, 田野裕秋, 益浦健, 深津幸二, 宮本孝道, 白子準, 中野啓史, 木村啓二, 笠原博徳

    情報処理学会研究会報告2006-ARC-170-01(デザインガイア2006)    2006.11  [Refereed]

  • Performance of OSCAR Multigrain Parallelizing Compiler on SMP Servers and Embedded Multicore

    Jun Shirako, Tomohiro Tagawa, Tsuyoshi Miura, Takamichi Miyamoto, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2006-ARC-170-02/ (DesignGaia2006)    2006.11  [Refereed]

  • Automatic Parallelization of Restricted C Progurams in OSCAR Compiler

    Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Hiroaki Tano, Takeshi Masuura, Koji Fukatsu, Takamichi Miyamoto, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2006-ARC-170-01/ (DesignGaia2006)    2006.11  [Refereed]

  • 最先端のコンピュータアーキテクチャ -経済産業省/NEDOリアルタイム情報家電用マルチコアプロジェクトを中心として-

    笠原 博徳

    東京電力EWE講演会2006    2006.10  [Refereed]

  • 最先端マルチコアコンパイラとその並列化・低消費電力化性能

    笠原 博徳

    アーム株式会社 ARMセミナー2006    2006.10  [Refereed]

  • Multi-core Parallelizing Compiler for Low Power High Performance Computing

    Hironori Kasahara

    University of Illinois at Urbana-Champaign, Hosted by Prof. David Padua    2006.10  [Refereed]

  • Advanced Computer Architecture: METI/NEDO Multicore-processor Technology for Real-time Consumer Electronics Project

    Hironori Kasahara

    Tokyo Electric Power Company EWE Seminor 2006    2006.10  [Refereed]

  • Advanced Multi-core Compiler and Its Parallelization and Power Reduction Performance

    Hironori Kasahara

    ARM Seminar 2006    2006.10  [Refereed]

  • C Language Support in OSCAR Multigrain Parallelizing Compiler using CoSy

    Masayoshi Mase, Keiji Kimura, Hironori Kasahara

    ACE 2nd CoSy Community Gathering    2006.10  [Refereed]

  • マルチコアプロセッサにおけるコンパイラ制御低消費電力化手法

    白子 準, 吉田 宗弘, 押山 直人, 和田 康孝, 中野 啓史, 鹿野 裕明, 木村 啓二, 笠原 博徳

    情報処理学会論文誌コンピューティングシステム   47 ( SIG12(ACS15) ) 147 - 158  2006.09  [Refereed]

  • Software Challenges in Multi-Core Chip Era (Panel Discussion)

    Guang R. Gao, Kasahara Hironori, Vivek Sarkar, Skevos Evripidou, Murphy Brian

    Workshop on Software Challenges for Multicore Architectures(Tshinghua Univ. Beijing, China)    2006.09  [Refereed]

  • OSCAR Multigrain Parallelizing Compiler for Multicore Architectures

    Hironori Kasahara

    Workshop on Software Challenges for Multicore Architectures(Tshinghua Univ. Beijing, China)    2006.09  [Refereed]

  • 並列化コンパイラ協調型 チップマルチプロセッサ技術

    笠原博徳, 木村啓二, 白子準, 和田康孝, 中野啓史, 宮本孝道

    STARCシンポジウム2006    2006.09  [Refereed]

  • Parallelizing Compiler Cooperative Chip Multiprocessor Technology

    Hironori Kasahara, Keiji Kimura, Jun Shirako, Yasutaka Wada, Hirofumi Nakano, Takamichi Miyamoto

    STARC Symposium 2006    2006.09  [Refereed]

  • Parallelization of Multi-Path Concurrent Search for Iterative Deepening using Proof and Disproof Numbers

    Fumiyo Takano, Yoshitaka Maekawa, Hironori Kasahara, Seinosuke Narita

    Technical Report of IPSJ, 2006-HPC-103-17 (SWoPP2006)    2006.08

  • Local Memory Management on OSCAR Multicore

    Hirofumi Nakano, Takumi Nito, Takanori Maruyama, Masahiro Nakagawa, Yuki Suzuki, Yosuke Naito, Takamichi Miyamoto, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2006-ARC-169-28 (SWoPP2006)    2006.08

  • 並列化コンパイラの最新動向

    笠原 博徳

    日本IBM 先駆的科学計算に関するフォーラム2006    2006.08  [Refereed]

  • 証明数・反証数を用いた反復深化法における複数経路並行探索の並列化

    鷹野芙美代, 前川仁孝, 笠原博徳, 成田誠之助

    情報処理学会研究会報告2006-HPC-103-17(SWoPP高知2006)    2006.08  [Refereed]

  • OSCARマルチコア上でのローカルメモリ管理手法

    中野啓史, 仁藤拓実, 丸山貴紀, 中川正洋, 鈴木裕貴, 内藤陽介, 宮本孝道, 和田康孝, 木村啓二, 笠原博徳

    情報処理学会研究会報告2006-ARC-169-28(SWoPP高知2006)    2006.08  [Refereed]

  • Parallelization of Multi-Path Concurrent Search for Iterative Deepening using Proof and Disproof Numbers

    Fumiyo Takano, Yoshitaka Maekawa, Hironori Kasahara, Seinosuke Narita

    Technical Report of IPSJ, 2006-HPC-103-17/ (SWoPP2006)    2006.08  [Refereed]

  • Local Memory Management on OSCAR Multicore

    Hirofumi Nakano, Takumi Nito, Takanori Maruyama, Masahiro Nakagawa, Yuki Suzuki, Yosuke Naito, Takamichi Miyamoto, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2006-ARC-169-28/ (SWoPP2006)    2006.08  [Refereed]

  • 情報家電用マルチコアと並列化コンパイラ

    笠原 博徳

    JEITAマイクロプロセッサ専門委員会講演会「マルチコアアーキテクチャの研究開発動向及び将来展望」    2006.08  [Refereed]

  • Multicores for Consumer Electronics and Parallelizing Compilers

    Hironori Kasahara

    JEITA SIG. on Microprocessor    2006.08  [Refereed]

  • The Latest Trend of Parallelizing Compiler

    Hironori Kasahara

    IBM Japan Forum on Pioneering Scientific Computing    2006.08  [Refereed]

  • イノベーション創出を目指した産官学連携と人材育成の試み(「イノベーションの創出に向けた 産学官連携の推進と人材の育成」パネリスト)

    笠原 博徳

    第5回産学官連携推進会議分科会    2006.06  [Refereed]

  • Trial s of Collaboration among Business, Academia and Governmentand Human Resource Development for Creation of Innovations(Panel on the Promotion of Collaboration among Business, Academia and Government and Human Resource Development for Creation of Innovations)

    Hironori Kasahara

    5th Conference for the Promotion of Collaboration Among Business, Academia, and Government (Section Meeting)    2006.06  [Refereed]

  • Compiler Controle Power Saving Scheme for Multicore Processors

    Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

    Symposium on Advanced Computing Systems and Infrastructures (SACSIS 2006)   47 ( SIG12(ACS15) ) 147 - 158  2006.05  [Refereed]

  • マルチCPUアーキテクチャと並列化コンパイラ技術の動向(コンスーマー機器への応用)

    笠原 博徳

    ソニー株式会社 技術講演会    2006.05  [Refereed]

  • Latest Trends of Multi-CPU Architectures and Parallelizing Compilers: Application for Consumer Electronics

    Hironori Kasahara

    Sony Technology seminar    2006.05  [Refereed]

  • マルチコアプロセッサにおけるコンパイラ制御低消費電力化手法

    白子 準, 吉田 宗広, 押山 直人, 和田 康孝, 中野 啓史, 鹿野 裕明, 木村 啓二, 笠原 博徳

    SACSIS2006 - 先進的計算基盤システムシンポジウム    2006.05  [Refereed]

  • Performance Evaluation of Heterogeneous Chip Multi-Processor with MP3 Audio Encoder

    Hiroaki Shikano, Yuki Suzuki, Yasutaka Wada, Jun Shirako, Keiji Kimura, Hironori Kasahara

    Proc. of IEEE Symposiumu on Low-Power and High Speed Chips (COOL Chips IX)     349 - 363  2006.04  [Refereed]

  • Data Transfer Overlap of Coarse Grain Task Parallel Processing on a Multicore Processor

    Takamichi Miyamoto, Masahiro Nakagawa, Shoichiro Asano, Yosuke Naito, Takumi Nito, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2006-ARC-167/HPC-105-10    2006.02

  • マルチコアプロセッサ上での粗粒度タスク並列処理におけるデータ転送オーバラップ方式

    宮本孝道, 中川正洋, 浅野尚一郎, 内藤陽介, 仁藤拓実, 中野啓史, 木村啓二, 笠原博徳

    情報処理学会研究報告2006ARC-167-10(HOKKE2006)    2006.02  [Refereed]

  • Data Transfer Overlap of Coarse Grain Task Parallel Processing on a Multicore Processor

    Takamichi Miyamoto, Masahiro Nakagawa, Shoichiro Asano, Yosuke Naito, Takumi Nito, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2006-ARC-167/HPC-105-10    2006.02  [Refereed]

  • A Static Scheduling Scheme for Coarse Grain Tasks on a Heterogeneous Chip Multi Processor

    Yasutaka Wada, Naoto Oshiyama, Yuki Suzuki, Yosuke Naito, Jun Shirako, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2006-ARC-166-3 (SHINING2006)   2006 ( 8 ) 13 - 18  2006.01

    　View Summary

    This paper proposes a static scheduling scheme for coarse grain tasks on a heterogeneous chip multi processor which integrates not only general purpose processors but also accelerators like DRP or DSP. A heterogeneous chip multi processor allows us to get high performance by using the accelerators and to save energy by frequency/voltage control by the compiler. In this scheme, the compiler aim to minimize the execution time of an application in consideration of the characteristic in each core. Performance of the proposed scheme is evaluated on a heterogeneous chip multi processor which has 4 general purpose processors and 2 accelerators using MP3 encoder and gives us 8.8 times speedup against sequencial execution without the proposed scheme.

    CiNii

  • Preliminary Evaluation of Heterogeneous Chip Multi-Processor with MP3 Audio Encoder

    Hiroaki Shikano, Yuki Suzuki, Yasutaka Wada, Jun Shirako, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2006-ARC-166-1 (SHINING2006)    2006.01

  • Parallelizing Compiler Cooperated Low Power High Effective Performance Multi-core Processors

    Hironori Kasahara

    Technical Report of IPSJ, 2006-ARC-166-6 (SHINING2006)    2006.01

  • 並列化コンパイラ協調型低消費電力・高実効性能マルチコアプロセッサの動向

    笠原 博徳

    情報処理学会2006 ARC-166-6(SHINING2006)    2006.01  [Refereed]

  • ヘテロジニアスチップマルチプロセッサにおける粗粒度タスクスタティックスケジューリング手法

    和田康孝, 押山直人, 鈴木裕貴, 内藤陽介, 白子準, 中野啓史, 鹿野裕明, 木村啓二, 笠原博徳

    情報処理学会2006 ARC-166-3(SHINING2006)    2006.01  [Refereed]

  • MP3エンコーダを用いたヘテロジニアスチップマルチプロセッサの性能評価

    鹿野裕明, 鈴木裕貴, 和田康孝, 白子準, 木村啓二, 笠原博徳

    情報処理学会2006 ARC-166-1(SHINING2006)    2006.01  [Refereed]

  • 2.マルチコアにおけるプログラミング( 「特集 マルチコアにおけるソフトウェア」)

    笠原博徳, 木村啓二

    情報処理   47 ( 1 ) 17 - 23  2006.01  [Refereed]

  • 1.マルチコア化するマイクロプロセッサ( 「特集 マルチコアにおけるソフトウェア」)

    笠原博徳, 木村啓二

    情報処理   47 ( 1 ) 10 - 16  2006.01  [Refereed]

  • Parallelizing Compiler Cooperated Low Power High Effective Performance Multi-core Processors

    Hironori Kasahara

    Technical Report of IPSJ,2006-ARC-166-6(SHINING2006)    2006.01  [Refereed]

  • A Static Scheduling Scheme for Coarse Grain Tasks on a Heterogeneous Chip Multi Processor

    Yasutaka Wada, Naoto Oshiyama, Yuki Suzuki, Yosuke Naito, Jun Shirako, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ,2006-ARC-166-3(SHINING2006)    2006.01  [Refereed]

  • Preliminary Evaluation of Heterogeneous Chip Multi-Processor with MP3 Audio Encoder

    Hiroaki Shikano, Yuki Suzuki, Yasutaka Wada, Jun Shirako, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ,2006-ARC-166-1(SHINING2006)    2006.01  [Refereed]

  • Parallelizing Compilation Scheme for Reduction of Power Consumption of Chip Multiprocessors

    Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

    Proc. of 12th Workshop on Compilers for Parallel Computers (CPC 2006)     426 - 440  2006.01  [Refereed]

  • 2.Programing for Multicore Systems

    Hironori Kasahara, Keiji Kimura

    IPSJ MAGAZINE   47 ( 1 ) 17 - 23  2006.01  [Refereed]

  • 1.Multicores Emerge as Next Generation Microprocessors

    Hironori Kasahara, Keiji Kimura

    IPSJ MAGAZINE   47 ( 1 ) 10 - 16  2006.01  [Refereed]

    CiNii

  • Compiler control power saving scheme for multi core processors

    Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)   4339   362 - 376  2006  [Refereed]

    　View Summary

    With the increase of transistors integrated onto a chip, multi core processor architectures have attracted much attention to achieve high effective performance, shorten development period and reduce the power consumption. To this end, the compiler for a multi core processor is expected not only to parallelize program effectively, but also to control the voltage and clock frequency of processors and storages carefully inside an application program. This paper proposes a compilation scheme for reduction of power consumption under the multigrain parallel processing environment that controls Voltage/Frequency and power supply of each processor core on a chip. In the evaluation, the OSCAR compiler with the proposed scheme achieves 60.7 percent energy savings for SPEC CFP95 applu without performance degradation on 4 processors, and 45.4 percent energy savings for SPEC CFP95 tomcatv with real-time deadline constraint on 4 processors, and 46.5 percent energy savings for SPEC CFP95 swim with the deadline constraint on 4 processors. © 2006 Springer-Verlag Berlin Heidelberg.

    DOI

    Scopus

    18
    Citation
    (Scopus)

  • Data Localization on a Multicore Processor

    Hiforumi Nakano, Shoichiro Asano, Yosuke Naito, Takumi Nito, Tomohiro Tagawa, Takaumichi Miyamoto, Takeshi Kodaka, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2005-ARC-165-10     51 - 56  2005.12  [Refereed]

  • マルチコアプロセッサ上でのデータローカライゼーション

    中野啓文, 浅野尚一郎, 内藤陽介, 仁藤拓実, 田川友博, 宮本孝道, 小高剛, 木村啓二, 笠原博徳

    情報処理学会研究会報告2005-ARC-165-10     51 - 56  2005.11  [Refereed]

  • マルチコアプロセッサ上でのデータローカライゼーション

    中野啓文, 浅野尚一郎, 内藤陽介, 仁藤拓実, 田川友博, 宮本孝道, 小高剛, 木村啓二, 笠原博徳

    情報処理学会研究会報告2005-ARC-165-10     51 - 56  2005.11  [Refereed]

  • ホモジニアスマルチコアにおけるコンパイラ制御低消費電力化手法

    白子 準, 押山 直人, 和田 康孝, 鹿野 裕明, 木村 啓二, 笠原博徳

    情報処理学会研究会報告2005-ARC-164-10(SwoPP2005)     55 - 60  2005.09  [Refereed]

  • チップマルチプロセッサ上でのMPEG2エンコードの並列処理

    小高 剛, 中野 啓史, 木村 啓二, 笠原 博徳

    情報処理学会論文誌   46 ( 9 ) 2311 - 2325  2005.09  [Refereed]

  • Parallel Processing of MPEG2 Encoding on a Chip Multiprocessor Architecture

    Takeshi Kodaka, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara

    Trans. of IPSJ   46 ( 9 ) 2311 - 2325  2005.09  [Refereed]

  • 並列化コンパイラ協調型チップマルチプロセッサ技術

    笠原 博徳, 木村 啓二, 中野 啓史, 白子 準, 宮本 孝道, 和田 康孝

    STARCシンポジウム2005    2005.09  [Refereed]

  • Compiler Control Power Saving Scheme for Homogeneous Multiprocessor

    Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2005-ARC-164-10 (SwoPP2005)     55 - 60  2005.08

  • 組み込みマルチコア用コンパイラ技術

    笠原 博徳

    アーム株式会社 ARMセミナー2005    2005.06  [Refereed]

  • Compiler technology for built-in multi-core processor

    H. Kasahara

    ARM Seminar 2005, Tokyo    2005.06  [Refereed]

  • 最先端の高性能コンピュータ

    笠原 博徳

    文部科学省 科学技術振興調整費 新興分野人材養成プログラム 「ナノ・IT・バイオ知財経営戦略スキルアッププログラム」 特別講座「先端技術と知的財産①ナノ・IT編」    2005.05  [Refereed]

  • コンピュータ分野のロードマップ

    笠原 博徳

    NEDO 電子・情報技術ロードマップ成果報告会    2005.05  [Refereed]

  • Road map of the computer area

    H. Kasahara

    NEDO Electronics and Information Technology Road map Accomplishment Report Symposium, Tokyo    2005.05  [Refereed]

  • Advanced High-Performance Computer

    H. Kasahara

    Lecture on 'Advanced technology and intellectual property in Nano and IT', Program for cultivation of people in new fields of study 'Upskilling program for Nano, IT, Bio - Intellectual Property Management Strategy', Promotion Budget for Science and Techno    2005.05  [Refereed]

  • Hierarchical parallelism control for multigrain parallel processing

    M Obata, J Shirako, H Kaminaga, K Ishizaka, H Kasahara

    LANGUAGES AND COMPILERS FOR PARALLEL COMPUTING   2481   31 - 44  2005  [Refereed]

    　View Summary

    To improve effective performance and usability of shared memory multiprocessor systems, a multi-grain compilation scheme, which hierarchically exploits coarse grain parallelism among loops, subroutines and basic blocks, conventional loop parallelism and near fine grain parallelism among statements inside a basic block, is important. In order to efficiently use hierarchical parallelism of each nest level, or layer, in multigrain parallel processing, it is required to determine how many processors or groups of processors should be assigned to each layer, according to the parallelism of the layer. This paper proposes an automatic hierarchical parallelism control scheme to assign suitable number of processors to each layer so that the parallelism of each hierarchy can be used efficiently. Performance of the proposed scheme is evaluated on IBM RS6000 SMP server with 8 processors using 8 programs of SPEC95FP.

  • Performance of OSCAR multigrain parallelizing compiler on SMP servers

    K Ishizaka, T Miyamoto, J Shirako, M Obata, K Kimura, H Kasahara

    LANGUAGES AND COMPILERS FOR HIGH PERFORMANCE COMPUTING   3602   319 - 331  2005  [Refereed]

    　View Summary

    This paper describes performance of OSCAR multigrain parallelizing compiler on various SMP servers, such as IBM pSeries 690, Sun Fire V880, Sun Ultra 80, NEC TX7/i6010 and SGI Altix 3700. The OSCAR compiler hierarchically exploits the coarse grain task parallelism among loops, subroutines and basic blocks and the near fine grain parallelism among statements inside a basic block in addition to the loop parallelism. Also, it allows us global cache optimization over different loops, or coarse grain tasks, based on data localization technique with interarray padding to reduce memory access overhead. Current performance of OSCAR compiler is evaluated on the above SMP servers. For example, the OSCAR compiler generating OpenMP parallelized programs from ordinary sequential Fortran programs gives us 5.7 times speedup, in the average of seven programs, such as SPEC CFP95 tomcatv, swim, su2cor, hydro2d, mgrid, applu and turb3d, compared with IBM XL Fortran compiler 8.1 on IBM pSeries 690 24 processors SMP server. Also, it gives us 2.6 times speedup compare with Intel Fortran Itanium Compiler 7.1 on SGI Altix 3700 Itanium 2 16 processors server, 1.7 times speedup compared with NEC Fortran Itanium Compiler 3.4 on NEC TX7/i6010 Itanium 2 8 processors server, 2.5 times speedup compared with Sun Forte 7.0 on Sun Ultra 80 UltraSPARC II4 processors desktop work-station, and 2.1 times speedup compare with Sun Forte compiler 7.1 on Sun Fire V880 UltraSPARC III Cu 8 processors server.

  • Performance of OSCAR multigrain parallelizing compiler on SMP servers

    K Ishizaka, T Miyamoto, J Shirako, M Obata, K Kimura, H Kasahara

    LANGUAGES AND COMPILERS FOR HIGH PERFORMANCE COMPUTING   3602   319 - 331  2005  [Refereed]

    　View Summary

    This paper describes performance of OSCAR multigrain parallelizing compiler on various SMP servers, such as IBM pSeries 690, Sun Fire V880, Sun Ultra 80, NEC TX7/i6010 and SGI Altix 3700. The OSCAR compiler hierarchically exploits the coarse grain task parallelism among loops, subroutines and basic blocks and the near fine grain parallelism among statements inside a basic block in addition to the loop parallelism. Also, it allows us global cache optimization over different loops, or coarse grain tasks, based on data localization technique with interarray padding to reduce memory access overhead. Current performance of OSCAR compiler is evaluated on the above SMP servers. For example, the OSCAR compiler generating OpenMP parallelized programs from ordinary sequential Fortran programs gives us 5.7 times speedup, in the average of seven programs, such as SPEC CFP95 tomcatv, swim, su2cor, hydro2d, mgrid, applu and turb3d, compared with IBM XL Fortran compiler 8.1 on IBM pSeries 690 24 processors SMP server. Also, it gives us 2.6 times speedup compare with Intel Fortran Itanium Compiler 7.1 on SGI Altix 3700 Itanium 2 16 processors server, 1.7 times speedup compared with NEC Fortran Itanium Compiler 3.4 on NEC TX7/i6010 Itanium 2 8 processors server, 2.5 times speedup compared with Sun Forte 7.0 on Sun Ultra 80 UltraSPARC II4 processors desktop work-station, and 2.1 times speedup compare with Sun Forte compiler 7.1 on Sun Fire V880 UltraSPARC III Cu 8 processors server.

  • Performance Evaluation of Minimum Execution Time Multiprocessor Scheduling Algorithms using Standard Task Graph Set Which Takes into Account Parallelism of Task Graphs

    Takanari Matsuzawa, Shinya Sakaida, Takao Tobita, Hironori Kasahara

    Technical Report of IPSJ, ARC2004-161-9    2005.01

  • Performance of OSCAR Multigrain Parallelizing Compiler on Shared Memory Multiprocessor Serers

    Jun Shirako, Takamichi Miyamoto, Kazuhisa Ishizaka, Motoki Obata, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, ARC2004-161-5   2005 ( 7 ) 21 - 26  2005.01

    　View Summary

    The needs for automatic parallelizing compilers are getting larger with widly use of multiprocessor systems. However, the loop parallelization techniques are almost matured and new generation of parallelization methods like multi-grain parallelization are required to achieve higher effective performance. This paper describes the performance of OSCAR multigrain parallelizing compiler that uses the coarse grain task parallelization and the near fine grain parallelization in addition to the loop parallelization. OSCAR compiler realizes the following two important techniques. The first is the automatic determination scheme of parallelizing layer, which decides the number of processors and parallelizing technique for each part of the program. The other is global cache memory optimization among loops and coarse grain tasks. In the evaluation using SPEC95FP benchmarks, OSCAR compiler gave us 4.78 times speedup compared with IBM XL Fortran compiler 8.1 on IBM pSeries690 Power4 24 processors server, 2.40 times speedup compared with Intel Fortran Itanium Compiler 7.1 on SGI Altix3700 Itanium2 16 processors server, 1.90 times speedup compared with Sun Forte compiler 7.1 on Sun Fire V880 Ultra SPARC III Cu 8 processors server.

    CiNii

  • Performance Evaluation of Electronic Circuit Simulation Using Code Generation Method without Array Indirect Access

    Akira Kuroda, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, ARC2005-161-1 (SHINING2005)    2005.01

  • 並列度を考慮した標準タスクグラフセットを用いた実行時間最小マルチプロセッサスケジューリングアルゴリズムの性能評価

    松澤能成, 坂井田真也, 飛田高雄, 笠原博徳

    情報処理学会研究報告ARC2005-161-5 (SHINING2005)    2005.01  [Refereed]

  • 共有メモリ型マルチプロセッササーバ上におけるOSCARマルチグレイン自動並列化コンパイラの性能評価

    白子準, 宮本孝道, 石坂一久, 小幡元樹, 木村啓二, 笠原博徳

    情報処理学会研究報告ARC2005-161-5 (SHINING2005)    2005.01  [Refereed]

  • 配列間接アクセスを用いないコード生成法を用いた電子回路シミュレーション手法の性能評価

    黒田亮, 木村啓二, 笠原博徳

    情報処理学会研究報告ARC2005-161-1 (SHINING2005)    2005.01  [Refereed]

  • Performance Evaluation of Electronic Circuit Simulation Using Code Generation Method without Array Indirect Access

    Akira Kuroda, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, ARC2005-161-1 (SHINING2005)    2005.01  [Refereed]

  • Performance Evaluation of Minimum Execution Time Multiprocessor Scheduling Algorithms using Standard Task Graph Set Which Takes into Account Parallelism of Task Graphs

    Takanari Matsuzawa, Shinya Sakaida, Takao Tobita, Hironori Kasahara

    Technical Report of IPSJ, ARC2004-161-9    2005.01  [Refereed]

  • Performance of OSCAR Multigrain Parallelizing Compiler on Shared Memory Multiprocessor Serers

    Jun Shirako, Takamichi Miyamoto, Kazuhisa Ishizaka, Motoki Obata, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, ARC2004-161-5    2005.01  [Refereed]

  • Multigrain parallel processing on compiler cooperative chip multiprocessor

    K Kimura, Y Wada, H Nakano, T Kodaka, J Shirako, K Ishizaka, H Kasahara

    9TH ANNUAL WORKSHOP ON INTERACTION BETWEEN COMPILERS AND COMPUTER ARCHITECTURES, PROCEEDINGS     11 - 20  2005  [Refereed]

    　View Summary

    This paper describes multigrain parallel processing on a compiler cooperative chip multiprocessor The multigrain parallel processing hierarchically exploits multiple grains of parallelism such as coarse grain task parallelism, loop iteration level parallelism and statement level near-fine grain parallelism. The chip multiprocessor has been designed to attain high effective peformance, cost effectiveness and high software productivity by supporting the optimizations of the multigrain parallelizing compiler, which is developed by Japanese Millennium Project IT21 "Advance Parallelizing Compiler". To achieve full potential of multigrain parallel processing, the chip multiprocessor integrates simple single-issue processors having distributed shared data memory for both optimal use of data locality and scalar data transfer local data memory for processor private data, in addition to centralized shared memory for shared data among processors. This paper focuses on the scalability of the chip multiprocessor having up to eight processors on a chip by exploiting of the multigrain parallelism from SPECfp95 programs. When microSPARC like the simple processor core is used under assumption of 90 nm technology and 2.8 GHz, the evaluation results show the speedups for eight processors and four processors reach 7.1 and 3.9, respectively. Similarly, when 400 MHz is assumed for embedded usage, the speedups reach 7.8 and 4.0, respectively.

  • Multigrain parallel processing on compiler cooperative chip multiprocessor

    K Kimura, Y Wada, H Nakano, T Kodaka, J Shirako, K Ishizaka, H Kasahara

    9TH ANNUAL WORKSHOP ON INTERACTION BETWEEN COMPILERS AND COMPUTER ARCHITECTURES, PROCEEDINGS     11 - 20  2005  [Refereed]

    　View Summary

    This paper describes multigrain parallel processing on a compiler cooperative chip multiprocessor The multigrain parallel processing hierarchically exploits multiple grains of parallelism such as coarse grain task parallelism, loop iteration level parallelism and statement level near-fine grain parallelism. The chip multiprocessor has been designed to attain high effective peformance, cost effectiveness and high software productivity by supporting the optimizations of the multigrain parallelizing compiler, which is developed by Japanese Millennium Project IT21 "Advance Parallelizing Compiler". To achieve full potential of multigrain parallel processing, the chip multiprocessor integrates simple single-issue processors having distributed shared data memory for both optimal use of data locality and scalar data transfer local data memory for processor private data, in addition to centralized shared memory for shared data among processors. This paper focuses on the scalability of the chip multiprocessor having up to eight processors on a chip by exploiting of the multigrain parallelism from SPECfp95 programs. When microSPARC like the simple processor core is used under assumption of 90 nm technology and 2.8 GHz, the evaluation results show the speedups for eight processors and four processors reach 7.1 and 3.9, respectively. Similarly, when 400 MHz is assumed for embedded usage, the speedups reach 7.8 and 4.0, respectively.

  • Parallel Processing for MPEG2 Encoding on OSCAR Chip Multiprocessor

    Takeshi Kodaka, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2004-ARC-160-07     119 - 127  2004.12

    Authorship：Last author

    　View Summary

    Currently, many people are enjoying multimedia applications with image and audio processing on PCs, PDAs, mobile phones and so on. With the popularization of the multimedia applications, needs for low cost, low power consumption and high performance processors has been increasing.To this end, chip multiprocessor architectures which allow us to attain scalable performance improvement by using multigrain parallelism are attracting much attention. However, in order to extract higher performance on a chip multiprocessor, more sophisticated software techniques are required, such as decomposing a program into adequate grain of tasks, assigning them onto processors considering parallelism, data locality optimization and so on. This paper describes a parallel processing scheme for MPEG2 encoding using data localization which improve execution efficiency assigning coarse grain tasks sharing same data on a same processor consecutively for a chip multiprocessor. The performance evaluation on OSCAR chip multiprocessor architecture shows that proposed scheme gives us 6.97 times speedup using 8 processors and 10.93 times speedup using 16 processors against sequential execution time respectively. Moreover, the proposed scheme gives us 1.61 times speedup using 8 processors and 2.08 times speedup using 16 processors against loop parallel processing which has been widely used for multiprocessor systems using the same number of processors. © 2004 IEEE.

    DOI

    Scopus

    2
    Citation
    (Scopus)

  • OSCARチップマルチプロセッサ上でのMPEG2エンコードの並列処理

    小高 剛, 中野 啓史, 木村 啓二, 笠原 博徳

    情報処理学会研究会報告2004-ARC-160-07    2004.12  [Refereed]

  • HPC用自動並列化コンパイラの動向と将来課題

    笠原 博徳

    第19回NEC・HPC研究会    2004.11  [Refereed]

  • Current and Future of Automatic Parallelizing Compilers

    H. Kasahara

    The 19th NEC HPC Forum    2004.11  [Refereed]

  • Performance of OSCAR Multigrain Parallelizing Compiler on SMP Servers

    Kazuhisa Ishizaka, Takamichi Miyamoto, Jun Shirako, Motoki Obata, Keiji Kimura, Hironori Kasahara

    Proc. of 17th International Workshop on Languages and Compilers for Parallel Computing(LCPC2004)    2004.09  [Refereed]

  • 世界一のコンパイラを作る--アドバンスト並列化コンパイラプロジェクト--

    笠原 博徳

    IBMライフサイエンス天城セミナー    2004.09  [Refereed]

  • Developing World Fastest Compiler: Advanced Parallelizing Compiler Project

    H. Kasahara

    IBM Life Science Amagi Seminar    2004.09  [Refereed]

  • Data Localization using Data Transfer Unit on OSCAR Chip Multiprocessor

    Hirofumi Nakano, Yosuke Naito, Takahisa Suzuki, Takeshi Kodaka, Kazuhisa Ishizaka, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2004-ARC-159-20    2004.07

  • Evaluation of Multigrain Parallelism on OSCAR Chip Multi Processor

    Yasutaka Wada, Jun Shirako, Kazuhisa Ishizaka, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2004-ARC-159-11    2004.07

  • OSCARチップマルチプロセッサ上でのデータ転送ユニットを用いたデータローカライゼーション

    中野 啓史, 内藤 陽介, 鈴木 貴久, 小高 剛, 石坂 一久, 木村 啓二, 笠原 博徳

    情報処理学会研究会報告2004-ARC-159-20    2004.07  [Refereed]

  • OSCARチップマルチプロセッサ上でのマルチグレイン並列性評価

    和田 康孝, 白子 準, 石坂 一久, 木村 啓二, 笠原 博徳

    情報処理学会研究会報告2004-ARC-159-11    2004.07  [Refereed]

  • Data Localization using Data Transfer Unit on OSCAR Chip Multiprocessor

    Hirofumi Nakano, Yosuke Naito, Takahisa Suzuki, Takeshi Kodaka, Kazuhisa Ishizaka, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2004-ARC-159-20    2004.07  [Refereed]

  • Evaluation of Multigrain Parallelism on OSCAR Chip Multi Processor

    Yasutaka Wada, Jun Shirako, Kazuhisa Ishizaka, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2004-ARC-159-11    2004.07  [Refereed]

  • 150回研究会記念特別企画(2)パネル討論:アーキテクチャ研究の将来 “産官学連携による高付加価値チップマルチプロセッサの開発”

    笠原 博徳

    第150回 計算機アーキテクチャ研究会    2004.05  [Refereed]

  • マルチグレイン並列性向上のための選択的インライン展開手法

    白子 準, 長澤 耕平, 石坂 一久, 小幡 元樹, 笠原 博徳

    情報処理学会論文誌   45 ( 4 ) 1354 - 1356  2004.05  [Refereed]

  • Selective Inline Expansion for Improvement of Multi Grain Parallelism

    Jun shirako, Kouhei Nagasawa, Kazuhisa Ishizaka, Motoki Obata, Hironori Kasahara

    Trans. of IPSJ   45 ( 5 ) 1354 - 1356  2004.05  [Refereed]

  • 150th ARC memorial special technical meeting(2), Panel: Future of Computer Architecture Research 'Development of high-value added Chip Multiprocessors by industry-government-academia collaboration'

    H. Kasahara

    150th IPSJ Special Interest Group on Computer Architecture    2004.05  [Refereed]

  • 配列間パディングを用いた粗粒度タスク間キャッシュ最適化

    石坂 一久, 小幡 元樹, 笠原 博徳

    情報処理学会論文誌   45 ( 4 )  2004.04  [Refereed]

  • Cache Optimization among Coarse Grain Tasks using Intra-Array Pading

    Kazuhisa Ishizaka, Motoki Obata, Hironori Kasahara

    Trans. of IPSJ   45 ( 4 )  2004.04  [Refereed]

  • IBM pSeries 690 上での OSCAR マルチグレイン自動並列化コンパイラの性能評価

    石坂 一久, 白子 準, 小幡 元樹, 木村 啓二, 笠原 博徳

    情報処理学会第66回全国大会    2004.03  [Refereed]

  • Software Development on Large Parallel Supercomputers in Japan -- Parallelizing Compilers and Parallel Programming Language Projects --

    H. Kasahara

    U.S.-Japan Forum on the Future of Supercomputing, 米国工学アカデミー、(社)日本工学アカデミー    2004.03  [Refereed]

  • Research on Parallelizing Compiler for High Performance Computing in Japan

    H. Kasahara

    Japan-U.S.A. Supercomputing Forum, The Engineering Academy of Japan Inc.(EAJ)    2004.03  [Refereed]

  • ミレニアムプロジェクトIT21アドバンスト並列化コンパイラとコンパイラ協調型チップマルチプロセッサ

    笠原 博徳

    NECソフト㈱ 第四回 VTC先端領域セミナー    2004.02  [Refereed]

  • Parallel Processing for MPEG2 Encoding using Data Localization

    Takeshi Kodaka, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2004-ARC-156-3   2004 ( 12 ) 13 - 18  2004.02

    　View Summary

    Recently, many people are getting to enjoy multimedia applications with image and audio processing on PCs, mobile phones and PDAs. For this situation, development of low cost, low power consumption and high performance processors for multimedia applications has been expected. To satisfy these demands, chip multiprocessor architectures which allows us to attain scalability using coarse grain level parallelism and loop level parallelism in addition to instruction level parallelism are attracting much attention. However, in order to extract much performance from chip multiprocessor architectures efficiently, highly sophisticated technique is required such as decomposing a program into adequate grain of tasks and assigning them onto processors considering parallelism and data locality of target applications. This paper describes a parallel processing scheme for MPEG2 encoding using data localization which improve execution efficiency assigning coarse grain tasks sharing same data on a same processor consecutively for a chip multiprocessor, and evaluate its performance. As the evaluation result on OSCAR CMP using 8 processors, proposed scheme gives us 1.64 times speedup against loop parallel processing, and 6.82 times speedup against sequential execution time.

    CiNii

  • データローカライゼーションを伴うMPEG2エンコーディングの並列処理

    小高 剛, 中野 啓史, 木村 啓二, 笠原 博徳

    情報処理学会研究会報告2004-ARC-156-3    2004.02  [Refereed]

  • Millennium Project IT21 Advanced Parallelizing Compiler and Compiler Cooperative Chip Multiprocessor

    H. Kasahara

    The 4th VTC Seminar, NEC Soft    2004.02  [Refereed]

  • Parallel Processing for MPEG2 Encoding using Data Localization

    Takeshi Kodaka, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2004-ARC-156-3    2004.02  [Refereed]

  • Selective inline expansion for improvement of multi grain parallelism

    J Shirako, K Nagasawa, K Ishizaka, M Obata, H Kasahara

    Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks     476 - 482  2004  [Refereed]

    　View Summary

    This paper proposes a selective procedure inlining scheme to improve a multi-grain parallelism, which hierarchically exploits the coarse grain task parallelism among loops, subroutines and basic blocks and near fine grain parallelism among statements inside a basic block in addition to the loop parallelism. Using the proposed scheme, the parallelism among, different layers(nested levels) can be exploited. In the evaluation using 103.su2cor, 107.mgrid and 125.turb3d in SPEC95FP benchmarks on 16 way IBM pSeries690 SMP server, the multi-,grain parallel processing with the proposed scheme gave us 3.65 to 5.34 times speedups against IBM XL Fortran compiler and 1.03 to 1.47 times speedups against conventional multi-grain parallelization.

  • Cache optimization for coarse grain task parallel processing using inter-array padding

    K Ishizaka, M Obata, H Kasahara

    LANGUAGES AND COMPILERS FOR PARALLEL COMPUTING   2958   64 - 76  2004  [Refereed]

    　View Summary

    The wide use of multiprocessor system has been making automatic parallelizing compilers more important. To improve the performance of multiprocessor system more by compiler, multigrain parallelization is important. In multigrain parallelization, Coarse grain task parallelism among loops and subroutines and near fine grain parallelism among statements are used in addition to the traditional loop parallelism. In addition, locality optimization to use cache effectively is also important for the performance improvement. This paper describes inter-array padding to minimize cache conflict misses among macro-tasks with data localization scheme which decomposes loops sharing the same arrays to fit cache size and executes the decomposed loops consecutively on the same processor. In the performance evaluation on Sun Ultra 80(4pe), OSCAR compiler on which the proposed scheme is implemented gave us 2.5 times speedup against the maximum performance of Sun Forte compiler automatic loop parallelization at the average of SPEC CFP95 tomcatv, swim hydro2d and turb3d programs. Also, OSCAR compiler showed 2.1 times speedup on IBM RS/6000 44p-270(4pe) against XLF compiler.

  • Parallel processing using data localization for MPEG2 encoding on OSCAR chip multiprocessor

    T Kodaka, H Nakano, K Kimura, H Kasahara

    INNOVATIVE ARCHITECTURE FOR FUTURE GENERATION HIGH-PERFORMANCE PROCESSORS AND SYSTEMS, PROCEEDINGS     119 - 127  2004  [Refereed]

    　View Summary

    Currently, many people are enjoying multimedia applications with image and audio processing on PCs, PDAs, mobile phones and so on. With the popularization of the multimedia applications, needs for low cost, low power consumption and high performance processors has been increasing. To this end, chip multiprocessor architectures which allow us to attain scalable performance improvement by using multigrain parallelism are attracting much attention. However, in order to extract higher performance on a chip multiprocessor, more sophisticated software techniques are required, such as decomposing a program into adequate grain of tasks, assigning them onto processors considering parallelism, data locality optimization and so on. This paper describes a parallel processing scheme for MPEG2 encoding using data localization which improve execution efficiency assigning coarse grain tasks sharing same data on a same processor consecutively for a chip multiprocessor. The performance evaluation on OSCAR chip multiprocessor architecture shows that proposed scheme gives us 6.97 times speedup using 8 processors and 10.93 times speedup using 16 processors against sequential execution time respectively. Moreover, the proposed scheme gives us 1.61 times speedup using 8 processors and 2.08 times speedup using 16 processors against loop parallel processing which has been widely used for multiprocessor systems using the same number of processors.

  • Memory management for data localization on OSCAR chip multiprocessor

    H Nakano, T Kodaka, K Kimura, H Kasahara

    INNOVATIVE ARCHITECTURE FOR FUTURE GENERATION HIGH-PERFORMANCE PROCESSORS AND SYSTEMS, PROCEEDINGS     82 - 88  2004  [Refereed]

    　View Summary

    Chip Multiprocessor (CMP) architecture has attracting much attention as a next-generation microprocessor architecture and many kinds of CMP are widely being researched. However, CMP architectures several difficulties for effective use of memory, especially cache or local memory near a processor core. The authors have proposed OSCAR CMP architecture, which cooperatively works with multigrain parallelizing compiler which gives us much higher parallelism than instruction level parallelism or loop level parallelism and high productivity of application programs. To support the compiler optimization for effective use of cache or local memory, OSCAR CMP has local data memory (LDM) for processor private data and distributed shared memory (DSM) for synchronization and fine grain data transfers among processors, in addition to centralized shared memory (CSM) to support dynamic task scheduling. This paper proposes a static coarse grain task scheduling scheme for data localization using live variable analysis. Furthermore, remote memory data transfer scheduling scheme using information of live variable analysis is also described. The proposed scheme is implemented on OSCAR FORTRAN multigrain parallelizing compiler and is evaluated on OSCAR CMP using Tomcatv and Swim in SPEC CFP 95 benchmark.

  • Selective inline expansion for improvement of multi grain parallelism

    J Shirako, K Nagasawa, K Ishizaka, M Obata, H Kasahara

    Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks     476 - 482  2004  [Refereed]

    　View Summary

    This paper proposes a selective procedure inlining scheme to improve a multi-grain parallelism, which hierarchically exploits the coarse grain task parallelism among loops, subroutines and basic blocks and near fine grain parallelism among statements inside a basic block in addition to the loop parallelism. Using the proposed scheme, the parallelism among, different layers(nested levels) can be exploited. In the evaluation using 103.su2cor, 107.mgrid and 125.turb3d in SPEC95FP benchmarks on 16 way IBM pSeries690 SMP server, the multi-,grain parallel processing with the proposed scheme gave us 3.65 to 5.34 times speedups against IBM XL Fortran compiler and 1.03 to 1.47 times speedups against conventional multi-grain parallelization.

  • The Data Prefetching of Coarse Grain Task Parallel Processing on Symmetric Multi Processor Machine

    Takamichi Miyamoto, Takahiro Yamaguchi, Takao Tobita, Kazuhisa Ishizaka, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2003-ARC-155-06   2003 ( 119 ) 63 - 68  2003.11

    　View Summary

    On the shared multi processor system used in current computing servers, the increase of memory access overhead with the speedup of CPU interfere to get the scalable performance improvement with the increase of the processors. In order to get scalable performance improvement, this paper proposes and evaluates the static scheduling algorithm which reduces the memory access overhead by using cache prefetch to overlap of data transfer and task processing. The proposed algorithm is used in static scheduling stage in a compiler, moreover the compiler generates a OpenMP parallelized Fortran program with prefetch directives for SUN Forte compiler for Sun Fire V880 server. Performance evaluation shows that the proposed algorithm gave us super linear speedup compared with sequential processing without prefetching by Sun Forte compiler such as 13.9 times speedup on 8 processors for SPEC95fp tomcatv program and 22.3 times speedup on 8 processors for SPEC95fp swim program. Futhermore, compared with automatic prefetching by SUN Forte compiler using the same number of processors, this algorithm shows that 1.1 times speedup on 1 processor, 3.86 times speedup on 8 processors for SPEC95fp tomcatv and 1.44 times speedup on 1processor, 1.85 times speedup on 8 processors for SPEC95fp swim.

    CiNii

  • SMPマシン上での粗粒度タスク並列処理におけるデータプリフェッチ手法

    宮本 孝道, 山口 高弘, 飛田 高雄, 石坂 一久, 木村 啓二, 笠原 博徳

    情報処理学会研究会報告2003-ARC-155-06    2003.11  [Refereed]

  • The Data Prefetching of Coarse Grain Task Parallel Processing on Symmetric Multi Processor Machine

    Takamichi Miyamoto, Takahiro Yamaguchi, Takao Tobita, Kazuhisa Ishizaka, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2003-ARC-155-06    2003.11  [Refereed]

  • Millennium Project IT21 Advanced Parallelizing Compiler

    H. Kasahara

    Information Processing Society of Japan Kansai Branch    2003.10  [Refereed]

  • ミレニアムプロジェクトIT21 アドバンスト並列化コンパイラ

    笠原 博徳

    (社)情報処理学会 関西支部大会    2003.10  [Refereed]

  • Data Localization Scheme using Static Scheduling on Chip Multiprocessor

    Hirofumi Nakano, Takeshi Kodaka, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2003-ARC-154-14   2003 ( 84 ) 79 - 84  2003.08

    　View Summary

    Recently, chip multiprocessor architecture that contains multiple processors on a chip becomes popular approach even in commercial area. The authors have proposed OSCAR chip multiprocessor (OSCAR CMP) that is aimed at exploiting multiple grains of parallelism hierarchically from a sequential program on a chip. OSCAR CMP has local data memory (LDM) for processor private data and distributed shared memory having two ports for processor shared data to control data allocation by a compiler appropriately. This paper describes data localization scheme for OSCAR CMP which exploits data locality by assigning coarse grain tasks sharing same data on a same processor consecutively. In addition, OSCAR CMP using data localization scheme is compared with shared cache architecture and snooping cache architecture. Then, current naive code generation for OSCAR CMP is considered using evaluation results.

    CiNii

  • Parallel Processing on MPEG2 Encoding for OSCAR Chip Multiprocessor

    Takeshi Kodaka, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2003-ARC-154-10    2003.08  [Refereed]

  • OSCAR CMP上でのスタティックスケジューリングを用いたデータローカライゼーション手法

    中野 啓史, 小高 剛, 木村 啓二, 笠原 博徳

    情報処理学会研究会報告2003-ARC-154-14    2003.08  [Refereed]

  • OSCARマルチプロセッサシステム上でのMPEG2エンコーディングの並列処理

    小高 剛, 中野 啓史, 木村 啓二, 笠原 博徳

    情報処理学会研究会報告2003-ARC-154-10    2003.08  [Refereed]

  • Millennium Project IT21 'Advanced Parallelizing Compiler' and Compiler Cooperative Chip Multiprocessor

    H. Kasahara

    The 2nd Super H Open Forum, Renesas Technology Corp. & Hitachi Ltd.    2003.08  [Refereed]

  • Data Localization Scheme using Static Scheduling on Chip Multiprocessor

    Hirofumi Nakano, Takeshi Kodaka, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, 2003-ARC-154-14    2003.08  [Refereed]

  • ミレニアムプロジェクトIT21”アドバンスト並列化コンパイラ”とコンパイラ協調型チップマルチプロセッサ

    笠原 博徳

    ㈱ルネサステクノロジ、㈱日立製作所 第2回 Super H オープンフォーラム    2003.08  [Refereed]

  • Static coarse grain task scheduling with cache optimization using OpenMP

    H Nakano, K Ishizaka, M Obata, K Kimura, H Kasahara

    INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING   31 ( 3 ) 211 - 223  2003.06  [Refereed]

    　View Summary

    Effective use of cache memory is getting more important with increasing gap between the processor speed and memory access speed. Also, use of multigrain parallelism is getting more important to improve effective performance beyond the limitation of loop iteration level parallelism. Considering these factors, this paper proposes a coarse grain task static scheduling scheme considering cache optimization. The proposed scheme schedules coarse grain tasks to threads so that shared data among coarse grain tasks can be passed via cache after task and data decomposition considering cache size at compile time. It is implemented on OSCAR Fortran multigrain parallelizing compiler and evaluated on Sun Ultra80 four-processor SMP workstation using Swim and Tomcatv from the SPEC fp 95. As the results, the proposed scheme gives us 4.56 times speedup for Swim and 2.37 times on 4 processors for Tomcatv respectively against the Sun Forte HPC Ver. 6 update 1 loop parallelizing compiler.

  • Inter-Array Padding for Data Localization with Static Scheduling

    Kazuhisa Ishizaka, Motoki Obata, Hironori Kasahara

    Technical Report of IPSJ, 2003-ARC-153-11    2003.05

  • スタティックスケジューリングを用いたデータローカライゼーションにおける配列間パディング

    石坂 一久, 小幡 元樹, 笠原 博徳

    情報処理学会研究会報告2003-ARC-153    2003.05  [Refereed]

  • Inter-Array Padding for Data Localization with Static Scheduling

    Kazuhisa Ishizaka, Motoki Obata, Hironori Kasahara

    Technical Report of IPSJ, 2003-ARC-153-11    2003.05  [Refereed]

  • IT競争力強化に向けた産官学連携

    笠原博徳

    朝日新聞社企画 WASEDA.COM, オピニオン    2003.04  [Refereed]  [Invited]

  • マルチグレイン並列処理のための階層的並列性制御手法

    小幡 元樹, 白子 準, 神長 浩気, 石坂 一久, 笠原 博徳

    情報処理学会論文誌   44 ( 4 )  2003.04  [Refereed]

  • 最先端の自動並列化コンパイラ技術

    笠原博徳

    情報処理学会誌   44 ( 4 ) 384 - 392  2003.04  [Refereed]

    CiNii

  • IT競争力強化のための研究開発人材---経済産業省アドバンスト並列化コンパイラプロジェクトリーダ,JEITA及びSTARC産官学連携講座の経験を通して---

    笠原 博徳

    経済産業省 大臣官房 イノベーション・システムにおける研究開発人材に関する研究会    2003.04  [Refereed]

  • Hierarchical Parallelism Control Scheme for Multigrain Parallelization

    Motoki Obata, Jun Shirako, Hiroki Kaminaga, Kazuhisa Ishizaka, Hironori Kasahara

    Trans. of IPSJ   44 ( 4 )  2003.04  [Refereed]

  • Multigrain parallel processing on compiler cooperative OSCAR chip multiprocessor architecture

    K Kimura, T Kodaka, M Obata, H Kasahara

    IEICE TRANSACTIONS ON ELECTRONICS   E86C ( 4 ) 570 - 579  2003.04  [Refereed]

    　View Summary

    This paper describes multigrain parallel processing on OSCAR (Optimally SCheduled Advanced multiprocessoR) chip multiprocessor architecture. OSCAR compiler cooperative chip multiprocessor architecture aims at development of scalable, high effective performance and cost effective chip multiprocessor with ease of use by compiler supports. OSCAR chip multiprocessor architecture integrates simple single issue processors having distributed shared data memory for optimal, use of data locality over different loops and fine grain data transfer and synchronization, local data memory for private data recognized by compiler, and compiler controllable data transfer unit for overlapping data transfer to hide data transfer overhead. This OSCAR chip multiprocessor and OSCAR multigrain parallelizing compiler have been developed. simultaneously. Performance of multigrain parallel processing on OSCAR chip multiprocessor architecture is evaluated using SPEC fp 2000/95 benchmark suite. When microSPARC like single issue core is used, OSCAR chip multiprocessor architecture gives us 2.36 times speedup in fpppp, 2.64 times in su2cor, 2.88 times in turb3d, 2.98 times in hydro2d, 3.84 times in tomcatv, 3.84 times in mgrid and 3.97 times in swim respectively for four processors against single processor.

  • Collaboration of Industry, Government and Academia for IT Competitive Power Strengthening

    Hironori Kasahara

    Opinions, WASEDA.COM, Asahi Shimbunnsha    2003.04  [Refereed]

  • R&D Human Resource for Strengthening IT Competitive Power---From the experience of a Project Leader of METI Advanced Parallelizing Compiler Project and JEITA & STARC Industry, Government and Academia Cooperative Lectures---

    H. Kasahara

    METI Minister's Secretariat Sig. on R&D Human Resource for Innovation Systems    2003.04  [Refereed]

  • Advanced Automatic Parallelizing Compiler Technology

    Hironori Kasahara

    IPSJ MAGAZINE   44 ( 4 ) 384 - 392  2003.04  [Refereed]

  • 研究開発競争力強化に向けた産官学連携寄付講座:JEITA IT最前線

    笠原博徳

    早稲田大 学理工学部・大学院報「塔」78号    2003.03  [Refereed]  [Invited]

  • Industry, Government and Academia Collaborative Donated Course for R&D Competitive Power Strengthening

    Hironori Kasahara

    Waseda University School of Science and Engineering, "Tower", No.78    2003.03  [Refereed]

  • Coarse grain task parallel processing with cache optimization on shared memory multiprocessor

    K Ishizaka, M Obata, H Kasahara

    LANGUAGES AND COMPILERS FOR PARALLEL COMPUTING   2624   352 - 365  2003  [Refereed]

    　View Summary

    In multiprocessor systems, the gap between peak and effective performance has getting larger. To cope with this performance gap, it is important to use multigrain parallelism in addition to ordinary loop level parallelism. Also, effective use of memory hierarchy is important for the performance improvement of multiprocessor systems because the speed gap between processors and memories is getting larger. This paper describes coarse grain task parallel processing that uses parallelism among macro-tasks like loops and subroutines considering cache optimization using data localization scheme. The proposed scheme is implemented on OSCAR automatic multigrain parallelizing compiler. OSCAR compiler generates OpenMP FORTRAN program realizing the proposed scheme from a sequential FORTRAN77 program. Its performance is evaluated on IBM RS6000 SP 604e High Node 8 processors SMP machine using SPEC95fp tomcatv, swim, mgrid. In the evaluation, the proposed coarse grain task parallel processing scheme with cache optimization gives us up to 1.3 times speedup on 1PE, 4.7 times speedup on 4PE and 8.8 times speedup on 8PE compared with a sequential processing time.

  • Data Localization using Coarse Grain Task Parallelization on Chip Multiprocessor

    Hirofumi Nakano, Takeshi Kodaka, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, ARC2003-151-3(SHINING2003)   2003 ( 10 ) 13 - 18  2003.01

    　View Summary

    Recently. Chip Multiprocessor(GMP)architecture has attracted much attention as a next-generation microprocessor architecture. and many kinds of GMP have widely developed. However, these GMP architectures still have the problem of effective use of memory system nearby processor cores such as cache and local memory. On the other hand, the authors have proposed OSCAR GMP. which cooperatively works with multigrain parallel processing, to achieve high effective performance and good cost effectiveness. To overcome the problem of effective use of cache and local memory. OSCAR GMP has local data memory(LDM)for processor private data and distributed shared memory(DSN) having two por for synchronization and data transfer among processor cores, in addition to centralized shared memory (CSM). The multigrain parallelizing compiler uses such memory architecture of OSCAR GMP with data localization scheme that fully uses compile time information. This paper proposes a coarse grain task static scheduling scheme considering data localization using live variable analysis. Furthermore, data transfer between CSM and LDM insertion scheme using information of live variable analysis is also described. This data localization scheme is implemented on OSCAR FORTRAN multigrain parallelizing compiler and is evaluated on OSCAR GMP using Tomcatv form SPEC fp 95 benchmark suite. As the results, the proposed scheme gives us about 1.3 times speedup using 20 clocks as the access latency of CSM, and about 1.6 times using 40 clocks as the access latency of CSM respectively against without data localization scheme.

    CiNii

  • Inline Expansion for Improvement of Multi Grain Parallelism

    Jun Shirako, Kouhei Nagasawa, Kazuhisa Ishizaka, Motoki Obata, Hironori Kasahara

    Technical Report of IPSJ, ARC2003-151-2（SHINING2003)    2003.01

  • チップマルチプロセッサ上での粗粒度タスク並列処理によるデータローカライゼーション

    中野 啓史, 小高 剛, 木村 啓二, 笠原 博徳

    情報処理学会研究報告ARC2003-151-3(SHINING2003)    2003.01  [Refereed]

  • マルチグレイン並列性向上のためのインライン展開手法

    白子 準, 長澤 耕平, 石坂 一久, 小幡 元樹, 笠原 博徳

    情報処理学会研究報告ARC2003-151-2(SHINING2003)    2003.01  [Refereed]

  • Data Localization using Coarse Grain Task Parallelization on Chip Multiprocessor

    Hirofumi Nakano, Takeshi Kodaka, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, ARC2003-151-3(SHINING2003)    2003.01  [Refereed]

  • Multigrain parallel processing on OSCAR CMP

    K Kimura, T Kodaka, M Obata, H Kasahara

    INNOVATIVE ARCHITECTURE FOR FUTURE GENERATION HIGH-PERFORMANCE PROCESSORS AND SYSTEMS     56 - 65  2003  [Refereed]

    　View Summary

    It seems that Instruction Level Parallelism (ILP) approach, which has been used by various superscalar processors and VLIW processors for a long time, reaches its limitation of performance improvement. To obtain scalable performance improvement, cost effectiveness and high productivity even in the era of one billion transistors, the cooperative work between software and hardware is getting increasingly important. For this reason, the authors have developed OSCAR (Optimally SCheduled Advanced multiprocessoR) Chip Multiprocessor (OSCAR CMP) and OSCAR multigrain compiler simultaneously. To preserve the scalability in the future, OSCAR CMP has mechanisms for efficient use of parallelism and data locality, and for hiding data transfer overhead. These mechanisms can be fully controlled by the OSCAR multigrain compiler In this paper, the authors focus on multigrain parallel processing on OSCAR CMP, which enables us to exploit loop iteration level parallelism and coarse grain task parallelism in addition to ILP from the entire of a program. Performance of multigrain parallel processing on OSCAR CMP architecture is evaluated using SPEC fp 2000195 benchmark suite. When microSPARC like single issue core is used, OSCAR CMP gives us from 1.77 to 3.96 times speedup for four processors against single processor In addition, OSCAR CMP is compared with Sun UltraSPARC II like processor to evaluate cost effectiveness. As a result, OSCAR CMP gives us 1.66 times better performance on the average under the condition that OSCAR CMP and UltraSPARC II are built from almost same number of transistors.

  • Multigrain Parallel Processing on OSCAR Chip Multiprocessor

    Keiji Kimura, Takeshi Kodaka, Motoki Obata, Hironori Kasahara

    Technical Report of IPSJ, ARC2002-150-7    2002.11

  • Multigrain Parallel Processing on Motion Vector Estimation for Single Chip Multiprocessor

    Takeshi Kodaka, Takahisa Suzuki, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, ARC2002-150-6    2002.11

  • OSCAR チップマルチプロセッサ上でのマルチグレイン並列処理

    木村 啓二, 小高 剛, 小幡 元樹, 笠原 博徳

    情報処理学会研究報告ARC2002-150-7    2002.11  [Refereed]

  • OSCAR 型シングルチップマルチプロセッサにおける動きベクトル探索処理

    小高 剛, 鈴木 貴久, 木村 啓二, 笠原 博徳

    情報処理学会研究報告ARC2002-150-6    2002.11  [Refereed]

  • Multigrain Parallel Processing on OSCAR Chip Multiprocessor

    Keiji Kimura, Takeshi Kodaka, Motoki Obata, Hironori Kasahara

    Technical Report of IPSJ, ARC2002-150-7    2002.11  [Refereed]

  • Multigrain Parallel Processing on Motion Vector Estimation for Single Chip Multiprocessor

    Takeshi Kodaka, Takahisa Suzuki, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, ARC2002-150-6    2002.11  [Refereed]

  • Multigrain Parallelizing Compiler for Chip Multiprocessors to High Performance Severs

    H. Kasahara

    Intel ICRC, China    2002.11  [Refereed]

  • A standard task graph set for fair evaluation of multiprocessor scheduling algorithms

    Takao Tobita, Hironori Kasahara

    Journal of scheduing, John Wiley & Sons Ltd   5 ( 5 ) 379 - 394  2002.10  [Refereed]

    CiNii

  • シングルチップマルチプロセッサにおけるJPEGエンコーディングのマルチグレイン並列処理

    小高 剛, 内田 貴之, 木村 啓二, 笠原 博徳

    情報処理学会ハイパフォーマンスコンピューティングシステム論文誌   43 ( Sig.6(HPS5) ) 153 - 62  2002.09  [Refereed]

  • NEDO-1 アドバンスト並列化コンパイラ技術

    笠原 博徳

    情報処理学会・電子情報通信学会FIT (Forum on Information Technology), 大型プロジェクト紹介(国家プロジェクト紹介), 東工大 百年記念館フェライト会議室    2002.09  [Refereed]

  • OSCAR Multigrain Parallelizing Compiler for Chip Multiprocessors to High Performance Severs

    H. Kasahara

    Polish-Japanese Institute of Information Technology (PJIIT) hosted by Prof. Marek Tudruj    2002.09  [Refereed]

  • NEDO-1 Advanced Parallelizing Technology, IPSJ-IEICE FIT2002 (Forum on Information Technology), National Project Introduction

    H. Kasahara

       2002.09  [Refereed]

  • Cache Optimization among Coarse Grain Tasks considering Line Conflict Miss

    Kazuhisa Ishizaka, Hirofumi Nakano, Motoki Obata, Hironori Kasahara

    Technical Report of IPSJ, ARC2002-149-25(SWoPP2002)    2002.08

  • Performance of OSCAR Multigrain Parallelizing Compiler on SMPs

    Motoki Obata, Jun Shirako, Kazuhisa Ishizaka, Hironori Kasahara

    Technical Report of IPSJ, ARC2002-149-20(SWoPP2002)    2002.08  [Refereed]

  • ラインコンフリクトミスを考慮した粗粒度タスク間キャッシュ最適化

    石坂 一久, 中野 啓史, 小幡 元樹, 笠原 博徳

    情報処理学会研究報告ARC2002-149-25(SWoPP2002)    2002.08  [Refereed]

  • SMPシステム上でのOSCARマルチグレイン並列化コンパイラの性能

    小幡 元樹, 石坂 一久, 白子 準, 笠原 博徳

    情報処理学会研究報告ARC2002-149-20(SWoPP2002)    2002.08  [Refereed]

  • ミレニアムプロジェクトIT21アドバンスト並列化コンパイラにおけるマルチグレイン並列処理

    笠原 博徳

    自律分散システム研究会(名古屋大学)    2002.08  [Refereed]

  • Cache Optimization among Coarse Grain Tasks considering Line Conflict Miss

    Kazuhisa Ishizaka, Hirofumi Nakano, Motoki Obata, Hironori Kasahara

    Technical Report of IPSJ, ARC2002-149-25(SWoPP2002)    2002.08  [Refereed]

  • Multigrain Parallel Processing in Millennium Project IT21 Advanced Parallelizing Compiler

    H. Kasahara

    Sig. on Autonomous Distributed Systems, Nagoya University hosted by Prof. Toshio Fukuda    2002.08  [Refereed]

  • Coarse Grain Task Parallel Processing with Automatic Determination Scheme of Parallel Processing Layer

    Jun Shirako, Hiroki Kaminaga, Noriaki Kondo, Kazuhisa Ishizaka, Motoki Obata, Hironori Kasahara

    Technical Report of IPSJ, ARC2002-148-4   2002 ( 37 ) 19 - 24  2002.05

    　View Summary

    For improvement performance and usablity of multiprocessor systems used from a chip multiprocessor to high performance computer, a multi-grain compilation scheme, which exploits coarse grain parallelism among loops, subroutines and basic blocks, conventional medium grain parallelism among loop-iterations in a Doall loop and near fine grain parallelism among statements inside a basic block, is important. In order to extract the parallelism of each layer(nest level) hierarchically and achieve a better performance in multi-grain parallel processing, it is necessary to determine how much processors or groups of processors(,or processor clusters) should be assigned to the layers, according to the parallelism of the target program layers. This paper proposes an automatic determination scheme of the number of processors to be assigned to each layer, to use the parallelism of each hierarchy in a program efficiently. Effectiveness of the proposed scheme is evaluated on IBM RS6000 SMP server with 8 processors using 8 programs of SPEC95FP.

    CiNii

  • Evaluation of Overhead with Coarse Grain Task Parallel Processing on SMP Machines

    Yasutaka Wada, Hirofumi Nakano, Keiji Kimura, Motoki Obata, Hironori Kasahara

    Technical Report of IPSJ, ARC2002-148-3    2002.05

  • 世界トップのIT産業を担う技術と人材の育成

    笠原博徳

    早稲田大学広報誌 月刊 Campus Now 2002/5号    2002.05  [Refereed]  [Invited]

  • シングルチップマルチプロセッサにおける JPEGエンコーディングのマルチグレイン並列処理

    小高 剛, 内田 貴之, 木村 啓二, 笠原 博徳

    情報処理学会並列処理シンポジウム(JSPP2002)    2002.05  [Refereed]

  • 並列処理階層自動決定手法を用いた粗粒度タスク並列処理

    白子 準, 神長 浩気, 近藤 巧章, 石坂 一久, 小幡 元樹, 笠原博徳

    情報処理学会研究報告ARC2002-148-4    2002.05  [Refereed]

  • SMPマシン上での粗粒度タスク並列処理オーバーへッドの解析

    和田 康孝, 中野 啓史, 木村 啓二, 小幡 元樹, 笠原博徳

    情報処理学会研究報告ARC2002-148-3    2002.05  [Refereed]

  • Upbringing of Technology and Human Resource Aiming at World Top IT Industry

    Hironori Kasahara

    Waseda Univ. Monthly Report "Campus Now" Vol.5, 2002    2002.05  [Refereed]

  • Coarse Grain Task Parallel Processing with Automatic Determination Scheme of Parallel Processing Layer

    Jun Shirako, Hiroki Kaminaga, Noriaki Kondo, Kazuhisa Ishizaka, Motoki Obata, Hironori Kasahara

    Technical Report of IPSJ, ARC2002-148-4    2002.05  [Refereed]

  • Evaluation of Overhead with Coarse Grain Task Parallel Processing on SMP Machines

    Yasutaka Wada, Hirofumi Nakano, Keiji Kimura, Motoki Obata, Hironori Kasahara

    Technical Report of IPSJ, ARC2002-148-3    2002.05  [Refereed]

  • JPEG Encoding using Multigrain Parallel Processing on a Shingle Chip Multiprocessor

    Takeshi Kodaka, Takayuki Uchida, Keiji Kimura, Hironori Kasahara

    Joint Symposium on Parallel Processing 2002 (JSPP2002)    2002.05  [Refereed]

  • 標準タスクグラフセットを用いた実行時間最小マルチプロセッサスケジューリングアルゴリズムの性能評価

    飛田 高雄, 笠原 博徳

    情報処理学会論文誌   43 ( 4 )  2002.04  [Refereed]

  • 共有メモリマルチプロセッサ上でのキャッシュ最適化を考慮した粗粒度タスク並列処理

    石坂 一久, 中野 啓史, 八木 哲志, 小幡 元樹, 笠原 博徳

    情報処理学会論文誌   43 ( 4 )  2002.04  [Refereed]

  • Coarse Grain Task Parallel Processing with Cache Optimization on Shared Memory Multiprocessor

    Kazuhisa Ishizaka, Hirofumi Nakano, Satoshi Yagi, Motoki Obata, Hironori Kasahara

    Trans. of IPSJ   43 ( 4 )  2002.04  [Refereed]

  • A Macrotask selection technique for Data-Localization Scheme on Shared-memory Multi-Processor

    Satoshi Yagi, Hiroki Itagaki, Hirofumi Nakano, Kazuhisa Ishizaka, Motoki Obata, Akimasa Yoshida, Hironori Kasahara

    Technical Report of IPSJ, ARC    2002.03

  • An Analysis-time Procedure Inlining and Flexible Cloning Scheme for Coarse-grain Automatic Parallelizing Compilation

    Shin-ya Kumazawa, Kazuhisa Ishizaka, Motoki Obata, Hironori Kasahara

    Technical Report of IPSJ, ARC    2002.03

  • 粗粒度並列性抽出のための解析時インライニングとフレキシブルクローニング

    熊澤 慎也, 石坂 一久, 小幡 元樹, 笠原 博徳

    情報処理学会研究報告 ARC    2002.03  [Refereed]

  • 共有メモリマルチプロセッサ上でのデータローカライゼーション対象マクロタスク決定手法

    八木 哲志, 板垣 裕樹, 中野 啓史, 石坂 一久, 小幡 元樹, 吉田 明正, 笠原 博徳

    情報処理学会研究報告 ARC    2002.03  [Refereed]

  • An Analysis-time Procedure Inlining and Flexible Cloning Scheme for Coarse-grain Automatic Parallelizing Compilation

    Shin-ya Kumazawa, Kazuhisa Ishizaka, Motoki Obata, Hironori Kasahara

    Technical Report of IPSJ, ARC    2002.03  [Refereed]

  • A Macrotask selection technique for Data-Localization Scheme on Shared-memory Multi-Processor

    Satoshi Yagi, Hiroki Itagaki, Hirofumi Nakano, Kazuhisa Ishizaka, Motoki Obata, Akimasa Yoshida, Hironori Kasahara

    Technical Report of IPSJ, ARC    2002.03  [Refereed]

  • Coarse Grain Task Parallel Processing on Commercial SMPs

    Motoki Obata, Kazuhisa Ishizaka, Hiroki Kaminaga, Hirofumi Nakano, Akimasa Yoshida, Hironori Kasahara

    Technical Report of IPSJ, ARC2002-146-10   2002 ( 9 ) 55 - 60  2002.02

    　View Summary

    This paper evaluates performance of coarse grain task parallel processing using OSCAR Multigrain Parallelizing Compiler for five applications from SPEC95FP and Perfect Club benchmarks on commercial SMP machines. The coarse grain task parallel processing is important to improve the effective performance of SMP machines beyond the limit of the loop parallelism. In this OSCAR compiler, One-time Single Level Thread Generation scheme using OpenMP API and a data localization scheme are used to realize coarse grain task parallelization efficiently on various SMP machines. The evaluation shows that the coarse grain parallel processing gives us 60-430% larger speed up than the automatic loop parallelizing compiler for the five applications by the reduction of overheads of thread management and shared memory access on SMP server IBM RS6000 SP 604e High Node and SMP workstation SUN Ultra80.

    CiNii

  • Multigrain Parallel Processing for JPEG Encoding Program on an OSCAR type Single Chip Multiprocessor

    Takeshi Kodaka, Takayuki Uchida, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, ARC2002-146-4   2002 ( 9 ) 19 - 24  2002.02

    　View Summary

    With the recent increase of multimedia contests using JPEG and MPEG, low cost, low power consumption and high performance processors for multimedia have been expected. Particularly, single chip multiprocessor architecture having simple processor cores is attracting much attention to develop such processors. This paper describes multigrain parallel processing scheme for a JPEG encoding program for OSCAR type single chip multiprocessor and its performance. The evaluation shows an OSCAR type single chip multiprocessor having four single-issue simple processor cores gave us 3.59 times speed-up than sequencial execution and 2.87 times speed-up than OSCAR type single chip multiprocessor that has a four-issue UltraSPARC-II type super-scaler processor core.

    CiNii

  • Multigrain Parallel Processing on Single Chip Multiprocessor

    Takayuki Uchida, Takeshi Kodaka, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, ARC2002-146-3   2002 ( 9 ) 13 - 18  2002.02

    　View Summary

    With the advances in semiconductor integration technology, efficient use of transisors on a chip and scalable performance improvement have been demanded. To satisfy this demand, many researches on next generation microprocessor architectures and its software, especially compilers, have been performed. In these next generation microprocessor architectures, a single chip multiprocessor(SCM) using multigrain parallel processing, which hierarchically exploits different level of parallelism from the whole program, is one of the most promising architectures. This paper evaluates performance of the SCM architectures for multigrain parallel processing, using five application programs from SPEC2000fp and SPEC95fp. The evaluation shows that a four-processor cores SCM using multigrain parallel processing gives us 1.4 to 3.8 times larger speed up against a simple processor.

    CiNii

  • シングルチップマルチプロセッサにおけるマルチグレイン並列処理

    内田 貴之, 木村 啓二, 小高 剛, 笠原 博徳

    情報処理学会研究報告ARC-2002-146-5    2002.02  [Refereed]

  • OSCAR型シングルチップマルチプロセッサ上でのJPEGエンコーディングプログラムのマルチグレイン並列処理

    小高 剛, 内田 貴之, 木村 啓二, 笠原 博徳

    情報処理学会研究報告ARC-2002-146-4    2002.02  [Refereed]

  • 商用SMP上での粗粒度タスク並列処理

    小幡 元樹, 石坂 一久, 神長 浩気, 中野 啓史, 吉田 明正, 笠原 博徳

    情報処理学会研究報告ARC-2002-146-10    2002.02  [Refereed]

  • Multigrain Parallel Processing for JPEG Encoding Program on an OSCAR type Single Chip Multiprocessor

    Takeshi Kodaka, Takayuki Uchida, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, ARC2002-146-4    2002.02  [Refereed]

  • Multigrain Parallel Processing on Single Chip Multiprocessor

    Takayuki Uchida, Takeshi Kodaka, Keiji Kimura, Hironori Kasahara

    Technical Report of IPSJ, ARC2002-146-3    2002.02  [Refereed]

  • Coarse Grain Task Parallel Processing on Commercial SMPs

    Motoki Obata, Kazuhisa Ishizaka, Hiroki Kaminaga, Hirofumi Nakano, Akimasa Yoshida, Hironori Kasahara

    Technical Report of IPSJ, ARC2002-146-10    2002.02  [Refereed]

  • Static coarse grain task scheduling with cache optimization using openMP

    Hirofumi Nakano, Kazuhisa Ishizaka, Motoki Obata, Keiji Kimura, Hironori Kasahara

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)   2327   479 - 489  2002  [Refereed]

    　View Summary

    Effective use of cache memory is getting more important with increasing gap between the processor speed and memory access speed. Also, use of multigrain parallelism is getting more important to improve effective performance beyond the limitation of loop iteration level parallelism. Considering these factors, this paper proposes a coarse grain task static scheduling scheme considering cache optimization. The proposed scheme schedules coarse grain tasks to threads so that shared data among coarse grain tasks can be passed via cache after task and data decomposition considering cache size at compile time. It is implemented on OSCAR Fortran multigrain parallelizing compiler and evaluated on Sun Ultra80 four-processor SMP workstation, using Swim and Tomcatv from the SPEC fp 95. As the results, the proposed scheme gives us 4.56 times speedup for Swim and 2.37 times on 4 processors for Tomcatv respectively against the Sun Forte HPC 6 loop parallelizing compiler. © 2002 Springer Berlin Heidelberg.

    DOI

    Scopus

    2
    Citation
    (Scopus)

  • Multigrain parallel processing for JPEG encoding on a single chip multiprocessor

    T Kodaka, K Kimura, H Kasahara

    INTERNATIONAL WORKSHOP ON INNOVATIVE ARCHITECTURE FOR FUTURE GENERATION HIGH-PERFORMANCE PROCESSORS AND SYSTEMS     57 - 63  2002  [Refereed]

    　View Summary

    With the recent increase of multimedia contents using JPEG and MPEG, low cost, low power consumption and high performance processors for multimedia application have been expected. Particularly, single chip multiprocessor architecture having simple processor cores that will attain good scalability and cost effectiveness is attracting much attention. To exploit full performance of single chip multiprocessor architecture, multigrain parallel processing, which exploits coarse grain task parallelism, loop parallelism and instruction level parallelism, is attractive. This paper describes a multigrain parallel processing scheme for the JPEG encoding on a single chip multiprocessor and its performance. The evaluation shows an OSCAR type single chip multiprocessor having four single-issue simple processor cores gave us 3.59 times speed-up against sequential execution time.

  • 自動並列化コンパイラ協調型シングルチップ・マルチプロセッサの研究

    笠原 博徳

    JEITA/EDS Fair 2002    2002.01  [Refereed]

  • Automatic Parallelizing Compiler Cooperative Single Chip Multiprocessor

    Hironori Kasahara

    JEITA/EDS Fair 2002    2002.01  [Refereed]

  • Humanoid Robots in Waseda University---Hadaly-2 and WABIAN

    S Hashimoto, S Narita, H Kasahara, K Shirai, T Kobayashi, A Takanishi, S Sugano, J Yamaguchi, H Sawada, H Takanobu, K Shibuya, T Morita, T Kurata, N Onoe, K Ouchi, T Noguchi, Y Niwa, S Nagayama, H Tabayashi, Matsui, I, M Obata, H Matsuzaki, A Murasugi, T Kobayashi, S Haruyama, T Okada, Y Hidaki, Y Taguchi, K Hoashi, E Morikawa, Y Iwano, D Araki, J Suzuki, M Yokoyama, Dawa, I, D Nishino, S Inoue, T Hirano, E Soga, S Gen, T Yanada, K Kato, S Sakamoto, Y Ishii, S Matsuo, Y Yamamoto, K Sato, T Hagiwara, T Ueda, N Honda, K Hashimoto, T Hanamoto, S Kayaba, T Kojima, H Iwata, H Kubodera, R Matsuki, T Nakajima, K Nitto, D Yamamoto, Y Kamizaki, S Nagaike, Y Kunitake, S Morita

    Autonomous Robots, 2002Kluwer Academic Publishers. Manufactured in The Netherlands   12 ( 1 ) 25 - 38  2002.01  [Refereed]

    　View Summary

    This paper describes two humanoid robots developed in the Humanoid Robotics Institute, Waseda University. Hadaly-2 is intended to realize information interaction with humans by integrating environmental recognition with vision, conversation capability (voice recognition, voice synthesis), and gesture behaviors. It also possesses physical interaction functions for direct contact with humans and behaviors that are gentle and safe for humans. WABIAN is a robot with a complete human configuration that is capable of walking on two legs and carrying things as with humans. Furthermore, it has functions for information interactions suite for uses at home.

  • Multigrain parallel processing for JPEG encoding on a single chip multiprocessor

    T. Kodaka, K. Kimura, H. Kasahara

    Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems   2002-   57 - 63  2002  [Refereed]

    　View Summary

    With the recent increase of multimedia content using JPEG and MPEG, low cost, low power consumption and high performance processors for multimedia application are desirable. In particular, single chip multiprocessor architecture having simple processor cores that will attain good scalability and cost effectiveness is attracting much attention. To exploit full performance of single chip multiprocessor architecture, multigrain parallel processing, which exploits coarse grain task parallelism, loop parallelism and instruction level parallelism, is attractive. This paper describes a multigrain parallel processing scheme for JPEG encoding on a single chip multiprocessor and its performance. The evaluation shows that an OSCAR type single chip multiprocessor having four single-issue simple processor cores gave a 3.59 times speed-up against sequential execution time.

    DOI

    Scopus

    12
    Citation
    (Scopus)

  • Multigrain automatic parallelization in Japanese Millennium Project IT21 Advanced Parallelizing Compiler

    H Kasahara, M Obata, K Ishizaka, K Kimura, H Kaminaga, H Nakano, K Nagasawa, A Murai, H Itagaki, J Shirako

    PAR ELEC 2002: INTERNATIONAL CONFERENCE ON PARALLEL COMPUTING IN ELECTRICAL ENGINEERING     105 - 111  2002  [Refereed]

    　View Summary

    This paper describes OSCAR multigrain parallelizing compiler which has been developed in Japanese Millennium Project IT21 "Advanced Parallelizing Compiler" project and its performance on SMP machines. The compiler realizes multigrain parallelization for chip-multiprocessors to high-end servers. It hierarchically exploits coarse grain task parallelism among loops, subroutines and basic blocks and near fine grain parallelism among statements inside a basic block in addition to loop parallelism. Also, it globally optimizes cache use over different loops, or coarse grain tasks, based on data localization technique to reduce memory access overhead Current performance of OSCAR compiler for SPEC95fp is evaluated on different SMPs. For example, it gives us 3.7 times speedup for HYDRO2D, 1.8 times for SWIM, 1.7 times for SU2COR, 2.0 times for MGRID, 3.3 times for TURB3D on 8 processor IBM RS6000, against XL Fortran compiler ver:7.1 and 4.2 times speedup for SWIM and 2.2 times speedup for TURB3D on 4 processor Sun Ultra80 workstation against Forte6 update 2.

  • A Static Scheduling Scheme for Coarse Grain Tasks considering Cache Optimization on SMP

    Hirofumi Nakano, Kazuhisa Ishizaka, Motoki Obata, Hironori Kasahara

    IPSJ SIG Notes 2001-ARC-144-12    2001.08

  • Near Fine Grain Parallel Processing on Multimedia Application for Single Chip Multiprocessor

    Takeshi Kodaka, Naohisa Miyashita, Keiji Kimura, Hironori Kasahara

    IPSJ SIG Notes 2001-ARC-144-11    2001.08

  • キャッシュ最適化を考慮したマルチプロセッサシステム上での粗粒度タスクスタティックスケジューリング手法

    中野 啓史, 石坂 一久, 小幡 元樹, 木村 啓二, 笠原 博徳

    情報処理学会研究報告ARC-2001-140-12   2001 ( 76 ) 67 - 72  2001.08  [Refereed]

    CiNii

  • シングルチップマルチプロセッサ上でのマルチメディアアプリケーションの近細粒度並列処理

    小高 剛, 宮下 直久, 木村 啓二, 笠原 博徳

    情報処理学会研究報告ARC-2001-140-11    2001.08  [Refereed]

  • Future of Automatic Parallelizing Compiler

    H. Kasahara

    The 14th International Workshop on Languages and Compilers for Parallel Computing (LCPC'01) Panel: Future of Languages and Compilers, Kentucky    2001.08  [Refereed]

  • A Static Scheduling Scheme for Coarse Grain Tasks considering Cache Optimization on SMP

    Hirofumi Nakano, Kazuhisa Ishizaka, Motoki Obata, Hironori Kasahara

    IPSJ SIG Notes 2001-ARC-144-12    2001.08  [Refereed]

  • Near Fine Grain Parallel Processing on Multimedia Application for Single Chip Multiprocessor

    Takeshi Kodaka, Naohisa Miyashita, Keiji Kimura, Hironori Kasahara

    IPSJ SIG Notes 2001-ARC-144-11    2001.08  [Refereed]

  • A Data Localization Scheme for Coarse Grain Task Parallel Processing on Shared Memory Multiprocessors

    Akimasa Yoshida, Satoshi Yagi, Hironori Kasahara

    Proc. of IEEE International Workshop on Advanced Compiler Technology for High Performance and Embedded Systems     111 - 118  2001.07  [Refereed]

    CiNii

  • OSCAR Single Chip Multiprocessor and Multigrain Parallelizing Compiler

    H. Kasahara

    IEEE International Workshop on Advanced Compiler Technology for High Performance and Embedded Systems (IWACT 2001) Panel : New Architecture and Their Compilers, Romania    2001.07  [Refereed]

  • Automatic Coarse Grain Task Parallel Processing Using OSCAR Multigrain Parallelizing Compiler

    Motoki Obata, Kazuhisa Ishizaka, Hironori Kasahara

    Ninth International Workshop on Compilers for Parallel Computers(CPC 2001)     173 - 182  2001.06  [Refereed]

  • 近細粒度並列処理用シングルチップマルチプロセッサにおけるプロセッサコアの評価

    木村 啓二, 加藤 孝幸, 笠原 博徳

    情報処理学会論文誌   42 ( 4 ) 692 - 703  2001.04  [Refereed]

    CiNii

  • 共有メモリマルチプロセッサシステム上での粗粒度タスク並列処理

    笠原 博徳, 小幡 元樹, 石坂 一久

    情報処理学会論文誌   42 ( 4 )  2001.04  [Refereed]

    CiNii

  • メタスケジューリング--自動並列分散処理の試み

    小出 洋, 笠原 博徳

    bit、共立出版   33 ( 4 ) 10 - 14  2001.04  [Refereed]

    J-GLOBAL

  • Meta-scheduling -- Trial for Automatic Distributed Computing

    Hiroshi Koide, Hironori Kasahara

    bit, Kyoritsu Shuppan   33 ( 4 ) 10 - 14  2001.04  [Refereed]

  • Evaluation of Processor Core Architecture for Single Chip Multiprocessor with Near Fine Grain Parallel Processing

    Keiji Kimura, Takayuki Kato, Hironori Kasahara

    Trans. of IPSJ   42 ( 4 ) 692 - 703  2001.04  [Refereed]

  • Coarse Grain Task Parallel Processing on a Shared Memory Multiprocessor System

    Hironori Kasahara, Motoki Obata, Kazuhisa Ishizaka

    Trans. of IPSJ   42 ( 4 )  2001.04  [Refereed]

  • 資源情報サーバにおける資源情報予測の評価

    小出 洋, 山岸 信寛, 武宮 博, 笠原 博徳

    情報処理学会論文誌   42 ( SIG03 ) 65 - 73  2001.03  [Refereed]

    J-GLOBAL

  • 標準タスクグラフセットを用いたデータ転送オーバーへッドを考慮したスケジューリングアルゴリズムの性能評価

    山口 高弘, 田中 雄一, 飛田 高雄, 笠原 博徳

    情報処理学会第62回全国大会   2Q-01  2001.03  [Refereed]

  • 近細粒度並列処理に適したシングルチップマルチプロセッサのメモリアーキテクチャの評価

    松元 信介, 木村 啓二, 笠原 博徳

    情報処理学会第62回全国大会   4P-01  2001.03  [Refereed]

  • 異機種分散計算機環境におけるOSCARマルチグレイン並列化コンパイラを用いたメタスケジューリング手法

    林 拓也, 茂田 有己光, 小出 洋, 飛田 高雄, 笠原 博徳

    情報処理学会第62回全国大会   3R-01 ( 1 )  2001.03  [Refereed]

    J-GLOBAL

  • メモリ容量を考慮したプレロード・ポストストアスケジューリングアルゴリズムの評価

    田中 崇久, 舟山 洋央, 飛田 高雄, 笠原 博徳

    情報処理学会第62回全国大会   4R-03  2001.03  [Refereed]

  • マルチメディアアプリケーションのシングルチップマルチプロセッサ上での近細粒度並列処理

    小高 剛, 木村 啓二, 宮下 直久, 笠原 博徳

    情報処理学会第62回全国大会   3P-08  2001.03  [Refereed]

  • マルチプロセッサシステム上でのキャッシュ最適化を考慮した粗粒度タスクスタティックスケジューリング手法

    中野 啓史, 石坂 一久, 小幡 元樹, 木村 啓二, 笠原 博徳

    情報処理学会第62回全国大会   4R-02  2001.03  [Refereed]

  • マルチグレイン並列処理用シングルチップマルチプロセッサにおけるデータ転送ユニットの検討

    宮下 直久, 木村 啓二, 小高 剛, 笠原 博徳

    情報処理学会第62回全国大会   4P-02  2001.03  [Refereed]

  • データマイニングツールdataFORESTを用いた異機種分散計算機環境におけるプロセッサ負荷予測

    茂田 有己光, 林 拓也, 小出 洋, 鹿島 亨, 筒井 宏明, 笠原 博徳

    情報処理学会第62回全国大会   3R-02 ( 1 )  2001.03  [Refereed]

    J-GLOBAL

  • OSCARマルチグレイン並列化コンパイラとシングルチップ・マルチプロセッサ

    笠原 博徳

    京都大学大型計算機センター研究開発部第66回研究セミナー    2001.03  [Refereed]

  • OSCAR Multigrain Parallelizing Compiler and Single Chip Multiprocessor

    H. Kasahara

    Data Processing Center, Kyoto University    2001.03  [Refereed]

  • Automatic coarse grain task parallel processing on SMP using openMP

    Hironori Kasahara, Motoki Obata, Kazuhisa Ishizaka

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)   2017   189 - 207  2001  [Refereed]

    　View Summary

    This paper proposes a simple and efficient implementation method for a hierarchical coarse grain task parallel processing scheme on a SMP machine. OSCAR multigrain parallelizing compiler automatically generates parallelized code including OpenMP directives and its performance is evaluated on a commercial SMP machine. The coarse grain task parallel processing is important to improve the effective performance of wide range of multiprocessor systems from a single chip multiprocessor to a high performance computer beyond the limit of the loop parallelism. The proposed scheme decomposes a Fortran program into coarse grain tasks, analyzes parallelism among tasks by “Earliest Executable Condition Analysis” considering control and data dependencies, statically schedules the coarse grain tasks to threads or generates dynamic task scheduling codes to assign the tasks to threads and generates OpenMP Fortran source code for a SMP machine. The thread parallel code using OpenMP generated by OSCAR compiler forks threads only once at the beginning of the program and joins only once at the end even though the program is processed in parallel based on hierarchical coarse grain task parallel processing concept. The performance of the scheme is evaluated on 8-processor SMP machine, IBM RS6000 SP 604e High Node, using a newly developed OpenMP backend of OSCAR multigrain compiler. The evaluation shows that OSCAR compiler with IBM XL Fortran compiler version 5.1 gives us 1.5 to 3 times larger speedup than the native XL Fortran compiler for SPEC 95fp SWIM, TOMCATV, HYDRO2D, MGRID and Perfect Benchmarks ARC2D.

    DOI

    Scopus

    14
    Citation
    (Scopus)

  • 特集:並列処理

    笠原 博徳

    情報処理学会論文誌   42 ( 4 ) 651 - 920  2001  [Refereed]

    CiNii

  • A Data-Localization Scheme for Macrotask-Graph with Data Dependencies on SMP

    Akimasa Yoshida, Satoshi Yagi, Hironori Kasahara

    Technical Report of IPSJ, ARC-141-6    2001.01

  • Evaluation of coarse grain task parallel processing on the shared memory multiprocessor system

    Kazuhisa Ishizaka, Satoshi Yagi, Motoki Obata, Akimasa Yoshida, Hironori Kasahara

    Technical Report of IPSJ, ARC-141-7    2001.01

  • 共有メモリマルチプロセッサシステム上での粗粒度タスク並列実現手法の評価

    石坂 一久, 八木 哲志, 小幡 元樹, 吉田 明正, 笠原 博徳

    情報処理学会研究報告ARC-141-7    2001.01  [Refereed]

  • SMP上でのデータ依存マクロタスクグラフのデータローカライゼーション手法

    吉田 明正, 八木 哲志, 笠原 博徳

    情報処理学会研究報告ARC-141-6    2001.01  [Refereed]

  • アドバンスト並列化コンパイラ技術研究開発の概要

    笠原 博徳

    経済産業省・NEDOミレニアムプロジェクト, 日本情報処理開発協会先端情報技術研究所    2001.01  [Refereed]

  • Evaluation of coarse grain task parallel processing on the shared memory multiprocessor system

    Kazuhisa Ishizaka, Satoshi Yagi, Motoki Obata, Akimasa Yoshida, Hironori Kasahara

    Technical Report of IPSJ, ARC-141-7    2001.01  [Refereed]

  • A Data-Localization Scheme for Macrotask-Graph with Data Dependencies on SMP

    Akimasa Yoshida, Satoshi Yagi, Hironori Kasahara

    Technical Report of IPSJ, ARC-141-6    2001.01  [Refereed]

  • Evaluation of Single Chip Multiprocessor Core Architecture with Near Fine Grain Parallel Processing

    Keiji Kimura, Hironori Kasahara

    Proc. of International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'01)    2001.01  [Refereed]

  • Overview of METI/NEDO Millennium Project 'Advanced Parallelizing Compiler'

    H. Kasahara

    Japan Information Processing Development Center Research Institute for Advanced Information Technology    2001.01  [Refereed]

  • OSCAR Multigrain Parallelizing Compiler and Single Chip Multiprocessor

    H. Kasahara

    University of Illinois at Urbana-Champaign, Hosted by Prof. David Padua, USA    2000.11  [Refereed]

  • Coarse-grain Task Parallel Processing using the OpenMP backend of the OSCAR Multigrain Parallelizing Compiler

    Kazuhisa Ishizaka, Hironori Kasahara, Motoki Obata

    Proc. of Third International Symposium, ISHPC 2000     352 - 365  2000.10  [Refereed]

  • Multigrain Parallel Processing Model for Future Single Chip Multiprocessor Systems

    H. Kasahara

    ISHPC2000, Panel "Programming Models for New Architectures"    2000.10  [Refereed]

  • Evaluation of the resource information prediction in the resource information server

    Hiroshi Koide, Nobuhiro Yamagishi, Hiroshi Takemiya, Hironori Kasahara

    Technical Report of IPSJ,PRO   42 ( SIG3(PRO10) )  2000.08  [Domestic journal]

    Authorship：Last author

    J-GLOBAL

  • Processor Core Architecture of Single Chip Multiprocessor for Near Fine Grain Parallel Processing

    Keiji Kimura, Takayuki Uhida, Takayuki Kato, Hironori Kasahara

    Technical Report of IPSJ, ARC-139-16    2000.08

  • Coarse Grain Task Parallel Processing with OpenMP API

    Kazuhisa Ishizaka, Motoki Obata, Hironori Kasahara

    Technical Report of IPSJ, ARC-139-32    2000.08

  • OpenMPを用いた粗粒度タスク並列処理現

    石坂 一久, 小幡 元樹, 笠原 博徳

    情報処理学会研究報告ARC-139-32(SWoPP2000)    2000.08  [Refereed]

  • 近細粒度並列処理用シングルチップマルチプロセッサにおけるプロセッサコアの構成

    木村 啓二, 内田 貴之, 加藤 孝幸, 笠原 博徳

    情報処理学会研究報告ARC-139-16(SWoPP2000)    2000.08  [Refereed]

  • Coarse Grain Task Parallel Processing with OpenMP API

    Kazuhisa Ishizaka, Motoki Obata, Hironori Kasahara

    Technical Report of IPSJ, ARC-139-32    2000.08  [Refereed]

  • Processor Core Architecture of Single Chip Multiprocessor for Near Fine Grain Parallel Processing

    Keiji Kimura, Takayuki Uhida, Takayuki Kato, Hironori Kasahara

    Technical Report of IPSJ, ARC-139-16    2000.08  [Refereed]

  • 標準タスクグラフセットを用いたマルチプロセッサスケジューリングアルゴリズムの性能評価

    飛田 高雄, 笠原 博徳

    情報処理学会2000年記念並列処理シンポジウム(JSPP2000)論文集     131 - 138  2000.05  [Refereed]

  • メタスケジューリングのための資源情報サーバの構築

    小出 洋, 山岸 信寛, 武宮 博, 林 拓也, 引田 雅之, 笠原 博徳

    計算工学講演会論文集   5  2000.05  [Refereed]

  • Performance Evaluation of Multiprocessor Scheduling Algorithms Using Standard Task Graph Set

    T. Tobita, H. Kasahara

    Joint Symposium on Parallel Processing 2000 (JSPP2000)     131 - 138  2000.05  [Refereed]

  • An Analysis-time Procedure Inlining Scheme for Multi-grain Automatic Parallelizing Compilation

    K. Yoshii, G. Matsui, M. Obata, S. Kumazawa, H. Kasahara

    IPSJ ARC/HPC    2000.03

  • Performance Evaluation and Parallelize of Electronic Circuit Simulation which generate code without array indirect access

    K. Manaka, R. Osakabe, Y. Maekawa, H. Kasahara

    IPSJ ARC/HPC    2000.03

  • 配列間接アクセスを用いないコード生成法による電子回路シミュレーションの高速化

    間中 邦之, 刑部 亮, 前川 仁孝, 笠原 博徳

    情報処理学会第60回全国大会   5H-08  2000.03  [Refereed]

  • 解析時インライニングを用いたマルチグレイン自動並列化手法

    吉井 謙一郎, 松井 巌徹, 小幡 元樹, 熊澤 慎也, 笠原 博徳

    情報処理学会第60回全国大会   4J-03  2000.03  [Refereed]

  • メモリ容量を考慮したデータプレロード・マルチプロセッサスケジューリング

    増田 高史, 飛田 高雄, 舟山 洋央, 笠原博徳

    情報処理学会第60回全国大会   4J-06  2000.03  [Refereed]

  • マルチグレイン並列処理における階層的並列処理のためのプロセッサクラスタリング決定手法

    山本 正行, 山本 晃正, 小幡 元樹, 笠原 博徳

    情報処理学会第60回全国大会   4J-05  2000.03  [Refereed]

  • データ依存のみを持つ任意形状のマクロタスクグラフに対するデータローカライゼーション手法

    成清暁博, 八木哲志, 松崎秀則, 小幡元樹, 吉田明正, 笠原博徳

    情報処理学会第60回全国大会   4J-02  2000.03  [Refereed]

  • シングルチップマルチプロセッサの近細粒度並列処理に対する性能評価

    加藤 考幸, 尾形 航, 木村 啓二, 内田 貴之, 笠原 博徳

    情報処理学会第60回全国大会   4J-07  2000.03  [Refereed]

  • SMP上での有限要素・境界要素法併用法による電磁界解析アプリケーション並列処理

    金子 大作, 小幡 元樹, 若尾 真治, 小貫 天, 笠原 博徳

    情報処理学会第60回全国大会   5H-07  2000.03  [Refereed]

  • OpenMPを用いたマルチグレイン並列処理の実現

    石坂 一久, 小幡 元樹, 瀧 康太郎, 笠原 博徳

    情報処理学会第60回全国大会   4J-04  2000.03  [Refereed]

  • 配列間接アクセスを用いないコード生成法による電子回路シミュレーションの高速化とその並列処理

    間中 邦之, 刑部 亮, 前川 仁孝, 笠原 博徳

    情報処理学会ARC研究会/HPC研究会    2000.03  [Refereed]

  • マルチグレイン自動並列化のための解析時インライニング

    吉井 謙一郎, 松井 巌徹, 小幡 元樹, 熊澤 慎也, 笠原 博徳

    情報処理学会ARC研究会/HPC研究会    2000.03  [Refereed]

  • Performance Evaluation and Parallelize of Electronic Circuit Simulation which generate code without array indirect access

    K. Manaka, R. Osakabe, Y. Maekawa, H. Kasahara

    IPSJ ARC/HPC    2000.03  [Refereed]

  • An Analysis-time Procedure Inlining Scheme for Multi-grain Automatic Parallelizing Compilation

    K. Yoshii, G. Matsui, M. Obata, S. Kumazawa, H. Kasahara

    IPSJ ARC/HPC    2000.03  [Refereed]

  • Evaluation of the resource information prediction in the resource information server

    Hiroshi Koide, Nobuhiro Yamagishi, Hiroshi Takemiya, Hironori Kasahara

    Trans. of IPSJ: Programming   42 ( SIG03 ) 65 - 73  2000.03  [Refereed]  [Domestic journal]

    Authorship：Last author

    J-GLOBAL

  • Near fine grain parallel processing using static scheduling on single chip multiprocessors

    K Kimura, H Kasahara

    INNOVATIVE ARCHITECTURE FOR FUTURE GENERATION HIGH-PERFORMANCE PROCESSORS AND SYSTEMS     23 - 31  2000  [Refereed]

    　View Summary

    With the increase of the number of transistors integrated on a chip, efficient use of transistors and scalable improvement of effective performance of a processor are getting important problems. However it has been thought that popular superscalar and VLIW would have difficulty, to obtain scalable improvement of effective performance in future because of the limitation of instruction level parallelism. To cope with this problem, a single chip multiprocessor (SCM) approach,vith multi grain parallelprocessing inside a chip, which hierarchically exploits loop parallelism and coarse grain parallelism among subroutines, loops and basic blocks in addition to instruction level parallelism, is thought one of the most promising approaches. This paper evaluates effectiveness of the single chip multiprocessor architectures with a shared cache, global registers, distributed shared memory and/or local memory for near fine grain parallel processing as the first step of research on SCM architecture to support multi grain parallel processing. The evaluation shows OSCAR (Optimally Scheduled Advanced Multiprocessor architecture having distributed shared memory and local memory in addition to centralized shared memory and attachment of global register gives us significant speed up such as 13.8% to 143.8% for four processors compared with shared cache architecture for applications which have been difficult to extract parallelism effectively.

  • A Data-Localization Scheme for Macrotask-Graphs with Data Dependencies

    A. Narikiyo, H. Matsuzaki, M. Obata, A. Yoshida, H. Kasahara

    Technical Report of IPSJ, ARC-136-8   2000 ( 1 ) 43 - 48  2000.01

    　View Summary

    This paper proposes a data-localization scheme for a part with data dependence edges in any kinds of macrotask-graphs in hierarchical coarse grain parallel processing. First, multiple loops having data dependence are decomposed into data-localization-groups in each macrotaskgraph layer. Next, the compiler generates a hierarchical dynamic scheduling routine with partial static task assignment, which assigns macrotasks inside data-localization-group to the same processor or processor-cluster in each layer, so that shared data can be transferred via local memory. This data localization scheme can be applied to a part or the whole macrotask graph which only has data dependence edges. This data localization scheme also handles loops with the lower and upper limit given by variables. As a result, most of array data is transferred via local memory. Finally, this paper describes the performance evaluation on a multi-processor system OSCAR. The evaluation shows that hierarchical coarse grain parallel processing with data-localization can reduce execution time about 20% compared with hierarchical coarse grain parallel processing without data-localization.

    CiNii

  • データ依存のみを持つマクロタスクグラフに対するデータローカライゼーション手法

    成清 暁博, 松崎 秀則, 小幡 元樹, 吉田 明正, 笠原 博徳

    情報処理学会ARC136-8研究会     43 - 48  2000.01  [Refereed]

  • A Data-Localization Scheme for Macrotask-Graphs with Data Dependencies

    A. Narikiyo, H. Matsuzaki, M. Obata, A. Yoshida, H. Kasahara

    Technical Report of IPSJ, ARC-136-8   2000 ( 1 ) 43 - 48  2000.01  [Refereed]

    　View Summary

    This paper proposes a data-localization scheme for a part with data dependence edges in any kinds of macrotask-graphs in hierarchical coarse grain parallel processing. First, multiple loops having data dependence are decomposed into data-localization-groups in each macrotaskgraph layer. Next, the compiler generates a hierarchical dynamic scheduling routine with partial static task assignment, which assigns macrotasks inside data-localization-group to the same processor or processor-cluster in each layer, so that shared data can be transferred via local memory. This data localization scheme can be applied to a part or the whole macrotask graph which only has data dependence edges. This data localization scheme also handles loops with the lower and upper limit given by variables. As a result, most of array data is transferred via local memory. Finally, this paper describes the performance evaluation on a multi-processor system OSCAR. The evaluation shows that hierarchical coarse grain parallel processing with data-localization can reduce execution time about 20% compared with hierarchical coarse grain parallel processing without data-localization.

    CiNii

  • Performance evaluation of minimum execution time multiprocessor scheduling algorithms using standard task graph set

    T Tobita, M Kouda, H Kasahara

    PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, VOLS I-V     745 - 751  2000  [Refereed]

    　View Summary

    This paper evaluates performance of heuristic algorithms such as CP (Critical Path), CP/MISF (Critical Path/Most Immediate Successors First), practical sequential optimization algorithm DF/IHS (Depth First/Implicit Heuristic Search) and practical parallel optimization algorithm PDF/IHS (Parallelized DF/IHS) using a "Standard Task Graph Set" for evaluation of multiprocessor scheduling algorithms. The Standard Task Graph Set has been developed to allow worldwide researchers to evaluate multiprocessor scheduling algorithms fairly under the same evaluation conditions. It includes random task graphs generated by several generation methods that were used in the previous papers published by many research groups. Performance evaluation shows that PDF/IHS gives us optimal solutions for 96.06% of tested 660 task graphs with 50 to 1900 tasks by using 6 parallel processors within 600 seconds in wall-clock, and heuristic algorithms can give us optimal solutions for about 75% of tested graphs.

  • Performance evaluation of minimum execution time multiprocessor scheduling algorithms using standard task graph set

    T Tobita, M Kouda, H Kasahara

    PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, VOLS I-V   43 ( 4 ) 745 - 751  2000  [Refereed]

    　View Summary

    This paper evaluates performance of heuristic algorithms such as CP (Critical Path), CP/MISF (Critical Path/Most Immediate Successors First), practical sequential optimization algorithm DF/IHS (Depth First/Implicit Heuristic Search) and practical parallel optimization algorithm PDF/IHS (Parallelized DF/IHS) using a "Standard Task Graph Set" for evaluation of multiprocessor scheduling algorithms. The Standard Task Graph Set has been developed to allow worldwide researchers to evaluate multiprocessor scheduling algorithms fairly under the same evaluation conditions. It includes random task graphs generated by several generation methods that were used in the previous papers published by many research groups. Performance evaluation shows that PDF/IHS gives us optimal solutions for 96.06% of tested 660 task graphs with 50 to 1900 tasks by using 6 parallel processors within 600 seconds in wall-clock, and heuristic algorithms can give us optimal solutions for about 75% of tested graphs.

  • マルチグレイン並列化FORTRANコンパイラ

    岡本 雅巳, 小幡 元樹, 松井 巌徹, 松崎 秀則, 笠原 博徳, 成田 誠之助

    情報処理学会論文誌   40 ( 12 ) 4296 - 4308  1999.12  [Refereed]

    　View Summary

    This paper describes a FORTRAN multi-grain parallelizing compiler. The multi-grain parallelizing compiler improves effective performance and ease of use of multiprocessor systems from single-chip multiprocessors to supercomputers. Multi-grain parallelizing scheme realizes effective parallel processing over the whole program by hierarchically appling coarse grain parallelization among subroutines, loops and basic blocks, and fine grain parallelization among statements or instructions in addition to conventional loop parallelization.

    CiNii

  • Multi-grain Parallelizing FORTRAN Compiler

    M. Okamoto, M. Obata, G. Matsui, H. Matsuzaki, H. Kasahara, S. Narita

    Trans. of IPSJ   40 ( 12 ) 4296 - 4308  1999.12  [Refereed]

    　View Summary

    This paper describes a FORTRAN multi-grain parallelizing compiler. The multi-grain parallelizing compiler improves effective performance and ease of use of multiprocessor systems from single-chip multiprocessors to supercomputers. Multi-grain parallelizing scheme realizes effective parallel processing over the whole program by hierarchically appling coarse grain parallelization among subroutines, loops and basic blocks, and fine grain parallelization among statements or instructions in addition to conventional loop parallelization.

    CiNii

  • Memory access analyzer for a Multi-grain parallel processing

    K. Iwai, M. Obata, K. Kimura, H. Amano, H. Kasahara

    Technical Report of IEICE,CPSY99   99 ( 252 ) 1 - 8  1999.08

  • Performance Evaluation of Near Fine Grain Parallel Processing on the Single Chip Multiprocessor

    K. Kimura, K. Manaka, W. Ogata, M. Okamoto, H. Kasahara

    Technical Report of IPSJ, ARC-134-5     19 - 24  1999.08

  • マルチグレイン並列化コンパイラのメモリアクセスアナライザ

    岩井 啓輔, 小幡 元樹, 木村 啓二, 天野 英晴, 笠原 博徳

    電子通信情報学会技術報告CPSY99-62   99 ( 252 ) 1 - 8  1999.08  [Refereed]

  • シングルチップマルチプロセッサ上での近細粒度並列処理の性能評価

    木村 啓二, 間中 邦之, 尾形 航, 岡本 雅巳, 笠原 博徳

    情報処理学会研究報告ARC134-4     19 - 24  1999.08  [Refereed]

  • Performance Evaluation of Near Fine Grain Parallel Processing on the Single Chip Multiprocessor

    K. Kimura, K. Manaka, W. Ogata, M. Okamoto, H. Kasahara

    Technical Report of IPSJ, ARC-134-5     19 - 24  1999.08  [Refereed]

  • Memory access analyzer for a Multi-grain parallel processing

    K. Iwai, M. Obata, K. Kimura, H. Amano, H. Kasahara

    Technical Report of IEICE,CPSY99   99 ( 252 ) 1 - 8  1999.08  [Refereed]

  • An Automatic Coarse Grain Parallel Processing Scheme Using Multiprocessor Scheduling Algorithms Considering Overlap of Task Execution and Data Transfer

    H. Kasahara, M. Kogou, T. Tobita, T. Masuda, T. Tanaka

    Proc. SCI99 and ISAS99   9   82 - 89  1999.08  [Refereed]

    CiNii

  • Meta-scheduling for a Cluster of Supercomputers

    H. Koide, T. Hirayama, A. Murasugi, T. Hayashi, H. Kasahara

    Proc. ICS99 Workshop     63 - 69  1999.06  [Refereed]

    CiNii

  • A Standard Task Graph Set for Fair Evaluation of Multiprocessor Scheduling Algorithms

    T. Tobita, H. Kasahara

    Proc. ICS99 Workshop     71 - 77  1999.06  [Refereed]

  • 階層型粗粒度並列処理における同一階層内ループ間データローカライゼーション手法

    吉田 明正, 越塚 健一, 岡本 雅巳, 笠原 博徳

    情報処理学会論文誌   40 ( 5 ) 2054 - 2063  1999.05  [Refereed]

    　View Summary

    This paper proposes a data-localization scheme for hierarchical macro-dataflow processing, which hierachically exploits coarse-grain parallelism. The proposed data-localization scheme consists of three parts: (1) hierarchical loop aligned decomposition, which decomposes multiple loops having data dependences into data-localization-groups in each layer; (2) generation of hierarchical dynamic sheduling routine with partial static task assignment, which assigns macrotasks inside data-localization-group to the same processor-cluster in each layer; (3) generation of data transfer code via local memory inside data-localization-group. Performance evaluation on a multiprocessor system OSCAR shows that hierarchical macro-dataflow processing with data-localization can reduce execution time by 10-20% compared with hierarchical macro-dataflow processing without data-localization.

    CiNii

  • シングルチップマルチプロセッサ上での近細粒度並列処理

    木村 啓二, 尾形 航, 岡本 雅巳, 笠原 博徳

    情報処理学会論文誌   40 ( 5 ) 1924 - 1934  1999.05  [Refereed]

  • 並列分散科学技術計算の支援環境─SSP─

    武宮 博, 太田 浩史, 今村 俊幸, 小出 洋, 松田 勝之, 樋口 健二, 平山 俊雄, 笠原 博徳

    計算工学講演会論文集   4  1999.05  [Refereed]

  • Near Fine Grain Parallel Processing on Single Chip Multiprocessors

    K. Kimura, W. Ogata, M. Okamoto, H. Kasahara

    Trans. of IPSJ   40 ( 5 ) 1924 - 1934  1999.05  [Refereed]

    CiNii

  • A Data-Localization Scheme among Loops for each Layer in Hierarchical Coarse Grain Parallel Processing

    A.Yoshida, K. Koshizuka, M. Okamoto, H. Kasahara

    Trans. of IPSJ   40 ( 5 ) 2054 - 2063  1999.05  [Refereed]

    　View Summary

    This paper proposes a data-localization scheme for hierarchical macro-dataflow processing, which hierachically exploits coarse-grain parallelism. The proposed data-localization scheme consists of three parts: (1) hierarchical loop aligned decomposition, which decomposes multiple loops having data dependences into data-localization-groups in each layer; (2) generation of hierarchical dynamic sheduling routine with partial static task assignment, which assigns macrotasks inside data-localization-group to the same processor-cluster in each layer; (3) generation of data transfer code via local memory inside data-localization-group. Performance evaluation on a multiprocessor system OSCAR shows that hierarchical macro-dataflow processing with data-localization can reduce execution time by 10-20% compared with hierarchical macro-dataflow processing without data-localization.

    CiNii

  • 処理とデータ転送のオーバーラップのための自動並列化手法

    古郷 誠, 田中 崇久, 藤本 謙作, 岡本 雅巳, 笠原 博徳

    情報処理学会第58回全国大会   3H-06  1999.03  [Refereed]

  • 最早実行可能条件解析を用いたキャッシュ最適化手法

    稲石 大祐, 木村 啓二, 藤本 謙作, 尾形 航, 岡本 雅巳, 笠原 博徳

    情報処理学会第58回全国大会   3H-07  1999.03  [Refereed]

  • マルチグレイン並列処理におけるサブルーチンを含むデータローカライゼーション手法

    宇治川 泰史, 成清 暁博, 小幡 元樹, 吉田 明正, 岡本 雅巳, 笠原 博徳

    情報処理学会第58回全国大会   2D-05  1999.03  [Refereed]

  • OSCARマルチグレイン並列化コンパイラを用いたスーパーコンピュータクラスタのためのメタ・スケジューリング手法

    村杉 明夫, 林 拓也, 飛田 高雄, 小出 洋, 笠原 博徳

    情報処理学会第58回全国大会   2D-06  1999.03  [Refereed]

  • OSCARマルチグレイン並列化コンパイラにおける階層的並列処理手法

    山本 晃正, 稲石 大祐, 宇治川 泰史, 小幡 元樹, 岡本 雅巳, 笠原 博徳

    情報処理学会第58回全国大会   2D-04  1999.03  [Refereed]

  • Near fine grain parallel processing using static scheduling on single chip multiprocessors

    Keiji Kimura, Hironori Kasahara

    Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems   1999-   23 - 31  1999  [Refereed]

    　View Summary

    With the increase of the number of transistors integrated on a chip, efficient use of transistors and scalable improvement of effective performance of a processor are getting im-portant problems. However, it has been thought that popular superscalar and VLIW would have difficulty to obtain scalable improvement of effective performance in future because of the limitation of instruction level parallelism. To cope with this problem, a single chip multiprocessor (SCM) approach with multi grain parallel processing inside a chip, which hierarchically exploits loop parallelism and coarse grain parallelism among subroutines, loops and basic blocks in addition to instruction level parallelism, is thought one of the most promising approaches. This paper evaluates effectiveness of the single chip multiprocessor architectures with a shared cache, global registers, distributed shared memory and/or local memory for near fine grain parallel processing as the first step of research on SCM architecture to support multi grain parallel processing. The evaluation shows OSCAR (Optimally Scheduled Advanced Multiprocessor) architecture having distributed shared memory and local memory in addition to centralized shared memory and attachment of global register gives us significant speed up such as 13.8% to 143.8% for four pro-cessors compared with shared cache architecture for applications which have been difficult to extract parallelism effectively.

    DOI

    Scopus

    7
    Citation
    (Scopus)

  • Job Scheduling Scheme for Pure Space Sharing among Rigid Jobs

    K. Aida, H. Kasahara, S. Narita

    Proc. 4th Workshop on Job Scheduling Strategies for Parallel Processing     98 - 121  1998.12  [Refereed]

  • OSCAR Scalable Multigrain Parallelizing Compiler for Single Chip Multiprocessors to A Cluster of Supercomputers

    H. Kasahara

    Hosted by Prof. David Padua, University of Illinois at Urbana-Champaign    1998.11  [Refereed]

  • A Cache Optimization with Earliest Executable Condition Analysis

    D. Inaishi, K. Kimura, K. Fujimoto, W. Ogata, M. Okamoto, H. Kasahara

    Technical Report of IPSJ, ARC-130-6   1998 ( 70 ) 31 - 36  1998.08

    　View Summary

    Cache optimizations by a compiler for a single processor machine have been mainly applied to a singlenested loop.On the contrary, this paper proposes a cache optimization scheme using earliest executable condition analysis for FORTRAN programs on a single processor system.OSCAR FORTRAN multi-grain automatic parallelizing compiler decomposes a FORTRAN program into three types of macrotasks(MT), such as loops, subroutines and basic blocks, and analyzes the earliest executable condition of each MT to extract coarse grain parallelism among MTs and generates a macrotask graph(MTG).The MTG represents data dependence and extended control dependence among MTs and an information of shared data among MTs.By using this MTG, a compiler realizes global code motion to use cache effectively.The code motion technique moves a MT, which accesses data accessed by a precedent MT on MTG, immediately after the precedent MT to increase a cache hit rate. This optimization is realized using OSCAR multi-grain compiler as a preprocessor to output an optimized sequential FORTRAN code.A performance evaluation shows about 62% speed up compared with original program on 167MHz UltraSPARC.

    CiNii

  • Multigrain parallel Processing on the Single Chip Multiprocessor

    K. Kimura, W. Ogata, M. Okamoto, H. Kasahara

    Technical Report of IPSJ,ARC-130-5    1998.08

  • Evaluation of Multigrain Parallelism using OSCAR FORTRAN Compiler

    M. Obata, G. Matsui, H. Matsuzaki, K. Kimura, D. Inaishi, Y. Ujigawa, T. Yamamoto, M. Okamoto, H. Kasahara

    Technical Report of IPSJ, ARC-130-3    1998.08

  • 最早実行可能条件解析を用いたキャッシュ利用の最適化

    稲石 大祐, 木村 啓二, 藤本 謙作, 尾形 航, 岡本 雅巳, 笠原 博徳

    情報処理学会研究報告ARC130-6    1998.08  [Refereed]

  • シングルチップマルチプロセッサ上でのマルチグレイン並列処理

    木村 啓二, 尾形 航, 岡本 雅巳, 笠原 博徳

    情報処理学会研究報告ARC130-5    1998.08  [Refereed]

  • OSCAR FORTRAN Compilerを用いたマルチグレイン並列性の評価

    小幡 元樹, 松井 巌徹, 松崎 秀則, 木村 啓二, 稲石 大祐, 宇治川 泰史, 山本 晃正, 岡本 雅巳, 笠原 博徳

    情報処理学会研究報告ARC130-3    1998.08  [Refereed]

  • Multigrain parallel Processing on the Single Chip Multiprocessor

    K. Kimura, W. Ogata, M. Okamoto, H. Kasahara

    Technical Report of IPSJ,ARC-130-5    1998.08  [Refereed]

  • A Cache Optimization with Earliest Executable Condition Analysis

    D. Inaishi, K. Kimura, K. Fujimoto, W. Ogata, M. Okamoto, H. Kasahara

    Technical Report of IPSJ, ARC-130-6    1998.08  [Refereed]

  • Evaluation of Multigrain Parallelism using OSCAR FORTRAN Compiler

    M. Obata, G. Matsui, H. Matsuzaki, K. Kimura, D. Inaishi, Y. Ujigawa, T. Yamamoto, M. Okamoto, H. Kasahara

    Technical Report of IPSJ, ARC-130-3    1998.08  [Refereed]

  • Job Scheduling Scheme for Pure Space Sharing among Rigid Jobs

    K. Aida, H. Kasahara, S. Narita

    Lecture Notes in Computer Science   1459, Springer   33 - 45  1998.08  [Refereed]

  • 実用的並列最適化マルチプロセッサスケジューリングアルゴリズム PDF/IHS の大規模問題への適用と性能評価

    飛田 高雄, 笠原 博徳

    情報処理学会並列処理シンポジウムJSPP '98論文集     31 - 37  1998.06  [Refereed]

  • 階層型マクロデータフロー処理における同一階層内ループ間データローカライゼーション手法

    吉田 明正, 越塚 健一, 岡本 雅巳, 小幡 元樹, 笠原 博徳

    情報処理学会並列処理シンポジウムJSPP '98論文集     375 - 382  1998.06  [Refereed]

  • Data-Localization among Doall and Sequential Loops in Coarse Grain Parallel Processing

    A. YOSHIDA, Y. UJIGAWA, M. OBATA, K. KIMURA, H. KASAHARA

    Seventh Workshop on Compilers for Parallel Computers, Linkoping, Sweden     266 - 277  1998.06  [Refereed]

  • Application and Evaluation of a Practical Parallel Optimization Algorithm PDF/IHS (Parallelized Depth First / Implicit Heuristic Search) to Large Scale Problems

    T. Tobita, H. Kasahara

    Joint Symposium on Parallel Processing (JSPP'98)     31 - 37  1998.06  [Refereed]

  • A Data-Localization Scheme among Loops inside the Same Layer of Hierarchical Macro-Dataflow Processing

    A. Yoshida, K. Koshizuka, M. Okamoto, M. Obata, H. Kasahara

    Joint Symposium on Parallel Processing (JSPP'98)     375 - 382  1998.06  [Refereed]

  • 並列分散科学技術計算環境STA(4)─異機種並列計算機の統合利用環境の構築

    今村 俊幸, 太田 浩史, 川崎 啄治, 小出 洋, 武宮 博, 樋口 健二, 久野 章則, 笠原 博徳, 相川裕史

    計算工学講演会論文集   3  1998.05  [Refereed]

  • 並列分散科学技術計算環境STA(3)─異機種並列計算機間通信ライブラリの構築

    小出 洋, 今村 俊幸, 太田 浩史, 川崎 啄治, 武宮 博, 樋口 健二, 笠原 博徳, 相川裕史

    計算工学講演会論文集   3  1998.05  [Refereed]

  • 並列分散科学技術計算環境STA(2)─エディタを中心に統合された並列プログラム開発環境PPDEの構築

    太田 浩史, 今村 俊幸, 川崎 啄治, 小出 洋, 武宮 博, 樋口 健二, 笠原 博徳, 相川裕史

    計算工学講演会論文集   3  1998.05  [Refereed]

  • 並列分散科学技術計算環境STA(1)─目的及び概要

    武宮 博, 今村 俊幸, 太田 浩史, 川崎 琢治, 小出 洋, 笠原 博徳, 相川 裕史

    計算工学講演会論文集   3  1998.05  [Refereed]

  • A data-localization compilation scheme using partial-static task assignment for Fortran coarse-grain parallel processing

    H Kasahara, A Yoshida

    PARALLEL COMPUTING   24 ( 3-4 ) 579 - 596  1998.05  [Refereed]

    　View Summary

    This paper proposes a compilation scheme for data localization using partial-static task assignment for Fortran coarse-grain parallel processing, or macro-dataflow processing, on a multiprocessor system with local memories and centralized shared memory. The data localization allows us to effectively use local memories and reduce data transfer overhead under dynamic task-scheduling environment. The proposed compilation scheme mainly consists of the following three parts: (1) loop-aligned decomposition, which decomposes each of the loops having data dependence among them into smaller loops, and groups the decomposed loops into data-localizable groups so that shared data among the decomposed loops inside each group can be passed via local memory and data transfer overhead among the groups can be minimum; (2) partial static task assignment, which gives information that the decomposed loops inside each data-localizable group are assigned to the same processor to a dynamic scheduling routine generator in the macro-dataflow compiler; (3) parallel machine code generation, which generates parallel machine code to pass shared data inside the group through local memory and transfer data among groups through centralized shared memory. This compilation scheme has been implemented for a multiprocessor system, OSCAR (Optimally SCheduled Advanced multiprocessoR), having centralized shared memory and distributed shared memory, in addition to local memory on each processor. Performance evaluation of OSCAR shows that macro-dataflow processing with the proposed data-localization scheme can reduce the execution time by 20%, in average, compared with macro-dataflow processing without data localization. (C) 1998 Elsevier Science B.V. All rights reserved.

  • A Multigrain Parallelizing Compiler and Its Architectural Support

    H. Kasahara, W. Ogata, K. Kimura, M. Obata, T. Tobita, D. Inaishi

    THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD98-10, CPSY98-10, FTS98-10)   98 ( 22 ) 71 - 76  1998.04

    　View Summary

    Currently, difficulty of enlargement of the world market for supercomputers caused by cost-performance, which does not seem excellent for real effective performance, and need of high experience for parallel tuning is getting a problem. Also, in general purpose microprocessors, limitations of extraction of instruction level parallelism being used by super-scalar and VLIW architectures are getting clear. This paper describes a multigrain compilation technology and architectural support for it as an approach to cope with the above difficulites and develop user friendly and excellent cors performance supercomputers and single chip multiprocesors.

    CiNii

  • 電磁界解析における有限要素・境界要素併用法の並列処理手法

    小幡 元樹, 前川 仁孝, 若尾 真治, 小貫 天, 笠原 博徳

    電気学会論文誌 A (基礎・材料・共通部門誌)   118-A ( 4 ) 377 - 379  1998.04  [Refereed]

  • マルチグレイン並列化コンパイラとそのアーキテクチャ支援

    笠原 博徳, 尾形 航, 木村 啓二, 小幡 元樹, 飛田 高雄, 稲石 大祐

    社団法人 電子情報通信学会, 信学技報, ICD98-10, CPSY98-10, FTS98-10    1998.04  [Refereed]

  • マルチグレイン並列化コンパイラとそのアーキテクチャ支援

    笠原 博徳

    社団法人 電子情報通信学会, 信学技報, ICD98-10, CPSY98-10, FTS98-10    1998.04  [Refereed]

  • Parallel Processing of Hybrid Finite Element and Boundary Element Method for Electro-magnetic Field Analysis

    M. Obata, Y. Maekawa, S. Wakao, T. Onuki, H. Kasahara

    Trans.IEE of Japan   118-A ( 4 ) 377 - 379  1998.04  [Refereed]

  • A Multigrain Parallelizing Compiler and Its Architectural Support

    H. Kasahara, W. Ogata, K. Kimura, M. Obata, T. Tobita, D. Inaishi

    THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD98-10, CPSY98-10, FTS98-10)    1998.04  [Refereed]

  • A Multigrain Parallelizing Compiler and Its Architectural Support, THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, TECHNICAL REPORT OF IEICE. (ICD98-10, CPSY98-10, FTS98-10)

    H. Kasahara

       1998.04  [Refereed]

  • Implementation of FPGA Based Architecture Test Bed For Multi Processor System

    W. Ogata, T. Yamamoto, M. Mizuno, K. Kimura, H. Kasahara

    IPSJ SIG Notes, 98-ARC-128-14    1998.03

  • 科学技術計算プログラムにおけるマルチグレイン並列性の評価

    小幡 元樹, 松井 巌徹, 松崎 秀則, 木村 啓二, 稲石 大裕, 宇治川 泰史, 山本 晃正, 岡本 雅巳, 笠原 博徳

    情報処理学会第56回全国大会   2E-07  1998.03  [Refereed]

  • 一般的なマクロタスクグラフに対するループ間データローカライゼーション手法

    松崎秀則, 吉田明正, 岡本雅巳, 松井巌徹, 小幡元樹, 宇治川泰史, 笠原博徳

    情報処理学会第56回全国大会   2E-05  1998.03  [Refereed]

  • 異機種並列分散コンピューティングのためのメタ・スケジューリングの構想

    小出 洋, 武宮 博, 今村 俊幸, 太田 浩史, 川崎 琢治, 樋口 健二, 笠原 博徳, 相川 裕史

    情報処理学会第56回全国大会   2J-10  1998.03  [Refereed]

  • マルチグレイン並列処理用シングルチップマルチプロセッサアーキテクチャ

    木村 啓二, 尾形 航, 岡本 雅巳, 笠原 博徳

    情報処理学会第56回全国大会   1N-03  1998.03  [Refereed]

  • マルチグレイン並列処理におけるインタープロシージャ解析

    松井 巌徹, 岡本 雅巳, 松崎 秀則, 小幡 元樹, 吉井 謙一郎, 笠原 博徳

    情報処理学会第56回全国大会   2E-04  1998.03  [Refereed]

  • マクロタスク最早実行可能条件解析を用いたキャッシュ最適化手法

    稲石 大祐, 木村 啓二, 尾形 航, 岡本 雅巳, 笠原 博徳

    情報処理学会第56回全国大会   2E-06  1998.03  [Refereed]

  • FPGAを用いたマルチプロセッサシステムテストベッドの実装

    尾形 航, 山本 泰平, 水尾 学, 木村 啓二, 笠原 博徳

    情報処理学会, ARC研究会,98-ARC-128-14    1998.03  [Refereed]

  • Job Scheduling Scheme for Pure Space Sharing among Rigid Jobs

    K. Aida, H. Kasahara, S. Narita

    Proc. 4th Workshop on Job Scheduling Strategies for Parallel Processing     98 - 121  1998.03  [Refereed]

  • Implementation of FPGA Based Architecture Test Bed For Multi Processor System

    W. Ogata, T. Yamamoto, M. Mizuno, K. Kimura, H. Kasahara

    IPSJ SIG Notes, 98-ARC-128-14    1998.03  [Refereed]

  • OSCAR multi-grain architecture and its evaluation

    H Kasahara, W Ogata, K Kimura, G Matsui, H Matsuzaki, M Okamoto, A Yoshida, H Honda

    INNOVATIVE ARCHITECTURE FOR FUTURE GENERATION HIGH-PERFORMANCE PROCESSORS AND SYSTEMS, PROCEEDINGS     106 - 115  1998  [Refereed]

    　View Summary

    OSCAR (Optimally Scheduled Advanced Multiprocessor) was designed to efficiently realize multi-grain parallel processing using static and dynamic scheduling. It is a shared memory multiprocessor system having centralized and distributed shared memories in addition to local memory on each processor with data transfer controller for overlapping of data transfer and task processing. Also, its Fortran multi-grain compiler hierarchically exploits coarse grain parallelism among loops, subroutines and basic blocks, conventional medium grain parallelism among loop-iterations in a Doall loop and near fine grain parallelism among statements. At the coarse grain parallel processing, data localization (automatic data distribution) have been employed to minimize data transfer overhear. In the near fine grain processing of a basic block, explicit synchronization can be removed by use of a clock level accurate code scheduling technique with architectural supports. This paper describes OSCAR's architecture, its compiler and the performance for the multi-grain parallel processing. OSCAR's architecture and compilation technology will be more important in future High Performance Computers and single chip multiprocessors.

  • Performance Evaluation of a Practical Parallel Optimization Multiprocessor Scheduling Algorithm PDF/HIS

    T. Tobita, H. Kasahara

    IPSJ SIG Notes   97 ( 113 ) 13 - 18  1997.11

  • 実用的並列最適化マルチプロセッサスケジューリングアルゴリズムPDF/IHSの性能評価

    飛田 高雄, 笠原 博徳

    情報処理学会研究報告   97 ( 113 ) 13 - 18  1997.11  [Refereed]

  • ヒューマンノイド-人間形高度情報処理ロボット-

    橋本 周司, 成田 誠之助, 白井 克彦, 小林 哲則, 高西 淳夫, 菅野 重樹, 笠原 博徳

    情報処理   38 ( 11 ) 959 - 969  1997.11  [Refereed]

  • Performance Evaluation of a Practical Parallel Optimization Multiprocessor Scheduling Algorithm PDF/HIS

    T. Tobita, H. Kasahara

    IPSJ SIG Notes   97 ( 113 ) 13 - 18  1997.11  [Refereed]

  • Humanoid - Intelligent Anthropomorphic Robot

    S. Hashimoto, S. Narita, K. Shirai, T. Kobayashi, A. Takanishi, S. Sugano, H. Kasahara

    IPSJ MAGAZINE   38 ( 11 ) 959 - 969  1997.11  [Refereed]

  • 21世紀へ向けたHPCにおける日本-EU技術移転と協力

    笠原 博徳

    教育・科学技術に関する日本・EU協力会議ラウンドテーブル論文集, United Nations University    1997.09  [Refereed]

  • Technology Transfer and Cooperation in HPC Toward the 21st Century Between Japan and EU

    H. Kasahara

    Conference on EU-Japan Co-operation in Education, Science and Technology: Round Table on Science and Technology    1997.09  [Refereed]

  • Parallel Processing of Hybrid Finite Element and Boundary Element Method for Electro-magnetic field analysis

    M. Obata, Y. Maekawa, S. Wakao, T. Onuki, H. Kasahara

    IPSJ SIG Notes, 97-HPC-67-3    1997.08

  • Multi-processor system for Multi-grain Parallel Processing

    K. Iwai, T. Fujiwara, T. Morimura, H. Amano, K. Kimura, W. Ogata, H. Kasahara

    Technical Report of IEICE, CPSY97-46    1997.08

  • A Macro Task Dynamic Scheduling Algorithm with Overlapping of Task Processing and Data Transfer

    K. Kimura, S. Hashimoto, M. Kogou, W. Ogata, H. Kasahara

    Technical Report of IEICE, CPSY97-40    1997.08

  • Evaluation of a Practical Parallel Optimization Algorithm for the Minimum Execution-Time Multiprocessor Scheduling Problem

    T. Tobita, H. Kasahara

    Technical Report of IEICE, CPSY97-39    1997.08

  • Data-Localization for Fortran Hierarchical Macro-Dataflow Processing

    Yoshida, K. Koshizuka, M. Okamoto, H. Kasahara

    IPSJ SIG Notes,97-ARC-125-2   1997 ( 76 ) 7 - 12  1997.08

    　View Summary

    This paper proposes a data-localization scheme for Fortran hierarchical macro-dataflow processing, which hierarchically exploits coarse-grain parallelism. The proposed data-localization scheme consists of three parts: (1) loop-aligned decomposition, which decomposes multiple loops having data dependences into data-localization-groups, (2) generation of dynamic scheduling routine with partial static task assignment, which assigns macrotasks inside data-localization-group to the same processor, (3) generation of data transfer code via local memory inside data-localization-group. Performance evaluations on a multiprocessor system OSCAR show that hierarchical macro-dataflow processing with data-localization can reduce execution time by 10%-20% compared with hierarchical macro-dataflow processing without data-localization.

    CiNii

  • 処理とデータ転送のオーバーラッピングを考慮したダイナミックスケジューリングアルゴリズム

    木村 啓二, 橋本 茂, 古郷 誠, 尾形 航, 笠原 博徳

    電子情報通信学会研究報告、CPSY97-40    1997.08  [Refereed]

  • 実行時間最小マルチプロセッサスケジューリング問題に対する実用的並列最適化アルゴリズムの性能評価

    飛田 高雄, 笠原 博徳

    電子情報通信学会研究報告、CPSY97-39    1997.08  [Refereed]

  • マルチグレイン並列処理用マルチプロセッサシステム

    岩井 啓輔, 藤原 崇, 森村 知弘, 天野 英晴, 木村 啓二, 尾形 航, 笠原 博徳

    電子情報通信学会研究報告, CPSY97-46    1997.08  [Refereed]

  • 電磁界解析における有限要素・境界要素併用法の並列処理

    小幡 元樹, 前川 仁孝, 若尾 真治, 小貫 天, 笠原 博徳

    電気学会電子・情報・システム部門大会講演論文集     549 - 554  1997.08  [Refereed]

  • Fortran階層型マクロデータフロー処理におけるデータローカライゼーション

    吉田 明正, 越塚 健一, 岡本 雅巳, 笠原 博徳

    情報処理学会研究会報告、97-ARC-125-2    1997.08  [Refereed]

  • 電磁界解析における有限要素・境界要素併用法の並列処理手法

    小幡 元樹, 前川 仁孝, 若尾 真治, 小貫 天, 笠原 博徳

    情報処理学会研究会報告, 97-HPC-67-3    1997.08  [Refereed]

  • Multi-processor system for Multi-grain Parallel Processing

    K. Iwai, T. Fujiwara, T. Morimura, H. Amano, K. Kimura, W. Ogata, H. Kasahara

    Technical Report of IEICE, CPSY97-46    1997.08  [Refereed]

  • A Macro Task Dynamic Scheduling Algorithm with Overlapping of Task Processing and Data Transfer

    K. Kimura, S. Hashimoto, M. Kogou, W. Ogata, H. Kasahara

    Technical Report of IEICE, CPSY97-40    1997.08  [Refereed]

  • Evaluation of a Practical Parallel Optimization Algorithm for the Minimum Execution-Time Multiprocessor Scheduling Problem

    T. Tobita, H. Kasahara

    Technical Report of IEICE, CPSY97-39    1997.08  [Refereed]

  • Parallel Processing of Hybrid Finite Element and Boundary Element Method for Electro-magnetic field analysis

    M. Obata, Y. Maekawa, S. Wakao, T. Onuki, H. Kasahara

    Proc. of the Electronics, Information and Systems Conference     549 - 554  1997.08  [Refereed]

  • Data-Localization for Fortran Hierarchical Macro-Dataflow Processing

    Yoshida, K. Koshizuka, M. Okamoto, H. Kasahara

    IPSJ SIG Notes,97-ARC-125-2    1997.08  [Refereed]

  • Parallel Processing of Hybrid Finite Element and Boundary Element Method for Electro-magnetic field analysis

    M. Obata, Y. Maekawa, S. Wakao, T. Onuki, H. Kasahara

    IPSJ SIG Notes, 97-HPC-67-3    1997.08  [Refereed]

  • マルチプロセッサシステム上でのプロセッサグループへの並列ジョブのスケジューリング手法

    合田 憲人, 笠原 博徳, 成田 誠之助

    電子情報通信学会論文誌   J-80-D-I ( 6 ) 463 - 473  1997.06  [Refereed]

  • A Scheduling Scheme of Parallel Jobs to Processor Groups on a Multiprocessor System

    K. Aida, H. Kasahara, S. Narita

    Trans. of IEICE   J-80-D-I ( 6 ) 463 - 473  1997.06  [Refereed]

  • 並列処理の電力系統解析への応用

    笠原 博徳, 成田 誠之助

    電気学会論文誌   117-B ( 5 ) 621 - 624  1997.05  [Refereed]

  • Application of Parallel Processing to Power Systems Analysis

    H. Kasahara, S. Narita

    Trans. IEEJ   117-B ( 5 ) 621 - 624  1997.05  [Refereed]

  • Data-localization scheduling inside processor-cluster for multigrain parallel processing

    A Yoshida, K Koshizuka, W Ogata, H Kasahara

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS   E80D ( 4 ) 473 - 479  1997.04  [Refereed]

    　View Summary

    This paper proposes a data-localization scheduling scheme inside a processor-cluster for multigrain parallel processing, which hierarchically exploits parallelism among coarse-grain tasks like loops, medium-grain tasks like loop iterations and near-fine-grain tasks like statements. The proposed scheme assigns near-fine-grain or medium-grain tasks inside coarse-grain tasks onto processors inside a processor-cluster so that maximum parallelism can be exploited and inter-processor data transfer can be minimum after data-localization for coarse-grain tasks across processor-clusters. Performance evaluation on a multiprocessor system OSCAR shows that multigrain parallel processing with the proposed data-localization scheduling can reduce execution time for application programs by 10% compared with multigrain parallel processing without data-localization.

  • Data-localization scheduling inside processor-cluster for multigrain parallel processing

    A Yoshida, K Koshizuka, W Ogata, H Kasahara

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS   E80D ( 4 ) 473 - 479  1997.04  [Refereed]

    　View Summary

    This paper proposes a data-localization scheduling scheme inside a processor-cluster for multigrain parallel processing, which hierarchically exploits parallelism among coarse-grain tasks like loops, medium-grain tasks like loop iterations and near-fine-grain tasks like statements. The proposed scheme assigns near-fine-grain or medium-grain tasks inside coarse-grain tasks onto processors inside a processor-cluster so that maximum parallelism can be exploited and inter-processor data transfer can be minimum after data-localization for coarse-grain tasks across processor-clusters. Performance evaluation on a multiprocessor system OSCAR shows that multigrain parallel processing with the proposed data-localization scheduling can reduce execution time for application programs by 10% compared with multigrain parallel processing without data-localization.

  • 電磁界解析のための有限要素・境界要素併用法の並列処理

    小幡元樹, 前川仁孝, 坂本哲也, 若尾真治, 小貫天, 笠原博徳

    情報処理学会第54回全国大会   5F-7  1997.03  [Refereed]

  • 実行時間最小・実用的並列最適化マルチプロセッサ・スケジューリング・ アルゴリズムの大規模問題への適用

    飛田高雄, 笠原博徳

    情報処理学会第54回全国大会   3J-5  1997.03  [Refereed]

  • 階層型マクロデータフロー処理におけるデータローカライゼーション手法

    越塚健一, 吉田明正, 岡本雅巳, 笠原博徳

    情報処理学会第54回全国大会   1L-5  1997.03  [Refereed]

  • 階層型マクロデータフローのためのダイナミック/スタティック併用スケジューリング手法

    桐原正樹, 岡本雅巳, 赤鹿秀樹, 笠原博徳

    情報処理学会第54回全国大会   1L-1  1997.03  [Refereed]

  • マルチプロセッサシステム上でのCFDの並列処理に関する研究

    柳川慎, 橋本茂, 前川仁孝, 岡本雅巳, 笠原博徳

    情報処理学会第54回全国大会   5F-8  1997.03  [Refereed]

  • マクロデータフロー処理における処理とデータ転送のオーバーラップ

    橋本茂, 藤本謙作, 岡本雅巳, 笠原博徳

    情報処理学会第54回全国大会   5F-6  1997.03  [Refereed]

  • Humanoid robot - Development of an information assistant robot Hadaly

    S Hashimoto, S Narita, H Kasahara, A Takanishi, S Sugano, K Shirai, T Kobayashi, H Takanobu, T Kurata, K Fujiwara, T Matsuno, T Kawasaki, K Hoashi

    RO-MAN '97 SENDAI: 6TH IEEE INTERNATIONAL WORKSHOP ON ROBOT AND HUMAN COMMUNICATION, PROCEEDINGS     106 - 111  1997  [Refereed]

    　View Summary

    This paper describes a humanoid robot "Hadaly," that was developed as a basic model for the final version of Humanoid. In this study, the authors feature an attempt to find the configurations and functions that are reguired for a humanoid. Hadaly consists of four systems; an audio-visual system, a head system, a speech system and an arm system. The configurations and functions reguired for a humanoid robot are clarified based on the results of the information assistance experiment with Hadaly.

  • A Macro Task Scheduling Method of Overlapping of Data Transfer and Task Processing

    S. Hashimoto, K. Fujimoto, M. Okamoto, H. Kasahara

    Technical Report of IEICE, CPSY96-107   96 ( 503 ) 65 - 72  1997.01

    　View Summary

    Recently, multiprocessor systems having local memory, distributed shared memory and data transfer units are getting popular. For those systems, minimization of data transfer overhead among processor elements is very important to efficiently use local memory. However, even if users and compilers minimize data transfer overhead by task scheduling, certain data transfers remain. To reduce data transfer overhead and to hide overhead caused by the remaining data transfers, this paper proposes heuristic scheduling methods considering data pre-loading and post-storing for overlapping of data transfers and task processing. A the prototype compiler (preprocessor)using the proposed method has been implemented and its preliminary performance is evaluated on Fujitsu VPP500.

    CiNii

  • データ転送と処理のオーバーラップを用いたマクロタスクスケジューリング手法

    橋本茂, 藤本謙作, 岡本雅巳, 笠原博徳

    電子情報通信学会、CPSY96-107    1997.01  [Refereed]

  • A Macro Task Scheduling Method of Overlapping of Data Transfer and Task Processing

    S. Hashimoto, K. Fujimoto, M. Okamoto, H. Kasahara

    Technical Report of IEICE, CPSY96-107    1997.01  [Refereed]

  • Near Fine Grain Parallel Processing without Explicit Synchronization on a Multiprocessor System

    W. Ogata, A. Yoshida, M. Okamoto, K. Kimura, H. Kasahara

    Proc. of Sixth Workshop on Compilers for Parallel Computers    1996.12  [Refereed]

  • Development of a Practical Level Multi-Grain FORTRAN Compiler

    M. Okamoto, K. Aida, A. Yoshida, H. Kasahara, S. Narita

    SIG Notes of IPSJ    1996.10

  • スタティックスケジューリングを用いた電子回路シミュレーションの粗粒度/近細粒度階層型並列処理手法

    前川 仁孝, 高井 峰生, 伊藤 泰樹, 西川 健, 笠原 博徳

    情報処理学会論文誌   37 ( 10 )  1996.10  [Refereed]

  • 実用レベルのマルチグレインFORTRANコンパイラの開発

    岡本 雅巳, 合田 憲人, 吉田 明正, 笠原 博徳, 成田 誠之助

    情報処理学会研究報告、96ARC    1996.10  [Refereed]

  • A Coarse Grain/Near Fine Grain Hierarchical Parallel Processing Scheme of Circuit Simulation Using Static Scheduling

    Y. Maekawa, M. Takai, T. Ito, T. Nishikawa, H. Kasahara

    Trans. of IPSJ   37 ( 10 )  1996.10  [Refereed]

  • Development of a Practical Level Multi-Grain FORTRAN Compiler

    M. Okamoto, K. Aida, A. Yoshida, H. Kasahara, S. Narita

    SIG Notes of IPSJ    1996.10  [Refereed]

  • Parallel Processing Scheme of the Hybrid Finite Element and Boundary Element Method

    Y. Maekawa, T. Sakamoto, M. Obata, S. Wakao, H. Kasahara, T. Onuki

    Technical Report of IEE Japan, IP-96-27    1996.09

  • Optimization of Data Transfer Order for Near Fine Grain Parallel Processing without Explicit Synchronization Code

    W. Ogata, A. Yoshida, M. Okamoto, H. Kasahara

    Technical Report of IEE Japan, IP-96-29    1996.09

  • データ転送と処理のオーバーラップを用いたデータ転送最小化自動並列化コンパイラ

    藤本謙作, 橋本茂, 笠原博徳

    電気学会情報処理研究会資料、IP-96-24,    1996.09  [Refereed]

  • 無同期近細粒度並列処理におけるデータ転送順序最適化

    尾形 航, 吉田 明正, 岡本 雅巳, 笠原 博徳

    電気学会情報処理研究会資料、IP-96-29    1996.09  [Refereed]

  • 有限要素・境界要素併用法の並列処理手法

    前川 仁孝, 坂本 哲也, 小幡 元樹, 若尾 真治, 笠原 博徳, 小貫 天

    電気学会情報処理研究会資料、IP-96-27    1996.09  [Refereed]

  • データ転送と処理のオーバーラップを用いたデータ転送最小化自動並列化コンパイラ

    藤本謙作, 橋本茂, 笠原博徳

    電気学会情報処理研究会資料、IP-96-24,    1996.09  [Refereed]

  • Optimization of Data Transfer Order for Near Fine Grain Parallel Processing without Explicit Synchronization Code

    W. Ogata, A. Yoshida, M. Okamoto, H. Kasahara

    Technical Report of IEE Japan, IP-96-29    1996.09  [Refereed]

  • Parallel Processing Scheme of the Hybrid Finite Element and Boundary Element Method

    Y. Maekawa, T. Sakamoto, M. Obata, S. Wakao, H. Kasahara, T. Onuki

    Technical Report of IEE Japan, IP-96-27    1996.09  [Refereed]

  • Parallelizing Compiler with Optimization of Overlapping of Data Transfer and Task Processing

    K. Fujimoto, S. Hashimoto, H. Kasahara

    Technical Report of IEE Japan, IP-96-24    1996.09

  • Evaluation of a Scheduling Scheme of Parallel Jobs on a Multiprocessor System

    K. Aida, H. Kasahara, S. Narita

    IPSJ SIG Notes OS-73-13    1996.08

  • A Near-Fine-Grain Task Scheduling Scheme for Multi-Grain Data-Localization

    Yoshida, K. Koshizuka, W. Ogata, H. Kasahara

    Technical Report of IEICE, CPSY96-66    1996.08

  • マルチグレインデータローカライゼーションのための近細粒度タスクスケジューリング

    吉田 明正, 越塚 健一, 尾形 航, 笠原 博徳

    電子情報通信学会技術研究報告、CPSY96-66    1996.08  [Refereed]

  • マルチプロセッサシステム上での並列ジョブのスケジューリング手法の評価

    合田 憲人, 笠原 博徳, 成田 誠之助

    情報処理学会研究報告 OS-73-13    1996.08  [Refereed]

  • A Near-Fine-Grain Task Scheduling Scheme for Multi-Grain Data-Localization

    Yoshida, K. Koshizuka, W. Ogata, H. Kasahara

    Technical Report of IEICE, CPSY96-66    1996.08  [Refereed]

  • Data Localization Using Loop Aligned Decomposition for Macro-Dataflow Processing

    A.Yoshida, H. Kasahara

    Proc. of 9th Workshop on Languages and Compilers for Parallel Computers     55 - 74  1996.08  [Refereed]

  • Evaluation of a Scheduling Scheme of Parallel Jobs on a Multiprocessor System

    K. Aida, H. Kasahara, S. Narita

    IPSJ SIG Notes OS-73-13    1996.08  [Refereed]

  • ソーテッドコードブックベクトル量子化の並列処理

    中野 恵一, 笠原 博徳

    情報処理学会論文誌   37 ( 7 )  1996.07  [Refereed]

  • マルチプロセッサ上での近細粒度並列処理

    笠原博徳

    情報処理学会学会誌   37 ( 7 )  1996.07  [Refereed]

  • Parallel Processing for Fast Vector Quantization with Sorted Codebook

    K. Nakano, H. Kasahara

    Trans. of IPSJ   37 ( 7 )  1996.07  [Refereed]

  • Near Fine Grain Parallel Processing on Multiprocessor Systems

    H. Kasahara

    Journal of IPSJ   37 ( 7 )  1996.07  [Refereed]

  • Data-Localization for Fortran Macro-Dataflow Computation Using Partial Static Task Assignment

    A.Yoshida, K. Koshizuka, H. Kasahara

    Proc. of 10th ACM International Conference on Supercomputing     61 - 68  1996.05  [Refereed]

  • 共有メモリ型マルチプロセッサシステム上でのFortran粗粒度タスク並列処理の性能評価

    合田 憲人, 岩崎 清, 岡本 雅巳, 笠原 博徳, 成田 誠之助

    情報処理学会論文誌   37 ( 3 ) 418 - 429  1996.03  [Refereed]

    　View Summary

    This paper presents an implementation and performance evaluation of the macrodataflow computation scheme that is a coarse grain parallel processing scheme on shared memory multi-processor systems. In macrodataflow computation, the compiler automatically generates coarse grain tasks called macrotasks, exploits parallelism among macrotasks and generates a dynamic scheduling routine to assign macrotasks to processors. A conventional coarse grain parallel processing scheme such as multi-tasking has drawbacks such as difficulty in the extraction of parallelism among coarse grain tasks by users and large dynamic scheduling overhead caused by OS calls. However, in macrodataflow computation, the compiler exploits parallelism among macrotasks automatically and dynamic scheduling overhead is small because the compiler optimizes a dynamic scheduling routine for each source program. Performance evaluation of the macrodataflow computation scheme on an Alliant FX/4 and a Kendall Square Research KSR1 shows that macrodataflow computation reduces execution time of programs to 1/1.92 - 1/8.10 of execution time by conventional schemes such as loop parallelization and multi-tasking.

    CiNii

  • 有限要素法と境界要素法を利用した電磁界解析の並列処理

    坂本 哲也, 前川 仁孝, 若尾 真治, 小貫 天, 笠原 博徳

    情報処理学会第52回全国大会   4L-8  1996.03  [Refereed]

  • 電力系統過渡安定度計算の階層的並列処理手法

    西川 健, 前川 仁孝, 中野 恵一, 笠原 博徳

    情報処理学会第52回全国大会   4L-9  1996.03  [Refereed]

  • 階層型マクロデータフロー処理のためのマクロタスクスケジューリング手法

    赤鹿 秀樹, 岡本 雅巳, 宮沢 稔, 安田 泰勲, 笠原 博徳

    情報処理学会第52回全国大会   1L-1  1996.03  [Refereed]

  • マルチプラットフォーム・マクロデータフローコンパイラの開発

    安田 泰勲, 合田 憲人, 岩井 啓輔, 岡本 雅巳, 笠原 博徳

    情報処理学会第52回全国大会   1L-3  1996.03  [Refereed]

  • データ転送と処理のオーバーラップを用いたデータ転送最小化自動並列化コンパイラ

    藤本 謙作, 橋本 茂, 笠原 博徳

    情報処理学会第52回全国大会   1L-2  1996.03  [Refereed]

  • Performance Evaluation of Fortran Coarse Grain Parallel Processing on Shared Memory Multi-processor Systems

    K. Aida, K. Iwasaki, M. Okamoto, H. Kasahara, S. Narita

    Trans. of IPSJ   37 ( 3 )  1996.03  [Refereed]

  • データ転送と処理のオーバーラップを考慮したヒューリスティックマルチプロセッサスケジューリングアルゴリズムの最適化アルゴリズムを用いた性能評価

    角谷 清司, 橋本 茂, 笠原 博徳

    1996年電子情報通信学会春季大会講演論文集   D-82  1996.03  [Refereed]

  • The Application of Parallel Processing to The Hybrid FE-BE Analysis

    S. Wakao, M. Hori, Y. Maekawa, T. Sakamoto, H. Kasahara, T. Onuki

    Technical Report of IEE Japan, SA-96-10, RM-96-60    1996

  • 並列処理の導入による有限要素・境界要素併用解析法の高速化

    若尾 真治, 堀 充利, 前川 仁孝, 坂本 哲也, 笠原 博徳, 小貫 天

    電気学会研究会資料、SA-96-10、RM-96-60    1996  [Refereed]

  • The Application of Parallel Processing to The Hybrid FE-BE Analysis

    S. Wakao, M. Hori, Y. Maekawa, T. Sakamoto, H. Kasahara, T. Onuki

    Technical Report of IEE Japan, SA-96-10, RM-96-60    1996  [Refereed]

  • Fortranマルチグレイン並列処理におけるデータローカライゼーション手法

    吉田 明正, 前田 誠司, 尾形 航, 笠原 博徳

    情報処理学会論文誌   36 ( 7 ) 1551 - 1559  1995.07  [Refereed]

  • A Data-Localization Scheme for Fortran Multi-Grain Parallel Processing

    A. Yoshida, S. Maeda, W. Ogata, H. Kasahara

    Trans. of IPSJ   36 ( 7 ) 1551 - 1559  1995.07  [Refereed]

  • Data-Localization for Macro-Dataflow Computation Using Static Macrotask Fusion

    A.Yoshida, S. Maeda, K. Fujimoto, H. Kasahara

    Proc. Fifth Workshop on Compilers for Parallel Computers     440 - 453  1995.07  [Refereed]

    CiNii

  • Parallel Processing Schemes for Fast Vector Quantization with Sorted Codebook

    K. Nakano, H. Kasahara

    Proc. JSPP'95     337 - 344  1995.05  [Refereed]

  • ソーテッドコードブックベクトル量子化の並列処理

    中野 恵一, 笠原 博徳

    JSPP'95 論文集     337 - 344  1995.05  [Refereed]

  • OSCAR Fortran Multigrain Compiler

    H. Kasahara

    Stanford University, Hosted by Professor John L. Hennessy and Professor Monica Lam    1995.05  [Refereed]

  • Scheduling Scheme among Hierarchically Parallel Executed Jobs

    K. Aida, M. Okamoto, H. Kasahara, S. Narita

    SIG Notes of IPSJ, ARC-111-1   1995 ( 29 ) 1 - 8  1995.03

    　View Summary

    This paper presents a job scheduling scheme for hierarchical parallel execution of multiple jobs. In the hierarchical parallel execution of multiple jobs, an OS job scheduler allocates processors(or a processor group) to each job referring the information obtained at compile time. On the processor group allocated to a job, tasks in a job are executed by processors using static scheduling or dynamic scheduling with a dynamic scheduling routine generated by the compiler. This paper proposes a job scheduling scheme to allocate processor groups to multiple jobs using Bin-packing algorithm named Fit Processors First Served(FPFS).

    CiNii

  • リカレントニューラルネットワークにおける学習の並列処理

    芹沢 一, 前川 仁孝, 中野 恵一, 笠原 博徳

    電子情報通信学会1995年総合大会   D-149  1995.03  [Refereed]

  • マルチグレイン並列処理用アーキテクチャシミュレータの概要

    太田 昌人, 尾形 航, 笠原 博徳

    電子情報通信学会1995年総合大会   D-133  1995.03  [Refereed]

  • 無同期近細粒度並列処理における並列コードスケジューリング

    尾形 航, 太田 昌人, 吉田 明正, 岡本 雅巳, 笠原 博徳

    情報処理学会第50回全国大会   1J-3  1995.03  [Refereed]

  • 電子回路シミュレーションの粗粒度/近細粒度並列処理手法

    伊藤 泰樹, 前川 仁孝, 高井 峰生, 西川 健, 笠原 博徳

    情報処理学会第50回全国大会   2J-9  1995.03  [Refereed]

  • 商用共有メモリ型マルチプロセッサシステム上でのマクロデータフロー処理の性能評価

    岩崎 清, 合田 憲人, 笠原 博徳, 成田誠之助

    情報処理学会第50回全国大会   1B-8  1995.03  [Refereed]

  • 自動並列化コンパイラにおけるデータプレロード・ポストストアを用いたデータ転送オーバヘッドの隠蔽

    藤本 謙作, 笠原 博徳

    情報処理学会第50回全国大会   1J-7  1995.03  [Refereed]

  • マルチグレイン並列処理におけるデータローカライゼーションのための近細粒度タスクスケジューリング

    吉田 明正, 尾形 航, 岡本 雅巳, 合田 憲人, 笠原 博徳

    情報処理学会第50回全国大会   1J-5  1995.03  [Refereed]

  • Array Subscript Bit Vector 表示によるデータ依存解析手法

    山下 浩一郎, 安田 泰勲, 宮沢 稔, 笠原 博徳

    情報処理学会第50回全国大会   1J-2  1995.03  [Refereed]

  • 階層並列実行ジョブ間スケジューリング手法

    合田 憲人, 岡本 雅巳, 笠原 博徳, 成田 誠之助

    情報処理学会研究報告、ARC-111-1    1995.03  [Refereed]

  • Scheduling Scheme among Hierarchically Parallel Executed Jobs

    K. Aida, M. Okamoto, H. Kasahara, S. Narita

    SIG Notes of IPSJ, ARC-111-1    1995.03  [Refereed]

  • Fortran粗粒度並列処理におけるDoall/シーケンシャルループ間データローカライゼーション手法

    吉田 明正, 前田 誠司, 尾形 航, 笠原 博徳

    電子情報通信学会論文誌   J78-D-I ( 2 )  1995.02  [Refereed]

  • A Data-Localization Scheme among Doall/Sequential Loops for Fortran Coarse-Grain Parallel Processing

    A. Yoshida, S. Maeda, W. Ogata, H. Kasahara

    Trans. of IEICE   J78-D-I ( 2 )  1995.02  [Refereed]

  • A Hierarchical Parallel Processing Scheme of Circuit Simulation

    Y. Maekawa, M. Takai, T. Ito, K. Nishikawa, H. Kasahara

    SIG Notes of IEE, CPSY95-22     87 - 94  1995

  • 電子回路シミュレーションの階層的並列処理手法

    前川 仁孝, 高井 峰生, 伊藤 泰樹, 西川 健, 笠原 博徳

    電子情報通信学会技術研究報告,CPSY95-22     87 - 94  1995  [Refereed]

  • ACM International Conference on Supercomputing(ICS'95)参加報告

    笠原博徳, 吉田明正

    電気学会論文誌   115-C ( 10 ) 1221  1995  [Refereed]

  • ICS'95参加報告

    吉田 明正, 笠原 博徳

    情報処理学会学会誌   36 ( 8 ) 777 - 778  1995  [Refereed]

  • Participation Report of ICS'95

    A. Yoshida, H. Kasahara

    Trans. of IPSJ   36 ( 8 ) 777 - 778  1995  [Refereed]

  • Participation Report of ACM International Conference on Supercomputing (ICS'95)

    H. Kasahara, A. Yoshida

    Trans. of IEEE   115-C ( 10 ) 1221  1995  [Refereed]

  • A Hierarchical Parallel Processing Scheme of Circuit Simulation

    Y. Maekawa, M. Takai, T. Ito, K. Nishikawa, H. Kasahara

    SIG Notes of IEE, CPSY95-22     87 - 94  1995  [Refereed]

  • Performance evaluation of macrodataflow computation on shared memory multiprocessors

    K AIDA, K IWASAKI, H KASAHARA, S NARITA

    IEEE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUTERS, AND SIGNAL PROCESSING - PROCEEDINGS     50 - 54  1995  [Refereed]

  • Hierarchical macro-dataflow computation scheme

    M OKAMOTO, K YAMASHITA, H KASAHARA, S NARITA

    IEEE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUTERS, AND SIGNAL PROCESSING - PROCEEDINGS     44 - 49  1995  [Refereed]

  • Near fine grain parallel processing of circuit simulation using direct method

    Y MAEKAWA, K NAKANO, M TAKAI, H KASAHARA

    IEEE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUTERS, AND SIGNAL PROCESSING - PROCEEDINGS     272 - 276  1995  [Refereed]

  • Compilation scheme for near fine grain parallel processing on a multiprocessor system without explicit synchronization

    W OGATA, K FUJIMOTO, M OOTA, H KASAHARA

    IEEE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUTERS, AND SIGNAL PROCESSING - PROCEEDINGS     327 - 332  1995  [Refereed]

  • A data-localization scheme using task-fusion for macro-dataflow computation

    A YOSHIDA, S MAEDA, K FUJIMOTO, H KASAHARA

    IEEE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUTERS, AND SIGNAL PROCESSING - PROCEEDINGS     135 - 140  1995  [Refereed]

  • Parallel Processing Scheme of Electronic Circuit Simulation Using Circuit Tearing

    Y. Maekawa, M. Takai, T. Itoh, T. Nishikawa, H. Kasahara

    SIG Notes of IEE, IP-94-44    1994.12

  • Compilation Scheme for Near Fine Grain Parallel Processing without Synchronization on Multiprocessor System OSCAR

    W. Ogata, M. Oota, A. Yoshida, M. Okamoto, H. Kasahara

    SIG Notes of IEE, IP-94-41    1994.12

  • A Data-Localization Scheme among Doall/Sequential Loops for Macro-Dataflow Computation

    A. Yoshida, S. Maeda, W. Ogata, H. Kasahara

    Technical Report of IEE Japan, IP-94-40    1994.12

  • 回路分割を用いた電子回路シミュレーションの並列化手法

    前川 仁孝, 高井 峰生, 伊藤 泰樹, 西川 健, 笠原 博徳

    電気学会情報処理研究会報告、IP-94-44    1994.12  [Refereed]

  • マルチプロセッサシステムOSCAR上での無同期近細粒度並列処理のためのコンパイル手法

    尾形 航, 太田 昌人, 吉田 明正, 岡本 雅巳, 笠原 博徳

    電気学会情報処理研究会報告、IP-94-41    1994.12  [Refereed]

  • マクロデータフロー処理におけるDoall/シーケンシャルループ間データローカライゼーション手法

    吉田 明正, 前田 誠司, 尾形 航, 笠原 博徳

    電気学会情報処理研究会資料、IP-94-40    1994.12  [Refereed]

  • A Data-Localization Scheme among Doall/Sequential Loops for Macro-Dataflow Computation

    A. Yoshida, S. Maeda, W. Ogata, H. Kasahara

    Technical Report of IEE Japan, IP-94-40    1994.12  [Refereed]

  • Parallel Processing Scheme of Electronic Circuit Simulation Using Circuit Tearing

    Y. Maekawa, M. Takai, T. Itoh, T. Nishikawa, H. Kasahara

    SIG Notes of IEE, IP-94-44    1994.12  [Refereed]

  • Compilation Scheme for Near Fine Grain Parallel Processing without Synchronization on Multiprocessor System OSCAR

    W. Ogata, M. Oota, A. Yoshida, M. Okamoto, H. Kasahara

    SIG Notes of IEE, IP-94-41    1994.12  [Refereed]

  • ソートされたコードブックを用いた高速ベクトル量子化

    中野 恵一, 笠原 博徳

    電子情報通信学会論文誌   J77-D-II ( 10 ) 1984 - 1992  1994.10  [Refereed]

  • Fast Vector Quantization Using Sorted Codebook

    K. Nakano, H. Kasahara

    Trans. of IEICE   J77-D-II ( 11 ) 1984 - 1992  1994.10  [Refereed]

  • Fortranマクロデータフロー処理におけるデータローカライゼーション手法

    吉田 明正, 前田 誠司, 尾形 航, 笠原 博徳

    情報処理学会論文誌   35 ( 9 ) 1848 - 1860  1994.09  [Refereed]

  • 粗粒度並列処理におけるDoall/シーケンシャルループ間データローカライゼーション手法

    吉田 明正, 前田 誠司, 尾形 航, 山下 浩一郎, 笠原 博徳

    情報処理学会第49回全国大会   4T-7  1994.09  [Refereed]

  • A Data-Localization Scheme for Fortran Macro-Dataflow Computation

    A. Yoshida, S. Maeda, W. Ogata, H. Kasahara

    Trans. of IPSJ   35 ( 9 ) 1848 - 1860  1994.09  [Refereed]

  • Parallel Search Scheme for Fast Vector Quantization with Sorted Codebook

    K. Nakano, H. Kasahara

    Technical Report of IEICE, CPSY94-42    1994.07

  • A Multi-job Execution Scheme for Macro-dataflow Computation

    K. Aida, M. Okamoto, H. Kasahara, S. Narita

    SIG Notes of IPSJ, OS-65-4    1994.07

  • ソーテッドコードブックベクトル量子化の並列探索による高速化手法

    中野 恵一, 笠原 博徳

    電子情報通信学会技術研究報告 CPSY94-42    1994.07  [Refereed]

  • マクロデータフロー処理のマルチジョブ実行手法

    合田 憲人, 岡本 雅巳, 笠原 博徳, 成田 誠之助

    情報処理学会研究報告、OS-65-4    1994.07  [Refereed]

  • Parallel Search Scheme for Fast Vector Quantization with Sorted Codebook

    K. Nakano, H. Kasahara

    Technical Report of IEICE, CPSY94-42    1994.07  [Refereed]

  • A Multi-job Execution Scheme for Macro-dataflow Computation

    K. Aida, M. Okamoto, H. Kasahara, S. Narita

    SIG Notes of IPSJ, OS-65-4    1994.07  [Refereed]

  • 直接法を用いた電子回路シミュレーションの近細粒度並列処理

    前川 仁孝, 田村 光雄, 中山 功, 吉成 泰彦, 笠原 博徳

    電気学会論文誌C   114-C ( 5 ) 579 - 587  1994.05  [Refereed]

  • マルチグレイン並列処理におけるデータローカライゼーション手法

    吉田 明正, 前田 誠司, 尾形 航, 笠原 博徳

    情報処理学会並列処理シンポジウム, JSPP'94論文集    1994.05  [Refereed]

  • Near Fine Grain Parallel Processing of Circuit Simulation Using Direct Method

    Y. Maekawa, M. Tamura, I. Nakayama, Y. Yoshinari, H. Kasahara

    Trans. IEE of Japan   114-C ( 5 ) 579 - 587  1994.05  [Refereed]

  • A Data-Localization Scheme for Multi-Grain Parallel Processing

    A. Yoshida, S. Maeda, W. Ogata, H. Kasahara

    Joint Symposium on Parallel Processing 1994    1994.05  [Refereed]

  • スタティックスケジューリングを用いたマルチプロセッサシステム上の無同期近細粒度並列処理

    尾形 航, 吉田 明正, 合田 憲人, 岡本 雅巳, 笠原 博徳

    情報処理学会論文誌   35 ( 4 ) 522 - 531  1994.04  [Refereed]

  • OSCARマルチグレインコンパイラにおける階層型マクロデータフロー処理手法

    岡本 雅巳, 合田 憲人, 宮沢 稔, 本多 弘樹, 笠原 博徳

    情報処理学会論文誌   35 ( 4 ) 513 - 521  1994.04  [Refereed]

  • Near Fine Grain Parallel Processing without Synchronization using Static Scheduling

    W. Ogata, A. Yoshida, K. Aida, M. Okamoto, H. Kasahara

    Trans. of IPSJ   35 ( 4 ) 522 - 531  1994.04  [Refereed]

    　View Summary

    A near fine grain parallel processing scheme using static scheduling algorithms has been proposed to process a Fortran basic block in parallel on a multiprocessor system. However, the scheme suffers from relatively large synchronization overhead since synchronization codes must be inserted into a parallel machine code to satisfy precedence constraints caused by data dependences among tasks. To cope with this problem, this paper proposes a parallel code generation scheme which removes all synchronizations codes by optimizing, or scheduling, execution timing of every instruction in machine clock level. Furthermore, it reports performance of the parallel processing without synchronization codes evaluated on an actual multiprocessor system OSCAR, which was designed to support the proposed scheme.

    CiNii

  • A Hierarchical Macro-dataflow Computation Scheme of OSCAR Multi-grain Compiler

    M. Okamoto, K. Aida, M. Miyazawa, H. Honda, H. Kasahara

    Trans. of IPSJ   35 ( 4 ) 513 - 521  1994.04  [Refereed]

  • Performance Evaluation of Macro-dataflow Computation on Shared Memory Multi-processor System

    K. AIDA, K. IWASAKI, K. MATSUMOTO, M. OKAMOTO, H. KASAHARA, S. NARITA

    Technical Report of IPSJ, ARC-105-9, HPC-50-9    1994.03

  • 主記憶共有型マルチプロセッサシステム上でのマクロデータフロー処理の性能評価

    松本健, 合田憲人, 岩崎清, 笠原博徳

    情報処理学会第48回全国大会   2B-5  1994.03  [Refereed]

  • 階層型マクロデータフロー 処理におけるサブルーチン並列処理手法

    宮沢稔, 岡本雅巳, 笠原博徳

    情報処理学会第48回全国大会   2B-4  1994.03  [Refereed]

  • マルチグレイン並列処理におけるタスク融合を用いたデータローカライゼション手法

    前田誠司, 吉田明正, 笠原博徳

    情報処理学会第48回全国大会   2B-3  1994.03  [Refereed]

  • マクロデータフロー処理のためのジョブスケジューリング

    合田憲人, 笠原博徳, 成田誠之助

    情報処理学会第48回全国大会   2H-5  1994.03  [Refereed]

  • OSCARアプリケーション専用目的コンパイラにおける超階層マクロデータフロー処理

    黒田泰, 田村光雄, 前川仁孝, 笠原博徳

    情報処理学会第48回全国大会   5G-7  1994.03  [Refereed]

  • 主記憶共有マルチプロセッサシステム上でのマクロデータフロー処理の性能評価

    合田 憲人, 岩崎 清, 松本 健, 岡本 雅巳, 笠原 博徳, 成田 誠之助

    情報処理学会研究会報告, ARC-105-9, HPC-50-9    1994.03  [Refereed]

  • Performance Evaluation of Macro-dataflow Computation on Shared Memory Multi-processor System

    K. AIDA, K. IWASAKI, K. MATSUMOTO, M. OKAMOTO, H. KASAHARA, S. NARITA

    Technical Report of IPSJ, ARC-105-9, HPC-50-9    1994.03  [Refereed]

  • 分散共有メモリ型マルチプロセッサシステムにおけるデータ転送と処理のオーバーラップスケジューリング手法

    平山直紀, 藤原和典, 笠原博徳

    1994年電子情報通信学会春季全国大会   D-134  1994.03  [Refereed]

  • プロセッサ間通信を考慮した実行時間最小マルチプロセッサスケジューリングアルゴリズム

    野沢幸輝, 笠原博徳

    1994年電子情報通信学会春季全国大会   D-133  1994.03  [Refereed]

  • 自動並列化コンパイラ

    笠原 博徳

    情報処理学会超並列計算機の現状と将来シンポジウム    1994.02  [Refereed]

  • Automatic Parallelizing Compilers

    H. Kasahara

    Symposium on current status and Future of Massively Parallel Machines    1994.02  [Refereed]

  • Fortran Macro-Dataflow Compiler

    H. Honda, K. Aida, M. Okamoto, A. Yoshida, W. Ogata, H. Kasahara

    Proceedings of Fourth Workshop on Compilers for Parallel Computers    1993.12  [Refereed]

  • Parallel Processing of Non-linear Equations Solution on Multiprocessor Systems -Load Flow Calculation as an Example-

    K. Nakano, H. Kasahara

    Technical Report of IEICE   93 ( 302 (CPSY93-36) ) 9 - 15  1993.11

  • マルチプロセッサシステム上における非線形方程式求解の並列処理:電力潮流計算を例として

    中野恵一, 笠原博徳

    電子情報通信学会技術研究報告   93 ( 302(CPSY93-36) ) 9 - 15  1993.11  [Refereed]

  • 連続・離散時間制御システムシミュレーションの並列処理

    山本裕治, 鳥居宏行, 前川仁孝, 田村光雄, 笠原博徳, 成田誠之助

    電気学会論文誌C   113-C ( 11 )  1993.11  [Refereed]

  • 並列処理ソフトウェア

    笠原博徳

    電気学会論文誌C   113-C ( 11 )  1993.11  [Refereed]

  • マルチプロセッサシステム上での非線形方程式求解の並列処理

    中野恵一, 笠原博徳

    電気学会論文誌   113-C ( 11 )  1993.11  [Refereed]

  • Software for Parallel Processing

    H. Kasahara

    Trans.IEE of Japan   113-C ( 11 )  1993.11  [Refereed]

  • Parallel Processing of Non-Linear Equations Solution on Multiprocessor Systems

    K. Nakano, H. Kasahara

    Trans.IEE of Japan   113-C ( 11 )  1993.11  [Refereed]

  • Parallel Processing of Continuous/Discrete-Time Control Systems Simulation

    Y. Yamamoto, H. Torii, Y. Maekawa, M. Tamura, H. Kasahara, S. Narita

    Trans.IEE of Japan   113-C ( 11 )  1993.11  [Refereed]

  • Parallel Processing of Non-linear Equations Solution on Multiprocessor Systems -Load Flow Calculation as an Example-

    K. Nakano, H. Kasahara

    Technical Report of IEICE   93 ( 302 (CPSY93-36) ) 9 - 15  1993.11  [Refereed]

    　View Summary

    This paper proposes a parallel processing scheme for solution of non-linear equations on a multiprocessor system.Load flow calculation using Newton-Raphson method is chosen as an example.In the proposed scheme,sparse linear equations appeared in Newton- Raphson method to solve non-linear equations are solved by a direct method because the relaxation methods have a problem in convergence.The proposed scheme parallelizes the direct solution method of non-linear equations with LU-decomposition.For efficient parallel processing on multiprocessor system,the proposed scheme generates optimized parallel machine code that minimizes data transfer and synchronization overhead by adopting static multiprocessor scheduling algorithm considering data transfers among processors.The effectiveness and practicality of the proposed scheme are demonstrated on an actual multiprocessor system named OSCAR that has been designed to take full advantages of the static

    CiNii

  • 並列処理のためのシステムソフトウェア

    笠原博徳

    情報処理   34 ( 9 ) p1133 - 1186  1993.09  [Refereed]

    CiNii

  • System Software for Parallel Processing

    H. Kasahara

    IPSJ MAGAZINE   34 ( 9 )  1993.09  [Refereed]

  • A Data-Localization Scheme for Macro-Dataflow Computation

    A. Yoshida, S. Maeda, W. Ogata, M. Okamoto, H. Honda, H. Kasahara

    Technical Report of IEICE   93 ( 180 (CPSY93-23) ) 81 - 88  1993.08

  • マクロデータフロー処理におけるデータローカライゼーション手法

    吉田明正, 前田誠司, 尾形航, 岡本雅巳, 笠原博徳, 本多弘樹

    電子情報通信学会技術研究報告   93 ( 180 (CPSY93-23) ) 81 - 88  1993.08  [Refereed]

  • A Data-Localization Scheme for Macro-Dataflow Computation

    A. Yoshida, S. Maeda, W. Ogata, M. Okamoto, H. Honda, H. Kasahara

    Technical Report of IEICE   93 ( 180 (CPSY93-23) ) 81 - 88  1993.08  [Refereed]

  • 実行開始条件による並列性検出手法ループへの拡張

    本多弘樹, 合田憲人, 岡本雅巳, 笠原博徳

    情報処理学会並列処理シンポジウムJSPP'93論文集    1993.05  [Refereed]

  • スタティックスケジューリングを用いたマルチプロセッサシステム上の無同期細粒度並列処理

    尾形航, 吉田明正, 合田憲人, 岡本雅巳, 笠原博徳

    情報処理学会並列処理シンポジウムJSPP'93論文集    1993.05  [Refereed]

  • OSCARマルチグレインコンパイラにおける階層型マクロデータフロー処理手法

    岡本雅巳, 合田憲人, 宮沢稔, 笠原博徳, 本多弘樹

    情報処理学会並列処理シンポジウムJSPP'93論文集    1993.05  [Refereed]

  • Parallelism Detection Scheme with Execution Conditions for Loops

    H. Honda, K. Aida, M. Okamoto, H. Kasahara

    Joint Symposium on Parallel Processing 1993    1993.05  [Refereed]

  • Near Fine Grain Parallel Processing without Synchronization using Static Scheduling

    W. Ogata, A. Yoshida, K. Aida, M. Okamoto, H. Kasahara

    Joint Symposium on Parallel Processing 1993    1993.05  [Refereed]

  • A Hierarchical Macro-Dataflow Computation Scheme of OSCAR Multi-grain Compiler

    M. Okamoto, K. Aida, M. Miyazawa, H. Honda, H. Kasahara

    Joint Symposium on Parallel Processing 1993    1993.05  [Refereed]

  • 並列コンピュータの動向

    笠原 博徳

    日本機械学会第70期総会先端技術フォーラム    1993.04  [Refereed]

  • 学会誌パネル討論会「並列計算機の実用化・商用化を逡巡させる諸要因とは その徹底分析と克服」

    稲上泰弘, 小柳義夫, 笠原博徳, 島崎真昭, 高橋延匡, 瀧和男(ICOT, 山田実(日本T, 吉岡顕(東大, 富田真治

    情報処理   34/4,  1993.04  [Refereed]

  • What are reasons to prevent parallel computer practical products?

    Y. Inagami, H. Shimazaki, M. Yamada, Y. Koyanagi, N. Takahashi, A. Yoshioka, H. Kasahara, K. Taki

    IPSJ   34 ( 4 )  1993.04  [Refereed]

  • Perspective on Parallel Computers

    H. Kasahara

    Advanced Technology Forum of the 70th Congress of The Japan Society of Mechanical Engineers    1993.04  [Refereed]

  • 無同期細粒度並列処理のためのデータ転送順序最適化

    尾形 航, 吉田 明正, 合田 憲人, 岡本 雅巳, 笠原 博徳

    報処理学会第46回全国大会   6L-3  1993.03  [Refereed]

  • 通信時間を含む実行時間最小マルチプロセッサスケジューリングアルゴリズム

    宮川 尚, 野沢 幸輝, 笠原 博徳

    電子情報通信学会春期全国大会   D-150  1993.03  [Refereed]

  • 直接解法による電子回路シミュレーションの並列処理

    吉成 泰彦, 中山 功, 田村 光雄, 前川 仁孝, 笠原 博徳, 成田 誠之助

    電子情報通信学会春期全国大会   D-159  1993.03  [Refereed]

  • ローカルメモリを有するマルチプロセッサシステムにおけるデータプレロード・ポストストアスケジューリングアルゴリズム

    林田 宏一, 藤原 和典, 笠原 博徳

    電子情報通信学会春期全国大会   D-152  1993.03  [Refereed]

  • マルチプロセッサシステム上の回路シミュレーションのための回路分割手法

    中山 功, 吉成 泰彦, 田村 光雄, 前川 仁孝, 笠原 博徳, 成田 誠之助

    電子情報通信学会春期全国大会   D-158  1993.03  [Refereed]

  • マルチプロセッサシステムのためのタスク融合手法

    中谷 徳夫, 宮本 宏行, 野沢 幸輝, 笠原 博徳

    電子情報通信学会春期全国大会   D-151  1993.03  [Refereed]

  • 実行開始条件による並列性検出手法 ループへの拡張

    本田 弘樹, 笠原 博徳

    情報処理学会第46回全国大会   6E-4  1993.03  [Refereed]

  • ソートされたコードブックを用いた高速ベクトル量子化

    中野 恵一, 笠原 博徳

    情報処理学会第46回全国大会   5K-1  1993.03  [Refereed]

  • Fortran マクロデータフロー処理におけるデータローカライゼーション

    吉田 明正, 前田 誠司, 岡本 雅巳, 合田 憲人, 本多 弘樹, 笠原 博徳

    情報処理学会第46回全国大会   8L-3  1993.03  [Refereed]

  • OSCAR Fortran Multi Grain Parallelizing Compiler

    Yoshida, M. Okamoto, K. Aida, W. Ogata, H. Honda, H. Kasahara

    SIG Notes of IPSJ   92 ( 85 (PRG-9) ) 71 - 78  1992.10

  • Near Fine Grain Parallel Processing on a Multiprocessor System Without Synchronization

    W. Ogata, M. Okamoto, H. Honda, H. Kasahara, S. Narita

    Technical Report of IEICE   92   59 - 66  1992.10

  • マルチプロセッサシステム上の無同期細粒度並列処理

    尾形 航, 岡本 雅巳, 本多 弘樹, 笠原 博徳, 成田 誠之助

    電子情報通信学会技術報告   92   59 - 66  1992.10  [Refereed]

  • OSCAR Fortranマルチグレインコンパイラ

    吉田 明正, 岡本 雅巳, 合田 憲人, 尾形 航, 本多 弘樹, 笠原 博徳

    情報処理学会研究報告   92 ( 85 (PRG-9) ) 71 - 78  1992.10  [Refereed]

    CiNii

  • Near Fine Grain Parallel Processing on a Multiprocessor System Without Synchronization

    W. Ogata, M. Okamoto, H. Honda, H. Kasahara, S. Narita

    Technical Report of IEICE   92   59 - 66  1992.10  [Refereed]

  • OSCAR Fortran Multi Grain Parallelizing Compiler

    Yoshida, M. Okamoto, K. Aida, W. Ogata, H. Honda, H. Kasahara

    SIG Notes of IPSJ   92 ( 85 (PRG-9) ) 71 - 78  1992.10  [Refereed]

  • Evaluation of Fortran Macro-dataflow Computation on a Multi-processor Supercomputer

    K. Aida, K. Matsumoto, M. Okamoto, A. Yoshida, H. Honda, H. Kasahara, S. Narita

    Technical Report of IEICE   92 ( 172 (CPSY92-13) ) 33 - 40  1992.08

  • A HIERARCHICAL MACRO-DATAFLOW COMPUTATION SCHEME OF FORTRAN PROGRAMS

    M. Okamoto, K. Aida, W. Ogata, A. Yoshida, H. Honda, H. Kasahara

    SIG Notes of IPSJ   92 ( 64 (ARC-95) ) 105 - 112  1992.08

    CiNii

  • 密結合型マルチプロセッサシステム上でのProlog OR並列処理の実現

    甲斐 宗徳, 加茂 正充, 佐藤 弘幸, 笠原 博徳

    電子情報通信学会論文誌   J75-D-I ( 8 ) 675 - 684  1992.08  [Refereed]

    CiNii

  • データプレロードおよびポストストアを考慮したマルチプロセッサスケジューリングアルゴリズム

    藤原 和典, 白鳥 健介, 鈴木 真, 笠原 博徳

    電子情報通信学会論文誌   J75-D-I ( 8 ) 495 - 503  1992.08  [Refereed]

    CiNii

  • Fortranマクロデータフロー処理のマクロタスク生成手法

    笠原 博徳, 合田 憲人, 吉田 明正, 岡本 雅巳, 本多 弘樹

    電子情報通信学会論文誌   J75-D-I ( 8 ) 511 - 525  1992.08  [Refereed]

    CiNii

  • Fortranプログラム粗粒度タスクのOSCARにおける並列実行方式

    本多 弘樹, 合田 憲人, 岡本 雅巳, 笠原 博徳

    電子情報通信学会論文誌   J75-D-I ( 8 ) 526 - 535  1992.08  [Refereed]

    CiNii

  • Fortran マクロデータフロー処理のマルチプロセッサスーパーコンピュータ上での評価

    合田 憲人, 松本 健, 岡本 雅巳, 吉田 明正, 本田 弘樹, 笠原 博徳, 成田 誠之助

    電子情報通信学会技術報告   92 ( 172 (CPSY92-13) ) 33 - 40  1992.08  [Refereed]

  • Fortranプログラムの階層的マクロデータフロー処理手法

    岡本 雅巳, 合田 憲人, 尾形 航, 吉田 明正, 本多 弘樹, 笠原 博徳

    情報処理学会研究報告   92 ( 64 (ARC-95) ) 105 - 112  1992.08  [Refereed]

  • Multiprocessor Scheduling Algorithms Considering Data-Preloading and Poststoring

    K. Fujiwara, K. Shiratori, M. Suzuki, H. Kasahara

    Trans. of IEICE   J75-D-I ( 8 ) 495 - 503  1992.08  [Refereed]

    CiNii

  • Implementation of an OR-Parallel Processing Scheme of Prolog on Tightly-Coupled Multiprocessor System

    M. Kai, M. Kamo, H. Sato, H. Kasahara

    Trans. of IEICE   J75-D-I ( 8 ) 675 - 684  1992.08  [Refereed]

    CiNii

  • Coarse Grain Parallel Execution Scheme of a Fortran Program on OSCAR

    H. Honda, K. Aida, M. Okamoto, H. Kasahara

    Trans. of IEICE   J75-D-I ( 8 ) 526 - 535  1992.08  [Refereed]

    CiNii

  • A Macro-Task Generation Scheme for Fortran Macro-Dataflow Computation

    H. Kasahara, K. Aida, A. Yoshida, M. Okamoto, H. Honda

    Trans. of IEICE   J75-D-I ( 8 ) 511 - 525  1992.08  [Refereed]

    CiNii

  • Evaluation of Fortran Macro-dataflow Computation on a Multi-processor Supercomputer

    K. Aida, K. Matsumoto, M. Okamoto, A. Yoshida, H. Honda, H. Kasahara, S. Narita

    Technical Report of IEICE   92 ( 172 (CPSY92-13) ) 33 - 40  1992.08  [Refereed]

  • A HIERARCHICAL MACRO-DATAFLOW COMPUTATION SCHEME OF FORTRAN PROGRAMS

    M. Okamoto, K. Aida, W. Ogata, A. Yoshida, H. Honda, H. Kasahara

    SIG Notes of IPSJ   92 ( 64 (ARC-95) ) 105 - 112  1992.08  [Refereed]

  • OSCAR Multigrain Parallelizing compiler and Its Performance

    H. Kasahara

    CSRD, University of Illinois at Urbana-Champaign, Hosted by Professor Rudolf Eigenmann    1992.08  [Refereed]

  • リアルタイムシステムにおける並列処理

    笠原 博徳

    計測と制御   31 ( 7 )  1992.07  [Refereed]

  • Multi-grain Parallelizing Compiler and Its Performance

    H. Kasahara

    Third Workshop on Compilers for Parallel Computers, Panel: How good are parallelizing compilers in practice? ,Vienna, Austria    1992.07  [Refereed]

  • Near Fine Grain Parallelizing Compiler for OSCAR

    H. Kasahara, H. Honda, K. Aida, M. Okamoto, A. Yoshida, W. Ogata, S. Narita

    Proceedings of Third Workshop on Compilers for Parallel Computers    1992.07  [Refereed]

  • Parallel Processing in Real Time Systems

    H. Kasahara

    Journal of the Society of Instrument and Control Engineers   31 ( 7 )  1992.07  [Refereed]

  • A PARALLEL PROCESSING SCHEME OF CIRCUIT SIMULATION ON A MULTIPROCESSOR SYSTEM

    W. Premchaiswadi, Y. Maekawa, M. Tamura, H. Kasahara, S. Narita

    日本シミュレーション学会論文誌   11 ( 2 )  1992.06  [Refereed]

  • 並列計算機の実用化・商用化を逡巡させる諸要因とは?並列化コンパイラの現状と将来 (パネルディスカッション)

    笠原 博徳

    情報処理学会並列処理シンポジウムJSPP'92    1992.06  [Refereed]

  • 近細粒度タスクを用いた電子回路シミュレーションの並列処理

    前川 仁孝, 田村 光雄, W. Premchaiswadi, 笠原 博徳, 成田 誠之助

    情報処理学会並列処理シンポジウムJSPP'92    1992.06  [Refereed]

  • Parallel Processing of Circuit Simulation Using the Near Fine Grain Tasks

    Y. Maekawa, M. Tamura, W. Premchaiswadi, H. Kasahara, S. Narita

    Joint Symposium on Parallel Processing 1992    1992.06  [Refereed]

  • Present and Future of Parallelizing Compilers

    H. Kasahara

    Joint Symposium on Parallel Processing 1992    1992.06  [Refereed]

  • A PARALLEL PROCESSING SCHEME OF CIRCUIT SIMULATION ON A MULTIPROCESSOR SYSTEM

    W. Premchaiswadi, Y. Maekawa, M. Tamura, H. Kasahara, S. Narita

    Trans. of the Japan Society for Simulation Technology   11 ( 2 )  1992.06  [Refereed]

  • Outline of 'Research and Development of Multiprocessor Supercomputer PHI'

    S. Suzuki, H. Kasahara

    IPSJ MAGAZINE   33 ( 5 ) p512 - 565  1992.05

    CiNii

  • OSCAR上でのスパース行列直接解法の並列処理

    笠原 博徳, ウィチェン プレムチャイサワディ, 田村 光雄, 前川 仁孝, 成田 誠之助

    情報処理学会論文誌   33 ( 4 )  1992.04  [Refereed]

  • Parallel Processing of Direct Solution Method for Unstructured Sparse Matrices on OSCAR

    H. Kasahara, W. Premchaiswadi, M. Tamura, Y. Maekawa, S. Narita

    Trans. of IPSJ   33 ( 4 )  1992.04  [Refereed]

  • A PARALLEL PROCESSING SCHEME FOR REAL TIME SIMULATION OF CONTINUOUS-AND DISCRETE-TIME CONTROL SYSTEM

    H. Torii, M. Tamura, Y. Maekawa, Y. Yamamoto, H. Kasahara, S. Narita

    Technical Report of IEICE   92 ( 28 (CPSY91-80) ) 67 - 74  1992.03

    CiNii

  • 連続・離散時間制御システム・リアルタイムシミュレーションの並列処理手法

    鳥居 宏行, 田村 光雄, 前川 仁孝, 山本 裕治, 笠原 博徳, 成田 誠之助

    電子情報通信学会技術研究報告   92 ( 28 (CPSY91-80) ) 67 - 74  1992.03  [Refereed]

  • 専用目的コンパイラ開発用並列化中間言語とその処理系

    田村 光雄, 前川 仁孝, 笠原 博徳, 成田 誠之助

    情報処理学会第44回全国大会   3D-1  1992.03  [Refereed]

  • 階層的マクロデータフロー処理のインプリメント手法

    岡本 雅巳, 合田 憲人, 尾形 航, 吉田 明正, 本多 弘樹, 笠原 博徳

    情報処理学会第44回全国大会   2D-9  1992.03  [Refereed]

  • 階層メモリマルチプロセッサシステム上でのデータ分割・配置及びデータ転送と処理のオーバーラッピング手法

    藤原 和典, 林田 宏一, 笠原 博徳

    情報処理学会第44回全国大会   2D-10  1992.03  [Refereed]

  • マルチプロセッサスーパーコンピュータ上でのFORTRANマクロデータフロー処理

    合田 憲人, 岡本 雅巳, 尾形 航, 本多 弘樹, 笠原 博徳, 成田 誠之助

    情報処理学会第44回全国大会   2D-6  1992.03  [Refereed]

  • OSCAR上での直接法を用いた回路シミュレーションの並列処理

    前川 仁孝, 田村 光雄, Wichian Premchaiswadi, 笠原 博徳, 成田 誠之助

    情報処理学会第44回全国大会   3D-2  1992.03  [Refereed]

  • A PARALLEL PROCESSING SCHEME FOR REAL TIME SIMULATION OF CONTINUOUS-AND DISCRETE-TIME CONTROL SYSTEM

    H. Torii, M. Tamura, Y. Maekawa, Y. Yamamoto, H. Kasahara, S. Narita

    Technical Report of IEICE   92 ( 28 (CPSY91-80) ) 67 - 74  1992.03  [Refereed]

  • Prolog OR並列処理における副作用対処法

    佐藤 弘幸, 加茂 正充, 甲斐 宗徳, 笠原 博徳

    1992年電子情報通信学会全国大会   D-127  1992.03  [Refereed]

  • OSCAR 上での連続・離散時間制御システムシミュレーションの並列処理

    鳥居 弘行, 山本 裕治, 川田 雄司, 笠原 博徳, 成田 誠之助

    1992年電子情報通信学会全国大会   D-128  1992.03  [Refereed]

  • A MULTI-GRAIN PARALLELIZING COMPILATION SCHEME FOR OSCAR (OPTIMALLY SCHEDULED ADVANCED MULTIPROCESSOR)

    H KASAHARA, H HONDA, A MOGI, A OGURA, K FUJIWARA, S NARITA

    LECTURE NOTES IN COMPUTER SCIENCE   589   281 - 297  1992  [Refereed]

    　View Summary

    This paper proposes a multi-grain parallelizing compilation scheme for Fortran programs. The scheme hierarchically exploits parallelism among coarse grain tasks, such as, loops, subroutines or basic blocks, among medium grain tasks like loop iterations and among near fine grain tasks like statements. Parallelism among the coarse grain tasks called the macrotasks is exploited by carefully analyzing control dependences and data dependences. The macrotasks are dynamically assigned to processor clusters to cope with run-time uncertainties, such as, conditional branches among the macrotasks and variation of execution time of each macrotask. The parallel processing of macrotasks is called the macro-dataflow computation. A macrotask composed of a Do-all loop, which is assigned onto a processor cluster, is processed in the medium grain in parallel by processors inside the processor cluster. A macrotask composed of a sequential loop or a basic block is processed on a processor cluster in the near fine grain by using static scheduling. A macro task composed of subroutine or a large sequential loop is processed by hierarchically applying macro-dataflow computation inside a processor cluster. Performance of the proposed scheme is evaluated on a multiprocessor system named 0 SCAR. The evaluation shows that the multi-grain parallel processing effectively exploits parallelism from Fortran programs.

  • A MULTI-GRAIN PARALLELIZING COMPILATION SCHEME FOR OSCAR (OPTIMALLY SCHEDULED ADVANCED MULTIPROCESSOR)

    H KASAHARA, H HONDA, A MOGI, A OGURA, K FUJIWARA, S NARITA

    LANGUAGES AND COMPILERS FOR PARALLEL COMPUTING   589   281 - 297  1992  [Refereed]

  • A parallel optimization algorithm for minimum execution‐time multiprocessor scheduling problem

    Hironori Kasahara, Atsusi Itoh, Hisamitsu Tanaka, Keisuke Itoh

    Systems and Computers in Japan   23 ( 13 ) 54 - 65  1992  [Refereed]

    　View Summary

    This paper proposes a parallel optimization algorithm PDF/IHS for the minimum execution‐time multiprocessor scheduling problem which is a strong NP‐hard optimization problem. PDF/IHS is a parallelization and efficient implementation of the only practical optimization algorithm DF/IHS among those which have been proposed for this scheduling problem. In PDF/IHS, processors perform depth‐first search in parallel on a heuristically generated search tree in such a way that it is searched hierarchically from the left‐ and right‐hand sides. The effectiveness of PDF/IHS has been verified by simulation and practical parallel processing on Alliant FX4. As a result, it has been recognized that most of the problems which required a long time by DF/IHS can be solved approximately in time 1/m by PDF/IHS using m processors. Moreover, even for a problem which required a very long time or could not be solved in a practical time by DF/IHS, it has been verified that PDF/IHS can give solutions in time less than 1/m. Copyright © 1992 Wiley Periodicals, Inc., A Wiley Company

    DOI

    Scopus

    4
    Citation
    (Scopus)

  • Fortran Macro-dataflow Computation on OSCAR

    A. Yoshida, K. Aida, M. Okamoto, H. Honda, H. Kasahara

    Technical Report of IEICE   91 ( 463 (CPSY91-69) ) 55 - 62  1992.01

  • OSCAR 上での Fortran マクロデータフロー処理

    吉田 明正, 合田 憲人, 岡本 雅巳, 本多 弘樹, 笠原 博徳

    電子情報通信学会技術研究報告   91 ( 463 (CPSY91-69) ) 55 - 62  1992.01  [Refereed]

  • Fortran Macro-dataflow Computation on OSCAR

    A. Yoshida, K. Aida, M. Okamoto, H. Honda, H. Kasahara

    Technical Report of IEICE   91 ( 463 (CPSY91-69) ) 55 - 62  1992.01  [Refereed]

  • A multi-grain parallel processing of Fortran programs

    M. Okamoto, K. Aida, H. Honda, H. Kasahara

    Technical Report of IEICE   91 ( 365 (CPSY91-55) ) 23 - 30  1991.12

  • Fortran マルチグレイン並列処理

    岡本 雅巳, 合田 憲人, 本多 弘樹, 笠原 博徳

    電子情報通信学会技術研究報告   91 ( 365 (CPSY91-55) ) 23 - 30  1991.12  [Refereed]

  • 海外の並列処理研究動向 イリノイ大学CSRDにおける並列処理研究

    笠原 博徳

    情報処理   32 ( 12 )  1991.12  [Refereed]

  • Parallel Processing Researches in CSRD of University of Illinois at Urbana-Champaign

    H. Kasahara

    Trans. of IPSJ   32 ( 12 )  1991.12  [Refereed]

  • A multi-grain parallel processing of Fortran programs

    M. Okamoto, K. Aida, H. Honda, H. Kasahara

    Technical Report of IEICE   91 ( 365 (CPSY91-55) ) 23 - 30  1991.12  [Refereed]

  • Implementation of OSCAR/Fortran Compiler

    H. Honda, M. Okamoto, K. Aida, H. Kasahara

    SIG Notes of IPSJ   91 ( 100 (ARC-91) ) 13 - 20  1991.11

  • 実行時間最小マルチプロセッサスケジューリング問題に対する並列最適化アルゴリズム

    笠原 博徳, 伊藤 敦, 田中 久充, 伊藤 敬介

    電子情報通信学会論文誌 D-I   J74-D-I ( 11 ) 755 - 764  1991.11  [Refereed]

  • OSCAR/Fortran コンパイラのインプリメンテーション

    本多 弘樹, 岡本 雅巳, 合田 憲人, 笠原 博徳

    情報処理学会研究報告   91 ( 100 (ARC-91) ) 13 - 20  1991.11  [Refereed]

  • A Parallel Optimization Algorithm for Minimum Execution-Time Multiprocessor Scheduling Problem

    H. Kasahara, A. Itoh, H. Tanaka, K. Itoh

    Trans. of IEICE D-I   J74-D-I ( 11 ) 755 - 764  1991.11  [Refereed]

  • Implementation of OSCAR/Fortran Compiler

    H. Honda, M. Okamoto, K. Aida, H. Kasahara

    SIG Notes of IPSJ   91 ( 100 (ARC-91) ) 13 - 20  1991.11  [Refereed]

  • Fortran Multigrain Compiler for a Multiprocessor OSCAR

    H. Kasahara

    Rice University, Hosted by Professor Ken Kennedy    1991.11  [Refereed]

  • OSCAR FORTRAN Compiler

    H. Kasahara, H. Honda, K. Aida, M. Okamoto, S. Narita

    International Logic Programming Symposium, Workshop on Compilation of (Symbolic) Languages for Parallel Computers    1991.11  [Refereed]

  • Perspective on Simulation

    H. Ishitani, H. Tsukui, Y. Ono, Y. Iida, S. Umeda, H. Ezure, H. Kasahara, M. Tago, K. Miki

    Technical Report of IEE(Part II)   374  1991.10  [Refereed]

  • 分担解説 シミュレーション最近の動向

    石谷 久, 都井 裕, 小野 祐一, 飯田 善久, 梅田 茂樹, エム, 江連 久, 笠原 博徳, 田子 精男, 三木 一克

    電気学会技術報告2部   374  1991.10  [Refereed]

  • A FORTRAN PARALLELIZING COMPILATION SCHEME FOR OSCAR USING DEPENDENCE GRAPH ANALYSIS

    H KASAHARA, H HONDA, S NARITA

    IEICE TRANSACTIONS ON COMMUNICATIONS ELECTRONICS INFORMATION AND SYSTEMS   74 ( 10 ) 3105 - 3114  1991.10  [Refereed]

    　View Summary

    This paper proposes a Fortran parallelizing compilation scheme for a multiprocessor system named OSCAR. The scheme hierarchically exploits parallelism among coarse grain tasks, such as, loops, subroutines or basic blocks. among medium grain tasks like loop iterations and among near fine grain tasks like statements. Parallelism among the coarse grain tasks called the macrotasks is detected by analyzing a macro-flow graph which explicitly represents control flow and data dependences. The detected parallelism among the macrotasks is represented by a directed acyclic graph called a macrotask graph. Macrotasks in a macrotask graph are dynamically assigned to processor clusters to cope with run-time uncertainties. A macrotask composed of a Do-all loop or a Do-across loop, which is assigned onto a processor cluster, is processed in the medium grain in parallel by processors inside the processor cluster. A macrotask composed of a basic block is processed on a processor cluster in the near fine grain by using static scheduling. A macrotask composed of subroutine or a large sequential loop is processed by hierarchically applying macro-dataflow computation inside a processor cluster. Performance of the proposed scheme is evaluated on OSCAR. The evaluation shows that the hierarchical parallel processing scheme using dynamic and static scheduling effectively exploits parallelism from Fortran programs.

  • Schemes for decomposition and fusion of macrotasks in the macro-dataflow computation

    K. Aida, M. Okamoto, A. Yoshida, H. Honda, H. Kasahara

    Technical Report of IEICE   91 ( 130 (CPSY91-30) ) 205 - 212  1991.07

  • Parallel Processing of Direct Solution Method for Random Sparse Matrix

    Y. Maekawa, M. Tamura, W. Premchaiswadi, H. Kasahara, S. Narita

    Technical Report of IEICE   91 ( 130 (CPSY91-17) ) 107 - 114  1991.07

  • Scheduling Algorithms Considering Data-preloading and Data-poststoring for Hierarchical Memory Multiprocessor Systems

    K. Fujiwara, K. Shiratori, M. Suzuki, H. Kasahara

    Technical Report of IEICE   91 ( 130 (CPSY91-14) ) 83 - 90  1991.07

  • 階層記憶マルチプロセッサシステムにおけるプレロード, ポストストアを考慮したスケジューリングアルゴリズム

    藤原 和典, 白鳥 健介, 鈴木 真, 笠原 博徳

    電子情報通信学会技術研究報告   91 ( 130 (CPSY91-14) ) 83 - 90  1991.07  [Refereed]

  • ランダムスパースマトリクス直接解法の並列処理

    前川 仁孝, 田村 光雄, W.Premchaiswadi, 笠原 博徳, 成田 誠之助

    電子情報通信学会技術研究報告   91 ( 130 (CPSY91-17) ) 107 - 114  1991.07  [Refereed]

  • マクロデータフロー処理におけるマクロタスク分割・融合手法

    合田 憲人, 岡本 雅巳, 吉田 明正, 本多 弘樹, 笠原 博徳

    電子情報通信学会技術研究報告   91 ( 130 (CPSY91-30) ) 205 - 212  1991.07  [Refereed]

  • Schemes for decomposition and fusion of macrotasks in the macro-dataflow computation

    K. Aida, M. Okamoto, A. Yoshida, H. Honda, H. Kasahara

    Technical Report of IEICE   91 ( 130 (CPSY91-30) ) 205 - 212  1991.07  [Refereed]

  • Scheduling Algorithms Considering Data-preloading and Data-poststoring for Hierarchical Memory Multiprocessor Systems

    K. Fujiwara, K. Shiratori, M. Suzuki, H. Kasahara

    Technical Report of IEICE   91 ( 130 (CPSY91-14) ) 83 - 90  1991.07  [Refereed]

  • Parallel Processing of Direct Solution Method for Random Sparse Matrix

    Y. Maekawa, M. Tamura, W. Premchaiswadi, H. Kasahara, S. Narita

    Technical Report of IEICE   91 ( 130 (CPSY91-17) ) 107 - 114  1991.07  [Refereed]

  • マルチプロセッサシステム上での非線形微分方程式の並列処理

    W.Pemchaiswadi, H. Kasahara, S. Narita

    シミュレーション   10 ( 2 ) 140 - 150  1991.06  [Refereed]

  • Parallel processing of nonlinear differential algebraic equations on a multiprocessor system

    W. Premchaiswadi, H. Kasahara, S. Narita

    Simulation   10 ( 2 ) 140 - 150  1991.06  [Refereed]

  • 将来の並列処理のあるべき姿 いま何をすべきか(パネルディスカッション)

    笠原 博徳

    情報処理学会並列処理シンポジウムJSPP'91    1991.05  [Refereed]

  • Future Parallel Processing Systems

    H. Kasahara

    Symposium of IPSJ JSPP'91    1991.05  [Refereed]

  • 並列コンパイラの諸技術

    笠原 博徳

    電子情報通信学会 第4回回路とシステム軽井沢ワークショップ論文集     227 - 232  1991.04  [Refereed]

  • マルチプロセッサシステムの動向

    笠原 博徳

    電子情報通信学会 第4回回路とシステム軽井沢ワークショップ論文集     127 - 132  1991.04  [Refereed]

  • 並列処理技術 マルチプロセッサシステムのハードウェア

    笠原 博徳

    コンピュータ・シミュレーション   2 ( 2 ) 32 - 41  1991.04  [Refereed]

  • Parallel Processor Technology: Hardware of Multiprocessor Systems

    H. Kasahara

    COMPUTER SIMULATION   2 ( 2 ) 32 - 41  1991.04  [Refereed]

  • Perspective on Multiprocessor Systems

    H. Kasahara

    Proc. of The Fourth KARUIZAWA Workshop on Circuits and Systems    1991.04  [Refereed]

  • Parallelizing Compilation Techniques

    H. Kasahara

    Proc. of The Fourth KARUIZAWA Workshop on Circuits and Systems    1991.04  [Refereed]

  • 階層メモリマルチプロセッサシステムのためのデータプレローディング及びポストストアアルゴリズム

    藤原 和典, 白鳥 健介, 鈴木 真, 笠原 博徳

    情報処理学会第42回全国大会講演論文集   ( 6 ) 6.66 - 6.67  1991.03  [Refereed]

  • データ転送を考慮した最適化マルチプロセッサスケジューリング・アルゴリズム

    伊藤 敬介, 宮川 尚, 笠原 博徳

    情報処理学会第42回全国大会講演論文集   ( 6 ) 6.64 - 6.65  1991.03  [Refereed]

  • OSCAR用デバッグシステム

    滝沢 和史, 笠原 博徳, 成田 誠之助

    情報処理学会第42回全国大会講演論文集   ( 6 ) 6.82 - 6.83  1991.03  [Refereed]

  • OSCAR上での階層型ニューラル・ネットワークの学習計算の並列処理

    飯田 晴彦, 若田 秀夫, 中野 恵一, 笠原 博徳

    情報処理学会第42回全国大会講演論文集   ( 6 ) 6.80 - 6.81  1991.03  [Refereed]

  • OSCAR上でのセルラ・ニューラル・ネットワーク・シミュレーションの並列処理手法

    吉岡 明広, 林 俊成, 笠原 博徳, 成田 誠之助, L. Chua

    情報処理学会第42回全国大会講演論文集   ( 6 ) 6.78 - 6.79  1991.03  [Refereed]

  • OSCAR上でのFortranサブルーチンの並列処理

    茂木 章善, 本多 弘樹, 笠原 博徳

    情報処理学会第42回全国大会講演論文集   ( 6 ) 6.74 - 6.75  1991.03  [Refereed]

  • OSCAR上でのFORTRANプログラムの階層的マクロデータフロー処理手法

    小椋 章央, 合田 憲人, 本多 弘樹, 笠原 博徳, 成田 誠之助

    情報処理学会第42回全国大会講演論文集   ( 6 ) 6.76 - 6.77  1991.03  [Refereed]

  • 報告 並列コンピュータの動向

    笠原 博徳

    電波新聞社    1991.01  [Refereed]

  • Perspective on Parallel Computers

    H. Kasahara

    Denpa-Shinbun    1991.01  [Refereed]

  • PARALLEL PROCESSING SCHEME FOR A FORTRAN PROGRAM ON A MULTIPROCESSOR SYSTEM OSCAR

    H HONDA, A MOGI, A OGURA, H KASAHARA, S NARITA

    IEEE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUTERS AND SIGNAL PROCESSING : CONFERENCE PROCEEDINGS, VOLS 1 AND 2   1   9 - 12  1991  [Refereed]

  • AN EFFICIENT OR PARALLEL PROCESSING SCHEME OF PROLOG - HIERARCHICAL PINCERS ATTACK SEARCH

    M KAI, H KASAHARA

    IEEE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUTERS AND SIGNAL PROCESSING : CONFERENCE PROCEEDINGS, VOLS 1 AND 2   2   677 - 680  1991  [Refereed]

  • PARALLEL PROCESSING OF SPARSE-MATRIX SOLUTION USING FINE-GRAIN TASKS ON OSCAR (OPTIMALLY SCHEDULED ADVANCED MULTIPROCESSOR)

    H KASAHARA, W PREMCHAISWADI, M TAMURA, Y MAEKAWA, S NARITA

    PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING, VOL 3     II322 - II323  1991  [Refereed]

  • Fortranプログラム粗粒度タスク間の並列性検出手法

    本多 弘樹, 岩田 雅彦, 笠原 博徳

    電子情報通信学会論文誌   J73-D-I ( 12 ) 951 - 960  1990.12  [Refereed]

  • Coarse Grain Parallelism Detection Scheme of a Fortran Program

    H. Honda, M. Iwata, H. Kasahara

    Trans. of IEICE   J73-D-I ( 1 ) 951 - 960  1990.12  [Refereed]

  • 原子プラント状態予測シミュレータへの並列処理の適用

    佐々木 和則, 神余 浩夫, 笠原 博徳, 成田 誠之助

    日本原子力学会誌   32 ( 10 ) 1099 - 1022  1990.10  [Refereed]

  • OSCAR上でのFortranプログラム基本ブロックの並列処理手法

    本多 弘樹, 水野 聡, 笠原 博徳, 成田 誠之助

    電子情報通信学会論文誌   J73-D-I ( 9 ) 756 - 766  1990.09  [Refereed]

  • 米国イリノイ大学滞在記

    笠原 博徳

    電気学会論文誌B    1990.09  [Refereed]

  • Parallel Processing Scheme of a Basic Block in a Fortran Program on OSCAR

    H. Honda, H. Kasahara, S. Narita, S. Mizuno

    Trans. of IEICE   J73-D-I ( 9 ) 756 - 766  1990.09  [Refereed]

  • Researching in University of Illinois at Urbana-Champaign

    H. Kasahara

    Trans. of IEE Japan B    1990.09  [Refereed]

  • 並列コンピュータの最新動向

    笠原 博徳

    ソニーコンピューターフェア'90    1990.06  [Refereed]

  • Perspective on Parallel Computers

    H. Kasahara

    Sony Computer Fair '90    1990.06  [Refereed]

  • 最適化並列コンパイラ技術の現状

    笠原 博徳

    電子情報通信学会学会誌   73 ( 3 )  1990.03  [Refereed]

  • OSCAR上での音声認識の並列処理手法

    飯田晴彦, 笠原博徳, 成田誠之助

    情報処理学会第41回全国大会講演論文集   ( 6 )  1990.03  [Refereed]

  • Current State of Optimal Parallelizing Compilers

    H. Kasahara

    Journal of ICICE   73 ( 3 )  1990.03  [Refereed]

  • 並列化マルチプロセッサ・スケジューリングアルゴリズムの性能評価

    守友祥史, 笠原博徳, 成田誠之助

    1990年電子情報通信学会全国大会講演論文集   Pt.6  1990.03  [Refereed]

  • 汎用目的マルチプロセッサシステムOSCARの実行環境

    入江豊, 本多弘樹, 笠原博徳, 成田誠之助

    1990年電子情報通信学会全国大会講演論文集   Pt.6  1990.03  [Refereed]

  • 階層型メモリマルチプロセッサシステムにおけるデータ転送とタスク分割の最適化

    白鳥健介, 鈴木真, 笠原博徳, 成田誠之助

    1990年電子情報通信学会全国大会講演論文集   Pt.6  1990.03  [Refereed]

  • ロールバックモデルに基づくOSCAR上での離散系シミュレーションの並列処理手法

    橋本高男, 笠原博徳, 成田誠之助

    1990年電子情報通信学会全国大会講演論文集   Pt.6  1990.03  [Refereed]

  • データ転送を考慮した最適化マルチプロセッサスケジューリング・アルゴリズム

    RATNA A. A. P, 伊藤敬介, 笠原博徳, 成田誠之助

    1990年電子情報通信学会全国大会講演論文集   Pt.6  1990.03  [Refereed]

  • データプレローディングを考慮したマルチプロセッサスタティックスケジューリングアルゴリズム

    鈴木真, 藤原和典, 笠原博徳, 成田誠之助

    1990年電子情報通信学会全国大会講演論文集   Pt.6  1990.03  [Refereed]

  • Prolog OR並列処理「階層型挟み打ち探索法」の拡張

    新名孝至, 甲斐宗徳, 湯浅理之, 笠原博徳

    1990年電子情報通信学会全国大会講演論文集   Pt.6  1990.03  [Refereed]

  • OSCAR上での常微分方程式求解並列処理の性能評価

    久永裕嗣, 笠原博徳, 成田誠之助

    1990年電子情報通信学会全国大会講演論文集   Pt.6  1990.03  [Refereed]

  • OSCAR上でのスパース線形方程式求解並列処理の性能評価

    佐藤東哉, 笠原博徳, 成田誠之助

    1990年電子情報通信学会全国大会講演論文集   Pt.6  1990.03  [Refereed]

  • OSCARコンパイラにおけるループ並列化手法

    市川伸治, 本多弘樹, 笠原博徳, 成田誠之助

    1990年電子情報通信学会全国大会講演論文集   Pt.6  1990.03  [Refereed]

  • PARALLEL PROCESSING OF NEAR FINE GRAIN TASKS ON OSCAR (Optimally Scheduled Advanced Multiprocessor)

    H. Kasahara, H. Honda, W. PREMCHAISWADI, A. Ogura, A. Mogi, S. Narita

    SIG Notes of IPSJ   90 ( 60(ARC-83) ) 97 - 102  1990

    CiNii

  • Parallelized Optimizing Multiprocessor Scheduling Algorithm

    H. Kasahara, H. Tanaka, K. Itoh

    SIG Notes of IPSJ   90 ( 60 (ARC-83) ) 91 - 96  1990

  • PARALLEL PROCESSING SCHEME OF THE SOLUTION OF STIFF NONLINEAR ORDINARY DIFFERENTIAL ALGEBRAIC EQUATIONS ON OSCAR

    W. Premchaiswadi, H. Honda, H. Kasahara, S. Narita

    SIG Notes of IPSJ   90 ( 60(ARC-83) ) 85 - 90  1990

  • 並列化マルチプロセッサ・スケジューリング・アルゴリズム

    笠原 博徳, 田中 久充, 伊藤 敬介

    情報処理学会研究報告   90 ( 60 (ARC-83) ) 91 - 96  1990  [Refereed]

  • OSCAR上での細粒度タスクの並列処理

    笠原 博徳, 本多 弘樹, W. Premchaiswadi, 小椋 章央, 茂木 章善, 成田 誠之助

    情報処理学会研究報告   90 ( 60(ARC-83) ) 97 - 102  1990  [Refereed]

  • OSCAR上でのスティッフ微分方程式求解の並列処理

    W. Premchaiswadi, H. Honda, H. Kasahara, S. Narita

    情報処理学会研究報告   90 ( 60(ARC-83) ) 85 - 90  1990  [Refereed]

  • Improvement in Hierarchical Pincers Attack Search for Or Parallel Processing of Prolog

    M. Kai, T. Shimmei, K. Kobayashi, H. Kasahara, H. Iizuka

    Technical Report of IEICE   89 ( 168 (CPSY89 45-58) )  1990  [Refereed]

  • Implementation and Performance Evaluation of Fortran Parallel Processing System on Oscar

    H. Honda, M. Hirota, Y. Irie, M. Suzuki, H. Kasahara, S. Narita

    Technical Report of IEICE   89 ( 168 (CPSY89 89-57) )  1990  [Refereed]

  • Parallelized Optimizing Multiprocessor Scheduling Algorithm

    H. Kasahara, H. Tanaka, K. Itoh

    SIG Notes of IPSJ   90 ( 60 (ARC-83) ) 91 - 96  1990  [Refereed]

  • PARALLEL PROCESSING SCHEME OF THE SOLUTION OF STIFF NONLINEAR ORDINARY DIFFERENTIAL ALGEBRAIC EQUATIONS ON OSCAR

    W. Premchaiswadi, H. Honda, H. Kasahara, S. Narita

    SIG Notes of IPSJ   90 ( 60(ARC-83) ) 85 - 90  1990  [Refereed]

  • PARALLEL PROCESSING OF NEAR FINE GRAIN TASKS ON OSCAR (Optimally Scheduled Advanced Multiprocessor)

    H. Kasahara, H. Honda, W. PREMCHAISWADI, A. Ogura, A. Mogi, S. Narita

    SIG Notes of IPSJ   90 ( 60(ARC-83) ) 97 - 102  1990  [Refereed]

    CiNii

  • A Compilation Scheme for Macro-dataflow computation on Hierarchical Multiprocessor System

    H. Kasahara, H. Honda, M. Iwata, M. Hirota

    Proc. Int Conf. on Parallel Processing     294 - 295  1990  [Refereed]

    CiNii

  • PARALLEL PROCESSING OF ROBOT ARM DYNAMIC CONTROL COMPUTATION ON MULTIMICROPROCESSORS

    H KASAHARA

    MICROPROCESSORS AND MICROSYSTEMS   14 ( 1 ) 3 - 9  1990.01  [Refereed]

  • APPLICATION OF PARALLEL PROCESSING TO PWR PLANT PREDICTIVE SIMULATOR

    K SASAKI, H KANAMARU, H KASAHARA, S NARITA

    JOURNAL OF THE ATOMIC ENERGY SOCIETY OF JAPAN   32 ( 10 ) 1009 - 1022  1990  [Refereed]

  • PARALLEL PROCESSING OF NEAR FINE-GRAIN TASKS USING STATIC SCHEDULING ON OSCAR (OPTIMALLY SCHEDULED ADVANCED MULTIPROCESSOR)

    H KASAHARA, H HONDA, S NARITA

    SUPERCOMPUTING 90     856 - 864  1990  [Refereed]

  • 並列処理技術-マルチプロセッサシステム上での並列シュミレーションの実例

    笠原 博徳

    日本シミュレーション学会誌   8 ( 4 )  1989.12  [Refereed]

  • Parallel Processing Technology-Practical Parallel Simulation on Multiprocessor Systems

    H. Kasahara

    Research Papers of the JSTT   8 ( 4 )  1989.12  [Refereed]

  • 並列処理技術-並列処理におけるソフトウェア

    笠原 博徳

    日本シミュレーション学会誌   8 ( 3 )  1989.09  [Refereed]

  • Parallel Processing Technology-Software for Parallel Processing Systems

    H. Kasahara

    Research Papers of the JSTT   8 ( 3 )  1989.09  [Refereed]

  • Parallel Processing of Real-time Dynamic Systems Simulation on OSCAR (Optimally SCheduled Advanced multiprocessoR)

    H. Kasahara, H. Honda, S. Narita

    Proc. 3rd NASA NSF DOD Conf. on Aerospace Computational Control    1989.08  [Refereed]

  • ロボット制御・シミュレーションの並列処理

    笠原 博徳

    計測自動制御学会SICE'88    1989.07  [Refereed]

  • OSCAR Fortran Compiler

    H. Kasahara

    IBM T. J. Watson Research Center, Hosted by Dr. Vivek Sarker    1989.07  [Refereed]

  • Parallel processing of robot control and simulation

    H. Kasahara

    The Society of Instrument and Control Engineers(SICE'88)    1989.07  [Refereed]

  • 並列処理技術-マルチプロセッサシステムのハードウェア

    笠原 博徳

    日本シミュレーション学会誌   8 ( 2 )  1989.06  [Refereed]

  • Parallel Processing Technology-Hardware of Multiprocessor Systems

    H. Kasahara

    Research Papers of the JSTT   8 ( 2 )  1989.06  [Refereed]

  • Parallel Processing of Robot Control and Simulation

    H. Kasahara, S. Narita

    Proc. Workshop on Parallel Algorithm of IEEE Conf. on Robotics and Automation    1989.05  [Refereed]

  • Fortran Macro-dataflow processing

    H. Kasahara

    CSRD, University of Illinois at Urbana-Champaign, Hosted by Professor David Padua    1989.04  [Refereed]

  • 並列処理技術-並列処理の概要-

    笠原博徳

    日本シミュレーション学会誌    1989.03  [Refereed]

  • 並列化マルチプロセッサ・スケジューリング・アルゴリズムの実マルチプロセッサ上でのインプリメント

    田中久充, 笠原博徳

    情報処理学会第38回全国大会講演論文集   ( 3 ) 1452 - 1453  1989.03  [Refereed]

  • 階層型挟み打ち法によるPROLOG OR並列処理

    小林和男, 甲斐宗徳, 笠原博徳

    情報処理学会第38回全国大会講演論文集   ( 3 ) 1454 - 1455  1989.03  [Refereed]

  • OSCAR上での並列化FORTRAN コンパイラのインプリメント

    広田雅一, 本多弘樹, 笠原博徳

    情報処理学会第38回全国大会講演論文集   ( 3 ) 1447 - 1448  1989.03  [Refereed]

  • OSCAR上での電力潮流計算の並列処理

    中野恵一, 佐藤東哉, 笠原博徳, 成田誠之助

    情報処理学会第38回全国大会講演論文集   ( 3 ) 1451  1989.03  [Refereed]

  • OSCAR上での階層型ニューラル・ネットワーク・シミュレーションの並列処理手法

    中野恵一, 奥田恒久, 笠原博徳

    情報処理学会第38回全国大会講演論文集   ( 3 ) 1445 - 1446  1989.03  [Refereed]

  • OSCAR上でのインプリシット常微分方程式求解の並列処理手法のインプリメント

    PREMCHAISWADI W, 奥田恒久, 佐藤東哉, 笠原博徳, 成田誠之助

    情報処理学会全国大会講講演論文集   ( 3 ) 1449 - 1450  1989.03  [Refereed]

  • A Parallel Processing Scheme for the Solution of Ordinary Differential Equations Using Static Optimal Multiprocessor Scheduling Algorithms

    H. Kasahara, H. Honda, E. Takane, S. Narita

    PROCEEDINGS OF THE THIRD ANNUAL PARALLEL PROCESSING SYMPOSIUM    1989.03  [Refereed]

  • Parallel Processing Technology -Overview of Parallel Processing-

    H. Kasahara

    Journal of the Japan Society for Simulation Technology    1989.03  [Refereed]

  • 階層型挟み打ち探索法を用いたProlog OR並列処理

    小林和男, 笠原博徳, 甲斐宗徳

    情報処理学会並列処理シンポジウムJSPP'89論文集    1989.02  [Refereed]

  • 階層型マルチプロセッサシステムOSCAR上でのFortran並列処理手法

    本多弘樹, 広田雅一, 笠原博徳

    情報処理学会並列処理シンポジウムJSPP'89論文集   2   251 - 258  1989.02  [Refereed]

    CiNii

  • Architecture of a General Purpose Multiprocessor System OSCAR

    H. Kasahara, H. Honda, S. Narita, S. Hashimoto

    Trans. of IPSJ   88 ( 3 )  1989.02  [Refereed]

  • Prolog OR Parallel Processing Using Hierarchical Pincers Attack Search

    K. Kobayashi, H. Kasahara, M. Kai

    Joint Symposium on Parallel Processing 1989    1989.02  [Refereed]

  • Parallel Processing Scheme of Fortran on Hierarchical Multiprocessor System Oscar

    H. Honda, M. Hirota, H. Kasahara

    Joint Symposium on Parallel Processing 1989    1989.02  [Refereed]

  • Improvement in Hierarchical Pincers Attack Search for Or Parallel Processing of Prolog

    M. Kai, T. Shimmei, K. Kobayashi, H. Kasahara, H. Iizuka

    Technical Report of IEICE   89 ( 168 (CPSY89 45-58) )  1989

  • Implementation and Performance Evaluation of Fortran Parallel Processing System on Oscar

    H. Honda, M. Hirota, Y. Irie, M. Suzuki, H. Kasahara, S. Narita

    Technical Report of IEICE   89 ( 168 (CPSY89 89-57) )  1989

  • Prolog並列処理「階層型挟み打ち探索法」の拡張

    甲斐宗徳, 新名孝至, 小林和男, 笠原博徳, 飯塚肇

    電子情報通信学会技術研究報告   89 ( 168(CPSY89 45-58) )  1989  [Refereed]

  • OSCAR上でのFortran並列処理系のインプリメントと性能評価

    本多弘樹, 広田雅一, 入江豊, 鈴木 真, 笠原博徳, 成田誠之助

    電子情報通信学会技術研究報告   89 ( 168 (CPSY89 89-57) )  1989  [Refereed]

  • 汎用目的マルチプロセッサ・システムOSCAR上での常微分方程式求解の並列処理

    笠原博徳, 高根栄二, 佐藤東哉, 久永裕嗣, 成田誠之助

    早稲田大学情報科学研究教育センタ紀要   8.Autumn  1988.09  [Refereed]

  • PROLOG 階層型挟み打ち並列探索法のALLIANT FX/4上での性能評価

    小林和男, 甲斐宗徳, 笠原博徳

    情報処理学会第37回全国大会講演論文集   37 ( 1 ) 188 - 189  1988.09  [Refereed]

    CiNii

  • Parallel Processing for the Solution of Sparse Linear Equations on OSCAR (Optimally Scheduled Advanced Multiprocessor)

    H. Kasahara, H. Nakayama, E. Takane, S. Narita

    Proc. IEE BISL CONPAR 88(Cambridge Univ Press)    1988.09  [Refereed]

  • ロボット用高度並列コンピュータの展望

    笠原博徳, 成田誠之助

    日本ロボット学会誌   6 ( 4 )  1988.08  [Refereed]

  • OSCAR(Optimally Scheduled Advanced Multiprocessor)のアーキテクチャ

    笠原博徳, 成田誠之助, 橋本親

    電子情報通信学会論文誌   J71-D ( 8 )  1988.08  [Refereed]

  • OSCAR(Optimally Scheduled Advanced Multiprocessor)上での連続システムシミュレーションの並列処理

    笠原 博徳

    計測自動制御学会システムシンポジウム講演論文集   14  1988.08  [Refereed]

  • Architecture of OSCAR(Optimally Scheduled Advanced Multiprocessor)

    H. Kasahara, S. Narita, S. Hashimoto

    Trans. of IEICE   J71-D ( 8 )  1988.08  [Refereed]

  • Parallel processing of continuous systems simulation on OSCAR(Optimally Scheduled Advanced Multiprocessor)

    H. Kasahara

    Symposium of SICE'88   14  1988.08  [Refereed]

  • Perspective on Advanced Parallel Processing System for Robotics

    H. Kasahara, S. Narita

    Journal of the Robotics Society of Japan   6 ( 4 )  1988.08  [Refereed]

  • 階層型挟み打ち探索によるPROLOG OR並列処理手法

    甲斐宗徳, 小林和男, 笠原博徳

    情報処理学会論文誌   29 ( 7 )  1988.07  [Refereed]

  • An OR Parallel Processing Scheme of PROLOG Using Hierarchical Pincers Attack Search

    M. Kai, K. Kobayashi, H. Kasahara

    Trans. of IPSJ   29 ( 7 )  1988.07  [Refereed]

  • Parallel Processing for The Solution of Sparse Linear Equations on OSCAR(Optimally SCheduled Advanced MultiprocessoR

    H. Kasahara, H. Nakayama, E. Takane, S. Hashimoto

    SIG Notes of IPSJ   88 ( 19(CA-70) )  1988.06  [Refereed]

  • A parallel processing scheme of Fortran programs on OSCAR's processor cluster

    H. Honda, S. Mizuno, M. Hirota, H. Kasahara

    Technical Report of IEICE   88 ( 155 )  1988.04

  • OSCAR単一プロセッサ・クラスタ上でのFortranの並列処理手法

    本多弘樹, 水野聡, 広田雅一, 笠原博徳

    電子情報通信学会技術研究報告   88 ( 155 )  1988.04  [Refereed]

  • A parallel processing scheme of Fortran programs on OSCAR's processor cluster

    H. Honda, S. Mizuno, M. Hirota, H. Kasahara

    Technical Report of IEICE   88 ( 155 )  1988.04  [Refereed]

  • OSCAR上での非線形方程式求解の並列処理手法-電力潮流計算として-

    中野恵一, 中山晴之, 高根栄二, 引池正則, 笠原博徳, 成田誠之助

    情報処理学会第36回全国大会講演論文集集   ( 1 ) 175 - 176  1988.03  [Refereed]

  • 階層型マルチプロセッサシステムOSCAR上でのFortran 並列処理手法

    笠原博徳, 本多弘樹

    情報処理学会第36回全国大会講演論文集   ( 1 ) 743 - 744  1988.03  [Refereed]

  • データ転送を考慮したヒューリスティック・マルチプロセッサ・スケジューリング・アルゴリズム

    田中久充, 笠原博徳

    情報処理学会第36回全国大会講演論文集   ( 1 ) 179 - 180  1988.03  [Refereed]

  • スタティック・マルチプロセッサ・スケジューリング・アルゴリズムを用いたインプリシットな常微分方程式の並列処理手法

    中山晴之, 奥田恒久, 笠原博徳

    情報処理学会第36回全国大会講演論文集   ( 1 ) 177 - 178  1988.03  [Refereed]

  • Prolog OR並列処理手法「階層型挟み打ち探索法」の性能評価

    甲斐宗徳, 小林和男, 笠原博徳

    情報処理学会第36回全国大会講演論文集   ( 1 ) 805 - 806  1988.03  [Refereed]

  • OSCAR上でのスパース線形方程式求解の並列処理

    中山晴之, 高根栄二, 笠原博徳, 成田誠之助, 富沢敬一

    情報処理学会第36回全国大会講演論文集   ( 1 ) 171 - 172  1988.03  [Refereed]

  • OSCAR上でのエクスプリシット常微分方程式求解の並列処理

    高根栄二, 橋本親, 大東尚司, 笠原博徳, 成田誠之助

    情報処理学会第36回全国大会講演論文集   ( 1 ) 173 - 174  1988.03  [Refereed]

  • OSCAR上でのFortran DOループの並列処理手法

    広田雅一, 本多弘樹, 笠原博徳

    情報処理学会第36回全国大会講演論文集   ( 1 ) 751 - 752  1988.03  [Refereed]

  • OSCARプロセッサ・クラスタ内でのFortranの並列処理

    水野聡, 本多弘樹, 吉田昌弘, 笠原博徳, 成田誠之助

    情報処理学会第36回全国大会講演論文集   ( 1 ) 749 - 750  1988.03  [Refereed]

  • Fortranマクロタスクグラフのダイナミックマルチプロセッサスケジューリング手法

    岩田雅彦, 笠原博徳

    情報処理学会第36回全国大会講演論文集   ( 1 ) 747 - 748  1988.03  [Refereed]

  • Fortran マクロフローグラフからの並列性抽出手法

    本多弘樹, 岩田雅彦, 笠原博徳

    情報処理学会第36回全国大会講演論文集   ( 1 ) 745 - 746  1988.03  [Refereed]

  • Performance Evaluation of Hierarchical Pincers Attack Search for Parallel Processing of PROLOG

    M. Kai, K. Kobayashi, H. Kasahara

    Proc. 36th Annual Convention IPSJ   ( 1 ) 805 - 806  1988.03  [Refereed]

  • Parallel Processing of the Solution of Explicit Ordinary Differential Equations on OSCAR

    E. Takane, S. Hashimoto, N. Ohigashi, H. Kasahara, S. Narita

    Proc. 36th Annual Convention IPSJ   ( 1 ) 173 - 174  1988.03  [Refereed]

  • Parallel Processing of The Solution of Sparse Linear Equations on OSCAR

    H. Nakayama, E. Takane, H. Kasahara, S. Narita, K. Tomizawa

    Proc. 36th Annual Convention IPSJ   ( 1 ) 171 - 172  1988.03  [Refereed]

  • Parallel Processing of Fortran Programs on OSCAR's Processor Cluster

    S. Mizuno, H. Honda, M. Yoshida, H. Kasahara, S. Narita

    Proc. 36th Annual Convention IPSJ   ( 1 ) 749 - 750  1988.03  [Refereed]

  • Heuristic Multiprocessor Scheduling Algorithms Considering Inter-Processor Data Transfer

    H. Tanaka, H. Kasahara

    Proc. 36th Annual Convention IPSJ   ( 1 ) 179 - 180  1988.03  [Refereed]

  • A Scheme for Extracting Parallelism from Fortran Macro Flow Graph

    H. Honda, M. Iwata, H. Kasahara

    Proc. 36th Annual Convention IPSJ   ( 1 ) 745 - 746  1988.03  [Refereed]

  • A Parallel Processing Scheme of Fortran Program on OSCAR

    H. Kasahara, H. Honda

    Proc. 36th Annual Convention IPSJ   ( 1 ) 743 - 744  1988.03  [Refereed]

  • A Parallel Processing Scheme of Fortran DO Loop on OSCAR

    M. Hirota, H. Honda, H. Kasahara

    Proc. 36th Annual Convention IPSJ   ( 1 ) 751 - 752  1988.03  [Refereed]

  • A Parallel Processing Scheme for the Solution of Non-linear Equations on OSCAR

    K. Nakano, H. Nakayama, E. Takane, M. Hikichi, H. Kasahara, S. Narita

    Proc. 36th Annual Convention IPSJ   ( 1 ) 175 - 176  1988.03  [Refereed]

  • A Parallel Processing Scheme for the Solution of Implicit Ordinary Differential Equations Using Static Multiprocessor Scheduling Algorithm

    H. Nakayama, T. Okuda, H. Kasahara

    Proc. 36th Annual Convention IPSJ   ( 1 ) 177 - 178  1988.03  [Refereed]

  • A Dynamic Multiprocessor Scheduling Scheme for Fortran Macro Task Graph

    M. Iwata, H. Kasahara

    Proc. 36th Annual Convention IPSJ   ( 1 ) 747 - 748  1988.03  [Refereed]

  • マルチプロセッサ・システムの研究動向

    笠原博徳

    電気学会論文誌C分冊   108-C ( 2 )  1988.02  [Refereed]

  • 汎用マルチプロセッサシステムOSCARのアーキテクチャ

    笠原博徳, 本多弘樹, 成田誠之助, 橋本親

    情報処理学会コンピュータシンポジウム論文集   88 ( 3 )  1988.02  [Refereed]

  • Research Prospect of Multiprocessor Systems

    H. Kasahara

    Trans. of IEE Japan   108-C ( 2 )  1988.02  [Refereed]

  • Parallel Processing for The Solution of Sparse Linear Equations on OSCAR(Optimally SCheduled Advanced MultiprocessoR

    H. Kasahara, H. Nakayama, E. Takane, S. Hashimoto

    SIG Notes of IPSJ   88 ( 19(CA-70) ) 1 - 8  1988

    CiNii

  • 汎用目的マルチプロセッサ・システムOSCAR上でのスパース線形方程式求解の並列処理

    笠原博徳, 中山晴之, 高根栄二, 橋本親

    情報処理学会研究報告   88 ( 19(CA-70) )  1988  [Refereed]

  • Application of df/ihs to minimum total weighted flow time multiprocessor scheduling problems

    Hironori Kasahara, Munenori Kai, Seinosuke Narita, Hidehiko Wada

    Systems and Computers in Japan   19 ( 6 ) 25 - 34  1988  [Refereed]

    　View Summary

    In most cases, the scheduling problem for the multiprocessor system is NP‐ or strong NP‐hard. For this problem, we have already proposed a practical optimization algorithm DF/IHS (Depth First/Implicit Heuristic Search), which combines the list‐scheduling algorithm and the depth‐first search, for the minimum parallel processing time multiprocessors scheduling problem. This paper presents a result of application of DF/IHS to the minimum total weighted flow time problem, which is used in the optimization of memory utilization. The problem of allocating tasks to m processors is considered with or without precedence constraints among the tasks. It was verified that the DF/IHS can be applied to this kind of problem very effectively, where the optimal or highly accurate approximate solution is obtained for the large‐scale problem with several hundreds of tasks. Copyright © 1988 Wiley Periodicals, Inc., A Wiley Company

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  • PARALLEL PROCESSING OF THE SOLUTION OF ORDINARY DIFFERENTIAL EQUATIONS ON GENERAL PURPOSE MULTIPROCESSOR SYSTEM OSCAR

    H. Kasahara, E. Takane, S. Narita, K. Tomizawa, N. Ohigashi

    Technical Report of IEICE   87 ( 349 )  1988.01

  • AN OR PARALLEL PROCESSING SCHEME OF PROLOG - HIERARCHICAL PINCERS ATTACK SEARCH -

    M. Kai, K. Kobayashi, H. Kasahara

    SIG Notes of IPSJ   88 ( 4(CA-69/MC-48) )  1988.01

  • マルチプロセッサスケジューリング問題に対する分枝限定法の適用

    笠原博徳

    日本オペレーションリサーチ学会誌   33 ( 1 )  1988.01  [Refereed]

  • 汎用目的マルチプロセッサ・システムOSCAR上での常微分方程式求解の並列処理

    笠原博徳, 高根栄二, 成田誠之助, 富沢敬一, 大東尚司

    電子情報通信学会技術研究報告   87 ( 349 )  1988.01  [Refereed]

  • Prolog OR並列処理手法-階層型挟み打ち探索法-

    甲斐宗徳, 小林和男, 笠原博徳

    情報処理学会研究報告   88 ( 4(CA-69/MC-48) )  1988.01  [Refereed]

  • PARALLEL PROCESSING OF THE SOLUTION OF ORDINARY DIFFERENTIAL EQUATIONS ON GENERAL PURPOSE MULTIPROCESSOR SYSTEM OSCAR

    H. Kasahara, E. Takane, S. Narita, K. Tomizawa, N. Ohigashi

    Technical Report of IEICE   87 ( 349 )  1988.01  [Refereed]

  • AN OR PARALLEL PROCESSING SCHEME OF PROLOG - HIERARCHICAL PINCERS ATTACK SEARCH -

    M. Kai, K. Kobayashi, H. Kasahara

    SIG Notes of IPSJ   88 ( 4(CA-69/MC-48) )  1988.01  [Refereed]

  • Application of Branch and Bound Method to a Multiprocessor Scheduling Problem

    H. Kasahara

    Communications of the Operations Research Society of Japan   33 ( 1 )  1988.01  [Refereed]

  • Application of df/ihs to minimum total weighted flow time multiprocessor scheduling problems

    Hironori Kasahara, Munenori Kai, Seinosuke Narita, Hidehiko Wada

    Systems and Computers in Japan   19 ( 6 ) 25 - 34  1988  [Refereed]

    　View Summary

    In most cases, the scheduling problem for the multiprocessor system is NP‐ or strong NP‐hard. For this problem, we have already proposed a practical optimization algorithm DF/IHS (Depth First/Implicit Heuristic Search), which combines the list‐scheduling algorithm and the depth‐first search, for the minimum parallel processing time multiprocessors scheduling problem. This paper presents a result of application of DF/IHS to the minimum total weighted flow time problem, which is used in the optimization of memory utilization. The problem of allocating tasks to m processors is considered with or without precedence constraints among the tasks. It was verified that the DF/IHS can be applied to this kind of problem very effectively, where the optimal or highly accurate approximate solution is obtained for the large‐scale problem with several hundreds of tasks. Copyright © 1988 Wiley Periodicals, Inc., A Wiley Company

    DOI

    Scopus

    1
    Citation
    (Scopus)

  • Parallel Processing of Robot Dynamics Simulation Using Optimal Multiprocessor Scheduling Algorithms

    Hironori Kasahara, Masahiko Iwata, Seinosuke Narita, Hirofumi Fujii

    Systems and Computers in Japan   19 ( 10 ) 45 - 54  1988  [Refereed]

    　View Summary

    This paper discusses the parallel processing of real‐time robot dynamics simulation. Real‐time robot dynamics simulation is an indispensable technique for a robot with a high‐level function. It is a computation procedure to determine the robot motion (joint position, speed, acceleration, etc.) for the given torque and driving force at each joint. In the proposed scheme, the optimal multiprocessor scheduling algorithms developed in this paper are employed, and the dynamics of the robot arm with arbitrary shape can be simulated with the minimum processing time on a multiprocessor system composed of an arbitrary number of parallel processors. The effectiveness and the practical usefulness of the proposed parallel processing scheme ire demonstrated on the robot motion simulator using a prototype multiprocessor system. This is the first report of the robot dynamics simulation being realized efficiently by the parallel processing on the real‐time multiprocessor system. Thus it is verified that the multiprocessor robot dynamics simulator with an excellent cost‐performance ratio can be realized. Copyright © 1988 Wiley Periodicals, Inc., A Wiley Company

    DOI

    Scopus

  • A Parallel Processing Scheme for the Calculation of Load Flow Using Scheduling Algorithms

    H. Kasahara, K. Nakano, H. Nakayama, E. Takane, S. Narita

    Technical Report of IEE Japan   IP-87 ( 1-12 ) 111 - 120  1987.11

  • スケジューリング・アルゴリズムを用いた電力潮流計算の並列処理手法

    笠原 博徳, 中野 恵一, 中山 晴之, 高根 栄二, 成田 誠之助

    電気学会情報処理研究会資料   IP-87 ( 1-12 ) 111 - 120  1987.11  [Refereed]

  • A Parallel Processing Scheme for the Calculation of Load Flow Using Scheduling Algorithms

    H. Kasahara, K. Nakano, H. Nakayama, E. Takane, S. Narita

    Technical Report of IEE Japan   IP-87 ( 1月12日 ) 111 - 120  1987.11  [Refereed]

  • スタティック・マルチプロセッサ・スケジューリング・アルゴリズムを用いた常微分方程式求解の並列処理

    笠原 博徳, 藤井 稔久, 本多 弘樹, 成田 誠之助

    情報処理学会論文誌   28 ( 10 ) 1060 - 1070  1987.10  [Refereed]

  • Parallel Processing of Solution of Ordinary Differential Equations Using Static Multiprocessor Scheduling Algorithms

    H. Kasahara, T. Fujii, H. Honda, S. Narita

    Trans. of IPSJ   28 ( 10 ) 1060 - 1070  1987.10  [Refereed]

  • 最適マルチプロセッサスケジューリングアルゴリズムを用いたロボットダイナミックスシミュレーションの並列処理

    笠原 博徳, 藤井 博文, 岩田 雅彦, 成田 誠之助

    電子情報通信学会論文誌   J70-D ( 9 ) 1783 - 1790  1987.09  [Refereed]

  • OSCAR上での常微分方程式求解並列処理の性能予測

    笠原 博徳, 高根 栄二, 本多 弘樹, 成田 誠之助, 富沢 敬一

    情報処理学会第35回全国大会講演論文集   ( 1 ) 101 - 102  1987.09  [Refereed]

  • OSCAR上でのPROLOG並列処理手法

    甲斐 宗徳, 笠原 博徳

    情報処理学会第35回全国大会講演論文集   ( 1 ) 1595 - 1596  1987.09  [Refereed]

  • Parallel Processing of Robot Dynamics Simulation Using Optimal Multiprocessor Scheduling Algorithms

    H. Kasahara, H. Fujii, M. Iwata, S. Narita

    Trans. of IEICE D   J70-D ( 9 ) 1783 - 1790  1987.09  [Refereed]

  • Performance Estimation of Parallel Processing of the Solution of Ordinary Differential Equations on OSCAR

    H. Kasahara, E. Takane, H. Honda, S. Narita, K. Tomizawa

    Proc. 35th Annual Convention IPSJ   ( 1 ) 101 - 102  1987.09  [Refereed]

  • Parallel Processing Scheme of PROLOG on OSCAR

    M. Kai, H. Kasahara

    Proc. 35th Annual Convention IPSJ   ( 1 ) 1595 - 1596  1987.09  [Refereed]

  • 並列処理技術

    笠原 博徳, 成田 誠之助

    コンピュートロール(コロナ社)   19   6 - 13  1987.07  [Refereed]

  • ロボット制御における並列処理

    笠原博徳

    コンピュートロール(コロナ社)   19   97 - 103  1987.07  [Refereed]

    CiNii

  • Parallel Processing of Robot Motion Simulation

    H. Kasahara, H. Fujii, M. Iwata

    Proc. IFAC 10th World Congress     329 - 336  1987.07  [Refereed]

  • Multiprocessor Scheduling Algorithms and Parallel Processing

    H. Kasahara

    Erlangen-Nurnberg University, Hosted by Prof. Wolfgang Handler    1987.07  [Refereed]

  • Parallel Processing of Robot Control

    H. Kasahara

    Computrol (CORONA PUBLISHING CO., LTD.)   19   97 - 103  1987.07  [Refereed]

  • Parallel Processing Technology

    H. Kasahara, S. Narita

    Computrol (CORONA PUBLISHING CO., LTD.)   19   6 - 13  1987.07  [Refereed]

  • トータル加重フロー時間最小マルチプロセッサスケジューリング問題に対するDF/IHSの応用

    笠原 博徳, 和田 英彦, 甲斐 宗徳, 成田 誠之助

    電子情報通信学会論文誌   J70-D ( 6 ) 1083 - 1091  1987.06  [Refereed]

  • An Application of DF/IHS to Minimum Total Weighted Flow Time Multiprocessor Scheduling Problem

    H. Kasahara, H. Wada, M. Kai, S. Narita

    Trans. of IEICE D   J70-D ( 6 ) 1083 - 1091  1987.06  [Refereed]

  • オプティカル・フロー計算およびカメラの運動パラメータ決定のための並列処理手法

    伊東 俊哉, 中野 恵一, 笠原 博徳, 成田 誠之助

    早稲田大学情報科学研究教育センタ紀要   BCIW'87-A-5   47 - 59  1987.05  [Refereed]

  • A Parallel Processing Scheme for the Solution of Sparse Linear Equations Using Static Optimal Multiprocessor Scheduling Algorithms

    H. Kasahara, T. Fujii, H. Nakayama, S. Narita, Leon O.Chua

    Proc. 2nd Int. Conf. on Supercomputing    1987.05  [Refereed]

  • A parallel Processing Scheme for the Calculation of Optical Flow and the Determination of Camera Motion Parameters

    T. Ito, K. Nakano, H. Kasahara, S. Narita

    Bulletin of the Center for Informatics, Waseda University   BCIW'87-A-5   47 - 59  1987.05  [Refereed]

  • 並列深さ優先インプリシットヒューリスティック探索法

    伊藤 敦, 笠原 博徳

    電子情報通信学会創立70周年記念総合全国大会講演論文集   6   105  1987.03  [Refereed]

  • オプティカル・フロー計算およびカメラの運動パラメータ決定のための並列処理手法

    伊東 俊哉, 中野 恵一, 笠原 博徳, 成田 誠之助

    電子情報通信学会創立70周年記念総合全国大会講演論文集   6   226  1987.03  [Refereed]

  • OSCAR上でのスパース・リニア方程式求解並列処理の性能予測

    笠原 博徳, 高根 栄二, 中山 晴之, 成田 誠之助

    電子情報通信学会創立70周年記念総合全国大会講演論文集   7   24  1987.03  [Refereed]

  • 汎用目的マルチプロセッサ・システムOSCAR(Optimally Scheduled Advanced Multiprocessor)

    笠原 博徳, 成田 誠之助, 吉田 昌弘, 富沢 敬一

    情報処理学会第34回全国大会講演論文集   ( 1 ) 267 - 268  1987.03  [Refereed]

  • 最適化マルチプロセッサスケジューリングアルゴリズムの並列処理手法

    伊藤 敦, 笠原 博徳

    情報処理学会第34回全国大会講演論文集   ( 1 ) 275 - 276  1987.03  [Refereed]

  • 最適マルチプロセッサ・スケジューリングアルゴリズムを利用したFortran並列化コンパイラ

    本多 弘樹, 水野 聡, 笠原 博徳, 成田 誠之助

    情報処理学会第34回全国大会講演論文集   ( 1 ) 277 - 278  1987.03  [Refereed]

  • マルチプロセッサ・スケジューリング・アルゴリズムを用いたMENDELの並列処理手法

    甲斐 宗徳, 笠原 博徳, 成田 誠之助, 本位田 真一, 内平 直志, 田村 信介

    情報処理学会第34回全国大会講演論文集   ( 1 ) 285 - 286  1987.03  [Refereed]

  • スタティック・マルチプロセッサ・スケジューリング・アルゴリズムを用いた線形方程式の並列処理の手法

    笠原 博徳, 藤井 稔久, 中山 晴之, 成田 誠之助

    情報処理学会第34回全国大会講演論文集   ( 1 ) 283 - 284  1987.03  [Refereed]

  • スタティック・マルチプロセッサ・スケジューリング・アルゴリズムを用いた常微分方程式求解の並列処理手法 -スカラアサイメント文の並列処理-

    笠原 博徳, 藤井 稔久, 中山 晴之, 本多 弘樹, 成田 誠之助

    情報処理学会第34回全国大会講演論文集   ( 1 ) 279 - 280  1987.03  [Refereed]

  • スタティック・マルチプロセッサ・スケジューリング・アルゴリズムを用いたロボット・シミュレーションの並列処理 -小マトリクス・ベクトル演算の並列処理-

    笠原 博徳, 岩田 雅彦, 藤井 博文, 成田 誠之助

    情報処理学会第34回全国大会講演論文集   ( 1 ) 281 - 282  1987.03  [Refereed]

  • スタティック・マルチプロセッサ・スケジューリング・アルゴリズムの強度とダイナミック・スケジューリング アルゴリズムへの拡張

    甲斐 宗徳, 岩田 雅彦, 伊藤 敦, 笠原 博徳

    情報処理学会第34回全国大会講演論文集   ( 1 ) 273 - 274  1987.03  [Refereed]

    CiNii

  • OSCARにおける複数バス制御方式

    大東 尚司, 引地 正則, 橋本 親, 笠原 博徳, 成田 誠之助

    情報処理学会第34回全国大会講演論文集   ( 1 ) 271 - 272  1987.03  [Refereed]

  • OSCARにおけるプロセッサエレメントのハードウエア構成

    橋本 親, 引地 正則, 富沢 敬一, 笠原 博徳, 成田 誠之助

    情報処理学会第34回全国大会講演論文集   ( 1 ) 269 - 270  1987.03  [Refereed]

  • Parallelized Optimal Multiprocessor Scheduling Algorithms

    A. Ito, H. Kasahara

    Technical Committee on Computation of IEICE    1987.03  [Refereed]

  • Robustness of Static Multiprocessor Scheduling Algorithm and Its Extension to Dynamic Scheduling

    M. Kai, M. Iwata, A. Ito, H. Kasahara

    Proc. 34th Annual Convention IPSJ   ( 1 ) 273 - 274  1987.03  [Refereed]

  • Parallel Processing of Robot Motion Simulation Using Static Scheduling Algorithms - Parallel Processing of Small-matrix/vector Operations -

    H. Kasahara, T. Iwata, H. Fujii, S. Narita

    Proc. 34th Annual Convention IPSJ   ( 1 ) 281 - 282  1987.03  [Refereed]

  • Parallel Processing of Optimal Multiprocessor Scheduling Algorithm

    A. Ito, H. Kasahara

    Proc. 34th Annual Convention IPSJ   ( 1 ) 275 - 276  1987.03  [Refereed]

  • OSCAR (Optimally Scheduled Advanced Multiprocessor)

    H. Kasahara, S. Narita, M. Yoshida, K. Tomizawa

    Proc. 34th Annual Convention IPSJ   ( 1 ) 267 - 268  1987.03  [Refereed]

  • Multiple bus control method of OSCAR

    N. Ohigashi, M. Hikichi, S. Hashimoto, H. Kasahara, S. Narita

    Proc. 34th Annual Convention IPSJ   ( 1 ) 271 - 272  1987.03  [Refereed]

  • Methods for Parallel Processing of MENDEL with Multiprocessor Scheduling Algorithms

    M. Kai, H. Kasahara, S. Narita, S. Honiden, N. Uchihira, S. Tamura

    Proc. 34th Annual Convention IPSJ   ( 1 ) 285 - 286  1987.03  [Refereed]

  • Hardware Architecture of Processor Element on OSCAR

    S. Hashimoto, M. Hikichi, K. Tomizawa, H. Kasahara, S. Narita

    Proc. 34th Annual Convention IPSJ   ( 1 ) 269 - 270  1987.03  [Refereed]

  • Fortran Parallelizer Using Optimal Multiprocessor Scheduling Algorithms

    H. Honda, S. Mizuno, H. Kasahara, S. Narita

    Proc. 34th Annual Convention IPSJ   ( 1 ) 277 - 278  1987.03  [Refereed]

  • A Parallel Processing Scheme for The Solution of Sparse Linear Equations Using Static Multiprocessor Scheduling Algorithm

    H. Kasahara, T. Fujii, H. Nakayama, S. Narita

    Proc. 34th Annual Convention IPSJ   ( 1 ) 283 - 284  1987.03  [Refereed]

  • A Parallel Processing Scheme for The Solution of Ordinary Differential Equations Using Static Multiprocessor Algorithms - Parallel Processing of Scalar Assignments -

    H. Kasahara, T. Fujii, H. Nakayama, H. Honda, S. Narita

    Proc. 34th Annual Convention IPSJ   ( 1 ) 279 - 280  1987.03  [Refereed]

  • A PARALLEL PROCESSING SCHEME FOR THE CALCULATION OF OPTICAL FLOW AND THE DETERMINATION OF MOTION PARAMETERS

    T. Ito, K. Nakano, H. Kasahara, S. Narita

    NATIONAL CONVENTION RECORD,1987 THE INSTITUTE OF ELECTRONICS,INFORMATION AND COMMUNICATION ENGINEERS   ( 6 ) 226  1987.03  [Refereed]

  • Parallelized Depth First Implicit Heuristic Search

    Ito, H. Kasahara

    NATIONAL CONVENTION RECORD,1987 THE INSTITUTE OF ELECTRONICS,INFORMATION AND COMMUNICATION ENGINEERS   ( 6 ) 105  1987.03  [Refereed]

  • Performance Estimation of Parallel Processing of Sparse Linear Equations on OSCAR

    H. Kasahara, E. Takane, H. Nakayama, S. Narita

    NATIONAL CONVENTION RECORD, 1987 THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS   ( 7 ) 24  1987.03  [Refereed]

  • Parallel Processing of MENDEL Using Multiprocessor Scheduling Algorithms

    M. Kai, H. Kasahara, S. Narita, S. Honiden, S. Tamura

    Trans. of IEEE Japan C, Vol.107-C, No.2   107-C ( 2 )  1987.02  [Refereed]

  • Parallel Processing of Ordinary Differential Equations

    H. Kasahara, T. Fujii, H. Honda, S. Narita

    SIG Notes of IPSJ   1987 ( 7 ) 1 - 8  1987.01

    CiNii

  • 常微分方程式求解の並列処理

    笠原 博徳, 藤井 稔久, 本多 弘樹, 成田 誠之助

    情報処理学会研究報告ARC-64-1    1987.01  [Refereed]

  • Parallel Processing of Ordinary Differential Equations

    H. Kasahara, T. Fujii, H. Honda, S. Narita

    SIG Notes of IPSJ    1987.01  [Refereed]

  • マルチプロセッサ・リアルタイム制御システムにおけるタスクスケジューリング手法

    甲斐 宗徳, 笠原 博徳, 成田 誠之助, 宇梶 仁志

    電気学会論文誌C分冊   106-C ( 12 )  1986.12  [Refereed]

  • Real-time simulation of robot motion dynamics on a multiprocessor system

    H. Kasahara, H. Fujii, M. Iwata, H. Honda, S. Narita

    Proceedings of the Seventh IFAC Workshop on Distributed Computer Control Systems 1986    1986.10  [Refereed]

  • A Multiprocessor Robot Motion Simulator

    H. Kasahara, H. Fujii, M. Iwata, H. Honda, S. Narita

    Proc. JSST International Conference    1986.07  [Refereed]

  • Parallel Processing of Prolog Based Concurrent Object Oriented Language Using Multiprocessor Scheduling Algorithms

    M. Kai, H. Kasahara, S. Narita, S. Honiden, N. Utihira, S. Tamura

    Technical Report of IECE   86 ( 10 )  1986.04

  • マルチプロセッサ・スケジューリング・アルゴリズムを用いた論理型オブジェクト指向言語の並列処理手法

    甲斐 宗徳, 笠原 博徳, 成田 誠之助, 本位田 真一, 内平 直志, 田村 信介

    電子通信学会技術研究報告   86 ( 10 )  1986.04  [Refereed]

  • Parallel Processing of Prolog Based Concurrent Object Oriented Language Using Multiprocessor Scheduling Algorithms

    M. Kai, H. Kasahara, S. Narita, S. Honiden, N. Utihira, S. Tamura

    Technical Report of IECE   86 ( 10 )  1986.04  [Refereed]

  • 加重フロー時間最小マルチプロセッサ・スケジューリング問題に対するDF/IHSの応用

    和田 英彦, 甲斐 宗徳, 笠原 博徳, 成田 誠之助

    電子通信学会技術研究報告   85 ( 320 )  1986.03  [Refereed]

  • Parallel Processing of Robot Dynamics Computation Using Multiprocessor Scheduling Algorithms

    H. Fujii, T. Yasui, K. Koumura, H. Kasahara, S. Narita

    Technical Report of IECE   85 ( 311 )  1986.03

  • 平均加重滞留時間最小マルチプロセッサ・スケジューリング問題に対するDF/HISの応用

    和田 英彦, 三宅 貴, 甲斐 宗徳, 笠原 博徳, 成田 誠之助

    電子通信学会総合全国大会    1986.03  [Refereed]

  • 二次元情報を利用した物体認識手法

    宮下 七郎, 長谷川 博昭, 伊東 俊哉, 笠原 博徳, 成田 誠之助

    電子通信学会総合全国大会    1986.03  [Refereed]

  • スケジューリング・アルゴリズムを用いたロボット・ダイナミクス計算の並列処理

    藤井 博文, 岩田 雅彦, 水野 正敏, 笠原 博徳, 成田 誠之助

    電子通信学会総合全国大会    1986.03  [Refereed]

  • 加重フロー時間最小マルチプロセッサ・スケジューリング問題に対するDF/IHSの応用

    和田 英彦, 甲斐 宗徳, 笠原 博徳, 成田 誠之助

    電子通信学会技術研究報告   85 ( 320 )  1986.03  [Refereed]

  • マルチプロセッサ・スケジューリング・アルゴリズムを用いたロボット・ダイナミクス計算の並列処理

    藤井 博文, 安井 卓也, 幸村 和久, 笠原 博徳, 成田 誠之助

    電子通信学会技術研究報告   85 ( 311 )  1986.03  [Refereed]

  • 並列化最適マルチプロセッサスケジューリングアルゴリズム

    伊藤 敦, 笠原 博徳

    電子情報通信学会コンピューテーション研究会 COMP86-89    1986.03  [Refereed]

  • Parallel Processing of Robot Dynamics Computation Using Multiprocessor Scheduling Algorithms

    H. Fujii, T. Yasui, K. Koumura, H. Kasahara, S. Narita

    Technical Report of IECE   85 ( 311 )  1986.03  [Refereed]

  • An Application of DF/IHS to Minimizing Weighted Flow Time Multiprocessor Scheduling Problem

    H. Wada, M. Kai, H. Kasahara, S. Narita

    Technical Report of IECE   85 ( 320 )  1986.03

  • Parallel Processing of Robot Dynamics Computation Using Scheduling Algorithms

    H. Fujii, M. Iwata, M. Mizuno, H. Kasahara, S. Narita

    Proc. 1985 Spring Annual Convention of IEICE    1986.03  [Refereed]

  • An Application of DF/IHS to Minimum Average Weighted Residence Time Multiprocessor Scheduling Problem

    H. Wada, T. Miyake, M. Kai, H. Kasahara, S. Narita

    Proc. 1985 Spring Annual Convention of IEICE    1986.03  [Refereed]

  • Object Recognition methods Using Two-dimensional Information

    S. Miyashita, H. Hasegawa, T. Itoh, H. Kasahara, S. Narita

    Proc. 1985 Spring Annual Convention IEICE    1986.03  [Refereed]

  • 並列化最適マルチプロセッサスケジューリングアルゴリズム

    伊藤 敦, 笠原 博徳

    電子情報通信学会コンピューテーション研究会 COMP86-89    1986.03  [Refereed]

  • Task Scheduling Algorithms for Multiprocessor Realtime Control Systems.

    Munenori Kai, Hironori Kasahara, Seinosuke Narita, Hitoshi Ukaji

    IEEJ Transactions on Electronics, Information and Systems   106 ( 12 ) 257 - 264  1986  [Refereed]

    DOI

    Scopus

  • An Approach to Supercomputing Using Multiprocessor Scheduling Algorithms

    H. Kasahara, S. Narita

    Proc. of IEEE 1st International Conf. on Supercomputing    1985.12  [Refereed]

  • Multiprocessor Scheduling Algorithms and Their application to Supercomputing

    H. Kasahara

    CSRD, University of Illinois at Urbana-Champaign, Hosted by Professor David Kuck    1985.12  [Refereed]

  • Parallel Processing for Simulation of Dynamical Systems

    H. Kasahara, H. Honda, M. Kai, T. Seki, S. Narita

    Proc. of IFAC 7th Conf. on Digital Computer Application to Process Control System    1985.09  [Refereed]

  • スケジューリング・アルゴリズムを用いたマルチプロセッサ連続システム・シミュレータ WAMUX

    笠原 博徳, 本多 弘樹, 藤井 稔久, 成田 誠之助, 富沢 敬一

    日本シミュレーション学会、第5回シミュレーション・テクノロジー・コンファレンス    1985.06  [Refereed]

  • Multiprocessor Continuous System Simulator WAMUX Using Scheduling Algorithms

    H. Kasahara, H. Honda, T. Fujii, S. Narita, K. Tomizawa

    The 5th Conference on Simulation Technology, Japan Society for Simulation Technology    1985.06  [Refereed]

  • Load Distribution Among Real time Control Computers: Multiprocessor Control of Tandem Rolling Mills

    M. Kai, H. Wada, H. Kasahara, S. Narita, H. Ukaji

    Proc. of 6th IFAC Workshop on DCCS    1985.05  [Refereed]

  • マルチプロセッサ・システム上で起動周期が変動する タスク集合を処理するためのスケジューリング手法

    甲斐 宗徳, 笠原 博徳, 成田 誠之助, 永井 英夫

    電気学会全国大会    1985.04  [Refereed]

  • A Scheduling Scheme for Processing of Task Set Fluctuating it's Start-up Cycle on Multiprocessor Systems.

    M. Kai, H. Kasahara, S. Narita, H. Nagai

    Proc. Annual Convention of IEE    1985.04  [Refereed]

  • マルチプロセッサ・スケジューリング問題に対するヒューリスティック・アルゴリズムの性能評価

    和田英彦, 笠原博徳, 成田誠之助

    電子通信学会, 1985年総合全国大会    1985.03  [Refereed]

  • ビジュアル・フィードバック機能を持つロボット制御系の並列処理

    関俊文, 藤沢栄蔵, 笠原博徳, 成田誠之助

    電子通信学会, 1985年総合全国大会    1985.03  [Refereed]

  • PARALLEL PROCESSING FOR ROBOT CONTROL WITH VISUAL FEEDBACK

    T. Seki, E. Fujisawa, H. Kasahara, S. Narita

    Proc. 1985 Spring Annual Convention IEICE    1985.03  [Refereed]

  • Performance Evaluation of Heuristic Algorithms for Multiprocessor Scheduling Problem

    H. Kasahara, H. Wada, S. Narita

    Proc. 1985 Spring Annual Convention IEICE    1985.03  [Refereed]

  • マルチプロセッサ・スケジューリング・アルゴリズムを用いたロボット制御・シミュレーションの並列処理

    笠原博徳, 安井卓也, 幸村和久, 甲斐宗徳, 成田誠之助

    電子通信学会、回路とシステム研究会    1985.02  [Refereed]

  • マルチプロセッサ・スケジューリング・アルゴリズムを用いたロボット制御・シミュレーションの並列処理

    笠原博徳, 安井卓也, 幸村和久, 甲斐宗徳, 成田誠之助

    電子通信学会、回路とシステム研究会    1985.02  [Refereed]

  • Parallel Processing of Robot Control and Simulation using Multiprocessor Scheduling Algorithms

    H. Kasahara, T. Yasui, K. Koumura, M. Kai, S. Narita

    Technical Report of IEICE    1985.02

  • Dynamic Task Scheduling for Control of Hot Strip Mill Lines

    M. Kai, A. Ito, H. Wada, H. Kasahara, S. Narita, H. Ukaji

    Bulletin of Centre for Informatics, Waseda University   2, Autumn  1985  [Refereed]

  • Practical multiprocessor scheduling algorithms for efficient parallel processing

    Hironori Kasahara, Seinosuke Narita

    Systems and Computers in Japan   16 ( 2 ) 11 - 19  1985  [Refereed]

    　View Summary

    This paper describes practical optimization/approximation algorithms for scheduling a set of partially ordered computational tasks with different processing times onto a multiprocessor system so that the schedule length is minimized. Since this problem belongs to the class of “strong” NP hard problems, we must eliminate the possibility of constructing not only pseudopolynomial time optimization algorithms, but also fully polynomial time approximation schemes unless P = NP. This paper proposes a heuristic algorithm CP/MISF (Critical Path/Most Immediate Successors First) and an optimization/approximation algorithm DF/IHS (Depth First/ Implicit Heuristic Search). DF/IHS is an excellent scheduling method which can reduce markedly the space complexity and average computation time by combining the branch‐and‐bound method with CP/MISF
    it allows us to solve very large‐scale problems with a few hundred tasks. Copyright © 1985 Wiley Periodicals, Inc., A Wiley Company

    DOI

    Scopus

    3
    Citation
    (Scopus)

  • Parallel Processing of Robot-Arm Control Computation on a Multimicroprocessor System

    Hironori Kasahara, Seinosuke Narita

    IEEE Journal on Robotics and Automation   1 ( 2 ) 104 - 113  1985  [Refereed]

    　View Summary

    A parallel-processing scheme is described for robot-arm control computation on any number of parallel processors. The scheme employs two multiprocessor scheduling algorithms called, respectively, depth first/implicit heuristic search (DF/IHS) and critical path/most immediate successors first (CP/MISF)
    these were recently developed by the authors. The scheme is applied to the parallel processing of dynamic control computation for the Stanford manipulator. In particular, the proposed algorithms are applied to the computation of the Newton-Euler equations of motion for the Stanford manipulator and implemented on a multimicroprocessor system. The test result was so successful that the use of six processor pairs in parallel could attain the processing time of 5.37 ms. It is also shown that the proposed parallel-processing scheme is applicable to an arbitrary number of processors. Copyright © 1985 by The Institute of Electrical and Electronics Engineers, Inc.

    DOI

    Scopus

    106
    Citation
    (Scopus)

  • ロボット・モーション・シミュレーションの並列処理手法

    笠原博徳, 安井卓也, 谷口浩一, 成田誠之助

    日本ロボット学会、学術講演会    1984.11  [Refereed]

  • ロボット・アーム制御計算の並列処理

    笠原博徳, 幸村和久, 谷口浩一, 成田誠之助

    日本ロボット学会、学術講演会    1984.11  [Refereed]

  • マルチプロセッサ・スケジューリング・アルゴリズムとその実システムの応用

    笠原博徳, 甲斐宗徳, 成田誠之助

    第7回情報処理論とその応用研究会    1984.11  [Refereed]

  • MULTI-PROCESSOR SCHEDULING ALGORITHMS AND THEIR PRACTICAL APPLICATIONS

    H. Kasahara, M. Kai, S. Narita

    The 7th Symposium on Information Theory and Its Applications    1984.11  [Refereed]

  • Parallel Processing of Robot Arm Control Computation

    H. Kasahara, H. Koumura, K. Taniguchi, S. Narita

    Proc. Annual Convention of The Robotics Society of Japan    1984.11  [Refereed]

  • A Parallel Processing Scheme for Robot Motion Simulation

    H. Kasahara, T. Yasui, K. Taniguchi, S. Narita

    Proc. Annual Convention of The Robotics Society of Japan    1984.11  [Refereed]

  • マルチプロセッサ・スケジューリング・アルゴリズムを用いたロボット・アーム制御計算の並列処理

    笠原博徳, 幸村和久, 安井卓也, 成田誠之助

    電子通信学会技術研究報告(電子計算機研究会)   84 ( 175 )  1984.10  [Refereed]

  • マルチプロセッサ・スケジューリングアルゴリズムを用いた連続システム・シミュレーションの並列処理

    笠原博徳, 甲斐宗徳, 関俊文, 本多弘樹, 成田誠之助

    電子通信学会技術研究報告(電子計算機研究会)   84 ( 175 )  1984.10  [Refereed]

  • マルチプロセッサ・スケジューリング・アルゴリズムを用いたロボット制御計算の並列処理手法

    笠原博徳, 成田誠之助

    日本ロボット学会誌   2 ( 5 )  1984.10  [Refereed]

  • マルチプロセッサ・スケジューリングアルゴリズムを用いた連続システム・シミュレーションの並列処理

    笠原博徳, 甲斐宗徳, 関俊文, 本多弘樹, 成田誠之助

    電子通信学会技術研究報告(電子計算機研究会)   84 ( 175 )  1984.10  [Refereed]

  • マルチプロセッサ・スケジューリング・アルゴリズムを用いたロボット・アーム制御計算の並列処理

    笠原博徳, 幸村和久, 安井卓也, 成田誠之助

    電子通信学会技術研究報告(電子計算機研究会)   84 ( 175 )  1984.10  [Refereed]

  • ロボット制御計算の並列処理

    笠原博徳, 成田誠之助

    第9回ロボット及び応用システム・シンポジウム    1984.10  [Refereed]

  • PARALLEL PROCESSING OF ROBOT ARM CONTROL COMPUTATION USING MULTI-PROCESSOR SCHEDULING ALGORITHMS

    H. Kasahara, K. Koumura, T. Yasui, S. Narita

    Technical Report of IEICE   84 ( 175 )  1984.10

  • PARALLEL PROCESSING OF CONTINUOUS SYSTEMS SIMULATION USING MULTI-PROCESSOR SCHEDULING ALGORITHMS

    H. Kasahara, M. Kai, T. Seki, H. Honda, S. Narita

    Technical Report of IEICE   84 ( 175 )  1984.10

  • Parallel Processing Scheme for Robot Control Computation Using Multi-Processor Scheduling Algorithm

    H. Kasahara, S. Narita

    Journal of Robotics Society of Japan   2 ( 5 )  1984.10  [Refereed]

  • Parallel processing of robot control calculation

    S. Narita, H. Kasahara

    9th Symposium on Robotics and Applied Systems    1984.10  [Refereed]

  • マルチプロセッサ・スケジューリング問題に対する実用的な最適及び近似アルゴリズム

    笠原博徳, 成田誠之助

    電子通信学会論文誌D   67-D ( 7 )  1984.07  [Refereed]

  • A Practical Optimal / Approximate Algorithm for Multi-Processor Scheduling Problem

    H. Kasahara, S. Narita

    Trans. of IEICE D   67-D ( 7 )  1984.07  [Refereed]

  • Load Distribution among Real-time Control Computers Connected via Communication Media

    H. Kasahara, S. Narita

    Proc. of 9th IFAC World Congress    1984.07  [Refereed]

  • Integrated Simulation System for Design and Evaluation of Distributed Computer Control Systems

    H. Kasahara, S. Narita

    Proc. of 9th IFAC World Congress    1984.07  [Refereed]

  • 並列処理時間最小マルチプロセッサ・スケジューリング・アルゴリズム

    笠原博徳, 有吉一雄, 成田誠之助

    電子通信学会 1984年総合全国大会    1984.03  [Refereed]

  • マイクロプロセッサを用いたローカルエリアネットワーク・テストベッド

    井村和久, 宮下訓, 笠原博徳, 成田誠之助

    電子通信学会 1984年総合全国大会    1984.03  [Refereed]

  • プロセッサ間データ転送を考慮したマルチプロセッサ・スケジューリング・アルゴリズム

    笠原博徳, 有吉一雄, 甲斐宗徳, 成田誠之助

    電子通信学会 1984年総合全国大会    1984.03  [Refereed]

  • スケジューリング理論を用いたロボット制御計算の汎用的並列処理手法

    笠原博徳, 横田友孝, 安井卓也, 成田誠之助

    電子通信学会 1984年総合全国大会    1984.03  [Refereed]

  • マルチプロセッサ・スケジューリング問題に対する最適及び近似アルゴリズム(2) - 最適アルゴリズム

    笠原博徳, 有吉一雄, 成田誠之助

    情報処理学会第28回全国大会講演論文集   ( 1 ) 13 - 14  1984.03  [Refereed]

  • マルチプロセッサ・スケジューリング問題に対する最適及び近似アルゴリズム(1) - ヒューリスティックアルゴリズムとその応用

    笠原博徳, 有吉一雄, 成田誠之助

    情報処理学会第28回全国大会講演論文集   ( 1 ) 11 - 12  1984.03  [Refereed]

  • Optimal / Approximate Algorithm for Multi-Processor Scheduling Problem(2) - Optimal Algorithms

    H. Kasahara, K. Ariyoshi, S. Narita

    Proc. 28th Annual Convention of IPSJ   ( 1 ) 13 - 14  1984.03  [Refereed]

  • Optimal / Approximate Algorithm for Multi-Processor Scheduling Problem(1) - Heuristic Algorithms and Their Applications

    H. Kasahara, K. Ariyoshi, S. Narita

    Proc. 28th Annual Convention of IPSJ   ( 1 ) 11 - 12  1984.03  [Refereed]

  • Multiprocessor Scheduling Algorithm minimizing parallel processing time

    H. Kasahara, K. Ariyoshi, S. Narita

    Proc. 1984 Spring Annual Convention IEICE    1984.03  [Refereed]

  • Multi-Processor Scheduling Algorithm Considering Inter-Processor Data Transfer

    H. Kasahara, K. Ariyoshi, M. Kai, S. Narita

    Proc. 1984 Spring Annual Convention IEICE    1984.03  [Refereed]

  • Local Area Network Testbed Using Microprocessor

    K. Imura, S. Miyashita, H. Kasahara, S. Narita

    Proc. 1984 Spring Annual Convention IEICE    1984.03  [Refereed]

  • General-Purpose Parallel Processing Scheme for Robot Control Computation using Scheduling Theory

    H. Kasahara, T. Yokota, T. Yasui, S. Narita

    Proc. 1984 Spring Annual Convention IEICE    1984.03  [Refereed]

  • PRACTICAL MULTIPROCESSOR SCHEDULING ALGORITHMS FOR EFFICIENT PARALLEL PROCESSING

    H KASAHARA, S NARITA

    IEEE TRANSACTIONS ON COMPUTERS   33 ( 11 ) 1023 - 1029  1984  [Refereed]

  • マルチプロセッサ連続システムシミュレーションのための並列処理手法

    笠原博徳, 成田誠之助

    日本シミュレーション学会誌   2 ( 3 )  1983.11  [Refereed]

  • Parallel Processing Scheme for Multi-processor Continuous System Simulator

    H. Kasahara, S. Narita

    JOURNAL OF THE JAPAN SOCIETY FOR SIMULATION TECHNOLOGY   2 ( 3 )  1983.11  [Refereed]

  • A PRACTICAL OPTIMIZATION / APPROXIMATION ALGORITHM FOR MULTI-PROCESSOR SCHEDULING PROBLEM

    H. Kasahara, S. Narita

    Technical Report of IEICE   83 ( 163 )  1983.10

  • マルチプロセッサ・スケジューリング問題に対する最適及び保証された解精度を持つ近似アルゴリズム

    笠原博徳, 成田誠之助

    電子通信学会技術研究報告(オートマトンと言語研究会)   83 ( 163 )  1983.10  [Refereed]

  • A PRACTICAL OPTIMIZATION / APPROXIMATION ALGORITHM FOR MULTI-PROCESSOR SCHEDULING PROBLEM

    H. Kasahara, S. Narita

    Technical Report of IEICE   83 ( 163 )  1983.10  [Refereed]

  • ディジタル制御系の解析に向くシミュレーション言語DOSP

    犬伏裕之, 笠原博徳, 佐藤博, 成田誠之助

    日本シミュレーション大会, 第3回シミュレーション・テクノロジー・コンファレンス    1983.07  [Refereed]

  • Simulation Language DOSP Appropriate for Analysis for Digital Control

    H. Inubushi, H. Kasahara, H. Sato, S. Narita

    The 3rd Conference on Simulation Technology, Japan Society for Simulation Technology    1983.07  [Refereed]

  • 分散制御システムのアベイラビリティ評価モデル

    若槻 直, 有吉 一雄, 笠原 博徳, 成田 誠之助

    電気学会全国大会    1983.04  [Refereed]

  • 所望の規範モデルを用いたPID調整則とその応用例

    上田 俊一, 犬伏 裕之, 笠原 博徳, 成田 誠之助

    電気学会全国大会    1983.04  [Refereed]

  • 産業用ローカルエリアネットワークの通信制御方式の評価

    中後 明, 井村 和久, 笠原 博徳, 成田 誠之助

    電気学会全国大会    1983.04  [Refereed]

  • マルチプロセッサ・ダイナミクス・シミュレータのための並列処理手法

    笠原博徳, 有吉一雄, 成田誠之助

    電気学会 全国大会    1983.04  [Refereed]

  • PID Tuning Using Desired Reference Model and Their Applications

    S. Ueda, H. Inubushi, H. Kasahara, S. Narita

    Proc. Annual Convention of IEE    1983.04  [Refereed]

  • Evaluation of Communication Control Method on Industrial Local Area Network

    A. Chugo, K. Imura, H. Kasahara, S. Narita

    Proc. Annual Convention of IEE    1983.04  [Refereed]

  • Availability Evaluation Model for Distributed Control System

    N. Wakatsuki, K. Ariyoshi, H. Kasahara, S. Narita

    Proc. Annual Convention of IEE    1983.04  [Refereed]

  • A Processing Scheme for Multiprocessor Dynamics Simulator

    H. Kasahara, K. Ariyoshi, S. Narita

    Proc. Annual Convention IEE    1983.04  [Refereed]

  • 分散制御システムにおける負荷分割、資源割り当て、及びスケジューリング手法

    笠原博徳, 成田誠之助

    電気四学会連合大会    1982.11  [Refereed]

  • Load distribution and resource allocation in distributed control systems

    H. Kasahara, S. Narita

    Unified convention of 4 electrical societies    1982.11  [Refereed]

  • Parallel Processing for Real Time Control and Simulation of Distributed Computer Control Systems

    H. Kasahara, S. Narita

    Proc. of 4th IFAC Workshop on DCCS    1982.05  [Refereed]

  • 分散制御システムの実時間シミュレーションのための並列処理

    笠原博徳, 若槻直, 斉藤浩, 成田誠之助

    電気学会 全国大会    1982.04  [Refereed]

  • マルチマイクロプロセッサを用いたダイナミック・シミュレータ

    斉藤浩, 中後明, 笠原博徳, 成田誠之助

    電気学会 全国大会    1982.04  [Refereed]

  • Parallel Processing for Real Time Simulation of Distributed Control Systems

    H. Kasahara, N. Wakatsuki, H. Saito, S. Narita

    Proc. Annual Convention of IEE    1982.04  [Refereed]

  • Dynamic Simulator Using Multi-microprocessor

    H. Saito, A. Chugo, H. Kasahara, S. Narita

    Proc. Annual Convention of IEE    1982.04  [Refereed]

  • Parallel Processing Algorithm for Real Time Control and Simulation of Distributed Control System

    H. Kasahara, N. Wakatsuki, S. Narita

    Technical Report of IEE SIG on Information Processing    1982.02

  • 分散制御システムの実時間制御・シミュレーションのための並列処理アルゴリズム

    笠原博徳, 若槻直, 成田誠之助

    電気学会情報処理研究会    1982.02  [Refereed]

  • Parallel Processing Algorithm for Real Time Control and Simulation of Distributed Control System

    H. Kasahara, N. Wakatsuki, S. Narita

    Technical Report of IEE SIG on Information Processing    1982.02  [Refereed]

  • モデル規範形サンプル値PIDコントローラとその応用例

    佐藤 博, 新井 弘志, 笠原 博徳, 成田 誠之助

    電気学会東京支部大会    1981.12  [Refereed]

  • Model Reference Sampling Value PID Controller and Their Applications

    H. Sato, H. Arai, H. Kasahara, S. Narita

    Proc. Annual Convention of Tokyo-based Affiliate of IEEE    1981.12  [Refereed]

  • A Parallel Processing Algorithm for Fast Load-Flow and Stability Calculations

    S. Narita, H. Tachiyeda, K. Omata, T. Mimura, H. Kasahara

    Proc. of the Seventh Power Systems Computation Conference    1981.07  [Refereed]

▼display all

Books and Other Publications

  • Technology Predictions

    Rosa M. Badia, Mary Baker, Tom Coughlin, Paolo Faraboschi, Eitan Frachtenberg, Vincent Kaabunga, Hironori Kasahara, Kim Keeton, Danny Lange, Phil Laplante, Andrea Matwyshyn, Avi Mendelson, Cecilia Metra, Dejan Milojicic, Nita Patel, Roberto Saracco, Michelle Tubb, Irene Pazos Viana( Part： Contributor)

    2022.01

  • Parallel Processing Technology

    Hironori Kasahara

    History of Information Process Society of Japan 50years, pp.195-198  2021.10

  • Embedded Multi-core Handbook (Basic)

    Hironori Kasahara( Part： Supervisor (editorial))

    JEITA  2021.09

  • Special Issue on Parallel Processing

    Hironori Kasahara

    IPSJ Journal Vol.42, No.4 pp.651-920  2021.04

  • Embedded Multi-core Handbook (Technology and Application)

    Hironori Kasahara( Part： Supervisor (editorial))

    JEITA  2021.02

  • Guest Editorial: Special Issue on Network and Parallel Computing for Emerging Architectures and Applications

    ( Part： Joint author)

    2019.03

  • NPC: 15th IFIP International Conference Network and Parallel Computing

    Feng Zhang, Jidong Zhai, Marc Snir, Hai Jin, Hironori Kasahara, Mateo Valero( Part： Edit)

    Lecture Notes in Computer Science, Vol.11276 LNCS  2018.11

  • Message from the CAP 2017 Organizing Committee

    Cristina Seceleanu, Hironori Kasahara, Tiberiu Seceleanu

    IEEE COMPSAC 2017 (The 41th IEEE Computer Society International Conference on Computers, Software & Applications)  2017.07

  • IEEE CS 2022 Report

    Hasan Alkhatib, Paolo Faraboschi, Eitan Frachtenberg, Hironori Kasahara, Danny Lange, Phil Laplante, Arif Merchant, Dejan Milojicic, Karsten Schwan

    IEEE Computer Society  2014.09

  • Languages and Compilers for Parallel Computing: 25th International Workshop, LCPC 2012, Tokyo, Japan, September 11-13, 2012, Revised Selected Papers

    Hironori Kasahara, Keiji Kimura( Part： Edit)

    Lecture Notes in Computer Science, Vol.7760  2013

  • Heterogeneous multicore processor technologies for embedded systems

    Kunio Uchiyama, Fumio Arakawa, Hironori Kasahara, Tohru Nojiri, Hideyuki Noda, Yasuhiro Tawara, Akio Idehara, Kenichi Iwata, Hiroaki Shikano( Part： Joint author)

    Springer New York  2012.10

  • Finish Electrical Engineer Examination Class 3

    Yoshitaka Maekawa, Hironori Kasahara

    Ohmsha  1995

  • Handbook of Information Processing

    Hironori Kasahara

    Ohmsha  1995

  • Special Issue on "Research and Development of Multiprocessor Supercomputer PHI"

    S. Suzuki, H. Kasahara

    IPSJ MAGAZINE, Vol.33, No.5  1992.05

  • Parallel Processing Technology

    H. Kasahara

    CORONA PUBLISHING CO., LTD  1991.06

  • Parallel Computation System for Robotics

    H. Kasahara

    World Scientific  1991

  • Microprocessors in Robotic and Manufacturing Systems

    H. Kasahara

    Kluwer Academic Pub.  1991

  • Robot Engineering Hand Book

    H. Kasahara

    Robotics Society of Japan  1990

  • Tutorial:Hard Real-Time Systems

    H. Kasahara

    IEEE Computer Society Press  1988

▼display all

Misc

▼display all

Industrial Property Rights

  • PARALLELISM EXTRACTION METHOD AND METHOD FOR MAKING PROGRAM

    2950211(EP)

    Hironori Kasahara, Keiji Kimura, Akihiro Hayashi, Hiroki Mikami, Yohei Kanehagi, Dan Umeda, Mitsuo Sawada

    Patent

  • PARALLELISM EXTRACTION METHOD AND METHOD FOR MAKING PROGRAM

    2950211(GB)

    Hironori Kasahara, Keiji Kimura, Akihiro Hayashi, Hiroki Mikami, Yohei Kanehagi, Dan Umeda, Mitsuo Sawada

    Patent

  • PARALLELISM EXTRACTION METHOD AND METHOD FOR MAKING PROGRAM

    602014078600.6(DE)

    Hironori Kasahara, Keiji Kimura, Akihiro Hayashi, Hiroki Mikami, Yohei Kanehagi, Dan Umeda, Mitsuo Sawada

    Patent

  • METHOD OF GENERATING CODE EXECUTABLE BY PROCESSOR

    3486767(EP)

    Hironori Kasahara, Keiji Kimura, Mase Masayoshi

    Patent

  • METHOD OF MANAGING A STORAGE AREA OF A MEMORY IN A MULTIPROCESSOR SYSTEM

    3486767(GB)

    Hironori Kasahara, Keiji Kimura, Mase Masayoshi

    Patent

  • METHOD OF MANAGING A STORAGE AREA OF A MEMORY IN A MULTIPROCESSOR SYSTEM

    602010065015.4(DE)

    Hironori Kasahara, Keiji Kimura, Mase Masayoshi

    Patent

  • PARALLEL PROGRAM GENERATING METHOD AND PARALLELIZATION COMPILING APPARATUS

    10698670(US)

    Hironori Kasahara, Keiji Kimura, Dan Umeda, Hiroki Mikami

    Patent

  • MULTIPROCESSOR SYSTEM AND MULTIGRAIN PARALLELIZING COMPILER

    2657839(EP)

    Hironori Kasahara, Keiji Kimura, Jun Shirako, Masaki Ito, Hiroaki Shikano

    Patent

  • MULTIPROCESSOR SYSTEM AND MULTIGRAIN PARALLELIZING COMPILER

    2657839(GB)

    Hironori Kasahara, Keiji Kimura, Jun Shirako, Masaki Ito, Hiroaki Shikano

    Patent

  • MULTIPROCESSOR SYSTEM AND MULTIGRAIN PARALLELIZING COMPILER

    602006059465.8(DE)

    Hironori Kasahara, Keiji Kimura, Jun Shirako, Masaki Ito, Hiroaki Shikano

    Patent

  • PROCESSOR SYSTEM AND ACCELERATOR

    2511672(GB)

    Hironori Kasahara, Keiji Kimura

    Patent

  • PARALLELIZING COMPILER PARALLELIZING COMPILATION APPARATUS, AND METHOD OF CREATING A PARALLEL PROGRAM

    特許6600888

    Hironori Kasahara, Keiji Kimura, Dan Umeda, Hiroki Mikami

    Patent

  • METHOD OF GENERATING CODE EXECUTABLE BY PROCESSOR

    2508992(EP)

    Hironori Kasahara, Keiji Kimura, Mase Masayoshi

    Patent

  • METHOD OF GENERATING CODE EXECUTABLE BY PROCESSOR

    2508992(GB)

    Hironori Kasahara, Keiji Kimura, Mase Masayoshi

    Patent

  • METHOD OF GENERATING CODE EXECUTABLE BY PROCESSOR

    602010059750.4(DE)

    Hironori Kasahara, Keiji Kimura, Mase Masayoshi

    Patent

  • PROCESSOR CORES AND PROCESSOR SYSTEM

    特許6525286

    Hironori Kasahara, Keiji Kimura

    Patent

  • PARALLELIZATION COMPILING METHOD, PARALLELIZATION COMPILER, AND VEHICULAR DEVICE

    10228923(US)

    Yoshihiro Yatoh, Noriyuki Suzuki, Kenichi Mineta, Hironori Kasahara, Keiji Kimura, Hiroki Mkiami, Dan Umeda

    Patent

  • PARALLELIZATION COMPILING METHOD, PARALLELIZATION COMPILER, AND VEHICULAR DEVICE

    特許6427055

    Kenichi Mineta, Noriyuki Suzuki, Hironori Kasahara, Keiji Kimura, Hiroki Mkiami, Dan Umeda

    Patent

  • PARALLELIZATION COMPILING METHOD AND PARALLELIZATION COMPILER

    特許6427054

    Yoshihiro Yatoh, Noriyuki Suzuki, Kenichi Mineta, Hironori Kasahara, Keiji Kimura, Hiroki Mkiami, Dan Umeda

    Patent

  • PARALLELIZATION COMPILING METHOD AND PARALLELIZATION COMPILER

    特許6427053

    Kazushi Nobuta, Noriyuki Suzuki, Hironori Kasahara, Keiji Kimura, Hiroki Mkiami, Dan Umeda

    Patent

  • PROCESSOR, ACCELERATOR, AND DIRECT MEMORY ACCESS CONTROLLER WITHIN A CORE READING/WRITING LOCAL SYNCHRONIZATION FLAG AREA FOR PARALLEL EXECUTION

    10095657(US)

    Hironori Kasahara, Keiji Kimura

    Patent

  • GLOBAL COMPILER FOR CONTROLLING HETEROGENEOUS MULTIPROCESSOR

    1881405(EP)

    Hironori Kasahara, Keiji Kimura, Hiroaki Shikano

    Patent

  • GLOBAL COMPILER FOR CONTROLLING HETEROGENEOUS MULTIPROCESSOR

    1881405(GB)

    Hironori Kasahara, Keiji Kimura, Hiroaki Shikano

    Patent

  • GLOBAL COMPILER FOR CONTROLLING HETEROGENEOUS MULTIPROCESSOR

    1881405(FR)

    Hironori Kasahara, Keiji Kimura, Hiroaki Shikano

    Patent

  • GLOBAL COMPILER FOR CONTROLLING HETEROGENEOUS MULTIPROCESSOR

    602007055494.2(DE)

    Hironori Kasahara, Keiji Kimura, Hiroaki Shikano

    Patent

  • PARALLEL PROGRAM GENERATING METHOD AND PARALLELIZATION COMPILING APPARATUS

    Hironori Kasahara, Keiji Kimura, Dan Umeda, Hiroki Mikami

    Patent

  • PARALLEL PROGRAM GENERATING METHOD AND PARALLELIZATION COMPILING APPARATUS

    Hironori Kasahara, Keiji Kimura, Dan Umeda, Hiroki Mikami

    Patent

  • Multiprocessor system

    特許6335253

    Hironori Kasahara, Keiji Kimura

    Patent

  • The method of extraction of parallelism METHOD, AND PROGRAM

    特許6319880

    Hironori Kasahara, Keiji Kimura, Akihiro Hayashi, Hiroki Mikami, Yohei Kanehagi, Dan Umeda, Mitsuo Sawada

    Patent

  • PARALLELIZATION COMPILING METHOD, PARALLELIZATION COMPILER, AND VEHICULAR DEVICE

    9934012(US)

    Kazushi Nobuta, Noriyuki Suzuki, Hironori Kasahara, Keiji Kimura, Hiroki Mkiami, Dan Umeda

    Patent

  • METHOD OF PROVIDING A NON-CACHEABLE AREA IN MEMORY

    9928057(US)

    Hironori Kasahara, Keiji Kimura, Mase Masayoshi

    Patent

  • PROCESSOR, ACCELERATOR, AND DIRECT MEMORY ACCESS CONTROLLER WITHIN A PROCESSOR CORE THAT EACH READS/WRITES A LOCAL SYNCHRONIZATION FLAG AREA FOR PARALLEL EXECUTION

    9846673(US)

    Hironori Kasahara, Keiji Kimura

    Patent

  • PARALLELIZATION COMPILING METHOD, PARALLELIZATION COMPILER, PARALLELIZING COMPILE APPARATUS, AND ONBOARD APPARATUS

    9760355(US)

    Yuji Mori, Mitsuhiro Tani, Hironori Kasahara, Keiji Kimura, Akihiro Hayashi, Hiroki Mikami, Dan Umeda, Yohei Kanehagi

    Patent

  • ACCELERATOR AND PROCESSOR SYSTEM

    I597661(TW)

    Hironori Kasahara, Keiji Kimura

    Patent

  • PROCESSOR SYSTEM AND ACCELERATOR

    ZL201280065692.7(CN)

    Hironori Kasahara, Keiji Kimura

    Patent

  • The processor system and accelerator

    特許6103647

    Keiji Kimura, Hironori Kasahara

    Patent

  • PARALLELIZATION COMPILING METHOD, PARALLELIZATION COMPILER, PARALLELIZING COMPILE APPARATUS, AND ONBOARD APPARATUS

    特許6018022

    Yuji Mori, Mitsuhiro Tani, Hironori Kasahara, Keiji Kimura, Akihiro Hayashi, Hiroki Mikami, Dan Umeda, Yohei Kanehagi

    Patent

  • PARALLELIZATION COMPILING METHOD, PARALLELIZATION COMPILER, AND VEHICULAR DEVICE

    Kenichi Mineta, Noriyuki Suzuki, Hironori Kasahara, Keiji Kimura, Hiroki Mkiami, Dan Umeda

    Patent

  • PARALLELIZATION COMPILING METHOD, PARALLELIZATION COMPILER, AND VEHICULAR DEVICE

    Kenichi Mineta, Noriyuki Suzuki, Hironori Kasahara, Keiji Kimura, Hiroki Mkiami, Dan Umeda

    Patent

  • PARALLELIZATION COMPILING METHOD, PARALLELIZATION COMPILER, AND VEHICULAR DEVICE

    Yoshihiro Yatoh, Noriyuki Suzuki, Kenichi Mineta, Hironori Kasahara, Keiji Kimura, Hiroki Mkiami, Dan Umeda

    Patent

  • PARALLELIZATION COMPILING METHOD, PARALLELIZATION COMPILER, AND VEHICULAR DEVICE

    Kazushi Nobuta, Noriyuki Suzuki, Hironori Kasahara, Keiji Kimura, Hiroki Mkiami, Dan Umeda

    Patent

  • MULTIPROCESSOR SYSTEM AND MULTIGRAIN PARALLELIZING COMPILER

    2620840(EP)

    Hironori Kasahara, Keiji Kimura, Jun Shirako, Masaki Ito, Hiroaki Shikano

    Patent

  • MULTIPROCESSOR SYSTEM AND MULTIGRAIN PARALLELIZING COMPILER

    2620840(GB)

    Hironori Kasahara, Keiji Kimura, Jun Shirako, Masaki Ito, Hiroaki Shikano

    Patent

  • MULTIPROCESSOR SYSTEM AND MULTIGRAIN PARALLELIZING COMPILER

    602006047921.2(DE)

    Hironori Kasahara, Keiji Kimura, Jun Shirako, Masaki Ito, Hiroaki Shikano

    Patent

  • PARALLELISM EXTRACTION METHOD AND METHOD FOR MAKING PROGRAM

    Hironori Kasahara, Keiji Kimura, Akihiro Hayashi, Hiroki Mikami, Yohei Kanehagi, Dan Umeda, Mitsuo Sawada

    Patent

  • METHOD OF GENRATING CODE WHICH IS EXECUTABLE BY A PROCESSOR AND STORAGE AREA MANAGEMENT METHOD

    ZL201080057540.3(CN)

    Hironori Kasahara, Keiji Kimura, Mase Masayoshi

    Patent

  • MULTIPROCESSOR SYSTEM

    Hironori Kasahara, Keiji Kimura, Jun Shirako, Masaki Ito, Hiroaki Shikano

    Patent

  • PARALLELIZATION COMPILING METHOD, PARALLELIZATION COMPILER, PARALLELIZING COMPILE APPARATUS, AND ONBOARD APPARATUS

    Yuji Mori, Mitsuhiro Tani, Hironori Kasahara, Keiji Kimura, Akihiro Hayashi, Hiroki Mikami, Dan Umeda, Yohei Kanehagi

    Patent

  • MULTIPROCESSOR SYSTE AND MULTIGRAIN PARALLELIZING COMPILER

    8812880(US)

    Hironori Kasahara, Keiji Kimura, Jun Shirako, Masaki Ito, Hiroaki Shikano

    Patent

  • PARALLELISM EXTRACTING METHOD AND PROGRAM CREATION METHOD

    Hironori Kasahara, Keiji Kimura, Akihiro Hayashi, Hiroki Mikami, Yohei Kanehagi, Dan Umeda, Mitsuo Sawada

    Patent

  • MEMORY MANAGEMENT METHOD, PROGRAM CREATION METHOD

    ZL200880003780.8(CN)

    Hironori Kasahara, Keiji Kimura, Hirofumi Nakano, Takumi Nito, Takanori Maruyama, Tsuyoshi Miura, Tomohiro Tagawa

    Patent

  • MULTIPROCESSOR SYSTEM AND METHOD OF SYNCHRONIZATION FOR MULTIPROCESSOR SYSTEM

    Hironori Kasahara, Keiji Kimura, Masayuki Ito, Tatsuya Kamei, Toshihiro Hattori

    Patent

  • METHOD OF GENERATING CODE EXECUTABLE BY PROCESSOR

    特許5283128

    Hironori Kasahara, Keiji Kimura, Mase Masayoshi

    Patent

  • MULTIPROCESSOR SYSTEM AND MULTIPROCESSOR SYSTEM SYNCHRONIZATION METHOD

    ZL200980103004(CN)

    Hironori Kasahara, Keiji Kimura, Masayuki Ito, Tatsuya Kamei, Toshihiro Hattori

    Patent

  • PROCESSOR SYSTEM AND ACCELERATOR

    Hironori Kasahara, Keiji Kimura

    Patent

  • MEMORY MANAGEMENT METHOD, INFORMATION PROCESSING DEVICE, PROGRAM CREATION METHOD, AND PROGRAM

    8438359(US)

    Hironori Kasahara, Keiji Kimura, Hirofumi Nakano, Takumi Nito, Takanori Maruyama, Tsuyoshi Miura, Tomohiro Tagawa

    Patent

  • MEMORY MANAGEMENT METHOD, INFORMATION PROCESSING DEVICE, PROGRAM CREATION METHOD, AND PROGRAM

    特許5224498

    Hironori Kasahara, Keiji Kimura, Hirofumi Nakano, Takumi Nito, Takanori Maruyama, Tsuyoshi Miura, Tomohiro Tagawa

    Patent

  • MEMORY MANAGEMENT METHOD, INFORMATION PROCESSING DEVICE, PROGRAM CREATON METHOD, AND PROGRAM

    10-1186174(KR)

    Hironori Kasahara, Keiji Kimura, Hirofumi Nakano, Takumi Nito, Takanori Maruyama, Tsuyoshi Miura, Tomohiro Tagawa

    Patent

  • MEHTOD FOR CONTROLLING HETEROGENEOUS MULTIPROCESSOR AND MULTIGRAIN PARALLELIZING COMPILER

    8250548(US)

    Hironori Kasahara, Keiji Kimura, Jun Shirako, Yasutaka Wada, Masaki Ito, Hiroaki Shikano

    Patent

  • MULTIGRAIN PARALLELIZATION COMPILING METHOD

    ZL2009100075365(CN)

    Hironori Kasahara, Keiji Kimura, Jun Shirako, Masaki Ito, Hiroaki Shikano

    Patent

  • DATA TRANSFER UNIT IN MULTI-CORE PROCESSOR

    8200934(US)

    Hironori Kasahara, Keiji Kimura, Takashi Todaka, Tatsuya kamei, Toshihiro Hattori

    Patent

  • MULTIPROCESSOR SYSTEM

    ZL200910146644.0(CN)

    Hironori Kasahara, Keiji Kimura, Jun Shirako, Masaki Ito, Hiroaki Shikano

    Patent

  • Method for controlling heterogeneous multiprocessor and multigrain parallelizing compiler

    特許4936517

    Hironori Kasahara, Keiji Kimura, Jun Shirako, Yasutaka Wada, Masaki Ito, Hiroaki Shikano

    Patent

  • MULTIPROCESSOR SYSTEM AND METHOD OF SYNCHRONIZATION FOR MULTIPROCESSOR SYSTEM

    8108660(US)

    Hironori Kasahara, Keiji Kimura, Masayuki Ito, Tatsuya Kamei, Toshihiro Hattori

    Patent

  • MEMORY MANAGEMENT METHOD AND INFORMATION PROCESSING DEVICE IMPLEMENTING THE METHOD

    2459802(GB)

    Hironori Kasahara, Keiji Kimura, Hirofumi Nakano, Takumi Nito, Takanori Maruyama, Tsuyoshi Miura, Tomohiro Tagawa

    Patent

  • MEMORY MANAGEMENT METHOD, INFORMATION PROCESSING DEVICE, PROGRAM CREATION METHOD

    2478874(GB)

    Hironori Kasahara, Keiji Kimura, Hirofumi Nakano, Takumi Nito, Takanori Maruyama, Tsuyoshi Miura, Tomohiro Tagawa

    Patent

  • GLOBAL COMPILER FOR CONTROLLING HETEROGENEOUS MULTIPROCESSOR

    8051412(US)

    Hironori Kasahara, Keiji Kimura, Hiroaki Shikano

    Patent

  • MULTIPROCESSOR AND MULTIPROCESSOR SYSTEM

    特許4784842

    Hironori Kasahara, Keiji Kimura

    Patent

  • Global compiler for controlling heterogeneous multiprocessor

    特許4784827

    Hironori Kasahara, Keiji Kimura, Hiroaki Shikano

    Patent

  • MULTIPROCESSOR

    特許4784792

    Hironori Kasahara, Keiji Kimura

    Patent

  • METHOD OF GENERATING CODE EXECUTABLE BY PROCESSOR

    Hironori Kasahara, Keiji Kimura, Mase Masayoshi

    Patent

  • MULTIPROCESSOR SYSTEM AND MULTIGRAIN PARALLELIZING COMPILER

    7895453(US)

    Hironori Kasahara, Keiji Kimura, Jun Shirako, Masaki Ito, Hiroaki Shikano

    Patent

  • PROCESSOR AND DATA TRANSFER UNIT

    特許4476267

    Hironori Kasahara, Keiji Kimura, Takashi Todaka, Tatsuya kamei, Toshihiro Hattori

    Patent

  • MULTIPROCESSOR

    Hironori Kasahara, Keiji Kimura

    Patent

  • MULTIPROCESSOR SYSTEM AND METHOD OF SYNCHRONIZATION FOR MULTIPROCESSOR SYSTEM

    Hironori Kasahara, Keiji Kimura, Masayuki Ito, Tatsuya Kamei, Toshihiro Hattori

    Patent

  • MULTIPROCESSOR SYSTEM AND MULTIPROCESSOR SYSTEM SYNCHRONIZATION METHOD

    Hironori Kasahara, Keiji Kimura, Masayuki Ito, Tatsuya Kamei, Toshihiro Hattori

    Patent

  • MULTIPROCESSOR SYSTEM AND MULTIGRAIN PARALLELIZING COMPILER

    ZL200680000666.0(CN)

    Hironori Kasahara, Keiji Kimura, Jun Shirako, Masaki Ito, Hiroaki Shikano

    Patent

  • MULTIPROCESSOR

    特許4304347

    Hironori Kasahara, Keiji Kimura

    Patent

  • GLOBAL COMPILER FOR HETEROGENEOUS MULTIPROCESSOR

    10-0878917(KR)

    Hironori Kasahara, Keiji Kimura, Hiroaki Shikano

    Patent

  • MULTIPROCESSOR SYSTEM AND MULTIGRAIN PARALLELIZING COMPILER

    10-0861631(KR)

    Hironori Kasahara, Keiji Kimura, Jun Shirako, Masaki Ito, Hiroaki Shikano

    Patent

  • MEMORY MANAGEMENT METHOD, INFORMATION PROCESSING DEVICE, PROGRAM CREATION METHOD

    Hironori Kasahara, Keiji Kimura, Hirofumi Nakano, Takumi Nito, Takanori Maruyama, Tsuyoshi Miura, Tomohiro Tagawa

    Patent

  • COMPILE METHOD, COMPILER AND COMPILE DEVICE

    特許4177681

    Hironori Kasahara, Kazuhisa Ishizaka, Hirofumi Nakano

    Patent

  • Multiprocessor system and multigrain parallelizing compiler

    特許4082706

    Hironori Kasahara, Keiji Kimura, Jun Shirako, Masaki Ito, Hiroaki Shikano

    Patent

  • MULTIPROCESSOR SYSTEM AND MULTIGRAIN PARALLELIZING COMPILER

    Hironori Kasahara, Keiji Kimura, Jun Shirako, Masaki Ito, Hiroaki Shikano

    Patent

  • GLOBAL COMPILER FOR HETEROGENEOUS MULTIPROCESSOR

    Hironori Kasahara, Keiji Kimura, Hiroaki Shikano

    Patent

  • MULTIPROCESSOR SYSTEM AND MULTIGRAIN PARALLELIZING COMPILER

    Hironori Kasahara, Keiji Kimura, Jun Shirako, Masaki Ito, Hiroaki Shikano

    Patent

  • MULTIPROCESSOR SYSTEM AND MULTIGRAIN PARALLELIZING COMPILER

    Hironori Kasahara, Keiji Kimura, Jun Shirako, Masaki Ito, Hiroaki Shikano

    Patent

  • ELECTRONIC CIRCUIT SIMULATOR

    Hironori Kasahara, Kuniyuki Manaka

    Patent

  • POWER GENERATION PLANT SIMULATION SYSTEM AND ITS SIMULATION CODE GENERATION SYSTEM

    特許2731252

    Seinosuke Narita, Hironori Kasahara, Hiroo Kanamaru, Kazunori sasaki

    Patent

  • PARALLEL DATA PROCESSING METHOD

    Seinosuke Narita, Hironori Kasahara

    Patent

  • PARALLEL DATA PROCESSING METHOD

    Seinosuke Narita, Hironori Kasahara

    Patent

  • INSTRUCTION CONTROL METHOD

    Seinosuke Narita, Hironori Kaahara, Shin Hashimoto, Masanori Hikichi, Keiichi Tomizawa

    Patent

▼display all

Awards

  • SCAT (Support Center for Advanced Telecommunications Technology Research) President Grand Award

    2021.01   SCAT (Support Center for Advanced Telecommunications Technology Research)  

    Winner： Hironori Kasahara

  • Information Processing Society of Japan, Contribution Award

    2020.06   Information Processing Society of Japan  

    Winner： Hironori Kasahara

  • Spirit of the IEEE Computer Society Award

    2019.10   IEEE Computer Society   Distinguished Contribution for Progress of Resarch, Education and Standard in Computer Technology in the World

    Winner： Hironori Kasahara

  • Fellow

    2017.01   IEEE  

    Winner： Hironori Kasahara

  • Information Processing Society of Japan Fellow Award

    2015.06  

    Winner： Hironori Kasahara

  • Prize for Science and Technology (Research Category),The Commendation for Science and Technology by the Minister of Education, Culture, Sports, Science and Technology

    2014.04  

    Winner： Hironori Kasahara, Keiji Kimura

  • IEEE Computer Society Golden Core Member

    2010.02   IEEE  

    Winner： Hironori Kasahara

  • Intel 2008 Asia Academic Forum Best Research Award

    2008.10   Intel  

    Winner： Hironori Kasahara

  • 2008 LSI Of-The-Year Second Prize

    2008.07  

  • STARC (Semiconductor Technology Academic Research Center) Industry-Academia Cooperative Research Award

    2005.01  

  • IPSJ Sakai Memorial Special Award

    1997  

  • IFAC World Congress Young Author Prize

    1987   IFAC (International Federation of Automatic Control)  

    Winner： Hironori Kasahara

▼display all

Research Projects

  • 組み込みマルチコアプロセッサ向け自動並列化技術の開発

    M社 

    Project Year :

    2021.04
    -
    2022.03
     

  • コンパイラ「OSCAR」を用いた自動並列化技術と省電力化技術の適用による第一原理計算シミュレーションの評価

    H社 

    Project Year :

    2021.02
    -
    2021.03
     

  • 組み込みマルチコアプロセッサ向け自動並列化技術の開発

    M社 

    Project Year :

    2020
    -
    2021
     

  • 深層学習における推論処理の高速化・低消費電力化に関する研究

    NT社 

    Project Year :

    2020
    -
    2021
     

  • 高効率・高速処理を可能とするAIチップ・次世代コンピューティングの技術開発／革新的AIエッジコンピューティング技術の開発／動的多分岐・結合トレース型ＡＩプロセッサのエコシステム開発 配分額3,897,000円

    NSI社 

    Project Year :

    2020
    -
    2021
     

  • 多粒子ビームの高速軌道解析アルゴリズム

    H社 

    Project Year :

    2020
    -
    2021
     

  • 磁場中線量分布解析の高精度化

    H社 

    Project Year :

    2020
    -
    2021
     

  • 深層学習における推論処理の高速化・軽量化に関する研究 配分額3,000,000円

    NT社 

    Project Year :

    2019
    -
    2020
     

  • 高効率・高速処理を可能とするAIチップ・次世代コンピューティングの技術開発／革新的AIエッジコンピューティング技術の開発／動的多分岐・結合トレース型ＡＩプロセッサのエコシステム開発 配分額3,897,000円

    NSI社 

    Project Year :

    2019
    -
    2020
     

  • 次世代の車載電子制御システムにおける高速並列処理に関する研究 配分額9,500,000円

    D社 

    Project Year :

    2019
    -
    2020
     

  • 遺伝的アルゴリズム（GA：Genetic Algorithm)の高速化に向けた検討 配分額2,000,000円

    H社 

    Project Year :

    2019
    -
    2020
     

  • 荷電粒子シミュレーション計算の高速化に関する共同研究 配分額2,200,000円

    H社 

    Project Year :

    2019
    -
    2020
     

  • 自動並列化コンパイラの研究 配分額2,200,000円

    N社 

    Project Year :

    2019
    -
    2020
     

  • マルチコアプロセッサ用並列化コンパイラの機能拡張に係る研究 配分額5,250,000円

    OT社 

    Project Year :

    2019
    -
    2020
     

  • 高効率・高速処理を可能とするAIチップ・次世代コンピューティングの技術開発／革新的AIエッジコンピューティング技術の開発／動的多分岐・結合トレース型ＡＩプロセッサのエコシステム開発 配分額3,823,000円

    NSI社 

    Project Year :

    2018
    -
    2019
     

  • 次世代の車載電子制御システムにおける高速並列処理に関する研究 配分額9,500,000円

    D社 

    Project Year :

    2018
    -
    2019
     

  • 車載制御・信号処理向け並列コンパイラ及びベクトル演算システムの研究(2) 配分額2,160,000円

    R社 

    Project Year :

    2018
    -
    2019
     

  • 自動並列化コンパイラの研究 配分額2,160,000円

    N社 

    Project Year :

    2018
    -
    2019
     

  • マルチコアプロセッサ用並列化コンパイラの機能拡張に係る研究 配分額11,500,000円

    OT社 

    Project Year :

    2018
    -
    2019
     

  • 自動並列化コンパイラの研究 配分額1,080,000円

    N社 

    Project Year :

    2017
    -
    2018
     

  • 動画像認識処理の自動並列化に関する研究 配分額1,080,000円

    S社 

    Project Year :

    2017
    -
    2018
     

  • オスカーコンパイラによるマルチコア機器の高速化の研究 配分額3,000,000円

    F社 

    Project Year :

    2017
    -
    2018
     

  • 組込みシステム向き並列最適化手法の研究 配分額5,000,000円

    M社 

    Project Year :

    2017
    -
    2018
     

  • 次世代の車載電子制御システムにおける高速並列処理に関する研究 配分額5,000,000円

    D社 

    Project Year :

    2017
    -
    2018
     

  • 自動並列化コンパイラの研究 配分額1,080,000円

    N社 

    Project Year :

    2017
    -
    2018
     

  • 車載制御・信号処理向け並列コンパイラ及びベクトル演算システムの研究(1) 配分額2,160,000円

    R社 

    Project Year :

    2017
    -
    2018
     

  • マルチコアプロセッサ用並列化コンパイラの機能拡張に係る研究 配分額11,500,000円

    OT社 

    Project Year :

    2017
    -
    2018
     

  • 車載制御ソフトウェア並列化における並列化技術の適用に関する課題導出と解決方法の策定 配分額1,080,000円

    H社 

    Project Year :

    2017
    -
    2018
     

  • 自動並列化コンパイラの研究 配分額1,080,000円

    N社 

    Project Year :

    2016
    -
    2017
     

  • グリーンコンピューティング技術による機械学習プログラムの最適化 配分額2,000,000円

    H社 

    Project Year :

    2016
    -
    2017
     

  • 鉄道車両のトンネル突入解析向けソフトウェアの高速化 配分額1,080,000円

    H社 

    Project Year :

    2016
    -
    2017
     

  • 並列計算による粒子線治療システム向けソフトウエアの高速化 配分額500,000円

    H社 

    Project Year :

    2016
    -
    2017
     

  • オスカーコンパイラによるマルチコア機器の高速化の研究 配分額1,000,000円

    F社 

    Project Year :

    2016
    -
    2017
     

  • OSCAR並列化コンパイラを適用して、リファクタリングを施した交通シュミレータの並列化による処理の高速化の研究 配分額1,000,000円

    ND社 

    Project Year :

    2016
    -
    2017
     

  • 組み込みシステム向き並列最適化手法の研究 配分額5,000,000円

    M社 

    Project Year :

    2016
    -
    2017
     

  • 次世代の車載電子制御システムにおける高速並列処理に関する研究 配分額12,000,000円

    D社 

    Project Year :

    2016
    -
    2017
     

  • 車載マルチ・メニーコア向け並列化コンパイラの研究（２）配分額1,080,000円

    R社 

    Project Year :

    2016
    -
    2017
     

  • マルチコアプロセッサ用並列化コンパイラの機能拡張に係る研究 配分額11,500,000円

    OT社 

    Project Year :

    2016
    -
    2017
     

  • グリーンコンピューティング技術によるシステム高度化の研究（４）配分額5,000,000円

    H社 

    Project Year :

    2016
    -
    2017
     

  • 画像処理アルゴリズム等のヘテロジニアス・メニーコア向け自動並列化に関する研究 配分額9,720,000円

    O社 

    Project Year :

    2016
    -
    2017
     

  • 自動並列化コンパイラの研究 配分額1,080,000円

    N社 

    Project Year :

    2015
    -
    2016
     

  • 組込みシステム向き最適化手法の研究 配分額5,000,000円

    M社 

    Project Year :

    2015
    -
    2016
     

  • マルチコア並列化コンパイラにおける自動メモリ管理方式の実用化 配分額3,000,000円

    JST知財活用促進ハイウェイ「大学特許価値向上支援」 

    Project Year :

    2015
    -
    2016
     

  • 画像処理及びアルゴリズム等のホモジニアス・メニーコア向け自動並列化に関する研究 配分額9,720,000円

    O社 

    Project Year :

    2015
    -
    2016
     

  • 次世代の車載電子制御システムにおける高速並列処理に関する研究 配分額9,720,000円

    D社 

    Project Year :

    2015
    -
    2016
     

  • 自動並列化コンパイラの研究 配分額1,080,000円

    N社 

    Project Year :

    2015
    -
    2016
     

  • グリーンコンピューティング技術によるシステム高速化の研究（3）配分額5,000,000円

    H社 

    Project Year :

    2015
    -
    2016
     

  • マルチコア・アーキテクチャおよびコンパイラの研究 配分額1,080,000円

    R社 

    Project Year :

    2015
    -
    2016
     

  • マクロタスク融合機能の開発 配分額9,000,000円

    OT社 

    Project Year :

    2015
    -
    2016
     

  • ﾏﾙﾁｺｱﾌﾟﾛｾｯｻ用並列化ｺﾝﾊﾟｲﾗの実用化の研究 配分額9,000,000円

    OT社 

    Project Year :

    2015
    -
    2016
     

  • 自動並列化コンパイラの研究 配分額1,080,000円

    N社 

    Project Year :

    2014
    -
    2015
     

  • android OS搭載ｽﾏｰﾄﾌｫﾝ上へのﾏﾙﾁｺｱ最適化技術を用いた電力削減機能移植における課題抽出 配分額1,000,000円

    KC社 

    Project Year :

    2014
    -
    2015
     

  • 画像処理およびシミュレーションアルゴリズムの自動並列化に関する研究 配分額9,720,000円

    O社 

    Project Year :

    2014
    -
    2015
     

  • 次世代の車載電子制御システムにおける高速並列処理に関する研究 配分額6,480,000円

    D社 

    Project Year :

    2014
    -
    2015
     

  • （BB＋AP）プラットフォーム開発に関する研究 配分額7,500,000円

    F社 

    Project Year :

    2014
    -
    2015
     

  • グリーンコンピューティング技術によるシステム高速化の研究 配分額10,400,000円

    H社 

    Project Year :

    2014
    -
    2015
     

  • マルチコア・アーキテクチャおよびコンパイラの研究 配分額 1,080,000円

    R社 

    Project Year :

    2014
    -
    2015
     

  • マルチコアプロセッサ用並列化コンパイラの実用化の研究 配分額9,000,000円

    OT社 

    Project Year :

    2014
    -
    2015
     

  • 画像処理およびシミュレーションアルゴリズムの自動並列化に関する研究 配分額9,450,000円

    O社 

    Project Year :

    2013
    -
    2014
     

  • 次世代の車載電子制御システムにおける高速並列処理に関する研究 配分額9,450,000円

    D社 

    Project Year :

    2013
    -
    2014
     

  • マルチコアプロセッサ用並列化アクセラレータの研究開発 配分額9,000,000円

    OT社 

    Project Year :

    2013
    -
    2014
     

  • 画像処理およびシミュレーションアルゴリズムの自動並列化に関する研究 配分額9,450,000円

    O社 

    Project Year :

    2013
    -
    2014
     

  • 次世代の車載電子制御システムにおける高速並列処理に関する研究 配分額9,450,000円

    D社 

    Project Year :

    2013
    -
    2014
     

  • 自動並列化コンパイラの研究 配分額4,725,000円

    N社 

    Project Year :

    2013
    -
    2014
     

  • （BB＋AP）プラットフォーム開発に関する研究 配分額20,000,000円

    F社 

    Project Year :

    2013
    -
    2014
     

  • グリーンコンピューティング技術によるシステム高速化の研究 配分額9,600,000円

    H社 

    Project Year :

    2013
    -
    2014
     

  • マルチコア・アーキテクチャおよびコンパイラの研究 配分額4,725,000円

    R社 

    Project Year :

    2013
    -
    2014
     

  • 画像処理およびシミュレーションアルゴリズムの自動並列化に関する研究 配分額9,450,000円

    O社 

    Project Year :

    2012
    -
    2013
     

  • 次世代の車載電子制御システムにおける高速並列処理に関する研究 配分額9,450,000円

    D社 

    Project Year :

    2012
    -
    2013
     

  • マルチコア並列化の研究 配分額3,000,000円

    RK社 

    Project Year :

    2012
    -
    2013
     

  • HEVCエンコーダを対象としたメニーコアプロセッサによる高速処理基盤の研究関する研究 配分額1,000,000円

    K社 

    Project Year :

    2012
    -
    2013
     

  • 自動並列化コンパイラの研究 配分額 4,725,000円

    N社 

    Project Year :

    2012
    -
    2013
     

  • 並列化コンパイラの車載適用研究 配分額9,988,000円

    T社 

    Project Year :

    2012
    -
    2013
     

  • （BB＋AP）プラットフォーム開発に関する研究 配分額 11,000,000円

    F社 

    Project Year :

    2012
    -
    2013
     

  • スーパーリアルタイムシミュレーション技術 配分額10,000,000円

    H社 

    Project Year :

    2012
    -
    2013
     

  • マルチコア・アーキテクチャおよびコンパイラの研究 配分額5,500,000円

    R社 

    Project Year :

    2012
    -
    2013
     

  • OSCAR APIを適用したメニーコア・サーバーの高速化及び省電力化の研究 配分額9,450,000円

    F社 

    Project Year :

    2011
    -
    2012
     

  • 次世代の車載電子制御システムにおける高速並列処理に関する研究 配分額9,450,000円

    D社 

    Project Year :

    2011
    -
    2012
     

  • 画像処理アルゴリズムの自動並列化に関する研究 配分額9,450,000円

    O社 

    Project Year :

    2011
    -
    2012
     

  • スーパーリアルタイムシミュレーション技術 配分額10,000,000円

    H社 

    Project Year :

    2011
    -
    2012
     

  • 自動並列化コンパイラの研究 配分額4,725,000円

    N社 

    Project Year :

    2011
    -
    2012
     

  • マルチコア・アーキテクチャ及びコンパイラの研究 配分額5,500,000円

    R社 

    Project Year :

    2011
    -
    2012
     

  • 並列化コンパイラの車載適用研究 配分額12,075,000円

    T社 

    Project Year :

    2011
    -
    2012
     

  • 平成21年度（2009年度）グリーンコンピュータセンター建設補助金 配分額：1,490,000,000円

    経済産業省 

    Project Year :

    2009.08
    -
    2011.03
     

  • 低消費電力メニーコア・プロセッサ基幹技術の先導研究

    Project Year :

    2009
    -
    2010
     

  • 低消費電力メニーコア・アーキテクチャ及びコンパイラ、APIの先導研究 配分額 24,753,750円

    経済産業省・NEDO 

    Project Year :

    2009
    　
    　
     

  • Heterogeneous multi-core technology for information appliances

    Project Year :

    2007
    -
    2009
     

  • 先進ヘテロジニアス・マルチプロセッサ（AHMP) 180,000,000円

    経済産業省・NEDO 

    Project Year :

    2004.07
    -
    2007.06
     

  • 次世代コンパイラの構築

    Project Year :

    2007
    　
    　
     

  • マルチコア・アーキテクチャおよびコンパイラの研究

    Project Year :

    2006
    -
    2007
     

  • 自動並列化に関する研究

    Project Year :

    2005
    -
    2007
     

  • Research and Development of Real-Time Multi-Core Technology for Information Appliances

    Project Year :

    2005
    -
    2007
     

  • 並列システムの性能・電力評価技術の研究

    Project Year :

    2005
    -
    2006
     

  • Automatic Parallelizing Compiler Cooperative Chip Multiprocessor

    Project Year :

    2004
    -
    2006
     

  • 先進ヘテロジニアス・マルチプロセッサ技術研究開発事業

    Project Year :

    2004
    -
    2006
     

  • Interactive Entertainment

    Project Year :

    2002
    -
    2006
     

  • フレシキシブルＳｏC向け並列処理技術の研究 配分額 3,000,000円

    株式会社日立製作所 

    Project Year :

    2002.04
    -
    2005.03
     

  • 自動並列化コンパイラ協調型シングル・チップ・マルチプロセッサの研究 配分額 24,300,000円

    株式会社半導体理工学研究センター 

    Project Year :

    2001.04
    -
    2004.03
     

  • Parallelizing Compiler Cooperative Single Chip Multiprocessor

    Project Year :

    2000
    -
    2004
     

  • ミレニアムプロジェクト：アドバンスト並列化コンパイラ技術（プロジェクトリーダ） 総額 1,094,552,550円（内早稲田大学共同研究分 110,906,250円）

    経済産業省・NEDO 

    Project Year :

    2000.09
    -
    2003.03
     

  • Advanced Parallelizing Compiler

    Project Year :

    2000
    -
    2003
     

  • 人と環境に優しい次世代情報処理技術

    文部科学省 

    Project Year :

    1999
    -
    2003
     

  • 計算機クラスタの研究動向調査とその応用研究 配分額 4,000,000円

    株式会社山武 

    Project Year :

    1998.04
    -
    2002.03
     

  • シングル・チップ・マルチプロセッサの研究 配分額11,900,000円

    株式会社半導体理工学研究センター 

    Project Year :

    1999.07
    -
    2001.03
     

  • マルチモーダルコラボレーションロボット

    文部科学省 

    Project Year :

    1997
    -
    2001
     

  • マルチプロセッサ用自動並列化技術 配布額 120,000,000円

    技術研究組合 新情報処理開発機構 

    Project Year :

    1998.01
    -
    2000.03
     

  • マルチプロセッサシステムに関する研究 配分額 1,113,000円

    財団法人 京都高度技術研究所 

    Project Year :

    1997.10
    -
    2000.03
     

  • 並列処理技術の研究 配分額 6,825,000円

    富士通株式会社 

    Project Year :

    1997.04
    -
    2000.03
     

  • 並列化コンパイラシステムに関する研究 配分額 5,715,000円

    株式会社 富士通研究所 

    Project Year :

    1993.04
    -
    2000.03
     

  • Multiprocessor Computing

    Project Year :

    1998
    -
    1999
     

  • Data-Localization for Fortran Macrodataflow Computation Using Static Macrotask Fusion.

    公益財団法人 矢崎科学技術振興記念財団 

    Project Year :

    1995
    　
    　
     

  • マルチプロセッサ・スーパーコンピューターに関する共同研究

    公益財団法人 矢崎科学技術振興記念財団 

    Project Year :

    1988
    　
    　
     

  • 音声特徴抽出法の高度化に関する研究

    　View Summary

    音声の特徴抽出を行う場合, 音声信号中に音声情報がいかなる形で埋め込まれているかを追求しながら, これらの効率的な抽出方法を開発していくことが必要である. 本研究では次の4つの側面からの問題に取り組んだ.1.生成モデルに基づく方法……音声生成モデルの精密化を行い, これから得られるパラメータの内, 有効性の高いものを有機的に組み合げ特徴抽出を行う. 本年度は母音モデルと子音モデルの融合を考え, 調音器官に対応する母音調音モデルの声道モデルへの変更を試みた. その結果, 声道モデルによってもほぼ正確に母音の推定を行うことができた.2.音声パワースペクトル包絡(PSE)に基づく方法……PSEを『短時間パワースペクトル特性において周波数軸上で零周波数を原点として基本数時間隔で標本化した値を原データ系列とし, そこから雑音成分を除いて推定される最適値である. 』と定義する. これを対数スペクトルパワー次元で余弦級数展開モデルで表してパラメータ推定を行った. その結果, 従来困難であった/mo/と/noの対の零を明確に捉えることができた.3.ベクトル量子化(VQ)に基づく方法……音響量を多角的に把握した上でベクトル量子化を適用し音響特徴と音韻特徴とのより有効な対応関係の確立をめざす. 本年度は量子化分布と呼ぶベクトル量子化頻度からなる特徴量を提案し, 音声信号中の話者性を捉えることを試みた. 具体的には, この特徴量により話者性を考慮した単語予備選択実験を行い, その有効性を確かめた.4.聴覚実験に基づく方法……母音知覚における周波数構造の影響に関して検討を行った. その際, 口膣形状に応じてホルマントの分類を行い前口膣, 後口膣の共振周波数に対応するものをそれぞれFホルマント, Bホルマントとした. これらのホルマント間の関係の母音知覚に対する影響を調べたが, 今後は子音を含めて音韻境界が他の環境要因にどの程度影響されるかを調べていく

  • Studies on CAD system of Application Specific VLSI Circuits for Signal Processing

    　View Summary

    We have already researed the VLSI design system (SYARDS) based on high-level description for 5 years before this project. Besides, This system was evaluated through a connection with the existing VLSI ligic-level synthesis tool. The connection showed possibilities of the high-level synthesis systems like SYARDS.In this project, this system is advanced and generalized in order to implement the system including the design environment, which aims not only processor design but also its application. Moreover, this project is proceeded for the purpose of founding the high-level design technology. Definitely, we deal with problems on the improvement of the specification description language including concurrent processings, its analysis system, and the scheduling and simulator in operation level.As another subject in the project, the design of a double layr parallel network is considered. This research is carried out by Takashi Matsumoto, and important results on a layred architecture for regularization neuro chips are acquired.The application specification processors which executes the algorithms described in high-level languages (Pascal or C) can automatically be designed using the design system (SYARDS). For 3-year term of project, we strengthen the performance of SYARDS through the optimal design method using the extraction of local parallelism including algorithms, the support technology for bit-width determination, which is needed in dealing with the realistic algorithms for digital signal processing, the introduction of concurrent processing description with C language, and the optimization on the pipeline designs.During the term of project, the concept of co-design is indicated in processor design which considers from both sides of hardware and software. However, this system is originally characterized to design compilers which generate its software as well as hardware. Therefore, this project is also close to the methodology of co-design.In the future, SYARDS will be extended to the direction like this, and the results of this project are considered to have a great deal of significance for the future VLSI design technology

  • スーパーコピュータ用自動並列化コンパイラに関する研究

    　View Summary

    主記憶共有マルチプロセッサシステム上でのFortranプログラムの並列処理では、従来よりマルチタスキングやマイクロカスキングなどの手法が用いられてきた.しかし,マルチタスキングでは,ユーザによる並列性指定が困難である,osコールなどによるスケジューリングオーバーヘッドが大きい等といった問題がある.マイクロタスキングは,最も広く用いられてきたループ並列化手法であるが,イタレーション間にまがる複雑なデータ依存やループ外への条件分岐によって並列化できないループが以前存在する.これらに対して当研究者当は、マクロデータフロー処理手法を提案した.マクロデータフロー処理手法では,コンパイラがプログラムを粗粒度タスクへ分割し,粗粒度タスクの最早実行可能条件を解析することにより粗粒度のアスク間の並列性を自動抽出する.コンパイラが各ソースプログラム専用に生成したスケジューリングルーチンを用いることで,スケジューリングオーバーヘッドを抑えることができる.また,マクロデータフロー処理を行なう場合,各データをデータ転送を最小化するよう考慮し,各プロセッサ上のローカルメモリに配置(データローカライズ)することによって,より効率の良い並列処理が可能となる.プロトタイプマルチプロセッサイステムOSCAR上での性能評価では,マクロデータフロー処理による粗粒度タスクの有効な並列処理を確認できた.また富士通VPP-500、Alliant FX/4、KSR1、NEC Cnju-3等,商用マルチプロセッサシステム上での性能評価でも,従来手法であるマルチタスキングおよびマイクロスタキングに比べ,マクロデータフロー処理の方が高い並列性の抽出が可能であることが分かった.さらに,それらの評価から従来手法に比べて低オーバーヘッドな処理を行なうことが可能で,プログラムの実行速度が向上することも確認された

  • Research on Multigrain Parallel Processing on Multiprocessor Systems

    　View Summary

    In 1994, which is the final year of this research project on "Multigrain Parallel Processing, " an automatic parallelizing compiler was developed and evaluated on an actual multiprocessor system. The compiler hierarchically combines a coarse grain parallel processing scheme which was developed by this research project in 1993, a near-fine grain parallel processing scheme, and traditional loop parallelization scheme. It was confirmed that the compiler allows us to efficiently exploit parallelism in a source program on the actual multiprocessor system.The multigrain parallel processing scheme consists of the following steps :1.Process macrotasks, or coarse grain tasks, in parallel among multiple processor clusters by using a macro-dataflow scheme developed by this project.2.Process a loop in parallel, which is assigned to a processor cluster, among processors inside a processor cluster by using Do-all or D-across scheme if the loop is parallelizable.(3)Process a sequential loop or a basic block in parallel, which is assigned to a processor cluster, among processors inside processor cluster by using a near-fine grain parallel processing scheme.Furthermore, this project also developed a new optimization technique called "near-fine grain parallel processing scheme without explicit synchronization" which minimizes synchronization overhead in near-fine grain parallel processing.The above results were or will be published as 7 journal papers, 6 international conference papers, 1 chapter of an international book, 3 symposium papers with review process, 10 technical reports of societies in Japan, and 15 short papers in annual conference of societies in Japan

  • Study on automatic parallelizing compiler for multiprocessor systems and architectural supports

    　View Summary

    In this research project, we developed data licalization schemes for multigrain parallel processing, multiprocessor scheduling algorithms considering maximum overlap of inter-processor data transfer and task processing to hide data transfer overhead, and precise machine code scheduling schemes for a "compiler back-end" to eliminate all synchronization instructions from parallelized machine code without deteriorating calculation accuracy. Also, we showed effectiveness of the developed schemes on a multiprocessor architecture simulator and a real supercomputer.Performance evaluation on a multiprocessor architecture simulator for the data localization schemes using the proposed aligned data decomposition and partial static assignment techniques showed us that the scheme can shorten average execution time of multigrain parallel processing using coarse grain parallelism, loop parallelism, and fine grain parallelism hierarchically by 20%.Also, it has been confirmed that the overlapping scheduling algorithms to hide data transfer overhead reduce execution time on Fujitsu VPP500 with 4 processors by 15% in average.futhermore, the development and evaluation of near fine grain parallel processing schemes made clear desirable architectural supports for advanced parallel machine code scheduling.The above compilation schemes and evalution using architecture simulator and the supercomputer made us clear necessary architectural supports for next generation multiprocessor supercomputers and a future single chip multiprocessor.These research accomplishment were published as 15 journal or international conference papers, 1 symposium paper with reviews, 5 technical reports and 12 short papers for domestic annual conventions

  • マルチモーダルな対話機能を有し人間と共同作業をする次世代ロボットの基礎研究

    　View Summary

    本年度は、本計画の最終年度である。前年度末に試作した2体のヒューマノイド型ロボットをプラットホームとして、以下のような研究を行い、全員で統合システムとしての取りまとめを行なった。1)環境モデルと実画像の対応付けによる自己位置認識システムの精度向上を図るとともに、環境変化に応じたモデル変更の方式を検討し試作ロボットでの確認を行なった。2)音声と画像を手がかりとしたシーン中での対話相手の検出、およびカラー画像とロボット視覚系を用いた人間の顔表情とジェスチャー認識の実験を行なった。3)連続音声認識の精度向上を図ると共に、並列処理系による高速化を試み、ジェスチャー、表情を合わせた、人間型ロボットによるマルチモーダル対話の実験に成功した。4)試作ロボットをネットワークに接続し、遠隔地からの相互制御の実験を行い、情報ネットワークにおけるインターフェース端末としてロボットを使用する可能性を検討した。5)完成した2足歩行系の自由度を増やし、方向変化等をより自在にできるようにすると共に、頭部、腕部などとの協調制御方式を検討し、実験的に検証した。6)コンプライアンス制御による柔軟な腕機構の制御方式を改良すると共に、人間との共同作業とジェスチャー生成を行う安全な腕として、外装を含めた総合的な設計基準を検討した

  • Implementation of Parallelizing Compiler for Massively Parallel Computers

    　View Summary

    In this research project, we first extract the intermediate representation from Parafrase-2 to develop a C++ version of our new parallelizing compiler called Narafrase. At the same time, we gave the definition of and designed the data partitioning graph as our universal intermediate representation. The optimization of communication overhead will be solved by our proposing cc-COMA technology. Then, we combined user interface library with the universal intermediate representation for Narafrase by collaborating with PROMIS parallelizing compiler developed by Prof. Polychronolous (investigator). We also implemented several parallelization methods on Narafrase with the use of the user interface library. Now we are implementing an algorithm for simultaneous partitioning of data and program for Narafrase. On the other hand, we have investigated and implemented a parallelization support tool by 3D visualization. The support tool, NaraView, collaborates with Narafrase so that users can parallelize their sequential programs effectively and easily. In this way, we have developed a prototype parallelizing compiler system for massively parallel computers

▼display all

Presentations

  • Open Innovation at Waseda University

    Hironori Kasahara  [Invited]

    BELGIAN ECONOMIC MISSION TO JAPAN, Waseda University IBUKA International Conference Center 

    Presentation date： 2022.12

  • Memory Optimization in OSCAR Parallelizing Compiler

    Hironori Kasahara  [Invited]

    Oxford-Waseda Symposium on New Memory Programming Language Support for Emerging Memory Technologies, Organizers: Peter Braam, Jeremy Gibbons, Oleg Kiselyov, and Hironori Kasahara with the Support by MEXT TGU Program "Waseda University ICT Robot Project" and Advanced Multicore Processor Research Institute, Green Computing Center at Waseda University 

    Presentation date： 2022.12

  • Research on Environment Friendly Green Computing

    Hironori Kasahara  [Invited]

    Green Computing Organization Early Career Researcher Symposium 

    Presentation date： 2022.09

  • Waseda University Open Innovation Valley Project: An Initiative toward Connected Collaborative University

    Hironori Kasahara  [Invited]

    Cisco Connect 

    Presentation date： 2022.06

  • RU11 special programme: Challenges and prospects for The World University Rankings -Japanese universities perspectives-

    Hironori Kasahara  [Invited]

    Panel Discussion, THE ASIA UNIVERSITIES SUMMIT, Fujita Health University, Aichi, Japan 

    Presentation date： 2022.05

  • Green Multicore Computing for Scientific, Image and Deep Learning Computation

    Hironori Kasahara  [Invited]

    Keynote Speech at IEEE International Conference on Image Processing and Robotics (ICIPRoB2022), Sri Lanka, Online 

    Presentation date： 2022.03

  • W-SPRING

    Hironori Kasahara  [Invited]

    W-SPRING Program Symposium, Waseda Open Innovation Forum WOI'22, Waseda Univ., Tokyo, Japan, Online 

    Presentation date： 2022.03

  • Waseda Open Innovation Forum WOI'22

    Hironori Kasahara  [Invited]

    Opening Remarks --Waseda Open Innovation Forum WOI'22--, Waseda Univ., Tokyo, Japan, Online 

    Presentation date： 2022.03

  • Waseda Open Innovation Eco-system Challenging Research Program (W-SPRING)

    Hironori Kasahara  [Invited]

    W-SPRING 2021 Kickoff Symposium, Waseda Univ., Tokyo, Japan, Online 

    Presentation date： 2022.01

  • Efforts for Implementation of Core-Facility, Panel Discussion of Stepwise Process or Efforts and Current Problems for Implementation of Research Equipment and Apparatus Core Facility in Each Organization

    Hironori Kasahara  [Invited]

    MEXT Research Infrastructure EXPO2022 Advanced Research Infrastructure Sharing Promotion Project Symposium 2022, Tokyo, Japan, Online 

    Presentation date： 2022.01

  • Introduction of Waseda Open Innovation Forum WOI'22

    Hironori Kasahara  [Invited]

    Waseda University Alumni Meeting in Economic Field, Waseda Univ., Tokyo, Japan, Online 

    Presentation date： 2022.01

  • Waseda Open Innovation Eco-system, Carbon Neutral, and WOI

    Hironori Kasahara  [Invited]

    Toshiba-Waseda University Technical Meeting, Tokyo, Japan, Online 

    Presentation date： 2022.01

  • Designing New Generation based University Key Management

    Hironori Kasahara  [Invited]

    Roundtable on University Management Innovation x Resilient, in UGSS2021 (The 15th Universities‘ Global Strategy Symposium), Tokyo, Japan, Online 

    Presentation date： 2021.12

  • IEEE COMPSAC2021 IEEE-HKN Panel Working in the IT world: a 20+ years overview in Japan

    Hironori Kasahara  [Invited]

    COMPSAC 2021 IEEE-HKN Panel - Working in the IT world: a 20+ years overview, IEEE COMPSAC 2021: IEEE Computer Society Signature Conference on Intelligent and Resilient Computing for a Collaborative World, Madrid, Spain, Online  (Madrid) 

    Presentation date： 2021.07

  • IEEE COMPSAC2021 Panel: Career Pointers from Computer Society Leadership: What is the Most Important Advice that Your Carrier Pointers have Taugh You?

    Hironori Kasahara  [Invited]

    Plenary Past President's Panel on Career Pointers from Computer Society Leadership, IEEE COMPSAC 2021: IEEE Computer Society Signature Conference on Intelligent and Resilient Computing for a Collaborative World, Madrid, Spain, Online  (Madrid) 

    Presentation date： 2021.07

  • IEEE COMPSAC2021 CS Presidents Panel

    Hironori Kasahara  [Invited]

    President's Panel, IEEE COMPSAC 2021: IEEE Computer Society Signature Conference on Intelligent and Resilient Computing for a Collaborative World, Madrid, Spain, Online  (Madrid) 

    Presentation date： 2021.07

  • Support Center for Advanced Telecommunications Technology Research (SCAT) Chairman Grand Prize Lecture: Parallelizing Compiler Contributing to Green Computing and Contribution to Pioneering Research on Compiler Co-designed Multicore Architecture

    Hironori Kasahara  [Invited]

    The 110th Telecommunication technology seminar, Support Center for Advanced Telecommunications Technology Research, Tokyo, Japan  (Tokyo) 

    Presentation date： 2021.07

  • Advanced Computing Technology and Waseda Open Innovation Valley Project

    Hironori Kasahara  [Invited]

    Waseda Independent Studies "Cultural Lectures for Science and Engineering", Tokyo, Japan, Online  (Tokyo) 

    Presentation date： 2021.05

  • Waseda Open Innovation Eco System

    Hironori Kasahara  [Invited]

    Waseda Open Innovation Forum 2021：Construction of Open Innovation Eco System as a Co-creation Place Originating Waseda University Ventures  (Tokyo) 

    Presentation date： 2021.03

  • Research & Development at Waseda Univ. Green Computing R & D Project and Advanced Multi-Core Processor Research Institute

    Hironori Kasahara  [Invited]

    Waseda Open Innovation Forum 2021：Waseda Univ. Green Computing Systems Research & Development Center 10th Anniversary Symposium  (Tokyo) 

    Presentation date： 2021.03

  • Waseda Open Innovation Forum 2021

    Hironori Kasahara  [Invited]

    Waseda Open Innovation Forum 2021  (Tokyo) 

    Presentation date： 2021.03

  • Oxford-Waseda Computer Science Symposium

    Hironori Kasahara  [Invited]

    Waseda Open Innovation Forum 2021:Oxford-Waseda Computer Science Symposium  (Tokyo) 

    Presentation date： 2021.03

  • Green Multicore Computing

    Hironori Kasahara  [Invited]

    Waseda Open Innovation Forum 2021: Oxford-Waseda Computer Science Symposium  (Tokyo) 

    Presentation date： 2021.03

  • OSCAR Automatic Parallelizing Compiler - Automatic Speedup and Power Reduction -

    Tohma Kawasumi, Yu Omori, Kazuki Yamamoto, Kazuki Fujita, Keiji Kimura, Hironori Kasahara

    Waseda Open Innovation Forum 2021 

    Presentation date： 2021.03

  • Transitioning Humanoid Robots from Laboratory to Home : From 3D Printing to AI-driven Computation

    Hironori Kasahara  [Invited]

    Science/AAAS 

    Presentation date： 2021.03

  • Core Facility Construction Support Program Execution Summary and Accomplishment Report

    Hironori Kasahara  [Invited]

    Research Fundation Innovation Group and MEXT Joint Symposium  (Tokyo) 

    Presentation date： 2021.01

  • Toward of Realization of WASEDA Eco-System

    Hironori Kasahara  [Invited]

    WASEDA Economist Summit 2021  (Tokyo) 

    Presentation date： 2021.01

  • WASEDA Univ. Online Education and WOI ’21 Coping with COVID-19

    Hironori Kasahara  [Invited]

    TOSHIBA-WASEDAUniv. Technology Exchanging Meeting  (Tokyo) 

    Presentation date： 2021.01

  • Welcome to Sozo Capital Formation Training

    Hironori Kasahara  [Invited]

    Business Skill Enhancement program by Sozo Ventures  (Tokyo) 

    Presentation date： 2020.12

  • IEEE InTech Forum Keynote Speeches Concluding Remarks by General Chair

    Hironori Kasahara  [Invited]

    IEEE InTech Forum--Forum on the Response and Resiliency to Covid-19 

    Presentation date： 2020.12

  • Welcome to University of Oxford and Waseda University International Workshop on Multiphase Flows:Analysis, Modelling and Numerics

    Hironori Kasahara  [Invited]

    Oxford-Waseda International Workshop on Multiphase Flows: Analysis, Modelling and Numerics  (Tokyo) 

    Presentation date： 2020.12

  • OSCAR Parallelizing and Power Reducing Compiler

    Tohma Kawasumi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara

    in ITBL Booth, IEEE ACM SC (Super Computing) 2020 Exhibition, Online: Atlanta 

    Presentation date： 2020.11

  • Multigrain Parallelization for MATLAB/SimulinkUsing the OSCAR Compiler

    Ryo Koyama, Yuta Tsumura, Dan Umeda, Keiji Kimura, Hironori Kasahara

    in ITBL Booth, IEEE ACM SC (Super Computing) 2020 Exhibition, Online: Atlanta 

    Presentation date： 2020.11

  • OSCAR Vector Multicore SystemPlatinum Vector Accelerator on FPGA

    Kazuki Fujita, Kazuki Yamamoto, Honoka Koike, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara

    in ITBL Booth, IEEE ACM SC (Super Computing) 2020 Exhibition, Online: Atlanta 

    Presentation date： 2020.11

  • Plenary Panel

    Hironori Kasahara  [Invited]

    Silicon Valley Japan Forum US Japan Relationship  (Tokyo) 

    Presentation date： 2020.11

  • Information Processing Society of Japan 60th Anniversary Panel Discussion--Design of future academic societies--

    Hironori Kasahara  [Invited]

    Information Processing Society of Japan 60th Anniversary Ceremony: Panel Discussion  (Tokyo) 

    Presentation date： 2020.10

  • Panel : Startup Ecosystems and Initiatives That Emerge from Universities Will Be Discussed

    Hironori Kasahara  [Invited]

    Y Combinater & Silicon Valley Japan Platform (SVJP)"Road to Silicon Valley - The Role of the University in the Innovation Ecosystem"  (Tokyo) 

    Presentation date： 2020.10

  • Waseda Open Innovation Ecosystem

    Hironori Kasahara  [Invited]

    Y Combinater & Silicon Valley Japan Platform (SVJP)"Road to Silicon Valley - The Role of the University in the Innovation Ecosystem"  (Tokyo) 

    Presentation date： 2020.10

  • Future Possibility and Problems of Computers -?High Performance, Low Power, Software Productivity--

    Hironori Kasahara  [Invited]

    JX Nippon Mining & Metals Corporation Seminar  (Tokyo) 

    Presentation date： 2020.10

  • Waseda Open Innovation Valley Project

    Hironori Kasahara  [Invited]

    Waseda Univ. Consortium for the Research Strategy of Next-generation Heat Pump Technology Opening Ceremony  (Tokyo) 

    Presentation date： 2020.10

  • Online Education for COVID-19 at Waseda University

    Hironori Kasahara  [Invited]

    2020 Global Information and Telecommunication Institute Forum  (Tokyo) 

    Presentation date： 2020.09

  • Waseda Univ Online/Hybrid Education

    Hironori Kasahara  [Invited]

    National Institute of Information [16th] Cyber Symposium - Information Sharing on Remote Education Started from April: Efforts for Remote/Face-to-face Hybrid Lectures  (Tokyo) 

    Presentation date： 2020.09

  • Plenary Panel: To Patent or Not to Patent?

    Hironori Kasahara  [Invited]

    IEEE COMPSAC 2020: IEEE Computer Society Signature Conference on Computers, Software and Applications  (Madrid) 

    Presentation date： 2020.07

  • World Shining WASEDA University ? High Performance Low Power Computing Technology and WASEDA Open Innovation Valley Project -

    Hironori Kasahara  [Invited]

    Waseda University Senior High School Special Lecture Series on Science and Technology  (Tokyo) 

    Presentation date： 2020.07

  • Open Innovation Targeted by WASEDA University

    Hironori Kasahara  [Invited]

    Waseda University Graduate School of Business and Finance“Lab to Market”Seminar,hosted by Prof. Kanetaka Maki  (Tokyo) 

    Presentation date： 2020.07

  • Waseda University Online Education Coping with COVID-19

    Hironori Kasahara  [Invited]

    Strategies for Teaching & Learning Continuity in Japan's Higher Education, Blackboard and the U.S. Commercial Service Tokyo at U.S. Embassy in Japan  (Tokyo) 

    Presentation date： 2020.06

  • Green Multicore Computing

    Hironori Kasahara  [Invited]

    Hosted by Prof. Jean-Luc Gaudiot, Distinguished Professor, University of California, Irvine, California, USA, 

    Presentation date： 2020.02

  • Activities as IEEE Computer Society President 2018 and Waseda Open Innovation Valley Project

    Hironori Kasahara  [Invited]

    Seminar in Toshiba Corporate Research & Development Center 

    Presentation date： 2020.01

  • Strengthening Research at Waseda University

    Hironori Kasahara  [Invited]

    Ministry of Education, Culture, Sports, Science and Technology Research Funds Committee 

    Presentation date： 2020.01

  • An Approach to Research Enhancement in Waseda University -- Waseda Open Innovation Valley Project --

    Hironori Kasahara  [Invited]

    Waseda University Trustee Forum 

    Presentation date： 2019.12

  • About Activities of IEEE Computer Society 2018 as President and the Concept of Waseda Open Innovation Valley

    Hironori Kasahara  [Invited]

    20th Anniversary Waseda Univ. DCC(Digital Campus Consortium) Invited talk 

    Presentation date： 2019.11

  • Automatic Parallelization by OSCAR Compiler for NEC SX-Aurora TSUBASA

    Hironori Kasahara  [Invited]

    NEC Aurora Community Meeting at SC19( IEEE ACM Super Computing2019) 

    Presentation date： 2019.11

  • OSCAR Vector Multicore System - Platinum Vector Accelerator on FPGA -

    Kazuki Yamamoto, Kazuki Fujita, Yuta Tadokoro, Tomoya Kashimata, Tomoya Kashimata, Boma A. Adhi, Yoshitake Ooki, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara

    in ITBL Booth, IEEE ACM SC (Super Computing) 2019 Exhibition, Denver  (Denver) 

    Presentation date： 2019.11

  • OSCAR Parallelizing & Power Reducing Compiler - Power is Reduced to 1/7 on ARM -

    Kazuki Yamamoto, Kazuki Fujita, Yuta Tadokoro, Tomoya Kashimata, Tomoya Kashimata, Boma A. Adhi, Yoshitake Ooki, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara

    in ITBL Booth, IEEE ACM SC (Super Computing) 2019 Exhibition, Denver  (Denver) 

    Presentation date： 2019.11

  • OSCAR Automatic Parallelizing Compiler - Automatic Speedup and Power Reduction -

    Kazuki Yamamoto, Kazuki Fujita, Yuta Tadokoro, Tomoya Kashimata, Tomoya Kashimata, Boma A. Adhi, Yoshitake Ooki, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara

    in ITBL Booth, IEEE ACM SC (Super Computing) 2019 Exhibition, Denver  (Denver) 

    Presentation date： 2019.11

  • Parallelising Compiler for Green Multicore Computing

    Hironori Kasahara  [Invited]

    Hosted by Prof. Jeremy Gibbons, Department of Computer Science, Oxford University 

    Presentation date： 2019.11

  • Future of Green Multicore Computing

    Hironori Kasahara  [Invited]

    Hitachi Academic System Study Group 

    Presentation date： 2019.09

  • Plenary Panel: Meeting of the Alliances

    Hironori Kasahara  [Invited]

    The(Times Higher Education) World Academic Summit 2019 in Zurich 

    Presentation date： 2019.09

  • Parallel Processing of MATLAB and Simulink Simulation and Control on Multicore Processors

    Hironori Kasahara  [Invited]

    MathWorks Asia Research Summit 

    Presentation date： 2019.09

  • High Performance Computing and Medical Treatment

    Hironori Kasahara  [Invited]

    Japan Medical Association 

    Presentation date： 2019.07

  • Green Multicore Compiler

    Hironori Kasahara  [Invited]

    MPSoC Forum 2019 

    Presentation date： 2019.07

  • Opening Remarks --Simon WRIGHT, Director - Programming, Japan House London --

    Hironori Kasahara  [Invited]

    SYMPOSIUM : Classical Arts x Digital Technologies 

    Presentation date： 2019.06

  • Collaboration as IEEE Computer Society President 2018 and Open Innovation Eco-system in Waseda University

    Hironori Kasahara  [Invited]

    Next Generation Industry Navigators Forum 

    Presentation date： 2019.03

  • Open Innovation Eco-system in Waseda University

    Hironori Kasahara  [Invited]

    Waseda Open Innovation Forum 2019 

    Presentation date： 2019.03

  • Green Multicore Computing: Low Power High Performance

    Hironori Kasahara  [Invited]

    Tencent-Waseda University Technical Tour 

    Presentation date： 2018.12

  • Collaborative Initiatives Promoting Institutional Joint Research between University of Birmingham and Waseda University

    Hironori Kasahara  [Invited]

    University of Birmingham Day at Waseda University 

    Presentation date： 2018.11

  • IEEE Computer Society

    Hironori Kasahara  [Invited]

    Ivannikov ISP RAS Open Conference 

    Presentation date： 2018.11

  • Green Multicore Computing: Low Power High Performance

    Hironori Kasahara  [Invited]

    Ivannikov ISP RAS Open Conference 

    Presentation date： 2018.11

  • SX-Aurora TSUBASA with Oscar Compiler Optimization

    Hironori Kasahara  [Invited]

    in NEC Booth, IEEE ACM SC (Super Computing) 2018 Exhibition 

    Presentation date： 2018.11

  • CS HPC Award Ceremony on Nov. 13 in SC2018, Dallas having 13,000 participants

    Hironori Kasahara  [Invited]

    IEEE ACM SC (Super Computing) 2018 

    Presentation date： 2018.11

  • OSCAR Vector Multicore System Platinum Vector Accelerator on FPGA

    Kazuki Miyamoto, Takumi Kawata, Ken Takahashi, Tomoya Kashimata, Yuto Abe, Boma A. Adhi, Yusuke Minato, Hiroki Mikami, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara

    in ITBL Booth, IEEE ACM SC (Super Computing) 2018 Exhibition, Dallas  (Dallas) 

    Presentation date： 2018.11

  • OSCAR Parallelizing & Power Reducing Compiler -Power is Reduced to 1/7 on ARM-

    Kazuki Miyamoto, Takumi Kawata, Ken Takahashi, Tomoya Kashimata, Yuto Abe, Boma A. Adhi, Yusuke Minato, Hiroki Mikami, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara

    in ITBL Booth, IEEE ACM SC (Super Computing) 2018 Exhibition, Dallas  (Dallas) 

    Presentation date： 2018.11

  • OSCAR Automatic Parallelizing Compiler Automatic Speedup and Power Reduction

    Kazuki Miyamoto, Takumi Kawata, Ken Takahashi, Tomoya Kashimata, Yuto Abe, Boma A. Adhi, Yusuke Minato, Hiroki Mikami, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara

    in ITBL Booth, IEEE ACM SC (Super Computing) 2018 Exhibition, Dallas  (Dallas) 

    Presentation date： 2018.11

  • Closing Address: AI and Robotics in Waseda University

    Hironori Kasahara  [Invited]

    Global AI Narratives Tokyo 

    Presentation date： 2018.09

  • Parallelizing Compiler Technology for Embedded Multicores and Manycores

    Hironori Kasahara  [Invited]

    Embedded Multicore &Manycore Software Development Technical Seminor 

    Presentation date： 2018.09

  • OSCAR Compiler for Automatic Multigrain Parallelization, Memory Optimization and Power Systems

    Hironori Kasahara  [Invited]

    International Symposium on Future of Computer Technology 2018：ISFCT 2018 

    Presentation date： 2018.07

  • IEEE Computer Society Annual Symposium on VLSI, Opening Address

    Hironori Kasahara  [Invited]

    IEEE Computer Society Annual Symposium on VLSI 

    Presentation date： 2018.07

  • Low Power High Performance Multicore Hardware and Software Co-Design

    Hironori Kasahara  [Invited]

    IEEE Computer Society Annual Symposium on VLSI 

    Presentation date： 2018.07

  • Automatic Multigrain Parallelization, Memory Optimization and Power Reduction Compiler for Multicore Systems

    Hironori Kasahara  [Invited]

    ICS-2018: The 32nd ACM International Conference on Supercomputing 

    Presentation date： 2018.06

  • IEEE COOL Chips21, April 18-20, 2018 Symposium on Low-Power and High-Speed Chips and Systems

    Hironori Kasahara  [Invited]

    IEEE Symposium on Low-Power and High-Speed Chips(COOL CHIPS 21) 

    Presentation date： 2018.04

  • Future of High Performance Low Power Multicore Computing

    Hironori Kasahara  [Invited]

    The 80th National Convention of IPSJ 

    Presentation date： 2018.03

  • OSCAR Automatic Parallelizing and Power Reducing Multicore Compiler for Realtime Embedded to High Performance Computing

    Hironori Kasahara  [Invited]

    Mitsubishi Electric Information Technology Research Institute 

    Presentation date： 2018.03

  • Future of High Performance Green OSCAR Multicore Computing

    Hironori Kasahara  [Invited]

    International Symposium on Future of High Performance Green Computing 2018 (HPGC2018) 

    Presentation date： 2018.03

  • HPGC Round table

    Hironori Kasahara  [Invited]

    International Symposium on Future of High Performance Green Computing 2018 (HPGC2018) 

    Presentation date： 2018.03

  • High Performance Green Multicore Computing

    Hironori Kasahara  [Invited]

    hosted by Prof. Kastury, University of South Florida 

    Presentation date： 2018.02

  • High Performance Low Power OSCAR Multicore and Compiler

    Hironori Kasahara  [Invited]

    hosted by Prof. David Kuck, University of Texas 

    Presentation date： 2018.02

  • Green Multicore Computing: Co-design of Software and Architecture

    Hironori Kasahara  [Invited]

    Korea Software Congress 2017 

    Presentation date： 2017.12

  • Future of High Performance & Low Power Multicore Technology

    Hironori Kasahara  [Invited]

    SEMICON Japan  (Tokyo) 

    Presentation date： 2017.12

  • Green Multicore Computing and Industry Collaboration

    Hironori Kasahara  [Invited]

    Ministry of foreign Affairs of Japan Russian IT Industry Japan Visiting Program  (Tokyo) 

    Presentation date： 2017.11

  • IEEE CS President Elect 2017, President 2018 Address

    Hironori Kasahara  [Invited]

    IEEE International Conference on Network and Service Management  (Tokyo) 

    Presentation date： 2017.11

  • World Tidal Current Zed by Computer Science

    Hironori Kasahara  [Invited]

    Waseda University "Advanced Data Related Human Resource Development Program" Symposium Kick off  (Tokyo) 

    Presentation date： 2017.11

  • OSCAR Automatic Parallelizing Compiler -Automatic Speedup and Power Reduction-[Parallel Processing of MATLAB/Simulink by OSCAR Compiler on Intel, ARM & Renesas multi cores, OSCAR Parallelizing & Power Reducing Compiler-Power is Reduced to 1/7 on ARM-, OSCAR Vector Multicore System -Platinum Vector Accelerator on FPGA-]

    Hiroki Mikami, Boma Anantasatya Adhi, Tomoya Kashimata, Satoshi Karino, Kazuki Miyamoto, Takumi Kawata, Ken Takahashi, Tetsuya Makita, Tomoya Shirakawa, Yoshitake Oki, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara

    in ITBL Booth, IEEE ACM SC (Super Computing) 2017 Exhibition, Denver  (Denver) 

    Presentation date： 2017.11

  • OSCAR Automatic Parallelizing Compiler-[Automatic Power Reduction of OpenCV Face Detection by OSCAR Compiler, Automatic parallelization of applications generated from MATLAB / Simulink(on Intel, arm, Renesas Chips)by OSCAR compiler]

    Ando Kazumasa, Tomoya Shirakawa, Yuya Nakada, Yuki Shimizu, Hiroki Shimizu, Yuto Abe, Hideo Yamamoto, Mamoru Shimaoka, Hiroki Mikami, Keiji Kimura, Hironori Kasahara

    Embedded Technology 2017,?Pacifico Yokohama  (Yokohama) 

    Presentation date： 2017.11

  • Performance and Low Power for Multicores

    Hironori Kasahara  [Invited]

    University of Cambridge Astrophysics Group SKA(Square Kilometre Array telescope project)  (Cambridge) 

    Presentation date： 2017.10

  • Multigrain Parallelization and Compiler/Architecture Co-design for 30 Years with LCPC

    Hironori Kasahara  [Invited]

    30th International Workshop on Languages and Compilers for Parallel Computing(LCPC),  (Texas) 

    Presentation date： 2017.10

  • Software and Hardware for High Performance and Low Power Homogeneous and Heterogeneous Multicore Systems

    Hironori Kasahara  [Invited]

    CPS Summer School 2017  (Sardinia) 

    Presentation date： 2017.09

  • Inauguration of IEEE Computer Society President 2018 and Industry and Academia Research and Development Collaboration on Green Multicores

    Hironori Kasahara  [Invited]

    Council of Departments of Computer Science & Engineering in Japanese University  (Tokyo) 

    Presentation date： 2017.07

  • Latest Trends in Automatic Parallelization and Power Reduction Compiler

    Hironori Kasahara  [Invited]

    Symposium on Embedded Multicores and Automatic Parallelizing and Power Consumption Reducing Compiler in Post-Moore Generation  (Tokyo) 

    Presentation date： 2017.07

  • Future of Green Multicore Computing

    Hironori Kasahara  [Invited]

    hosted by Prof. Stefano Zanero, Politecnico di Milano  (Milano) 

    Presentation date： 2017.07

  • COMPSAC 2017 Plenary Panel Future of Computing: Exciting Research in Computers, Software and Applications Green Multicore Computing

    Hironori Kasahara  [Invited]

    IEEE COMPSAC 2017 (The 41th IEEE Computer Society International Conference on Computers, Software & Applications)  (Torino) 

    Presentation date： 2017.07

  • Automatic Cache and Local Memory Optimization for Multicores

    Hironori Kasahara  [Invited]

    17th INTERNATIONAL FORUM ON MPSoC for software-defined hardware  (Annecy) 

    Presentation date： 2017.07

  • 2017 COOL Chips 20 Cerebration for the 20th Anniversary of IEEE Symposium on Low-Power and High-Speed Chips, Opening Address

    Hironori Kasahara  [Invited]

    IEEE Symposium on Low-Power and High-Speed Chips(COOL CHIPS 20)  (Yokohama) 

    Presentation date： 2017.04

  • Cool Chips, Low Power Multicores, Open the Way to the Future, Panel Discussion

    Hironori Kasahara  [Invited]

    IEEE Symposium on Low-Power and High-Speed Chips(COOL CHIPS 20)  (Yokohama) 

    Presentation date： 2017.04

  • The Low Power Multicore and Its Software for Embedded to HighPerformance Computing

    Hironori Kasahara  [Invited]

    3rd IEEE PCSC '17 (IEEE Pakistan Computer Society Congress), Key Note Speech, IEEE Computer Society Karachi Section, Arts Auditorium University of Karachi (UOK)  (Karachi) 

    Presentation date： 2017.04

  • Integrated Development of Parallelizing and Power Reducing Compiler and Multicore Architecture for HPC to Embedded Applications

    Hironori Kasahara  [Invited]

    SISA (International Workshop A Strategic Initiative of Computing Systems and Applications)  (Waseda) 

    Presentation date： 2017.01

  • Elected IEEE Computer Society President 2018 and Research and Development of High-performance and Low power Multicores

    Hironori Kasahara  [Invited]

    IEEE CSJapan Chapter Young Author Award 2016  (Tokyo) 

    Presentation date： 2016.12

  • Oscar Automatic Parallelizing Compiler -- Automatic Speeding and Power Reduction of Multicores --

    Izumino Katsuhiko, Yuhei Hosokawa, Ando Kazumasa, Tomoya Shirakawa, Risako Kitamura, Yuya Nakada, Hideo Yamamoto, Mamoru Shimaoka, Hiroki Mikami, Keiji Kimura, Hironori

    Embedded Technology 2016,Pacifico Yokohama  (Yokohama) 

    Presentation date： 2016.11

  • OSCAR Automatic Parallelizing Compiler --Automatic Speedup and Power Reduction--

    Akira Maruoka, Yuya Mushu, Satoshi Karino, Kazuki Miyamoto, Takumi Kawata, Kouhei Yamamoto, Tomoya Shirakawa, Yoshitake Oki, Toshiaki Kitamura, Moriyuki Takamura, Keiji Kimura, Hironori Kasahara

    in ITBL Booth, IEEE ACM SC (Super Computing) 2016 Exhibition, Salt Lake City 

    Presentation date： 2016.11

  • Toward for Exa-scale and Beyond from Parallelizing Compiler Aspect

    Hironori Kasahara  [Invited]

    NPC2016  (Xian) 

    Presentation date： 2016.10

  • OSCAR Parallelizing and Power Reducing Compiler for Multicores

    Hironori Kasahara  [Invited]

    NPC2016  (Xian) 

    Presentation date： 2016.10

  • Parallelization and Power Reduction Compiler for Heterogeneous Multicores for Emerging Applications

    Hironori Kasahara  [Invited]

    IEEE ACM PACT2016  (Haifa) 

    Presentation date： 2016.09

  • Automatic Paralleling of Automobile Engine Control Programs on Multicores

    Hironori Kasahara  [Invited]

    16th International Forum on MPSoC for Software-defined Hardware  (Nara) 

    Presentation date： 2016.07

  • COMPSAC 2106 Plenary Panel -Rebooting Computing: Future of Architecture and Software- 'Multicore Software and Architecture'

    Hironori Kasahara  [Invited]

    IEEE COMPSAC 2016 (The 40th IEEE Computer Society International Conference on Computers, Software & Applications)  (Atlanta) 

    Presentation date： 2016.07

  • OSCAR Automatic Parallelizing and Power Reducing Compiler for Embedded to High Performance Multicore Applications

    Hironori Kasahara  [Invited]

    hosted by Prof.Vivek Sarkar, Rice University  (Texas) 

    Presentation date： 2016.06

  • OSCAR Automatic Paralleling and Power Reducing Compiler for Embedded to High Performance Multicores

    Hironori Kasahara  [Invited]

    hosted by Prof. Vladimir Getov, School of Electronics and Computer Science, University of Westminster  (London) 

    Presentation date： 2016.05

  • OSCAR Automatic Paralleling and Power Reducing Compiler for Multicores

    Hironori Kasahara  [Invited]

    INC12,IMEC  (Leuven) 

    Presentation date： 2016.05

  • OSCAR Automatic Parallelizing Compiler、Automatic Power Reduction of Real-Time Face Detection by OSCAR Compiler、Automatic Parallelization of Model-based Development Application by OSCAR Compiler

    Iizuka Shuhei, Yabuki Jun, Ando Kazumasa, Bui Binh Duc, Takahiro Suzuki, Dan Umeda, Izumino Katsuhiko, Yuhei Hosokawa, Hideo Yamamoto, Mamoru Shimaoka, Hiroki Mikami, Keiji Kimura, Hironori Kasahara

    Embedded Technology 2015,Pacifico Yokohama  (Yokohama) 

    Presentation date： 2015.11

  • OSCAR Parallelizing and Power Reducing

    Hironori Kasahara  [Invited]

    hosted by Prof. Yan Solihin, Dept. of Electrical & Computer Eng.  (North Carolina) 

    Presentation date： 2015.09

  • OSCAR Automatic Parallelization and Power Reduction Compiler for Homogeneous and Heterogeneous Multicores

    Hironori Kasahara  [Invited]

    GTC Japan 2015  (Tokyo) 

    Presentation date： 2015.09

  • Parallelization and Power Reduction of Embedded Real-time Applications by OSCAR Compiler on ARM and Intel Multicores

    Hironori Kasahara  [Invited]

    15th International Forum on MPSoC for Software-defined Hardware  (Ventura) 

    Presentation date： 2015.07

  • Plenary Panel : Rebooting Computing -- Low Power Multicores with Accelerators and Automatic Parallelizing and Power Reducing Compiler for Exponential Performance Scaling --

    Hironori Kasahara  [Invited]

    IEEE COMPSAC 2015 (The 39th Annual International Computers, Software & Applications Conference)  (Taichung) 

    Presentation date： 2015.07

  • Industry and Academia Collaborative Research for Advanced Multicore -- Green Multicore Computing --

    Hironori Kasahara  [Invited]

    Microwave and Photonics Symposium  (Tokyo) 

    Presentation date： 2014.12

  • Automatic Parallelization of MATLAB/Simulink on Multicore Processors -- Parallel processing of automobile engine control C code generated by embedded coder --

    Hironori Kasahara  [Invited]

    MathWorks Asian Research Faculty Summit 2014  (Tokyo) 

    Presentation date： 2014.11

  • OSCAR Automatic Parallelizing Compiler、Automatic Power Reduction on Android Multicore、Automatic Power Reduction of Real-Time Face Detection by OSCAR Compiler

    Tomohiro Hirano, Takashi Goto, Shuhei Iizuka, Hideo Yamamoto, Hiroki Mikami, Jun Yabuki, Izumino Katsuhiko, Fujieda Misaki, Moriyuki Takamura, Keiji Kimura, Hironori Kasahara

    Embedded Technology 2014,Pacifico Yokohama  (Yokohama) 

    Presentation date： 2014.11

  • Android Movie Player System Combined with Automatically Parallelized and Power Optimized Code by OSCAR Compiler

    Duc Binh Bui, Tomohiro Hirano, Hillenbrand Dominic, Hiroki Mikami, Keiji Kimura, Hironori Kasahara

    Embedded System Symposium2014 

    Presentation date： 2014.10

  • Power Reduction of H.264/AVC Decoder on Android Multicore Using OSCAR Compiler

    Shuhei Iizuka, Hideo Yamamoto, Tomohiro Hirano, Takashi Goto, Hiroki Mikami, Uichiro Takahashi, Sakae Yamamoto, Moriyuki Takamura, Keiji Kimura, Hironori Kasahara

    IPSJ SIG Technical Report Vol.2014-ARC-204 

    Presentation date： 2014.10

  • Multi-platform Automatic Parallelization and Power Reduction by OSCAR Compiler

    Hironori Kasahara  [Invited]

    14th International Forum on Embedded MPSoC and Multicore  (Margaux) 

    Presentation date： 2014.07

  • Hierarchical Parallel Processing of HEVC Encoder

    Hiroki Mikami, Keiji Kimura, Hironori Kasahara

    Poster Session, COOL Chips XVII, IEEE Symposium on Low-Power and High-Speed Chips 

    Presentation date： 2014.04

  • Technologies, I have been excited and am excited now

    Hironori Kasahara  [Invited]

    Technical Report of IPSJ, 200 times commemorative panel session, Tokyo Institute of Technology  (Tokyo) 

    Presentation date： 2014.01

  • OSCAR Automatic Prallelizing Compiler, OSCAR API : Automatic Speed up and Power Reduction on Murticore

    Kohei Muto, Takashi Goto, Hideo Yamamoto, Hiroki Mikami, Tomohiro Hirano, Moriyuki Takamura, Keiji Kimura, Hironori Kasahara

    Embedded Technology 2013, Pacifico Yokohama  (Yokohama) 

    Presentation date： 2013.11

  • Industry-Academia Collaborative Research on Advanced Multicore Processors : Application of low power multicore hardware and software to automobiles, smartphones, medical systems and servers.

    Hironori Kasahara  [Invited]

    EWE Sangetsu-kai 

    Presentation date： 2013.10

  • Automatic Parallelization of Automatically Generated Engine Control C Codes by Model-based Design

    Dan Umeda, Youhei Kanehagi, Hiroki Mikami, Akihiro Hayashi, Mitsuhiro Tani(DENSO, Yuji Mori(DENSO, Keiji Kimura, Hironori Kasahara

    Embedded System Symposium2013 

    Presentation date： 2013.10

  • Profile-Based Automatic Parallelization and Sequential Program Tuning for Android 2D Rendering on Nexus7

    Kohei Muto, Takashi Goto, Hideo Yamamoto, Fujitsu Laboratories LTD, Hiroki Mikami, Tomohiro Hirano, Moriyuki Takamura(Fujitsu Laboratories LTD, Keiji Kimura, Hironori Kasahara

    Poster Session, LCPC 2013, Qualcomm Research Silicon Valley 

    Presentation date： 2013.09

  • Parallel Processing of Multimedia Applications on TILEPro64

    Yohei Kishimoto, Hiroki Mikami, Keiichi Nakano(Olympus Corpora, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara

    Poster Session, COOL Chips XVI, IEEE Symposium on Low Power and High-Speed Chips 

    Presentation date： 2013.08

  • OSCAR Parallelizing Compiler and Its Performance for Embedded Applications

    Hironori Kasahara  [Invited]

    13th International Forum on Embedded MPSoC and Multicore 

    Presentation date： 2013.07

  • Panel Discussion 'Starting-ups and their possibility in Industry-Academia Collaboration'

    Hironori Kasahara  [Invited]

    Industry-Academia Cooperation Venture Summit, Industry-Academia Collaborative human resource development seminars, Tohmatsu Venture Support Co., Ltd. 

    Presentation date： 2013.07

  • Panel on Perspective and Problems for New Application Development

    Hironori Kasahara  [Invited]

    IPSJ, SIG on Computer Architecture 

    Presentation date： 2013.01

  • Industry-Academia Coopertative Research and Developed on Gree Computing

    Hironori Kasahara  [Invited]

    Technical Report of IPSJ, Vol.2012-ARC-195 

    Presentation date： 2013.01

  • Opportunities and Challenges of Application-Power Control in the Age of Dark Silicon

    Dominic Hillenbrand, Yuuki Furuyama, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara

    Poster Session, The 8th HiPEAC conference, Berlin 

    Presentation date： 2013.01

  • Multicore Research and Development in Green Computing Systems R&D Center

    Hironori Kasahara  [Invited]

    EWE 100 Years Memorial Event  (Tokyo) 

    Presentation date： 2012.11

  • Panel on Charm of IT Electronics and Human Resources Expected Future

    Hironori Kasahara  [Invited]

    The 4th JEITA Industry and Academic Collaborasion Symposium on Future of IT/Electronics and Desirable Human Resources  (Tokyo) 

    Presentation date： 2012.11

  • Future of Green Computing and Collaboration with Industry

    Hironori Kasahara  [Invited]

    The 4th JEITA Industry and Academic Collaborasion Symposium on Future of IT/Electronics and Desirable Human Resources  (Tokyo) 

    Presentation date： 2012.11

  • Green Computing Using Automatic Parallelizing and Power Reducing Compiler with Multiplatform API for Homogeneous and Heterogeneous Multicores

    Hironori Kasahara  [Invited]

    Illinois-Intel Parallelism Center at the University of Illinois at Urbana-Champaign I2PC Distinguished Speaker Series Seminar,  (Illinois) 

    Presentation date： 2012.10

  • OSCAR Compiler and API for High Performance Low Power Multicores and Their Application to Smartphones, Automobiles, Medical Systems

    Hironori Kasahara  [Invited]

    Intel/Kai, Champaign,  (Illinois) 

    Presentation date： 2012.10

  • Green Computing Systems Research and Development with Industry

    Hironori Kasahara  [Invited]

    Industrial Technology Research Institute ? Waseda University, Joint Research Workshop 2012  (Tokyo) 

    Presentation date： 2012.10

  • Parallel processing of multimedia applications on TILEPro64 using OSCAR API for embedded multicore

    Yohei Kishimoto, Hiroki Mikami, Keiichi Nakano, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara

    Embedded System Symposium2012 

    Presentation date： 2012.10

  • Compiler Level Low Power Control

    Hironori Kasahara  [Invited]

    The 43th STARC Advanced Seminor on Low Power Technology  (Kawasaki) 

    Presentation date： 2012.09

  • Green Computing Systems to Save Lives and Strengthen Industrial Competitiveness

    Hironori Kasahara  [Invited]

    Industrial Top Information Exchange Meeting  (Tokyo) 

    Presentation date： 2012.07

  • Green Computing by Low Power Consumption Multicore

    Hironori Kasahara  [Invited]

    2012 the First Social and Public Systems Special Interest Group in Hitachi Users, Waseda University Advanced Multicore Processor Reserch Insutitute co-sponsored  (Tokyo) 

    Presentation date： 2012.07

  • OSCAR Compiler for Automatic Parallelization and Power Reduction for Multicores and Manycores

    Hironori Kasahara  [Invited]

    12th International Forum on Embedded MPSoC and Multicore  (Quebec) 

    Presentation date： 2012.07

  • Automatic Parallelizing and Power Control Compiler and API for Manycore Processors

    Hironori Kasahara  [Invited]

    NEDO Manycore Symposium  (Tokyo) 

    Presentation date： 2012.03

  • Multicore Technology for Green Computing

    Hironori Kasahara  [Invited]

    The Japan Society of Applied Physics (JSAP) the 59th Spring Meeting Special Symposium, Waseda University  (Tokyo) 

    Presentation date： 2012.03

  • Automatic Parallelization of Dose Calculation Engine for A Particle Therapy

    Akihiro Hayashi, Takuji Matsumoto, Hiroki Mikami, Keiji Kimura, Keiji Yamamoto, Hironori Saki, Yasuyuki Takatani, Hironori Kasahara

    Symposium on High-Performance Computing and Computer Science(HPCS2012) 

    Presentation date： 2012.01

  • Multicore/Manycore Architectures and Software for Green Computing

    Hironori Kasahara  [Invited]

    The 34th Electrical Engineering Conference(EECON-34)  (Pattaya) 

    Presentation date： 2011.12

  • Low Power Multicores, Parallelizing Compiler and Multiplatform API for Green Computing

    Hironori Kasahara  [Invited]

    Dasan Conference on "Green IT", The Korean Federation of Science and Technology Society  (Jeju) 

    Presentation date： 2011.11

  • Green Computing Systems Reserch and Development Center

    Hironori Kasahara  [Invited]

    Innovation Policy Social Meeting in October  (Tokyo) 

    Presentation date： 2011.10

  • Homogeneous and Heterogeneous Multicore / Manycore Processors, Parallelizing Compiler and Multiplatform API for Green Computing

    Hironori Kasahara  [Invited]

    Keynote Speech, MPSoC2011(11th International Forum on Embedded MPSoC and Multicore)  (Beaune) 

    Presentation date： 2011.07

  • Low Power Real-time Homogeneous & Heterogeneous Multicores, Automatic Parallelizing Compilers and Multi-Platoform API

    Hironori Kasahara  [Invited]

    Sig. on The 5th Automoble Control and Model, The Society of Automotive Engineers of Japan (JSAE) ＆ The Society of Instrument and Control Engineers （SICE)  (Tokyo) 

    Presentation date： 2011.06

  • Future of Green Computing

    Hironori Kasahara  [Invited]

    Waseda Univ. Green Computing Systems Research & Development Center Opening Memorial Symposium:Green Computing for Opening Future --For future of enviroment friendly computing--  (Tokyo) 

    Presentation date： 2011.05

  • OSCAR Low Power Manycores and Compiler and API for Exa-scale Supercomputing

    Hironori Kasahara  [Invited]

    Panel Discussion on GPUs for Climate models,Climate 13:The 13th International Specialist Meeting on the Next Generation Models of Climate Change and Sustainability for Advanced High Performance Computing Facilities  (Hawaii) 

    Presentation date： 2011.03

  • Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-Time Heterogeneous Multicores

    Akihiro Hayashi, Yasutaka Wada, Takeshi Watanabe, Takeshi Sekiguchi, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara

    Symposium on Advanced Computing Systems and Infrastructures (SACSIS 2011) 

    Presentation date： 2011.02

  • Many-core Chip for Green Computing

    Hironori Kasahara  [Invited]

    8th International Workshop on Future Information Processing Technologies(IWFIPT)  (Kyoto) 

    Presentation date： 2010.10

  • Hardware and software for Solar Panel Driven Low Power Multicores and Manycores

    Hironori Kasahara  [Invited]

    Bluespec User Group Meeting 2010  (Tokyo) 

    Presentation date： 2010.07

  • Future of Low Power High Performance Computer:Solar Battery Operational Multicores /Manycores and their Software

    Hironori Kasahara  [Invited]

    Hyperworks Technology Conference2010  (Tokyo) 

    Presentation date： 2010.06

  • OSCAR API for Real-time Low-Power Multicores

    Keiji Kimura, Masayoshi Mase, Hiroki Mikiami, Takamichi Miyamoto, Jun Shirako, Hironori Kasahara  [Invited]

    Waseda University Seoul National University Joint Workshop on Future Low Power Processor Architecture and Software  (Tokyo) 

    Presentation date： 2010.05

  • OSCAR Low Power Multicores and Parallelizing Compiler for Performance and PowerReduction

    Prof.Hironori Kasahara  [Invited]

    Waseda University Seoul National University Joint Workshop on Future Low Power Processor Architecture and Software  (Tokyo) 

    Presentation date： 2010.05

  • Hardware and software for Advanced Low Power High Performance Processor Technology

    Hironori Kasahara  [Invited]

    EWE  (Tokyo) 

    Presentation date： 2010.05

  • Advanced Research of NEDO Manycore Processor Technology

    Hironori Kasahara  [Invited]

    Low Power Manycore Processor System Technology Symposium Latest Trends of Manycore Architecture, Compiler and API,http://www.waseda.jp/jp/events/index.html  (Tokyo) 

    Presentation date： 2010.02

  • Parallelizing Compiler and API for Low Power Multicores

    Hironori Kasahara  [Invited]

    STARC Advanced Seminar  (Tokyo) 

    Presentation date： 2009.11

  • Research and Development of Advanced Low Power Computer (Multicore/Manycore)Hardware and Software

    Hironori Kasahara  [Invited]

    ＥＷＥ  (Tokyo) 

    Presentation date： 2009.11

  • OSCAR Multicore Compiler and API for Low Power High Performance Computing

    Hironori Kasahara

    Microsoft Research Computing in the 21st Century Conference Poster Session 

    Presentation date： 2009.11

  • Compiler and API for Low Power High Performance Computing on Multicore and Manycore Processors

    Hironori Kasahara  [Invited]

    UPCRC Seminar hosted by Prof. Josep Torrrellas  (Tokyo) 

    Presentation date： 2009.10

  • Future of Low Energy Computing Systems --- Low Power Multi-core and Many-core processors and Their Software ---

    Hironori Kasahara  [Invited]

    IEEE 125 Anniversary Memorial Technical Seminor  (Yokohama) 

    Presentation date： 2009.10

  • Roles of Parallelizing Compilers for Low Power Manycores”, Panel: "What do compiler optimizations mean for many-cores?"

    Hironori Kasahara  [Invited]

    The 22nd International Workshop on Languages and Compilers for Parallel Computing (LCPC09)  (Illinois) 

    Presentation date： 2009.10

  • Multicore processors for real-time consumer electronics

    Waseda Univ(Kasahara, Kimura Lab.), Hitachi, Renesas Technology

    CEATEC JAPAN 2009 

    Presentation date： 2009.10

  • Low Power Multicore Processor Driven by Solar Panel and Its Software

    Hironori Kasahara  [Invited]

    Waseda University DCC Industry and Academia Cooperation Forum  (Tokyo) 

    Presentation date： 2009.09

  • OSCAR Parallelizing Compiler Cooperative Heterogeneous Multi-core Architecture

    Akihiro Hayashi, Yasutaka Wada, Hiroaki Shikano, Teruo Kamiayama, Takeshi Watanabe, Takeshi Sekiguchi and Masayoshi Mase

    The Eighteenth International Conference on Parallel Architectures and Compilation Techniques (PACT2009), Raleigh, North Carolina. 

    Presentation date： 2009.09

  • Multi-core API & Compiler Technology

    Hironori Kasahara, Jun Shirako  [Invited]

    The IEEE Computer Society 2009 Vail Computer Elements Workshop  (Newark) 

    Presentation date： 2009.06

  • Parallelizing Compiler and API for Low Power Multicores

    Hironori Kasahara  [Invited]

    IPSJ LSI and Systems Workshop 2009  (Tokyo) 

    Presentation date： 2009.05

  • A Power Reduction Scheme for Parallelizing Compiler Using OSCAR API on Multicore Processors

    Ryo Nakagawa, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara

    Symposium on Advanced Computing Systems and Infrastructures (SACSIS 2009) 

    Presentation date： 2009.05

  • Multicore processors for real-time consumer electronics

    Waseda Univ(Kasahara, Kimura Lab.), Hitachi, Renesas Technology

    12th Embedded Systems Expo(ESEC2009) 

    Presentation date： 2009.05

  • New Markets Opened by Embedded Multicores and Forefront of Parallelizing Compiler Technology

    Hironori Kasahara  [Invited]

    Embedded Processor and Platform Workshop 2009  (Denver) 

    Presentation date： 2009.04

  • OSCAR Parallelizing Compiler and API for Low Power High Performance Multicores

    Hironori Kasahara  [Invited]

    The 11th International Specialist Meeting on The Next generation Models on Climate Change and Sustainability for Adavanced High-performance Computing Facilities (Climate Meeting 2009)  (Tokyo) 

    Presentation date： 2009.03

  • 低消費電力マルチコアプロセッサとソフトウェア技術

    Hironori Kasahara  [Invited]

    Waseda University Technical Presentation Meeting  (Kitakyushu) 

    Presentation date： 2009.03

  • Parallelizing Compiler and API for Embedded Multi-cores

    Hironori Kasahara  [Invited]

    TRON Association 

    Presentation date： 2009.02

  • Panel Discussions: Japanese Challenges for Multicore -Low Power High Performance Multicores,Compiler and API-

    Hironori Kasahara  [Invited]

    Intel Higher Education Program 2008 Asia Academic Forum 

    Presentation date： 2008.10

  • OSCAR Multicore Compiler for Low Power High Performance Computing

    Hironori Kasahara

    Intel Higher Education Program 2008 Asia Academic Forum 

    Presentation date： 2008.10

  • High Performance ECO Multicore Computer

    Hironori Kasahara & Keiji Kimura Laboratory

    TechnoFair WASEDA 

    Presentation date： 2008.10

  • Multicore Technologies for Realization of Low-carbon Society and Challenge for Utilization Technologies

    Hironori Kasahara  [Invited]

    IBM HPC Forum 2008 

    Presentation date： 2008.09

  • Low Power High Performance Multicores Technology

    Hironori Kasahara  [Invited]

    JAPAN ASSOCIATION for HEAT PIPE Seminar 

    Presentation date： 2008.07

  • Multi-Core Technologies for Information Appliance (Parallelizing Compiler, Multi-Core API, 8CPU-LSI)

    Hironori Kasahara, Toshihiro Hattori  [Invited]

    Microprocessor Forum Japan 2008 

    Presentation date： 2008.07

  • Compiler Cooperative Heterogeneous Multicore Processor

    Akihiro Hayashi, Yasutaka Wada, Hiroaki Shikano, Jun Shirako, Keiji Kimura, Hironori Kasahara

    Waseda University Global COE Program the 2nd International Symposium "Ambient SoC; Recent Topics in Nano-Technology and Information Technology Appl 

    Presentation date： 2008.07

  • Compiler and API for Low Power High Performance Multicores

    Hironori Kasahara  [Invited]

    8th International Forum on Application-Specific Multi-Processor SoC (MpSoc '08) 

    Presentation date： 2008.06

  • OSCAR Low Power High Performance Multicore and Parallelizing Compiler

    Hironori Kasahara  [Invited]

    Nokia 

    Presentation date： 2008.06

  • Parallelization of Multimedia Applications by Compiler on Multicores for Consumer Electronics

    Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Keiji Kimura, Hironori Kasahara

    Symposium on Advanced Computing Systems and Infrastructures (SACSIS 2008) 

    Presentation date： 2008.05

  • Embedded Multi-cores Advanced Parallelizing Compiler Technologies

    Hironori Kasahara  [Invited]

    11th Embedded Systems Expo 

    Presentation date： 2008.05

  • OSCAR Multigrain Parallelizing Compiler for High Performance Low Power Multicores

    Hironori Kasahara  [Invited]

    The 14th Workshop on Compiler Techniques for High-Performance Computing(CTHPC2008) 

    Presentation date： 2008.05

  • Panel Discussions: Multi-Core and Many-Core: the 5 to 10 Year View

    Hironori Kasahara  [Invited]

    IEEE Cool Chips XI: Symposium on Low-Power and High-Speed Chips 2008 

    Presentation date： 2008.04

  • Multicore Compiler for Low Power High Performance Embedded Computing

    Hironori Kasahara  [Invited]

    IEEE Cool Chips XI: Symposium on Low-Power and High-Speed Chips 2008 

    Presentation date： 2008.04

  • Developed multicore was introduced in the CSTP at the Prime Minister's office

    Waseda Univ(Kasahara, Kimura Lab.), Hitachi, Renesas Technology

    Council for Science and Technology Policy 74th session 

    Presentation date： 2008.04

  • A Multigrain Parallelizing Compiler with Power Control for Multicore Processors

    Hironori Kasahara  [Invited]

    Google Headquarter, Hosted by Dr. Shih-wei Liao 

    Presentation date： 2008.02

  • A Multigrain Parallelizing Compiler with Power Control for Multicore Processors

    Hironori Kasahara  [Invited]

    Intel Headquarter, Hosted by Dr. Peng Tu 

    Presentation date： 2008.02

  • Advanced Parallelizing Compiler Technology for High Performance Low Power Multicores

    Hironori Kasahara  [Invited]

    VDEC Refresh Seminar 

    Presentation date： 2008.01

  • Low Power High Performance Multicores and Compiler Technology

    Hironori Kasahara  [Invited]

    The 5th Technology Link in W.T.L.O - For International Research Center in Collaboration of Industry and Academia 

    Presentation date： 2007.10

  • Parallelizing Compiler Cooperative Multicore Technology -- Easy-to-use, High performance, Low power consumption, High-value added Multicore Prosessor --

    Hironori Kasahara, Keiji Kimura

    Parallelizing Compiler Cooperative Multicore Technology -- Easy-to-use, High performance, Low power consumption, High-value added Multicore Prosessor -- 

    Presentation date： 2007.10

  • How is specifically multicore programming different from traditional parallel computing?", Panel Discussion on "How is specifically multicore programming different from traditional parallel computing?

    Hironori Kasahara  [Invited]

    The 20th International Workshop on Languages and Compilers for Parallel Computing (LCPC2007) Siebel Center for Computer Science Urbana, Illinois  (Illinois) 

    Presentation date： 2007.10

  • A Multi-core Parallelizing Compiler for Low-Power High-Performance Computing

    Hironori Kasahara  [Invited]

    Colloquium Electrical and Computer Engineering, Computer and Information Technology Institute, Computer Science, and Dean of Engineering 

    Presentation date： 2007.10

  • Multigrain Parallelization of Restricted C Programs in SMP Execution Mode of a Multicore for Consumer Electronics

    Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Hiroaki Tano, Takeshi Masuura, Takamichi Miyamoto, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara

    Embedded Systems Symposium 2007 （ESS 2007) 

    Presentation date： 2007.10

  • Multicore Innovation

    Hironori Kasahara  [Invited]

    Waseda Univ. 125 th & Faculty of Science and Engineering 100th Anniversary Symposium "Innovative Information, Electronics, and Optical technology" 

    Presentation date： 2007.09

  • Power-Aware Compiler Controllable Heterogeneous Chip Multiprocessor

    Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

    The Sixteenth International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania 

    Presentation date： 2007.09

  • Advanced Parallelizing Compiler Technologies for Embedded Multi-cores

    Hironori Kasahara  [Invited]

    DA Symposium 2007 

    Presentation date： 2007.08

  • C Language Support in OSCAR Multigrain Parallelizing Compiler using CoSy

    Masayoshi Mase, Keiji Kimura, Hironori Kasahara  [Invited]

    ACE 2nd CoSy Community Gathering 

    Presentation date： 2006.10

  • Advanced Multi-core Compiler and Its Parallelization and Power Reduction Performance

    Hironori Kasahara  [Invited]

    ARM Seminar 2006 

    Presentation date： 2006.10

  • Advanced Computer Architecture: METI/NEDO Multicore-processor Technology for Real-time Consumer Electronics Project

    Hironori Kasahara  [Invited]

    Tokyo Electric Power Company EWE Seminor 2006 

    Presentation date： 2006.10

  • Multi-core Parallelizing Compiler for Low Power High Performance Computing

    Hironori Kasahara  [Invited]

    University of Illinois at Urbana-Champaign, Hosted by Prof. David Padua 

    Presentation date： 2006.10

  • Parallelizing Compiler Cooperative Chip Multiprocessor Technology

    Hironori Kasahara, Keiji Kimura, Jun Shirako, Yasutaka Wada, Hirofumi Nakano, Takamichi Miyamoto

    STARC Symposium 2006 

    Presentation date： 2006.09

  • Software Challenges in Multi-Core Chip Era

    Guang R. Gao, Kasahara Hironori, Vivek Sarkar, Skevos Evripidou, Murphy Brian  [Invited]

    Workshop on Software Challenges for Multicore Architectures 

    Presentation date： 2006.09

  • OSCAR Multigrain Parallelizing Compiler for Multicore Architectures

    Hironori Kasahara  [Invited]

    Workshop on Software Challenges for Multicore Architectures 

    Presentation date： 2006.09

  • The Latest Trend of Parallelizing Compiler

    Hironori Kasahara  [Invited]

    IBM Japan Forum on Pioneering Scientific Computing 

    Presentation date： 2006.08

  • Multicores for Consumer Electronics and Parallelizing Compilers

    Hironori Kasahara  [Invited]

    JEITA SIG. on Microprocessor 

    Presentation date： 2006.08

  • Trial s of Collaboration among Business, Academia and Government and Human Resource Development for Creation of Innovations(Panel on the Promotion of Collaboration among Business, Academia and Government and Human Resource Development for Creation of Inn

    Hironori Kasahara  [Invited]

    5th Conference for the Promotion of Collaboration Among Business, Academia, and Government (Section Meeting) 

    Presentation date： 2006.06

  • Compiler Controle Power Saving Scheme for Multicore Processors

    Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

    Symposium on Advanced Computing Systems and Infrastructures (SACSIS 2006) 

    Presentation date： 2006.05

  • Latest Trends of Multi-CPU Architectures and Parallelizing Compilers: Application for Consumer Electronics

    Hironori Kasahara  [Invited]

    Sony Technology seminar 

    Presentation date： 2006.05

  • Parallelizing Compiler Cooperated Low Power High Effective Performance Multi-core Processors

    Hironori Kasahara  [Invited]

    158th IPSJ Special Interest Group on Computer Architecture (SHINING 2006) 

    Presentation date： 2006.01

  • Parallelizing Compiler Cooperative Chip Multiprocessor Technology

    Hironori Kasahara, Keiji Kimura, Hirofumi Nakano, Jun Shirako, Takamichi Miyamoto, Yasutaka Wada

    STARC Symposium 2005 

    Presentation date： 2005.09

  • Compiler technology for built-in multi-core processor

    H. Kasahara  [Invited]

    ARM Seminar 2005 

    Presentation date： 2005.06

  • Advanced High-Performance Computer

    H. Kasahara  [Invited]

    Lecture on 'Advanced technology and intellectual property in Nano and IT', Program for cultivation of people in new fields of study 'Upskilling program for Nano, IT, Bio - Intellectual Property Management Strategy', Promotion Budget for Science and Techno 

    Presentation date： 2005.05

  • Road map of the ｃomputer area

    H. Kasahara  [Invited]

    NEDO Electronics and Information Technology Road map Accomplishment Report Symposium 

    Presentation date： 2005.05

  • Multigrain Parallel Processing on Chip Multiprocessor

    Yasutaka Wada, Jun Shirako, Takamichi Miyamoto, Hirofumi Nakano, Takeshi Kodaka, Kazuhisa Ishizaka, Keiji Kimura, Hironori Kasahara

    EDS Fair 2005 

    Presentation date： 2005.01

  • Current and Future of Automatic Parallelizing Compilers

    H. Kasahara  [Invited]

    The 19th NEC HPC Forum 

    Presentation date： 2004.11

  • Developing World Fastest Compiler: Advanced Parallelizing Compiler Project

    H. Kasahara  [Invited]

    IBM Life Science Amagi Seminar 

    Presentation date： 2004.09

  • 150th ARC memorial special technical meeting(2), Panel: Future of Computer Architecture Research 'Development of high-value added Chip Multiprocessors by industry-government-academia collaboration'

    H. Kasahara  [Invited]

    150th IPSJ Special Interest Group on Computer Architecture 

    Presentation date： 2004.05

  • Evaluation of OSCAR Multigrain Automatic Parallelizing Compiler on IBM pSeries 690

    Kazuhisa Ishizaka, Jun Shirako, Motoki Obata, Keiji Kimura, Hironori Kasahara

    Kazuhisa Ishizaka, Jun Shirako, Motoki Obata, Keiji Kimura, Hironori Kasahara 

    Presentation date： 2004.03

  • Software Development on Large Parallel Supercomputers in Japan -- Parallelizing Compilers and Parallel Programming Language Projects --

    H. Kasahara  [Invited]

    Japan-U.S.A. Supercomputing Forum, The Engineering Academy of Japan Inc.(EAJ) 

    Presentation date： 2004.03

  • Millennium Project IT21 Advanced Parallelizing Compiler and Compiler Cooperative Chip Multiprocessor

    H. Kasahara  [Invited]

    The 4th VTC Seminar, NEC Soft 

    Presentation date： 2004.02

  • Millennium Project IT21 Advanced Parallelizing Compiler

    H. Kasahara  [Invited]

    Information Processing Society of Japan Kansai Branch 

    Presentation date： 2003.10

  • Millennium Project IT21 'Advanced Parallelizing Compiler' and Compiler Cooperative Chip Multiprocessor

    H. Kasahara  [Invited]

    The 2nd Super H Open Forum, Renesas Technology Corp. & Hitachi Ltd. 

    Presentation date： 2003.08

  • R&D Human Resource for Strengthening IT Competitive Power---From the experience of a Project Leader of METI Advanced Parallelizing Compiler Project and JEITA & STARC Industry, Government and Academia Cooperative Lectures---

    H. Kasahara  [Invited]

    METI Minister's Secretariat Sig. on R&D Human Resource for Innovation Systems 

    Presentation date： 2003.04

  • Multigrain Parallelizing Compiler for Chip Multiprocessors to High Performance Severs

    H. Kasahara  [Invited]

    Intel ICRC 

    Presentation date： 2002.10

  • NEDO-1 Advanced Parallelizing Technology

    H. Kasahara  [Invited]

    IPSJ-IEICE FIT2002 (Forum on Information Technology), National Project Introduction 

    Presentation date： 2002.09

  • Multigrain Automatic Parallelization in Japanese Millenium Project IT21 Advanced Parallelizing Compiler

    H. Kasahara, M. Obata, K. Ishizaka, K. Kimura, H. Kaminaga, H. Nakano, K. Nagasawa, A. Murai, H. Itagaki, J. Shirako  [Invited]

    Proc. of IEEE PARELEC (IEEE International Conference on Parallel Computing in Electrical Engineering) 

    Presentation date： 2002.09

  • OSCAR Multigrain Parallelizing Compiler for Chip Multiprocessors to High Performance Severs

    H. Kasahara  [Invited]

    Polish-Japanese Institute of Information Technology (PJIIT) hosted by Prof. Marek Tudruj 

    Presentation date： 2002.09

  • Multigrain Parallel Processing in Japanese Millennium Project IT21 'Advanced Parallelizing Compiler'

    H. Kasahara  [Invited]

    Distinguished Lecture ECE Graduate Seminar hosted by Prof. Rudolf Eigenmann 

    Presentation date： 2002.09

  • Performance of Multigrain Parallelization in Japanese Millennium Project IT21 'Advanced Parallelizing Compiler'

    H. Kasahara  [Invited]

    Computer Engineering Seminar hosted by Prof. David Padua 

    Presentation date： 2002.09

  • Multigrain Parallel Processing in Millennium Project IT21 Advanced Parallelizing Compiler

    H. Kasahara  [Invited]

    Sig. on Autonomous Distributed Systems 

    Presentation date： 2002.08

  • Multigrain Parallelization in Japanese Millennium Project IT21 'Advanced Parallelizing Compiler'

    H. Kasahara  [Invited]

    Chinese Academy of Science (ICT) 

    Presentation date： 2002.07

  • JPEG Encoding using Multigrain Parallel Processing on a Shingle Chip Multiprocessor

    Takeshi Kodaka, Takayuki Uchida, Keiji Kimura, Hironori Kasahara

    Joint Symposium on Parallel Processing 2002 (JSPP2002) 

    Presentation date： 2002.05

  • Automatic Parallelizing Compiler Cooperative Single Chip Multiprocessor

    Hironori Kasahara

    JEITA/EDS Fair 2002 

    Presentation date： 2002.01

  • Future of Automatic Parallelizing Compiler

    H. Kasahara  [Invited]

    The 14th International Workshop on Languages and Compilers for Parallel Computing (LCPC'01) Panel: Future of Languages and Compilers 

    Presentation date： 2001.08

  • OSCAR Single Chip Multiprocessor and Multigrain Parallelizing Compiler

    H. Kasahara  [Invited]

    IEEE International Workshop on Advanced Compiler Technology for High Performance and Embedded Systems (IWACT 2001) Panel : New Architecture and Their Compilers 

    Presentation date： 2001.07

  • A Data Transfer Unit on the Single Chip Multiprocessor for Multigrain Parallel Processing

    N. Miyashita, K. Kimura, T. Kodaka, H. Kasahar

    N. Miyashita, K. Kimura, T. Kodaka, H. Kasahar 

    Presentation date： 2001.03

  • Performance Evaluation of Single Chip Multiprocessor Memory Architecture for Near Fine Grain Parallel Processing

    N. Matsumoto, K. Kimura, H. Kasahara

    N. Matsumoto, K. Kimura, H. Kasahara 

    Presentation date： 2001.03

  • Near Fine Grain Parallel Processing on Multimedia Application for Single Chip Multiprocessor

    T. Kodaka, K. Kimura, N. Miyashita, H. Kasahara

    T. Kodaka, K. Kimura, N. Miyashita, H. Kasahara 

    Presentation date： 2001.03

  • Performance Evaluation of Preload-Poststore Scheduling Algorithm Considering Memory Capacity

    T. Tanaka, H. Funayama, T. Tobita, H. Kasahara

    T. Tanaka, H. Funayama, T. Tobita, H. Kasahara 

    Presentation date： 2001.03

  • A Static Scheduling Method for Coarse Grain Tasks considering Cache Optimization on Multiprocessor Systems

    H. Nakano, K. Ishizaka, M. Obata, K. Kimura, H. Kasahara

    H. Nakano, K. Ishizaka, M. Obata, K. Kimura, H. Kasahara 

    Presentation date： 2001.03

  • CPU Load Prediction on Hererogeneous Distributed Computing Environments Using dataFOREST Data-Mining Tool

    Y. Moda, T. Hayashi, H. Koike, T. Shikashima, H. Tsutsui, H. Kasahara

    Y. Moda, T. Hayashi, H. Koike, T. Shikashima, H. Tsutsui, H. Kasahara 

    Presentation date： 2001.03

  • Meta-Scheduling Method for Heterogeneous Distributed Environment Using OSCAR Fortran Multi-Grain Parallelizing Compiler

    T. Hayashi, Y. Moda, H. Koike, T. Tobita, H. Kasahara

    T. Hayashi, Y. Moda, H. Koike, T. Tobita, H. Kasahara 

    Presentation date： 2001.03

  • Performance Evaluation of Scheduling Algorithms with Data Transfer Using Standard Task Graph Set

    T. Yamaguchi, Y. Tanaka, T. Tobita, H. Kasahara

    T. Yamaguchi, Y. Tanaka, T. Tobita, H. Kasahara 

    Presentation date： 2001.03

  • OSCAR Multigrain Parallelizing Compiler and Single Chip Multiprocessor

    H. Kasahara  [Invited]

    Data Processing Center 

    Presentation date： 2001.03

  • Overview of METI/NEDO Millennium Project 'Advanced Parallelizing Compiler'

    H. Kasahara  [Invited]

    Japan Information Processing Development Center Research Institute for Advanced Information Technology 

    Presentation date： 2001.01

  • Multigrain Parallel Processing Model for Future Single Chip Multiprocessor Systems

    H. Kasahara  [Invited]

    ISHPC2000, Panel 'Programming Models for New Architectures' 

    Presentation date： 2000.10

  • OSCAR Multigrain Parallelizing Compiler and Single Chip Multiprocessor

    H. Kasahara  [Invited]

    University of Illinois at Urbana-Champaign, Hosted by Prof. David Padua 

    Presentation date： 2000.10

  • Moderator, Super-Panel 'Road to Petaflops'

    Hironori Kasahara  [Invited]

    IPSJ Millennium Memorial Symposium on Parallel Processing JSPP2000 

    Presentation date： 2000.06

  • IMPLEMENTATION OF RESOURCE INFORMATION SERVER FOR META-SCHEDULING

    Hiroshi KOIDE, Nobuhiro YAMAGISHI, Hiroshi TAKEMIYA, Takuya HAYASHI, Masayuki HIKITA, Hironori KASAHARA

    Hiroshi KOIDE, Nobuhiro YAMAGISHI, Hiroshi TAKEMIYA, Takuya HAYASHI, Masayuki HIKITA, Hironori KASAHARA 

    Presentation date： 2000.05

  • Performance Evaluation of Multiprocessor Scheduling Algorithms Using Standard Task Graph Set

    T. Tobita, H. Kasahara

    Joint Symposium on Parallel Processing 2000 (JSPP2000) 

    Presentation date： 2000.05

  • Performance Evaluation of Electronic Circuit Simulation which generate code without array indirect access

    K. Manaka, R. Osakabe, Y. Maekawa, H. Kasahara

    K. Manaka, R. Osakabe, Y. Maekawa, H. Kasahara 

    Presentation date： 2000.03

  • Parallel processing of hybrid FEM and BEM for electro magnetic field analysis on SMP machine

    D. Kaneko, M. Obata, S. Wakao, T. Onuki, H. Kasahara

    D. Kaneko, M. Obata, S. Wakao, T. Onuki, H. Kasahara 

    Presentation date： 2000.03

  • Performance Evaluation of Single Chip Multiprocessor for Near Fine Grain Parallel Processing

    T. Kato, W. Ogata, K. Kimura, T. Uchida, H. Kasahara

    T. Kato, W. Ogata, K. Kimura, T. Uchida, H. Kasahara 

    Presentation date： 2000.03

  • A Multiprocessor Scheduling Scheme Considering Memory Capacity with Data Preload

    T. Masuda, T. Tobita, H. Funayama, H. Kasahar

    T. Masuda, T. Tobita, H. Funayama, H. Kasahar 

    Presentation date： 2000.03

  • A Processor Clustering Decision Scheme for Hierarchical Parallel Processing in Multi-Grain Parallel Processing

    M. Yamamoto, T. Yamamoto, M. Obata, H. Kasahara

    M. Yamamoto, T. Yamamoto, M. Obata, H. Kasahara 

    Presentation date： 2000.03

  • Multi-Grain Parallelization using OpenMP

    K. Ishizaka, M. Obata, K. Taki, H. Kasahara

    K. Ishizaka, M. Obata, K. Taki, H. Kasahara 

    Presentation date： 2000.03

  • A Multi-grain Automatic Parallelizing Compilation Scheme with Analysis-time Procedure Inlining

    K. Yoshii, G. Matsui, M. Obata, S. Kumazawa, H. Kasahara

    K. Yoshii, G. Matsui, M. Obata, S. Kumazawa, H. Kasahara 

    Presentation date： 2000.03

  • A Data Localization Scheme for Any Macrotask Graphs with Data Dependencies

    Narikiyo, S. Yagi, H. Matsuzaki, M. Obata, A. Yoshida, H. Kasahara

    Narikiyo, S. Yagi, H. Matsuzaki, M. Obata, A. Yoshida, H. Kasahara 

    Presentation date： 2000.03

  • Distributed Parallel Scientific Computing Environment -SSP-

    Hiroshi TAKEMIYA, Hiroshi OHTA, Toshiyuki IMAMURA, Hiroshi KOIDE, Katsuyuki MATSUDA, Kenji HIGUCHI, Toshio HIRAYAMA, Hironori KASAHARA

    Hiroshi TAKEMIYA, Hiroshi OHTA, Toshiyuki IMAMURA, Hiroshi KOIDE, Katsuyuki MATSUDA, Kenji HIGUCHI, Toshio HIRAYAMA, Hironori KASAHARA 

    Presentation date： 1999.05

  • A Cache Optimization Scheme Using Earliest Executable Condition Analysis

    D. Inaishi, K. Kimura, K. Fujimoto, W. Ogata, M. Okamoto, H. Kasahara

    D. Inaishi, K. Kimura, K. Fujimoto, W. Ogata, M. Okamoto, H. Kasahara 

    Presentation date： 1999.03

  • An Automatic Parallelization Method for Overlapping of Macro Task Processing and Data Transfer

    M. Kogou, T. Tanaka, K. Fujimoto, M. Okamoto, H. Kasahara

    M. Kogou, T. Tanaka, K. Fujimoto, M. Okamoto, H. Kasahara 

    Presentation date： 1999.03

  • Meta-scheduling for a Supercomputer Cluster using OSCAR Fortran Multigrain Parallelizing Compiler

    A. Murasugi, T. Hayashi, T. Tobita, H. Koide, H. Kasahara

    A. Murasugi, T. Hayashi, T. Tobita, H. Koide, H. Kasahara 

    Presentation date： 1999.03

  • A Data-Localization Scheme for a Program with Subroutine in Multi-Grain Parallel Processing

    Y. Ujigawa, A. Narikiyo, M. Obata, A. Yoshida, M. Okamoto, H. Kasahara

    Y. Ujigawa, A. Narikiyo, M. Obata, A. Yoshida, M. Okamoto, H. Kasahara 

    Presentation date： 1999.03

  • A Hierarchical Parallel Processing Scheme in OSCAR Multi-Grain Parallelizing Fortran Compiler

    T. Yamamoto, D. Inaishi, Y. Ujigawa, M. Obata, M. Okamoto, H. Kasahara

    T. Yamamoto, D. Inaishi, Y. Ujigawa, M. Obata, M. Okamoto, H. Kasahara 

    Presentation date： 1999.03

  • OSCAR Scalable Multigrain Parallelizing Compiler for Single Chip Multiprocessors to A Cluster of Supercomputers

    H. Kasahara  [Invited]

    Hosted by Prof. David Padua, University of Illinois at Urbana-Champaign 

    Presentation date： 1998.10

  • A Data-Localization Scheme among Loops inside the Same Layer of Hierarchical Macro-Dataflow Processing

    A. Yoshida, K. Koshizuka, M. Okamoto, M. Obata, H. Kasahara

    Joint Symposium on Parallel Processing (JSPP'98) 

    Presentation date： 1998.06

  • Application and Evaluation of a Practical Parallel Optimiza