Concurrent Post
-
Faculty of Science and Engineering Graduate School of Fundamental Science and Engineering
-
Affiliated organization Global Education Center
Details of a Researcher
Updated on 2023/02/06
Faculty of Science and Engineering Graduate School of Fundamental Science and Engineering
Affiliated organization Global Education Center
Research Organization for Open Innovation Strategy Concurrent Researcher
Waseda Research Institute for Science and Engineering Concurrent Researcher
Center for Data Science Concurrent Researcher
Research Institute for Next-Gen Computing Director of Research Institute
Waseda University Graduate School of Science and Engineering Electrical Engieering
Waseda University Graduate School of Science and Engineering
Waseda University School of Science and Engineering
Waseda University Dr. Eng.
Waseda University Faculty of Science and Engineering
Waseda University Faculty of Science and Engineering
Waseda University Faculty of Science and Engineering
The University of Kitakyushu Faculty of Environmental Engineering
Waseda University Advanced Research Institute for Science and Engineering
Waseda University School of Science and Engineering
ACM
IEEE
情報処理学会
電子情報通信学会
Information security
Computer system
information security
integrated system design
LSI design technology for integrated systems that realizes ultralow energy
Information Communication
Elucidating the vulnerability of IC cards and establishing countermeasures
Information Communication
Chemical Health Monitor Kind to Skin
Life sciences
Hybrid Annealing Method Based on subQUBO Model Extraction With Multiple Solution Instances.
Yuta Atobe, Masashi Tawada, Nozomu Togawa
IEEE Transactions on Computers 71 ( 10 ) 2606 - 2619 2022 [Refereed]
Hardware-Trojan Detection Based on the Structural Features of Trojan Circuits Using Random Forests.
Tatsuki Kurihara, Nozomu Togawa
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 105-A ( 7 ) 1049 - 1060 2022 [Refereed]
QUBO Matrix Distorting Method for Consumer Applications.
Tomokazu Yoshimura, Tatsuhiko Shirai, Masashi Tawada, Nozomu Togawa
ICCE 1 - 6 2022 [Refereed]
Efficient Coefficient Bit-Width Reduction Method for Ising Machines.
Yuta Yachi, Yousuke Mukasa, Masashi Tawada, Nozomu Togawa
ICCE 1 - 6 2022 [Refereed]
A PDR Method Using Smartglasses Reducing Accumulated Errors by Detecting User's Stop Motions.
Dai Sato, Nozomu Togawa
ICCE 1 - 2 2022 [Refereed]
Carrying-mode Free Indoor Positioning Using Smartphone and Smartwatch and Its Evaluations.
Tomoya Wakaizumi, Nozomu Togawa
J. Inf. Process. 30 52 - 65 2022 [Refereed]
Kazunari Takasaki, Ryoichi Kida, Nozomu Togawa
Proceedings - 2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design, IOLTS 2021 1 - 7 2021.06 [Refereed]
Hardware-trojan classification based on the structure of trigger circuits utilizing random forests
Tatsuki Kurihara, Nozomu Togawa
Proceedings - 2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design, IOLTS 2021 1 - 4 2021.06 [Refereed]
Data Augmentation for Machine Learning-Based Hardware Trojan Detection at Gate-Level Netlists
Kento Hasegawa, Seira Hidano, Kohei Nozawa, Shinsaku Kiyomoto, Nozomu Togawa
Proceedings - 2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design, IOLTS 2021 1 - 4 2021.06 [Refereed]
An Approach to the Vehicle Routing Problem with Balanced Pick-up Using Ising Machines
Siya Bao, Masashi Tawada, Shu Tanaka, Nozomu Togawa
2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings 2021.04 [Refereed]
Natsuhito Yoshimura, Masashi Tawada, Shu Tanaka, Junya Arai, Satoshi Yagi, Hiroyuki Uchiyama, Nozomu Togawa
IEICE Transactions on Information and Systems E104.D ( 4 ) 481 - 489 2021.04 [Refereed]
Solving constrained slot placement problems using an ising machine and its evaluations
Sho Kanamaru, Kazushi Kawamura, Shu Tanaka, Yoshinori Tomita, Nozomu Togawa
IEICE Transactions on Information and Systems E104D ( 2 ) 226 - 236 2021.02 [Refereed]
An Indoor Positioning Method using Smartphone and Smartwatch Independent of Carrying Modes
Tomoya Wakaizumi, Nozomu Togawa
Digest of Technical Papers - IEEE International Conference on Consumer Electronics 2021-January 2021.01 [Refereed]
Visiting-Route Recommendation in Amusement Parks and its Evaluations by an Ising Machine
Yosuke Mukasa, Tomoya Wakaizumi, Shu Tanaka, Nozomu Togawa
Digest of Technical Papers - IEEE International Conference on Consumer Electronics 2021-January 1 - 6 2021.01 [Refereed]
Shota Matsuno, Masashi Tawada, Nozomu Togawa
Digest of Technical Papers - IEEE International Conference on Consumer Electronics 2021-January 1 - 6 2021.01 [Refereed]
Multi-day Travel Planning Using Ising Machines for Real-world Applications.
Siya Bao, Masashi Tawada, Shu Tanaka, Nozomu Togawa
24th IEEE International Intelligent Transportation Systems Conference(ITSC) 3704 - 3709 2021 [Refereed]
A PDR Method Combining Smartphone and Smartwatch based on Multi-Scenario Map Matching.
Tomoya Wakaizumi, Nozomu Togawa
GCCE 308 - 309 2021 [Refereed]
An autonomous driving system utilizing image processing accelerated by FPGA.
Kazunari Takasaki, Kota Hisafuru, Ryotaro Negishi, Kazuki Yamashita, Keisuke Fukada, Tomoya Wakaizumi, Nozomu Togawa
FPT 1 - 4 2021 [Refereed]
Toward Learning Robust Detectors from Imbalanced Datasets Leveraging Weighted Adversarial Training.
Kento Hasegawa, Seira Hidano, Shinsaku Kiyomoto, Nozomu Togawa
CANS 392 - 411 2021 [Refereed]
A Three-Stage Annealing Method Solving Slot-Placement Problems Using an Ising Machine.
Keisuke Fukada, Matthieu Parizy, Yoshinori Tomita, Nozomu Togawa
IEEE Access 9 134413 - 134426 2021 [Refereed]
Experimental evaluations of parallel tempering on an ising machine
Yosuke Mukasa, Shu Tanaka, Nozomu Togawa
IPSJ Transactions on System LSI Design Methodology 14 27 - 29 2021 [Refereed]
Performance Comparison of Typical Binary-Integer Encodings in an Ising Machine
Kensuke Tamura, Tatsuhiko Shirai, Hosho Katsura, Shu Tanaka, Nozomu Togawa
IEEE Access 9 81032 - 81039 2021 [Refereed]
Generating adversarial examples for hardware-trojan detection at gate-level netlists
Kohei Nozawa, Kento Hasegawa, Seira Hidano, Shinsaku Kiyomoto, Kazuo Hashimoto, Nozomu Togawa
Journal of Information Processing 29 236 - 246 2021 [Refereed]
Yuta Ishizaki, Yurie Koyama, Toshinori Takayama, Nozomu Togawa
Journal of Information Processing 29 81 - 92 2021 [Refereed]
A capacitance measurement device for running hardware devices and its evaluations
Makoto Nishizawa, Kento Hasegawa, Nozomu Togawa
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E103A ( 9 ) 1018 - 1027 2020.09 [Refereed]
Trojan-net classification for gate-level hardware design utilizing boundary net structures
Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
IEICE Transactions on Information and Systems E103D ( 7 ) 1618 - 1622 2020.07 [Refereed]
Kazunari Takasaki, Kento Hasegawa, Ryoichi Kida, Nozomu Togawa
Proceedings - 2020 26th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2020 1 - 4 2020.07 [Refereed]
Evaluation on Hardware-Trojan Detection at Gate-Level IP Cores Utilizing Machine Learning Methods
Tatsuki Kurihara, Kento Hasegawa, Nozomu Togawa
Proceedings - 2020 26th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2020 1 - 4 2020.07 [Refereed]
Masashi Tawada, Nozomu Togawa
NEWCAS 2020 - 18th IEEE International New Circuits and Systems Conference, Proceedings 271 - 274 2020.06 [Refereed]
Siya Bao, Nozomu Togawa
Proceedings - 14th IEEE International Conference on Semantic Computing, ICSC 2020 311 - 314 2020.02 [Refereed]
Multi-Resolutional Image Format Using Stochastic Numbers and Its Hardware Implementation
Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020 1 - 4 2020.02 [Refereed]
Adversarial examples for hardware-trojan detection at gate-level netlists
Kohei Nozawa, Kento Hasegawa, Seira Hidano, Shinsaku Kiyomoto, Kazuo Hashimoto, Nozomu Togawa
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 11980 LNCS 341 - 359 2020 [Refereed]
How to Reduce the Bit-width of an Ising Model by Adding Auxiliary Spins
Daisuke Oku, Masashi Tawada, Shu Tanaka, Nozomu Togawa
IEEE Transactions on Computers 71 ( 1 ) 223 - 234 2020 [Refereed]
Guiding Principle for Minor-Embedding in Simulated-Annealing-Based Ising Machines
Tatsuhiko Shirai, Shu Tanaka, Nozomu Togawa
IEEE Access 8 210490 - 210502 2020 [Refereed]
A new LDPC code decoding method: Expanding the scope of ising machines
Masashi Tawada, Shu Tanaka, Nozomu Togawa
Digest of Technical Papers - IEEE International Conference on Consumer Electronics 2020-January 1 - 6 2020.01 [Refereed]
Theory of Ising Machines and a Common Software Platform for Ising Machines
Shu Tanaka, Yoshiki Matsuda, Nozomu Togawa
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 2020-January 659 - 666 2020.01 [Refereed]
FPGA-based Heterogeneous Solver for Three-Dimensional Routing
Kento Hasegawa, Ryota Ishikawa, Makoto Nishizawa, Kazushi Kawamura, Masashi Tawada, Nozomu Togawa
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 2020-January 11 - 12 2020.01 [Refereed]
Scalable stochastic number duplicators for accuracy-flexible arithmetic circuit design
Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
IPSJ Transactions on System LSI Design Methodology 13 10 - 20 2020 [Refereed]
A travel decision support algorithm: Landmark activity extraction from japanese travel comments
Siya Bao, Masao Yanagisawa, Nozomu Togawa
Studies in Computational Intelligence 849 109 - 123 2020 [Refereed]
Implementation of a ROS-Based Autonomous Vehicle on an FPGA Board
Kento Hasegawa, Kazunari Takasaki, Makoto Nishizawa, Ryota Ishikawa, Kazushi Kawamura, Nozomu Togawa
2019 International Conference on Field-Programmable Technology (ICFPT) 2019.12
Yuri Usami, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
IEICE Transactions 102-A ( 8 ) 953 - 965 2019 [Refereed]
Jinghao Ye, Nozomu Togawa, Masao Yanagisawa, Youhua Shi
IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, May 26-29, 2019 2019-May 1 - 4 2019 [Refereed]
Efficient Ising Model Mapping to Solving Slot Placement Problem.
Sho Kanamaru, Daisuke Oku, Masashi Tawada, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa
IEEE International Conference on Consumer Electronics, ICCE 2019, Las Vegas, NV, USA, January 11-13, 2019 1 - 6 2019 [Refereed]
An FPGA Implementation Method based on Distributed-register Architectures.
Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
IPSJ Trans. System LSI Design Methodology 12 38 - 41 2019 [Refereed]
Sae Iwata, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
IEICE Transactions 102-A ( 6 ) 860 - 865 2019 [Refereed]
Tensei Nishimura, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
IEICE Transactions 102-A ( 4 ) 641 - 653 2019 [Refereed]
Personalized landmark recommendation algorithm based on language-specific satisfaction prediction using heterogeneous open data sources
Siya Bao, Masao Yanagisawa, Nozomu Togawa
Proceedings - 2018 10th International Conference on Computational Intelligence and Communication Networks, CICN 2018 70 - 76 2018.08
Robust AES circuit design for delay variation using suspicious timing error prediction
Yuki Yahagi, Masao Yanagisawa, Nozomu Togawa
Proceedings - International SoC Design Conference 2017, ISOCC 2017 101 - 102 2018.05 [Refereed]
A selector-based FFT processor and its FPGA implementation
Yuya Hirai, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
Proceedings - International SoC Design Conference 2017, ISOCC 2017 88 - 89 2018.05 [Refereed]
A loop structure optimization targeting high-level synthesis of fast number theoretic transform
Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
Proceedings - International Symposium on Quality Electronic Design, ISQED 2018- 106 - 111 2018.05 [Refereed]
Sae Iwata, Tomoyuki Nitta, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E101A ( 5 ) 831 - 843 2018.05 [Refereed]
A hardware-Trojan classification method utilizing boundary net structures
Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
2018 IEEE International Conference on Consumer Electronics, ICCE 2018 2018- 1 - 4 2018.03 [Refereed]
Road-illuminance level inference across road networks based on Bayesian analysis
Siya Bao, Masao Yanagisawa, Nozomu Togawa
2018 IEEE International Conference on Consumer Electronics, ICCE 2018 2018- 1 - 6 2018.03 [Refereed]
Daisuke Oku, Masao Yanagisawa, Nozomu Togawa
IPSJ Transactions on System LSI Design Methodology 11 16 - 28 2018.02 [Refereed]
Designing hardware trojans and their detection based on a SVM-based approach
Tomotaka Inoue, Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
Proceedings of International Conference on ASIC 2017- 811 - 814 2018.01 [Refereed]
A low cost and high speed CSD-based symmetric transpose block FIR implementation
Jinghao Ye, Youhua Shi, Nozomu Togawa, Masao Yanagisawa
Proceedings of International Conference on ASIC 2017- 311 - 314 2018.01 [Refereed]
Daiki Asai, Masao Yanagisawa, Nozomu Togawa
Proceedings of International Conference on ASIC 2017- 64 - 67 2018.01 [Refereed]
Soft error tolerant latch designs with low power consumption (invited paper)
Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi
Proceedings of International Conference on ASIC 2017- 52 - 55 2018.01 [Refereed]
Detecting the Existence of Malfunctions in Microcontrollers Utilizing Power Analysis.
Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
24th IEEE International Symposium on On-Line Testing And Robust System Design, IOLTS 2018, Platja D'Aro, Spain, July 2-4, 2018 97 - 102 2018 [Refereed]
An Effective Stochastic Number Duplicator and Its Evaluations Using Composite Arithmetic Circuits.
Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
24th IEEE International Symposium on On-Line Testing And Robust System Design, IOLTS 2018, Platja D'Aro, Spain, July 2-4, 2018 53 - 56 2018 [Refereed]
Hardware Trojan Detection Utilizing Machine Learning Approaches.
Kento Hasegawa, Youhua Shi, Nozomu Togawa
17th IEEE International Conference On Trust, Security And Privacy In Computing And Communications / 12th IEEE International Conference On Big Data Science And Engineering, TrustCom/BigDataSE 2018, New York, NY, USA, August 1-3, 2018 1891 - 1896 2018 [Refereed]
An Ising model mapping to solve rectangle packing problem.
Kotaro Terada, Daisuke Oku, Sho Kanamaru, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa
2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 16-19, 2018 1 - 4 2018 [Refereed]
A Relaxed Bit-Write-Reducing and Error-Correcting Code for Non-Volatile Memories.
Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
IEICE Transactions 101-A ( 7 ) 1045 - 1052 2018 [Refereed]
A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element.
Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi
IEICE Transactions 101-A ( 7 ) 1025 - 1034 2018 [Refereed]
Extension and Performance/Accuracy Formulation for Optimal GeAr-Based Approximate Adder Designs.
Ken Hayamizu, Nozomu Togawa, Masao Yanagisawa, Youhua Shi
IEICE Transactions 101-A ( 7 ) 1014 - 1024 2018 [Refereed]
Stochastic Number Duplicators Based on Bit Re-Arrangement Using Randomized Bit Streams.
Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
IEICE Transactions 101-A ( 7 ) 1002 - 1013 2018 [Refereed]
A Multiple Cyclic-Route Generation Method for Strolling Based on Point-of-Interests.
Tensei Nishimura, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
8th IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2018, Berlin, Germany, September 2-5, 2018 1 - 2 2018 [Refereed]
Robust Indoor/Outdoor Detection Method based on Sparse GPS Positioning Information.
Sae Iwata, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
8th IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2018, Berlin, Germany, September 2-5, 2018 1 - 4 2018 [Refereed]
Designing Subspecies of Hardware Trojans and Their Detection Using Neural Network Approach.
Tomotaka Inoue, Kento Hasegawa, Yuki Kobayashi, Masao Yanagisawa, Nozomu Togawa
8th IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2018, Berlin, Germany, September 2-5, 2018 1 - 4 2018 [Refereed]
Landmark Seasonal Travel Distribution and Activity Prediction Based on Language-specific Analysis.
Siya Bao, Masao Yanagisawa, Nozomu Togawa
IEEE International Conference on Big Data, Big Data 2018, Seattle, WA, USA, December 10-13, 2018 3628 - 3637 2018 [Refereed]
Makoto Nishizawa, Kento Hasegawa, Nozomu Togawa
2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, Chengdu, China, October 26-30, 2018 362 - 365 2018 [Refereed]
Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
IEICE Transactions 101-A ( 12 ) 2320 - 2326 2018 [Refereed]
Ryoya Momose, Tomoyuki Nitta, Masao Yanagisawa, Nozomu Togawa
2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017 2017- 1 - 5 2017.12 [Refereed]
A stayed location estimation method for sparse GPS positioning information
Sae Iwata, Tomoyuki Nitta, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017 2017- 1 - 5 2017.12 [Refereed]
Personalized one-day travel with multi-nearby-landmark recommendation
Siya Bao, Masao Yanagisawa, Nozomu Togawa
IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2017- 239 - 242 2017.12 [Refereed]
A robust scan-based side-channel attack method against HMAC-SHA-256 circuits
Daisuke Oku, Masao Yanagisawa, Nozomu Togawa
IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2017- 79 - 84 2017.12 [Refereed]
A bitwidth-aware high-level synthesis algorithm using operation chainings for tiled-DR architectures
Kotaro Terada, Masao Yanagisawa, Nozomu Togawa
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E100A ( 12 ) 2911 - 2924 2017.12 [Refereed]
Siya Bao, Tomoyuki Nitta, Masao Yanagisawa, Nozomu Togawa
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E100A ( 11 ) 2439 - 2450 2017.11 [Refereed]
Effective write-reduction method for MLC non-volatile memory
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
Proceedings - IEEE International Symposium on Circuits and Systems 1 - 4 2017.09 [Refereed]
Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
Proceedings - IEEE International Symposium on Circuits and Systems 1 - 4 2017.09 [Refereed]
Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
Proceedings - IEEE International Symposium on Circuits and Systems 100-A ( 12 ) 2857 - 2868 2017.09 [Refereed]
Hardware Trojans classification for gate-level netlists using multi-layer neural networks
Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017 227 - 232 2017.09 [Refereed]
Hardware Trojan detection and classification based on steady state learning
Masaru Oya, Masao Yanagisawa, Nozomu Togawa
2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017 215 - 220 2017.09 [Refereed]
A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation
Koki Igawa, Masao Yanagisawa, Nozomu Togawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E100A ( 7 ) 1439 - 1451 2017.07 [Refereed]
Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E100A ( 7 ) 1427 - 1438 2017.07 [Refereed]
Efficient Multiplexer Networks for Field-Data Extractors and Their Evaluations
Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E100A ( 4 ) 1015 - 1028 2017.04 [Refereed]
Message from the Editor-in-Chief.
Nozomu Togawa
IPSJ Trans. System LSI Design Methodology 10 1 2017 [Refereed]
Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E99A ( 12 ) 2398 - 2411 2016.12 [Refereed]
A Highly-Adaptable and Small-Sized In-Field Power Analyzer for Low-Power IoT Devices
Ryosuke Kitayama, Takashi Takenaka, Masao Yanagisawa, Nozomu Togawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E99A ( 12 ) 2348 - 2362 2016.12 [Refereed]
Masaru Oya, Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo, Masao Yanagisawa, Nozomu Togawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E99A ( 12 ) 2335 - 2347 2016.12 [Refereed]
Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms
Koki Igawa, Masao Yanagisawa, Nozomu Togawa
IEICE ELECTRONICS EXPRESS 13 ( 18 ) 20160641 2016.09 [Refereed]
Bi-Partitioning Based Multiplexer Network for Field-Data Extractors
Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E99A ( 7 ) 1410 - 1414 2016.07 [Refereed]
Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E99A ( 7 ) 1294 - 1310 2016.07 [Refereed]
A Multi-Scenario High-Level Synthesis Algorithm for Variation-Tolerant Floorplan-Driven Design
Koki Igawa, Masao Yanagisawa, Nozomu Togawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E99A ( 7 ) 1278 - 1293 2016.07 [Refereed]
Indoor Navigation Based on Real-time Direction Information Generation Using Wearable Glasses
Ryota Iwanaji, Tomoyuki Nitta, Kazuaki Ishikawa, Masao Yanagisawa, Nozomu Togawa
2016 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS-ASIA (ICCE-ASIA) 2016 [Refereed]
A High-level Synthesis Algorithm for FPGA Designs Optimizing Critical Path with Interconnection-delay and Clock-skew Consideration
Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2016 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT) 2016 [Refereed]
Rotator-Based Multiplexer Network Synthesis for Field-Data Extractors
Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa
2016 29TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC) 194 - 199 2016 [Refereed]
In-situ Trojan Authentication for Invalidating Hardware-Trojan Functions
Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
PROCEEDINGS OF THE SEVENTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN ISQED 2016 152 - 157 2016 [Refereed]
A Delay Variation and Floorplan Aware High-level Synthesis Algorithm with Body Biasing
Koki Igawa, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
PROCEEDINGS OF THE SEVENTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN ISQED 2016 75 - 80 2016 [Refereed]
A High-performance Circuit Design Algorithm using Data Dependent Approximation
Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) 95 - 96 2016 [Refereed]
Hash-Table and Balanced-Tree Based FIB Architecture for CCN Routers
Kenta Shimazaki, Takashi Aoki, Takahiro Hatano, Takuya Otsuka, Akihiko Miyazaki, Toshitaka Tsuda, Nozomu Togawa
2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) 67 - 68 2016 [Refereed]
Ryosuke Kitayama, Takashi Takenaka, Masao Yanagisawa, Nozomu Togawa
2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) 978 - 981 2016 [Refereed]
Redesign for Untrusted Gate-level Netlists
Masaru Oya, Masao Yanagisawa, Nozomu Togawa
2016 IEEE 22ND INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS) 219 - 220 2016 [Refereed]
Hardware Trojans Classification for Gate-level Netlists based on Machine Learning
Kento Hasegawa, Masaru Oya, Masao Yanagisawa, Nozomu Togawa
2016 IEEE 22ND INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS) 203 - 206 2016 [Refereed]
Pedestrian Navigation Based on Landmark Recognition Using Glass-type Wearable Devices
Ryoya Yano, Tomoyuki Nitta, Kazuaki Ishikawa, Masao Yanagisawa, Nozomu Togawa
2016 IEEE 5TH GLOBAL CONFERENCE ON CONSUMER ELECTRONICS 1 - 2 2016 [Refereed]
Keisuke Kono, Tomoyuki Nitta, Kazuaki Ishikawa, Masao Yanagisawa, Nozomu Togawa
2016 IEEE 5TH GLOBAL CONFERENCE ON CONSUMER ELECTRONICS 1 - 2 2016 [Refereed]
A Safe and Comprehensive Route Finding Method for Pedestrian Based on Lighting and Landmark
Siya Bao, Tomoyuki Nitta, Kazuaki Ishikawa, Masao Yanagisawa, Nozomu Togawa
2016 IEEE 5TH GLOBAL CONFERENCE ON CONSUMER ELECTRONICS 1 - 5 2016 [Refereed]
Implementation Evaluation of Scan-based Attack against a Trivium Cipher Circuit
Daisuke Oku, Masao Yanagisawa, Nozomu Togawa
2016 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS) 220 - 223 2016 [Refereed]
Scan-Based Side-Channel Attack on the Camellia Block Cipher Using Scan Signatures
Huiqian Jiang, Mika Fujishiro, Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E98A ( 12 ) 2547 - 2555 2015.12 [Refereed]
A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists
Masaru Oya, Youhua Shi, Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo, Satoshi Goto, Masao Yanagisawa, Nozomu Togawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E98A ( 12 ) 2537 - 2546 2015.12 [Refereed]
ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E98A ( 12 ) 2494 - 2504 2015.12 [Refereed]
Code Generation Limiting Maximum and Minimum Hamming Distances for Non-Volatile Memories
Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E98A ( 12 ) 2484 - 2493 2015.12 [Refereed]
An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead
Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E98A ( 7 ) 1406 - 1418 2015.07 [Refereed]
A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs
Koichi Fujiwara, Kazushi Kawamura, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E98A ( 7 ) 1392 - 1405 2015.07 [Refereed]
Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E98A ( 7 ) 1376 - 1391 2015.07 [Refereed]
Kotaro Terada, Masao Yanagisawa, Nozomu Togawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E98A ( 7 ) 1366 - 1375 2015.07 [Refereed]
Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating
Akasaka Hiroyuki, Abe Shin-ya, Yanagisawa Masao, Togawa Nozomu
IMT 10 ( 1 ) 1 - 7 2015
Fast source optimization by clustering algorithm based on lithography properties
Masashi Tawada, Takaki Hashimoto, Keishi Sakanushi, Shigeki Nojima, Toshiya Kotani, Masao Yanagisawa, Nozomu Togawa
DESIGN-PROCESS-TECHNOLOGY CO-OPTIMIZATION FOR MANUFACTURABILITY IX 9427 2015 [Refereed]
A Floorplan-Aware High-Level Synthesis Technique with Delay-Variation Tolerance
Kazushi Kawamura, Yuta Hagio, Youhua Shi, Nozomu Togawa
PROCEEDINGS OF THE 2015 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC) 122 - 125 2015 [Refereed]
Scan-based Side-channel Attack against Symmetric Key Ciphers Using Scan Signatures
Mika Fujishiro, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
PROCEEDINGS OF THE 2015 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC) 309 - 312 2015 [Refereed]
Partitioning-Based Multiplexer Network Synthesis for Field-Data Extractors
Koki Ito, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa
2015 28TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC) 263 - 268 2015 [Refereed]
Koki Igawa, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2015 28TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC) 7 - 12 2015 [Refereed]
Kotaro Terada, Masao Yanagisawa, Nozomu Togawa
2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) 2129 - 2132 2015 [Refereed]
Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2015 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) 682 - 689 2015 [Refereed]
Effective Parallel Algorithm for GPGPU-Accelerated Explicit Routing Optimization
Ko Kikuta, Eiji Oki, Naoaki Yamanaka, Nozomu Togawa, Hidenori Nakazato
2015 IEEE GLOBAL COMMUNICATIONS CONFERENCE (GLOBECOM) 1 - 6 2015 [Refereed]
A Landmark-based Route Recommendation Method for Pedestrian Walking Strategies
Siya Bao, Tomoyuki Nitta, Daisuke Shindou, Masao Yanagisawa, Nozomu Togawa
2015 IEEE 4TH GLOBAL CONFERENCE ON CONSUMER ELECTRONICS (GCCE) 672 - 673 2015 [Refereed]
A Visible Corner-Landmark Based Route Finding Algorithm for Pedestrian Navigation
Kengo Takeda, Tomoyuki Nitta, Daisuke Shindou, Masao Yanagisawa, Nozomu Togawa
2015 IEEE 4TH GLOBAL CONFERENCE ON CONSUMER ELECTRONICS (GCCE) 601 - 602 2015 [Refereed]
A Score-Based Classification Method for Identifying Hardware-Trojans at Gate-Level Netlists
Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE) 465 - 470 2015 [Refereed]
A Bit-Write Reduction Method based on Error-Correcting Codes for Non-Volatile Memories
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
2015 20TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC) 496 - 501 2015 [Refereed]
Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) 1 - 4 2015 [Refereed]
A low-power soft error tolerant latch scheme
Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa
PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) 1 - 4 2015 [Refereed]
Small-Sized and Noise-Reducing Power Analyzer Design for Low-Power IoT Devices
Ryosuke Kitayama, Takashi Takenaka, Masao Yanagisawa, Nozomu Togawa
PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) 1 - 4 2015 [Refereed]
Image Synthesis Circuit Design Using Selector-logic-based Alpha Blending and Its FPGA Implementation
Keita Igarashi, Masao Yanagisawa, Nozomu Togawa
PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) 1 - 4 2015 [Refereed]
Clock Skew Estimate Modeling for FPGA High-level Synthesis and Its Application
Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) 1 - 4 2015 [Refereed]
Scan-Based Side-Channel Attack on the LED Block Cipher Using Scan Signatures
Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E97A ( 12 ) 2434 - 2442 2014.12 [Refereed]
Scan-Based Attack against Trivium Stream Cipher Using Scan Signatures
Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E97A ( 7 ) 1444 - 1451 2014.07 [Refereed]
A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures
Hagio Yuta, Yanagisawa Masao, Togawa Nozomu
IMT 9 ( 4 ) 446 - 455 2014
Throughput Driven Check Point Selection in Suspicious Timing Error Prediction based Designs
Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2014 IEEE 5TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS (LASCAS) 1 - 4 2014 [Refereed]
Scan-based Attack on the LED Block Cipher Using Scan Signatures
Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa
2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) 1460 - 1463 2014 [Refereed]
Linear and Bi-linear Interpolation Circuits Selector Logics and their Evaluations
Masashi Shio, Masao Yanagisawa, Nozomu Togawa
2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) 1436 - 1439 2014 [Refereed]
In-situ Timing Monitoring Methods for Variation-Resilient Designs
Youhua Shi, Nozomu Togawa
2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS) 735 - 738 2014 [Refereed]
Secure scan design using improved random order and its evaluations
Masaru Oya, Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS) 555 - 558 2014 [Refereed]
A Write-Reducing and Error-Correcting Code Generation Method for Non-Volatile Memories
Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS) 304 - 307 2014 [Refereed]
An Area-Overhead-Oriented Monitoring-Path Selection Algorithm for Suspicious Timing Error Prediction
Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS) 300 - 303 2014 [Refereed]
Scan-based Side-Channel Attack on Camellia Cipher Using Scan Signatures
Huiqian Jiang, Mika Fujishiro, Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa
2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS) 252 - 255 2014 [Refereed]
Kotaro Terada, Masao Yanagisawa, Nozomu Togawa
2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS) 248 - 251 2014 [Refereed]
A Floorplan-Aware High-level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs
Koichi Fujiwara, Shinya Abe, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS) 244 - 247 2014 [Refereed]
A delay-variation-aware high-level synthesis algorithm for RDR architectures
Yuta Hagio, Masao Yanagisawa, Nozomu Togawa
IPSJ Transactions on System LSI Design Methodology 7 81 - 90 2014 [Refereed]
Energy-efficient high-level synthesis for HDR architecture with multi-stage clock gating
Hiroyuki Akasaka, Shin-Ya Abe, Masao Yanagisawa, Nozomu Togawa
IPSJ Transactions on System LSI Design Methodology 7 74 - 80 2014 [Refereed]
Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E96A ( 12 ) 2597 - 2611 2013.12 [Refereed]
A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches
Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E96A ( 6 ) 1283 - 1292 2013.06 [Refereed]
Scan-based Attack against DES and Triple DES Cryptosystems Using Scan Signatures
Kodera Hirokazu, Yanagisawa Masao, Togawa Nozomu
IMT 8 ( 3 ) 867 - 874 2013
Akasaka Hiroyuki, Abe Shin-ya, Yanagisawa Masao, Togawa Nozomu
IMT 8 ( 4 ) 913 - 923 2013
An Energy-efficient High-level Synthesis Algorithm Incorporating Interconnection Delays and Dynamic Multiple Supply Voltages
Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT) 2013 [Refereed]
High-Level Synthesis with Post-Silicon Delay Tuning for RDR Architectures
Yuta Hagio, Masao Yanagisawa, Nozomu Togawa
2013 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) 194 - 197 2013 [Refereed]
Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT) 1 - 4 2013 [Refereed]
Secure scan design with dynamically configurable connection
Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 256 - 262 2013 [Refereed]
Suspicious Timing Error Prediction with In-Cycle Clock Gating
Youhua Shi, Hiroaki Igarashi, Nozomu Togawa, Masao Yanagisawa
PROCEEDINGS OF THE FOURTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2013) 335 - 340 2013 [Refereed]
A partial redundant fault-secure high-level synthesis algorithm for RDR architectures
Kazushi Kawamura, Sho Tanaka, Masao Yanagisawa, Nozomu Togawa
Proceedings - IEEE International Symposium on Circuits and Systems 1736 - 1739 2013 [Refereed]
Concurrent Faulty Clock Detection for Crypto Circuits against Clock Glitch based DFA
Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) 1432 - 1435 2013 [Refereed]
Energy Evaluation for Two-level On-chip Cache with Non-Volatile Memory on Mobile Processors
Shota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa, Tadahiko Sugibayashi
2013 IEEE 10TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) 1 - 4 2013 [Refereed]
Scan-based Attack against Trivium Stream Cipher Independent of Scan Structure
Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa
2013 IEEE 10TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) 1 - 4 2013 [Refereed]
Scan-based attack against DES and Triple DES cryptosystems using scan signatures
Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa
Journal of Information Processing 21 ( 3 ) 572 - 579 2013 [Refereed]
Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
IPSJ Trans. System LSI Design Methodology 6 101 - 111 2013 [Refereed]
A thermal-aware high-level synthesis algorithm for RDR architectures through binding and allocation
Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E96-A ( 1 ) 312 - 321 2013 [Refereed]
Scan-Based Attack on AES through Round Registers and Its Countermeasure
Youhua Shi, Nozomu Togawa, Masao Yanagisawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E95A ( 12 ) 2338 - 2346 2012.12 [Refereed]
Seungju Lee, Masao Yanagisawa, Nozomu Togawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E95A ( 9 ) 1538 - 1549 2012.09 [Refereed]
Energy-efficient High-level Synthesis for HDR Architectures
Abe Shin-ya, Yanagisawa Masao, Togawa Nozomu
IMT 7 ( 4 ) 1319 - 1330 2012
Dynamically Changeable Secure Scan Architecture against Scan-Based Side Channel Attack
Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2012 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) 155 - 158 2012 [Refereed]
Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating
Hiroyuki Akasaka, Masao Yanagisawa, Nozomu Togawa
2012 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) 135 - 138 2012 [Refereed]
A Novel BMNoC Configuration Algorithm Utilizing Communication Volume and Locality among Cores
Seungju Lee, Nozomu Togawa, Takashi Aoki, Akira Onozawa
2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012) 1668 - 1671 2012 [Refereed]
Shin-ya Abet, Masao Yanagisawa, Nozomu Togawat
2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012) 576 - 579 2012 [Refereed]
Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2012 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS) 607 - 610 2012 [Refereed]
Weighted Adders with Selector Logics for Super-resolution and Its FPGA-based Evaluation
Hiromine Yoshihara, Masao Yanagisawa, Nozomu Togawa
2012 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS) 603 - 606 2012 [Refereed]
Scan-based Attack against DES Cryptosystems Using Scan Signatures
Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa
2012 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS) 599 - 602 2012 [Refereed]
A Hybrid NoC Architecture Utilizing Packet Transmission Priority Control Method
Seungju Lee, Nozomu Togawa, Yusuke Sekihara, Takashi Aoki, Akira Onozawa
2012 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS) 404 - 407 2012 [Refereed]
Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 20 ( 1 ) 176 - 181 2012.01 [Refereed]
Energy-efficient high-level synthesis for HDR architectures
Shin-Ya Abe, Masao Yanagisawa, Nozomu Togawa
IPSJ Transactions on System LSI Design Methodology 5 106 - 117 2012 [Refereed]
A fastweighted adder by reducing partial product for reconstruction in super-resolution
Hiromine Yoshihara, Masao Yanagisawa, Nozomu Togawa
IPSJ Transactions on System LSI Design Methodology 5 96 - 105 2012 [Refereed]
Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
IEICE ELECTRONICS EXPRESS 9 ( 17 ) 1414 - 1422 2012 [Refereed]
Mikiko Sode Tanaka, Nozomu Togawa, Masao Yanagisawa, Satoshi Goto
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E94A ( 12 ) 2482 - 2489 2011.12 [Refereed]
Speeding-up exact and fast FIFO-based cache configuration simulation
Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
IEICE ELECTRONICS EXPRESS 8 ( 14 ) 1161 - 1167 2011.07 [Refereed]
Mikiko Sode Tanaka, Nozomu Togawa, Masao Yanagisawa, Satoshi Goto
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E94A ( 4 ) 1082 - 1090 2011.04 [Refereed]
Exact and Fast L1 Cache Configuration Simulation for Embedded Systems with FIFO/PLRU Cache Replacement Policies
Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2011 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT) 247 - 250 2011 [Refereed]
Exact, fast and flexible L1 cache configuration simulation for embedded systems
Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
IPSJ Transactions on System LSI Design Methodology 4 166 - 181 2011 [Refereed]
A fault-secure high-level synthesis algorithm for RDR architectures
Sho Tanaka, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
IPSJ Transactions on System LSI Design Methodology 4 150 - 165 2011 [Refereed]
A fast selector-based subtract-multiplication unit and its application to butterfly unit
Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
IPSJ Transactions on System LSI Design Methodology 4 60 - 69 2011 [Refereed]
Scan vulnerability in elliptic curve cryptosystems
Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
IPSJ Transactions on System LSI Design Methodology 4 47 - 59 2011 [Refereed]
Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures
Ryuta Nara, Kei Satoh, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E93A ( 12 ) 2481 - 2489 2010.12 [Refereed]
Improved Launch for Higher TDF Coverage With Fewer Test Patterns
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 29 ( 8 ) 1294 - 1299 2010.08 [Refereed]
State-dependent Changeable Scan Architecture against Scan-based Side Channel Attacks
Ryuta Nara, Hiroshi Atobe, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS 1867 - 1870 2010 [Refereed]
Performance-driven High-level Synthesis with floorplan for GDR Architectures and its Evaluation
Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS 921 - 924 2010 [Refereed]
Scan-Based Attack against Elliptic Curve Cryptosystems
Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2010 15TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2010) 402 - 407 2010 [Refereed]
VLSI Implementation of a Fast Intra Prediction Algorithm for H.264/AVC Encoding
Youhua Shi, Kenta Tokumitsu, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
PROCEEDINGS OF THE 2010 IEEE ASIA PACIFIC CONFERENCE ON CIRCUIT AND SYSTEM (APCCAS) 1139 - 1142 2010 [Refereed]
A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Radix-2 Butterfly Unit
Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
PROCEEDINGS OF THE 2010 IEEE ASIA PACIFIC CONFERENCE ON CIRCUIT AND SYSTEM (APCCAS) 1083 - 1086 2010 [Refereed]
BusMesh NoC: A Novel NoC Architecture Comprised of Bus-based Connection and Global Mesh Routers
SeungJu Lee, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
PROCEEDINGS OF THE 2010 IEEE ASIA PACIFIC CONFERENCE ON CIRCUIT AND SYSTEM (APCCAS) 712 - 715 2010 [Refereed]
A Two-Level Cache Design Space Exploration System for Embedded Applications
Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E92A ( 12 ) 3238 - 3247 2009.12 [Refereed]
A Scan-Based Attack Based on Discriminators for AES Cryptosystems
Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E92A ( 12 ) 3229 - 3237 2009.12 [Refereed]
Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures
Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E92A ( 12 ) 3169 - 3179 2009.12 [Refereed]
X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E92A ( 12 ) 3119 - 3127 2009.12 [Refereed]
Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2(n))
Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E92A ( 9 ) 2304 - 2317 2009.09 [Refereed]
An L1 Cache Design Space Exploration System for Embedded Applications
Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E92A ( 6 ) 1442 - 1453 2009.06 [Refereed]
Design-for-Secure-Test for Crypto Cores
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
ITC: 2009 INTERNATIONAL TEST CONFERENCE 618 - 618 2009 [Refereed]
Exact and Fast L1 Cache Simulation for Embedded Systems
Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
PROCEEDINGS OF THE ASP-DAC 2009: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2009 817 - 822 2009 [Refereed]
A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E91A ( 12 ) 3514 - 3523 2008.12 [Refereed]
Floorplan-driven high-level synthesis for distributed/shared-register architectures
Akira Ohchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
IPSJ Transactions on System LSI Design Methodology 1 78 - 90 2008.08 [Refereed]
Low power LDPC code decoder architecture based on intermediate message compression technique
Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E91A ( 4 ) 1054 - 1061 2008.04 [Refereed]
A secure test technique for pipelined advanced encryption standard
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E91D ( 3 ) 776 - 780 2008.03 [Refereed]
High-level synthesis algorithms with floorplaning for distributed/shared-register architectures
Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM 164 - 167 2008 [Refereed]
Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2(n))
Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 667 - 672 2008 [Refereed]
GECOM: Test data compression combined with all unknown response masking
Youhua Shi, Nozontu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 537 - 542 2008 [Refereed]
Unknown Response Masking with Minimized Observable Response Loss and Mask Data
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4 1779 - + 2008 [Refereed]
Dynamically Reconfigurable Architecture for Multi-Rate Compatible Regular LDPC Decoding
Akiyuki Nagashima, Yuta Imai, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4 705 - 708 2008 [Refereed]
FIR Filter Design on Flexible Engine/Generic ALU Array and Its Dedicated Synthesis Algorithm
Ryo Tamura, Masayuki Honma, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Makoto Satoh
2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4 701 - + 2008 [Refereed]
携帯機器向けMPEG-A Photo Playerのメタデータ生成システムのハードウェア化に関する一考察
元橋雅人, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 VLD2006 ( 552 ) 31 - 36 2007.03
アプリケーションプロセッサ向けデータキャッシュ構成最適化システムとその評価
堀内一央, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 VLD2006 2007.03
SIMD型プロセッサコア最適化設計のための多重ループに対応したSIMD命令合成手法
中島裕貴, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 VLD2006 ( 551 ) 13 - 18 2007.03
SIMD型プロセッサコアを対象としたハードウェア/ソフトウェア分割フレームワーク
大東真崇, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 VLD2006 ( 551 ) 7 - 12 2007.03
SIMD型プロセッサコア設計におけるプロセッシングユニット最適化手法
繁田裕之, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 VLD2006 ( 551 ) 1 - 6 2007.03
Power-Efficient LDPC Code Decoder Architecture
Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto
ISLPED'07: PROCEEDINGS OF THE 2007 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN 359 - 362 2007 [Refereed]
Design for secure test - A case study on pipelined Advanced Encryption Standard
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11 149 - 152 2007 [Refereed]
XMLをベースとしたCDFGマニピュレーションフレームワーク: CoDaMa
小原俊逸, 史又華, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 VLD2006-97 19 - 24 2007.01
楕円曲線暗号向けGF(2m)上のDigit-Serial乗算器の設計
奈良竜太, 小原俊逸, 清水一範, 戸川望, 池永剛, 柳澤政生, 後藤敏, 大附辰夫
電子情報通信学会技術研究報告 VLD2006-89 ( 455 ) 25 - 30 2007.01
Power-efficient LDPC decoder architecture based on accelerated message-passing schedule
Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E89A ( 12 ) 3602 - 3612 2006.12 [Refereed]
アプリケーションプロセッサのフォワーディングユニット最適化手法
日浦敏俊, 小原俊逸, 史又華, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 ( VLD2006-80 ) 2006.11
今井優太, 清水一範, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 RECONF2006-43 ( 393 ) 35 - 40 2006.11
歩行者ナビゲーションにおける微小画面での視認性とユーザの迷いにくさを考慮した略地図生成手法
二宮直也, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 ITS2006-34 ( 266 ) 53 - 58 2006.09
屋内用歩行者ナビゲーションにおける歩行者の嗜好を反映させる経路探索手法
荒井亨, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 ITS2006-33 ( 266 ) 47 - 52 2006.09
屋内向け歩行者ナビゲーションにおけるユーザの嗜好性と混雑状況を考慮した目的地決定手法
小林和馬, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 ITS2006-32 ( 266 ) 41 - 45 2006.09
大高宏介, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 ITS2006-18 ( 265 ) 19 - 24 2006.09
H.264符号化向けDSPにおける動き予測演算器の設計
高橋豊和, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 ( VLD2006 ) 2006.06
アプリケーションプロセッサの面積/遅延見積もり手法
山崎大輔, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 CAS2006-1 ( VLD2006-14, SIP2006-24 ) 2006.06
Selective low-care coding: A means for test data compression in circuits with multiple scan chains
YH Shi, N Togawa, S Kimura, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E89A ( 4 ) 996 - 1004 2006.04 [Refereed]
Partially-parallel LDPC decoder achieving high-efficiency message-passing schedule
K Shimizu, T Ishikawa, N Togawa, T Ikenaga, S Goto
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E89A ( 4 ) 969 - 978 2006.04 [Refereed]
Hardware architecture of efficient message-passing schedule based on modified min-sum algorithm for decoding LDPC codes
Proc. Synthesis and System Integration of Mixed Technologies (SASIMI 2006) 2006.04
A pipelined functional unit generation method in HW/SW cosynthesis for SIMD processor cores
Proc. Synthesis and System Integration of Mixed Technologies (SASIMI 2006) 2006.04
Hardware architecture of efficient message-passing schedule based on modified min-sum algorithm for decoding LDPC codes
清水一範, 石川達之, 戸川望, 池永剛, 後藤敏
Proc. Synthesis and System Integration of Mixed Technologies (SASIMI 2006) 2006.04
A pipelined functional unit generation method in HW/SW cosynthesis for SIMD processor cores
小原俊逸, 栗原輝, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
Proc. Synthesis and System Integration of Mixed Technologies (SASIMI 2006) 2006.04
堀内一央, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会第19回回路とシステム軽井沢ワークショップ論文集 19 583 - 588 2006.04
FIFOバッファによる高効率Message-Passingスケジュールを用いたLDPC復号器
清水一範, 石川達之, 戸川望, 池永剛, 後藤敏
電子情報通信学会第19回回路とシステム軽井沢ワークショップ論文集 19 211 - 216 2006.04
A fast elliptic curve cryptosystem LSI embedding word-based Montgomery multiplier
J Uchida, N Togawa, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON ELECTRONICS E89C ( 3 ) 243 - 249 2006.03 [Refereed]
歩行者向け地図情報配信システムにおける道路交通標識を用いた位置特定手法
中口智史, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 ( ITS2005-114 ) 2006.03
SIMD型プロセッサコアの自動合成におけるパイプライン構成最適化手法
栗原輝, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 105 ( VLD2005-115, ICD2005-232 ) 43 - 48 2006.03
動的フローに対応したネットワークプロセッサの改良とその評価
田淵英孝, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 ( VLD2005-112, ICD2005-229 ) 2006.03
設計ナビゲーション機構を有するシステムLSI設計のためのHW/SW分割システム
小島洋平, 戸川望, 橘昌良, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 105 ( VLD2005-111, ICD2005-228 ) 19 - 24 2006.03
高速移動体のためのハンドオフメッセージ数を最小化した高速ハンドオフ手法
伊藤光司, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 ( IN2005-222 ) 2006.03
ASIC implementation of LDPC decoder accelerating message-passing schedule
SHIMIZU Kazunori
IEEE International Solid State Circuits Confeference (ISSCC), DAC/ISSCC2006 Student Design Contest (Conceptual Category: 1st Place Winner), San Franscisco 2006.02
ASIC implementation of LDPC decoder accelerating message-passing schedule
清水一範, 石川達之, 戸川望, 池永剛, 後藤敏
IEEE International Solid State Circuits Confeference (ISSCC), DAC/ISSCC2006 Student Design Contest (Conceptual Category: 1st Place Winner), San Franscisco 2006.02
A parallel LSI architecture for LDPC decoder improving message-passing schedule
Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Gotot
2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS 5099 - + 2006 [Refereed]
FCSCAN: An efficient multiscan-based test compression technique for test cost reduction
Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 653 - 658 2006 [Refereed]
An interface-circuit synthesis method with configurable processor core in IP-based SoC designs
Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 594 - 599 2006 [Refereed]
Memory-efficient accelerating schedule for LDPC decoder
Kazunori Shimizu, Nozonm Togawa, Takeshi Ikenaga, Satoshi Goto
2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS 1317 - + 2006 [Refereed]
A parallel LSI architecture for LDPC decoder improving message-passing schedule
Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Gotot
2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS 5099 - + 2006
Selective low-care coding: A means for test data compression in circuits with multiple scan chains
Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A ( 4 ) 996 - 1003 2006
FCSCAN: An efficient multiscan-based test compression technique for test cost reduction
Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 653 - 658 2006
An interface-circuit synthesis method with configurable processor core in IP-based SoC designs
Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 594 - 599 2006
MPEG-4形状符号化/復号化に対応したDSP組み込み向け専用演算器の設計
古宇多朋史, 小原俊逸, 史又華, 戸川望, 柳澤政生, 大附辰夫
情報処理学会組込みシステムシンポジウム2006論文集(ESS2006) 2006
連携処理を考慮したネットワークプロセッサ合成システム
中山敬史, 戸川望, 柳澤政生, 大附辰夫
情報処理学会DAシンポジウム2006論文集 2006
レジスタ分散・共有併用型アーキテクチャを対象としたフロアプランを考慮した高位合成手法
大智輝, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫
情報処理学会DAシンポジウム2006論文集 2006
SIMD型プロセッサコアの自動合成のためのパイプライン演算ユニット生成手法
栗原輝, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
情報処理学会論文誌 vol. 47 ( no. 6 ) 2006
高橋豊和, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 CAS2006-10 ( VLD2006-23, SIP2006-33 ) 13 - 18 2006
A parallel LSI architecture for LDPC decoder improving message-passing schedule
Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Gotot
2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS 5099 - + 2006
FCSCAN: An efficient multiscan-based data compression technique for test cost reduction
史又華, 戸川望, 木村晋二, 柳澤政生, 大附辰夫
Proc. IEEE Asia and South Pacific Design Automation Conference 2006 (ASP-DAC 2006) 653 - 658 2006.01
An interface-circuit synthesizer with configurable processor core in IP-based SOC design
小原俊逸, 友野直紀, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
Proc. IEEE Asia and South Pacific Design Automation Conference 2006 (ASP-DAC 2006) 594 - 599 2006.01
重回帰分析により得られた1次式によるインダクタンスを考慮した配線遅延の見積り
鈴木康成, マルタディナタ アンワル, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 105 ( VLD2005-72 ) 67 - 72 2005.12
レジスタ分散・共有アーキテクチャを対象としたフロアプラン指向高位合成手法
大智輝, 戸川望, 柳澤雅夫, 大附辰夫
電子情報通信学会技術研究報告 105 ( VLD2005-66 ) 31 - 36 2005.12
SIMD型プロセッサの自動合成におけるパイプライン演算ユニット生成手法
栗原輝, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
情報処理学会DAシンポジウム2005論文集 25 - 30 2005.08
画像処理向けシステムLSI設計における設計ナビゲーションを考慮したHW/SW分割システム
小島洋平, 戸川望, 橘昌良, 柳澤政生, 大附辰夫
情報処理学会DAシンポジウム2005論文集 19 - 24 2005.08
Reconfigurable adaptive FEC system based on Reed-Solomon code with interleaving
K Shimizu, N Togawa, T Ikenaga, S Goto
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E88D ( 7 ) 1526 - 1537 2005.07 [Refereed]
A SIMD instruction set and functional unit synthesis algorithm with SIMD operation decomposition
N Togawa, K Tachikake, Y Miyaoka, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E88D ( 7 ) 1340 - 1349 2005.07 [Refereed]
レジスタ分散型アーキテクチャを対象とするフロアプランとタイミング制約を考慮した高位合成手法
田中真, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
情報処理学会論文誌 46 ( 6 ) 1383 - 1394 2005.05
Sub-operation parallelism optimization in SIMD processor core synthesis
H Kawazu, J Uchida, Y Miyaoka, N Togawa, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E88A ( 4 ) 876 - 884 2005.04 [Refereed]
IP再利用を考慮したシステムLSI設計におけるインタフェース回路生成システム
小原俊逸, 友野直紀, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会第18回回路とシステム軽井沢ワークショップ論文集 581 - 586 2005.04
SIMD型プロセッサコア向けHW/SW協調合成システムにおけるパイプライン演算ユニット生成手法
栗原輝, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会第18回回路とシステム軽井沢ワークショップ論文集 575 - 580 2005.04
A selective care bits coding method for test data compression
史又華, 戸川望, 木村晋二, 柳澤政生, 大附辰夫
電子情報通信学会第18回回路とシステム軽井沢ワークショップ論文集 241 - 246 2005.04
信頼度の伝播効率を改善する部分並列LDPC復号器の実装と評価
清水一範, 石川達之, 戸川望, 池永剛, 後藤敏
電子情報通信学会第18回回路とシステム軽井沢ワークショップ論文集 181 - 186 2005.04
インダクタンスを考慮した配線遅延の近似式による見積もり
鈴木康成, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会第18回回路とシステム軽井沢ワークショップ論文集 1 - 6 2005.04
ネットワークプロセッサ合成システムの改良とその評価
升本英行, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 VLD2004 2005.03
細田宗一郎, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 VLD2004 ( 709 ) 79 - 84 2005.03
ワードベースモンゴメリ乗算器を搭載した高速楕円曲線暗号LSI
内田純平, 奈良竜太, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 VLD2004 ( 708 ) 5 - 10 2005.03
面積制約を考慮したマルチスレッドプロセッサの合成手法
麻生雄一, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 2005.03
Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations
N Togawa, Y Miyaoka, H Kawazu, M Yanagisawa, J Uchida, T Ohtsuki
2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS 3499 - 3502 2005 [Refereed]
Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm
K Shimizu, T Ishikawa, N Togawa, T Ikenaga, S Goto
2005 IEEE International Conference on Computer Design: VLSI in Computers & Processors, Proceedings 503 - 510 2005 [Refereed]
Low power test compression technique for designs with multiple scan chains
YH Shi, N Togawa, S Kimura, M Yanagisawa, T Ohtsuki
14TH ASIAN TEST SYMPOSIUM, PROCEEDINGS 386 - 389 2005 [Refereed]
Reconfigurable adaptive FEC system with interleaving
Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto
ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 1252 - 1255 2005 [Refereed]
A processor core synthesis system in IP-based SoC design
Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 286 - 291 2005 [Refereed]
A processor core synthesis system in IP-based SoC design
Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 286 - 291 2005
A Processor Core Synthesis System in IP-based SoC Design
友野直紀, 小原俊逸, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
Proceedings of the ASP-DAC 2005 2005.01
FPGA-based reconfigurable adaptive FEC
K Shimizu, J Uchida, Y Miyaoka, N Togawa, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E87A ( 12 ) 3036 - 3046 2004.12
High-level power optimization based on thread partitioning
J Uchida, N Togawa, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E87A ( 12 ) 3075 - 3082 2004.12
レジスタ分散型アーキテクチャを対象とするフロアプランを考慮した高位合成手法
田中真, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 VLD2004 2004.12
FPGA-based reconfigurable adaptive FEC
K Shimizu, J Uchida, Y Miyaoka, N Togawa, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E87A ( 12 ) 3036 - 3046 2004.12
High-level power optimization based on thread partitioning
J Uchida, N Togawa, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E87A ( 12 ) 3075 - 3082 2004.12
A sub-operation parallelism optimization algorithmin HW/SW partitioning for SIMD processor cores
SASIMI2004 483 - 490 2004.10
A sub-operation parallelism optimization algorithmin HW/SW partitioning for SIMD processor cores
川津秀樹, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
SASIMI2004 483 - 490 2004.10
IP再利用を考慮したシステムLSIにおけるプロセッサコア合成システム
友野直紀, 小原俊逸, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
情報処理学会 DAシンポジウム 2004 19 - 24 2004.07
フロアプランとタイミング制約に基づくレジスタ間データ転送を考慮した高位合成手法
田中真, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
情報処理学会 DAシンポジウム 2004 283 - 288 2004.07
A hardware/software cosynthesis algorithm for processors with heterogeneous datapaths
Y Miyaoka, N Togawa, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E87A ( 4 ) 830 - 836 2004.04
SIMD型プロセッサコア向けHW/SW分割におけるSIMD型演算最適化手法
川津秀樹, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会第17回 回路とシステム(軽井沢)ワークショップ 579 - 584 2004.04
A hardware/software cosynthesis algorithm for processors with heterogeneous datapaths
Y Miyaoka, N Togawa, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E87A ( 4 ) 830 - 836 2004.04
ネットワークプロセッサ合成システム
松浦努, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 VLD2003-145 55 - 60 2004.03
小田雄一, 内田純平, 宮岡祐一郎, 戸川望, 橘昌良, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 VLD2003-158 ( 703 ) 47 - 52 2004.03
Packed SIMD型命令を持つプロセッサ合成システムのためのリターゲッタブルコンパイラ
加藤久晴, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 VLD2003-157 41 - 46 2004.03
面積制約を考慮したCAMプロセッサ最適化手法
石川裕一朗, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 VLD2003-152 13 - 18 2004.03
インターリーブを考慮したReconfigurable Adaptive FEC
清水一範, 内田純平, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 VLD2003-151 ( 703 ) 7 - 12 2004.03
携帯機器を対象としたJava動的コンパイラにおけるプロファイリングシステム
船田雅史, 内田純平, 戸川望, 柳澤政生, 大附辰夫
情報処理学会研究報告,2004-MBL-28 2004 ( 21 ) 55 - 62 2004.03
YH Shi, S Kimura, N Togawa, M Yanagisawa, T Ohtsuki
13TH ASIAN TEST SYMPOSIUM, PROCEEDINGS 432 - 437 2004 [Refereed]
Instruction set and functional unit synthesis for SIMD processor cores
N Togawa, K Tachikake, Y Miyaoka, M Yanagisawa, T Ohtsuki
ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 743 - 750 2004 [Refereed]
A cosynthesis algorithm for application specific processors with heterogeneous datapaths
Y Miyaoka, N Togawa, M Yanagisawa, T Ohtsuki
ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 250 - 255 2004 [Refereed]
A thread partitioning algorithm in low power high-level synthesis
J Uchida, N Togawa, M Yanagisawa, T Ohtsuki
ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 74 - 79 2004 [Refereed]
A reconfigurable adaptive FEC system for reliable wireless communications
K Shimizu, N Togawa, T Ikenaga, M Yanagisawa, S Goto, T Ohtsuki
PROCEEDINGS OF THE 2004 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1 AND 2 13 - 16 2004
Experimental evaluation of high-level energy optimization based on thread partitioning
J Uchida, Y Miyaoka, N Togawa, M Yanagisawa, T Ohtsuki
PROCEEDINGS OF THE 2004 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1 AND 2 161 - 164 2004
An efficient algorithm/architecture codesign for image encoders
J Choi, N Togawa, T Ikenaga, S Goto, M Yanagisawa, T Ohtsuki
2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS 469 - 472 2004
Reducing test data volume for multiscan-based designs through single/sequence mixed encoding
Y Shi, S Kimura, N Togawa, M Yanagisawa, T Ohtsuki
2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS 445 - 448 2004
Instruction set and functional unit synthesis for SIMD processor cores
N Togawa, K Tachikake, Y Miyaoka, M Yanagisawa, T Ohtsuki
ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 743 - 750 2004
A cosynthesis algorithm for application specific processors with heterogeneous datapaths
Y Miyaoka, N Togawa, M Yanagisawa, T Ohtsuki
ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 250 - 255 2004
A thread partitioning algorithm in low power high-level synthesis
J Uchida, N Togawa, M Yanagisawa, T Ohtsuki
ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 74 - 79 2004
A reconfigurable adaptive FEC system for reliable wireless communications
K Shimizu, N Togawa, T Ikenaga, M Yanagisawa, S Goto, T Ohtsuki
PROCEEDINGS OF THE 2004 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1 AND 2 13 - 16 2004
Experimental evaluation of high-level energy optimization based on thread partitioning
J Uchida, Y Miyaoka, N Togawa, M Yanagisawa, T Ohtsuki
PROCEEDINGS OF THE 2004 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1 AND 2 161 - 164 2004
An efficient algorithm/architecture codesign for image encoders
J Choi, N Togawa, T Ikenaga, S Goto, M Yanagisawa, T Ohtsuki
2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS 469 - 472 2004
Reducing test data volume for multiscan-based designs through single/sequence mixed encoding
Y Shi, S Kimura, N Togawa, M Yanagisawa, T Ohtsuki
2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS 445 - 448 2004
Instruction set and functional unit synthesis for SIMD processor cores
N Togawa, K Tachikake, Y Miyaoka, M Yanagisawa, T Ohtsuki
ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 743 - 750 2004
A cosynthesis algorithm for application specific processors with heterogeneous datapaths
Y Miyaoka, N Togawa, M Yanagisawa, T Ohtsuki
ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 250 - 255 2004
A thread partitioning algorithm in low power high-level synthesis
J Uchida, N Togawa, M Yanagisawa, T Ohtsuki
ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 74 - 79 2004
A hardware/software partitioning algorithm for processor cores with packed SIMD-type instructions
N Togawa, K Tachikake, Y Miyaoka, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E86A ( 12 ) 3218 - 3224 2003.12
A retargetable simulator generator for DSP processor cores with packed SIMD-type instructions
N Togawa, K Kasahara, Y Miyaoka, J Choi, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E86A ( 12 ) 3099 - 3109 2003.12
A hardware/software partitioning algorithm for processor cores with packed SIMD-type instructions
N Togawa, K Tachikake, Y Miyaoka, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E86A ( 12 ) 3218 - 3224 2003.12
A retargetable simulator generator for DSP processor cores with packed SIMD-type instructions
N Togawa, K Kasahara, Y Miyaoka, J Choi, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E86A ( 12 ) 3099 - 3109 2003.12
石川裕一朗, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術研究報告 VLD2003-89 ( 478 ) 115 - 120 2003.11
面積制約を考慮したCAMプロセッサ向けハードウェア/ソフトウェア協調設計手法
石川裕一朗, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 IE2003-98 ( 380 ) 83 - 88 2003.10
FPGAを用いたReconfigurable Adaptive FECの実装と評価
清水一範, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 Reconf2003-9 2003.09
公共空間におけるハンドオフ時間短縮を考慮したBluetoothネットワークの手順に関する一検討
寺崎暁, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 CQ2003-58 25 - 28 2003.09
動的再構成可能システムによるAdaptive FECの実装
清水一範, 戸川望, 柳澤政生, 大附辰夫
情報処理学会 DAシンポジウム 2003 25 - 30 2003.07
システムLSI設計における定性的側面を考慮したハードウェア/ソフトウェア分割システム
小田雄一, 宮岡祐一郎, 戸川望, 橘昌良, 柳澤政生, 大附辰夫
情報処理学会 DAシンポジウム 2003 169 - 174 2003.07
冗長記述を利用したVHDLへの透かし埋め込み手法
久保ゆきこ, 戸川望, 柳澤政生, 大附辰夫
情報処理学会 DAシンポジウム 2003 37 - 42 2003.07
System Architecture based on Hardware/Software Codesign for Optimization of Video Encoders
The 2003 International Technical Conference on Circuits/Systems,Computers and Communications 2003.06
System Architecture based on Hardware/Software Codesign for Optimization of Video Encoders
崔鎮求, 戸川望, 柳澤政生, 大附辰夫
The 2003 International Technical Conference on Circuits/Systems,Computers and Communications 2003.06
A hardware/software cosynthesis system for processor cores with content addressable memories
N Togawa, T Totsuka, T Wakui, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E86A ( 5 ) 1082 - 1092 2003.05
A hardware/software cosynthesis system for processor cores with content addressable memories
N Togawa, T Totsuka, T Wakui, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E86A ( 5 ) 1082 - 1092 2003.05
An Instruction-Set Simulator Generator for SIMD Processor Cores
Proceedings of workshop SASIMI2003 160 - 167 2003.04
ネットワークスイッチング処理を対象としたCAMプロセッサ自動合成システム
田中英夫, 戸川望, 柳澤政生, 大附辰夫
回路とシステム(軽井沢)ワークショップ 435 - 440 2003.04
不規則なデータパスを持つプロセッサのハードウェア/ソフトウェア協調合成手法
宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
回路とシステム(軽井沢)ワークショップ 441 - 446 2003.04
An Instruction-Set Simulator Generator for SIMD Processor Cores
宮岡祐一郎, 戸川望, 笠原亨介, 崔鎮求, 柳澤政生, 大附辰夫
Proceedings of SASIMI2003 160 - 167 2003.04
閾値検索機能付きCAMプロセッサの最適化手法
戸塚崇夫, 宮岡祐一郎, 石川裕一朗, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 VLD2002-158 19 - 24 2003.03
SIMD型プロセッサコア向けHW/SW分割におけるSIMD型演算最適化手法
太刀掛宏一, 宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 VLD2002-157 13 - 18 2003.03
高位合成システムにおけるスレッド分割を用いた低消費電力化手法
内田純平, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 VLD2002-156 7 - 12 2003.03
A hardware/software partitioning algorithm for SIMD processor cores
K Tachikake, N Togawa, Y Miyaoka, J Choi, M Yanagisawa, T Ohtsuki
ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 135 - 140 2003 [Refereed]
ハードウェアIPの応答時間を考慮したプロセッサコアのハードウェア/ソフトウェア分割手法
田川博規, 小原俊逸, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 VLD2002-136 ( 609 ) 37 - 42 2003.01
ハードウェアIPの応答時間を考慮したプロセッサコア合成システム
小原俊逸, 田川博規, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 VLD2002-135 ( 609 ) 31 - 36 2003.01
MPEG-4コアプロファイル符号化向けDSP
石本剛, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 VLD2002-134 25 - 30 2003.01
A high-level energy-optimizing algorithm for system VLSIs based on area/time/power estimation
S Noda, N Togawa, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E85A ( 12 ) 2655 - 2666 2002.12
An algorithm and a flexible architecture for fast block-matching motion estimation
J Choi, N Togawa, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E85A ( 12 ) 2603 - 2611 2002.12
A high-level energy-optimizing algorithm for system VLSIs based on area/time/power estimation
S Noda, N Togawa, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E85A ( 12 ) 2655 - 2666 2002.12
An algorithm and a flexible architecture for fast block-matching motion estimation
J Choi, N Togawa, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E85A ( 12 ) 2603 - 2611 2002.12
戸塚崇夫, 石川裕一朗, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 VLD2002-113 ( 476 ) 197 - 192 2002.11
動的再構成可能システムによるプロトコルブースタの実装
清水一範, 陳暁梅, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 VLD2002-103 127 - 132 2002.11
ストリーミングを主目的としたアクセスネットワークでの最大許容遅延を考慮した制御方式
柳澤政生, 佐藤隆之, 戸川望, 大附辰夫
電子情報通信学会技術報告,MoMuC 2-Jul ( 251 ) 13 - 18 2002.07
仮想IP類推機構を有する動画像処理向けシステムVLSIのためのハードウェア/ソフトウェア分割システム
小田雄一, 磯田新平, 戸川望, 橘昌良, 柳澤政生, 大附辰夫
情報処理学会 DAシンポジウム 2002 173 - 178 2002.07
A Software/Hardware Codesign for MPEG Encoder
FIT(Forum on Information Technology)2002 2002.06
System-level Function and Architecture Codesign for Optimization of MPEG Encoder
ITC-CSCC'02 2002.06
Packed SIMD 型命令を持つプロセッサを対象としたハードウェア/ソフトウェア協調合成システムのための並列化コンパイル手法
鈴木伸治, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 VLD2002-78 ( 168 ) 79 - 84 2002.06
Packed SIMD型命令セットを持った画像処理プロセッサのためのハードウェア/ソフトウェア分割手法
太刀掛宏一, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 VLD2002-53 ( 168 ) 85 - 90 2002.06
A Software/Hardware Codesign for MPEG Encoder
崔鎮求, 戸川望, 柳澤政生, 大附辰夫
FIT(Forum on Information Technology)2002 2002.06
System-level Function and Architecture Codesign for Optimization of MPEG Encoder
崔鎮求, 戸川望, 柳澤政生, 大附辰夫
ITC-CSCC'02 2002.06
モバイル環境における一対多通信 -シミュレーションによるFTPとSRMの比較-
佐藤隆之, 柳生健吾, 戸川望, 大附辰夫
電子情報通信学会技術報告,MoMuC 2-Jun 33 - 38 2002.05
ディジタル信号処理向けプロセッサのためのシミュレータ生成手法
笠原亨介, 戸川望, 柳澤政生, 大附辰夫
情報処理学会論文誌 vol.43 No.5 1202 - 1213 2002.05
Packed SIMD型命令を持つプロセッサを対象としたハードウェア/ソフトウェア協調合成システムのためのハードウェアユニット生成手法
宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
情報処理学会論文誌 vol.43 No.5 ( 5 ) 1191 - 1201 2002.05
High-level area/delay/power estimation for low power system VLSIs with gated clocks
S Noda, N Togawa, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E85A ( 4 ) 827 - 834 2002.04
DSPプロセッサコアのハードウェア/ソフトウェア協調合成システムのための演算語長縮小化手法
田川博規, 嶋下和宏, 戸川望, 柳澤政生, 大附辰夫
回路とシステム軽井沢ワークショップ 429 - 434 2002.04
High-level area/delay/power estimation for low power system VLSIs with gated clocks
S Noda, N Togawa, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E85A ( 4 ) 827 - 834 2002.04
制御処理ハードウェア高位合成のためのコントロールデータフローグラフ変形手法
石井哲雄, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 VLD2001-165 ( 695 ) 41 - 48 2002.03
IP再利用を考慮した動画像処理システムVLSI向けハードウェア/ソフトウェア分割設計支援システム
磯田新平, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 VLD2001-164 ( 695 ) 33 - 40 2002.03
Packed SIMD 型演算器を持つディジタル信号処理プロセッサのためのリターゲッタブルシミュレータ生成手法
笠原亨介, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 VLD2001-162 24 - 17 2002.03
VLSI architecture for a flexible motion estimation with parameters
J Choi, N Togawa, M Yanagisawa, T Ohtsuki
ASP-DAC/VLSI DESIGN 2002: 7TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE AND 15TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS 452 - 457 2002 [Refereed]
Y Miyaoka, A Choi, N Togawa, M Yanagisawa, T Ohtsuki
APCCAS 2002: ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS 171 - 176 2002 [Refereed]
An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions
Y Miyaoka, A Choi, N Togawa, M Yanagisawa, T Ohtsuki
APCCAS 2002: ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS 171 - 176 2002
ロジック入力用レベルシフトコンパレーター設計考察
宮崎英敏, 戸川望, 柳澤政生, 大附辰夫, 茨木栄武, 新谷悟
電子回路研究会,ETC-02-16 13 - 17 2002.01
システムVLSIのための高位面積/遅延/消費電力見積もりに基づく低消費電力指向高位合成手法
野田真一, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 VLD2001-144 ( 577 ) 93 - 100 2002.01
A new hardware/software partitioning algorithm for DSP processor cores with two types of register files
N Togawa, T Sakurai, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E84A ( 11 ) 2802 - 2807 2001.11
Area and delay estimation in hardware/software cosynthesis for digital signal processor cores
N Togawa, Y Kataoka, Y Miyaoka, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E84A ( 11 ) 2639 - 2647 2001.11
メモリとのインターフェース仕様を考慮した演算語長縮小に基づくプロセッサコアのハードウェア/ソフトウェア協調合成システム
嶋下和宏, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 VLD2001-110 ( 467 ) 127 - 132 2001.11
A new hardware/software partitioning algorithm for DSP processor cores with two types of register files
N Togawa, T Sakurai, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E84A ( 11 ) 2802 - 2807 2001.11
Area and delay estimation in hardware/software cosynthesis for digital signal processor cores
N Togawa, Y Kataoka, Y Miyaoka, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E84A ( 11 ) 2639 - 2647 2001.11
A Hardware/Software Cosynthesis System for CAM Processors
SASIMI2001 2001.10
A Hardware/Software Cosynthesis System for CAM Processors
戸川望, 涌井達彦, 柳澤政生, 大附辰夫
SASIMI2001 2001.10
Implementation of Motion Estimation IP Core for MPEG Encoder
ITC-CSCC 2001 2001.07
Packed SIMD型命令を持つプロセッサを対象としたハードウェア/ソフトウェア協調合成システムのためのハードウェアユニット生成手法
宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
情報処理学会 DAシンポジウム 2001 223 - 228 2001.07
Implementation of Motion Estimation IP Core for MPEG Encoder
崔鎮求, 戸川望, 柳澤政生, 大附辰夫
ITC-CSCC 2001 2001.07
An area/time optimizing algorithm in high-level synthesis of control-based hardwares
N Togawa, M Ienaga, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E84A ( 5 ) 1166 - 1176 2001.05
An area/time optimizing algorithm in high-level synthesis of control-based hardwares
N Togawa, M Ienaga, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E84A ( 5 ) 1166 - 1176 2001.05
ディジタル信号処理向けプロセッサコアのPacked SIMD型ハードウェアユニット生成手法
宮岡祐一郎, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 VLD2001-2 ( 45 ) 7 - 13 2001.05
Gated Clockによる低消費電力化システムVLSIの高位面積/遅延/消費電力見積り
野田真一, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会第14回 回路とシステム(軽井沢)ワークショップ 591 - 596 2001.04
ソフトIPのための保護アルゴリズム
堀川哲郎, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会第14回 回路とシステム(軽井沢)ワークショップ 411 - 416 2001.04
システムLSIを対象としたハードウェア/ソフトウェア分割システム
小田龍之介, 磯田新平, 戸川望, 橘昌良, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 VLD2000-140 ( 646 ) 37 - 42 2001.03
画像処理を対象としたPacked SIMD型命令セットを持つプロセッサのハードウェア/ソフトウェア協調合成システムにおける並列化Cコンパイラ
野々垣直浩, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 VLD2000-139 ( 646 ) 31 - 36 2001.03
制御処理ハードウェアの高位合成システムのための面積/遅延見積もり手法
余田貴幸, 戸川望, 柳澤政生, 大附辰夫
情報処理学会研究報告 2001-SLDM-100-4,pp.25-32 ( 12 ) 25 - 32 2001.02
RC等価回路に基づくクロストーク低減配線手法
曽根原理仁, 戸川望, 柳澤政生, 大附辰夫
情報処理学会研究報告 2001-SLDM-100-3,pp.17-24 17 - 24 2001.02
Area/delay estimation for digital signal processor cores
Y Miyaoka, Y Kataoka, N Togawa, M Yanagisawa, T Ohtsuki
PROCEEDINGS OF THE ASP-DAC 2001: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2001 156 - 161 2001 [Refereed]
発見的算法と分枝限定法を用いた時間的予測に基づくリソースバイディング
中村洋, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 VLD2000-119 ( 532 ) 17 - 24 2001.01
FPGAを用いた動的再構成可能システムを対象とするスケジューリング手法
石飛貴志, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 VLD2000-115 33 - 40 2001.01
香西伸治, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 VLD2000-114 ( 531 ) 25 - 32 2001.01
CAM processor synthesis based on behavioral descriptions
N Togawa, T Wakui, T Yoden, M Terajima, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E83A ( 12 ) 2464 - 2473 2000.12
CAM processor synthesis based on behavioral descriptions
N Togawa, T Wakui, T Yoden, M Terajima, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E83A ( 12 ) 2464 - 2473 2000.12
CAMプロセッサを対象とするハードウェア/ソフトウェア協調合成システム
涌井達彦, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 VLD2000-84 89 - 94 2000.11
機能メモリを使用したプロセッサの面積/遅延見積もり手法
余傅達彦, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 VLD2000-83 83 - 88 2000.11
制御処理ハードウェアの高位合成システムのための面積/時間最適化アルゴリズム
家長真行, 戸川望, 柳澤政生, 大附辰夫
情報処理学会DAシンポジウム2000 27 - 32 2000.07
A Behavioral Synthesis System for Processors with Content Addressable Memories
涌井達彦, 余傅達彦, 寺島信, 戸川望, 柳澤政生, 大附辰夫
Proc.SASIMI2000 56 - 63 2000.04
システムVLSIの動作合成におけるレイアウト面積・遅延見積もり手法
諏訪勝, 戸川望, 柳澤政生, 大附辰夫
電子情報通信学会第13回回路とシステム(軽井沢)ワークショップ 125 - 130 2000.04
A hardware/software cosynthesis system for digital signal processor cores with two types of register files
N Togawa, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E83A ( 3 ) 442 - 451 2000.03
歩行者を対象とした地図データ配信システムにおける専用プロセッサの設計と評価
伊澤義貴, 濱未希子, 柳澤政生, 大附辰夫
電子情報通信学会技術報告 VLD99-267 ( 658 ) 15 - 22 2000.03
A hardware/software cosynthesis system for digital signal processor cores with two types of register files
N Togawa, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E83A ( 3 ) 442 - 451 2000.03
An area/time optimizing algorithm in high-level synthesis for control-based hardwares
Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 309 - 312 2000 [Refereed]
A hardware/software partitioning algorithm for digital signal processor cores with two types of register files
N Togawa, T Sakurai, M Yanagisawa, T Ohtsuki
2000 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS 544 - 547 2000
A Behavioral Synthesis System for Processors with Content Addressable Memories
Proc. SASIMI 2000 56 - 63 2000
A hardware/software partitioning algorithm for digital signal processor cores with two types of register files
N Togawa, T Sakurai, M Yanagisawa, T Ohtsuki
2000 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS pp.544-547 544 - 547 2000
An area/time optimizing algorithm in high-level synthesis for control-based hardwares
戸川望, 家長真行, 柳澤政生, 大附辰夫
Proceedings of IEEE Asia and South Pacific Design Automation Conference 2000 (ASP-DAC 2000) 2000.01
A simultaneous placement and routing algorithm for FPGAs with power optimization
Journal of Circuits, Systems and Computers 9;1,2 99 - 112 1999.12
A hardware/software cosynthesis system for digital signal processor cores
N Togawa, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E82A ( 11 ) 2325 - 2337 1999.11
2種類のレジスタファイルを持つディジタル信号処理向けプロセッサのハードウェア/ソフトウェア分割手法
電子情報通信学会技術報告 VLD99-76 1999.11
KATAOKA Yoshiharu, YOSHIZAWA Dai, TOGAWA Nozomu, YANAGISAWA Masao, OHTSUKI Tatsuo
電子情報通信学会技術報告 VLD99-75 ( 475 ) 1 - 8 1999.11
A hardware/software cosynthesis system for digital signal processor cores
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences E82-A;11 2325 - 2337 1999.11
制御処理ハードウェアの高位合成システムのための面積/時間最適化アルゴリム
IENAGA Masayuki, TOGAWA Nozomu, YANAGISAWA Masao, OHTSUKI Tatsuo
電子情報通信学会技術報告 VLD99-66 ( 317 ) 15 - 22 1999.09
制御処理を主体としたハードウェアを対象とする高位合成システムとその適用
情報処理学会DAシンポジウム'99論文集 1999.07
2種類のレジスタファイルを持ったディジタル信号処理向けプロセッサのハードウェア/ソフトウェア協調合成システム
電子情報通信学会第12回回路とシステム軽井沢ワークショップ論文集 1999.04
分枝限定法に基づく最適解を保証するリソースバインディング手法
情報処理学会論文誌 40;4 1565 - 1577 1999.04
A depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured LUTs
N Togawa, K Ara, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E82A ( 3 ) 473 - 482 1999.03
FPGAを用いた再構成可能システムとその応用
電子情報通信学会技術研究報告 VLD98;143 1999.03
A depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured LUTs
N Togawa, K Ara, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E82A ( 3 ) 473 - 482 1999.03
A simultaneous placement and global routing algorithm for FPGAS with power optimization
N Togawa, K Ukai, M Yanagisawa, T Ohtsuki
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 9 ( 1-2 ) 99 - 112 1999.02 [Refereed]
A simultaneous placement and global routing algorithm for FPGAS with power optimization
N Togawa, K Ukai, M Yanagisawa, T Ohtsuki
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 9 ( 1-2 ) 99 - 112 1999.02
2種類のレジスタファイルを持ったディジタル信号処理向けプロセッサのハードウェア/ソフトウェア協調合成システムとその並列化コンパイラ
NAKAMURA Tsuyoshi, TOGAWA Nozomu, YANAGISAWA Masao, OHTSUKI Tatsuo
電子情報通信学会技術研究報告 FTS98;132 71 - 78 1999.02
A hardware/software partitioning algorithm for processor cores of digital signal processing
N Togawa, T Sakurai, M Yanagisawa, T Ohtsuki
PROCEEDINGS OF ASP-DAC '99 335 - 338 1999 [Refereed]
A hardware/software partitioning algorithm for processor cores of digital signal processing
N Togawa, T Sakurai, M Yanagisawa, T Ohtsuki
PROCEEDINGS OF ASP-DAC '99 335 - 338 1999
A high-level synthesis system for digital signal processing based on data-flow graph enumeration
N Togawa, T Hisaki, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E81A ( 12 ) 2563 - 2575 1998.12
FPGAのマクロブロックを対象とした配置概略配線同時処理手法
情報処理学会研究報告 98-DA;90 1998.12
A high-level synthesis system for digital signal processing based on data-flow graph enumeration
N Togawa, T Hisaki, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E81A ( 12 ) 2563 - 2575 1998.12
N Togawa, M Yanagisawa, T Ohtsuki
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 17 ( 9 ) 803 - 818 1998.09 [Refereed]
最適解を保証するリソースバインディング手法
情報処理学会DAシンポジウム'98論文集 1998.07
A fast scheduling algorithm based on gradual time-frame reduction for datapath synthesis
N Togawa, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E81A ( 6 ) 1231 - 1241 1998.06
An FPGA layout reconfiguration algorithm based on global routes for engineering changes in system design specifications
N Togawa, K Hagi, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E81A ( 5 ) 873 - 884 1998.05
An FPGA layout reconfiguration algorithm based on global routes for engineering changes in system design specifications
N Togawa, K Hagi, M Yanagisawa, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E81A ( 5 ) 873 - 884 1998.05
ツリー状に接続されたLUTを対象とした深さ制約付きテクノロジーマッピング手法
電子情報通信学会第11回回路とシステム軽井沢ワークショップ論文集 1998.04
パイプラインプロセッサのハードウェア記述自動生成手法
電子情報通信学会技術研究報告 VLD97;117 1998.03
ディジタル信号処理向けプロセッサの自動合成システムにおける並列化コンパイラ
電子情報通信学会技術研究報告 VLD97;116 1998.03
ディジタル信号処理向けプロセッサのハードウェア/ソフトウェア協調合成システム
TOGAWA Nozomu, SAKURAI Takashi, YANAGISAWA Masao, OHTSUKI Tatsuo
電子情報通信学会技術研究報告 VLD97;115 ( 576 ) 17 - 24 1998.03
平成9年度(第21回)丹羽記念賞
丹羽記念会 1998.02
An incremental placement and global routing algorithm for field-programmable gate arrays
N Togawa, K Hagi, M Yanagisawa, T Ohtsuki
PROCEEDINGS OF THE ASP-DAC '98 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1998 WITH EDA TECHNO FAIR '98 519 - 526 1998 [Refereed]
A high-level synthesis system for digital signal processing based on enumerating data-flow graphs
N Togawa, T Hisaki, M Yanagisawa, T Ohtsuki
PROCEEDINGS OF THE ASP-DAC '98 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1998 WITH EDA TECHNO FAIR '98 265 - 274 1998 [Refereed]
A Fast Scheduling Algorithm Based on Gradual Time-Frame Reduction for Datapath Synthesis
IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences E81-A/6 1231 - 1240 1998
A simultaneous placement and global routing algorithm for FPGAs with power optimization
N Togawa, K Ukai, M Yanagisawa, T Ohtsuki
APCCAS '98 - IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS 125 - 128 1998
An incremental placement and global routing algorithm for field-programmable gate arrays
N Togawa, K Hagi, M Yanagisawa, T Ohtsuki
PROCEEDINGS OF THE ASP-DAC '98 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1998 WITH EDA TECHNO FAIR '98 519 - 526 1998
A high-level synthesis system for digital signal processing based on enumerating data-flow graphs
N Togawa, T Hisaki, M Yanagisawa, T Ohtsuki
PROCEEDINGS OF THE ASP-DAC '98 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1998 WITH EDA TECHNO FAIR '98 265 - 274 1998
N Togawa, M Sato, T Ohtsuki
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 7 ( 5 ) 373 - 393 1997.10 [Refereed]
A performance-oriented simultaneous placement and global routing algorithm for transport-processing FPGAs
N Togawa, M Sato, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E80A ( 10 ) 1795 - 1806 1997.10
連想メモリを搭載したハードウェアエンジンによる故障回路並列故障シミュレーションの高速化手法
電子情報通信学会技術研究報告 CPSY97;76 ( 103 ) 81 - 88 1997.10
Fast scheduling and allocation algorithms for entropy CODEC
K Suzuki, N Togawa, M Sato, T Ohtsuki
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E80D ( 10 ) 982 - 992 1997.10
A performance-oriented simultaneous placement and global routing algorithm for transport-processing FPGAs
N Togawa, M Sato, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E80A ( 10 ) 1795 - 1806 1997.10
機能メモリを使用したプロセッサを対象とするハードウェア/ソフトウェア協調合成システム
電子情報通信学会技術研究報告 CPSY98;85 1997.09
ディジタル信号処理を対象とした高位合成システムにおける高速なスケジューリングアルゴリズム
情報処理学会DAシンポジウム'97論文集 1997.07
FPGAを対象とした低消費電力指向配置・概略配線同時処理手法
UKAI Kaoru, TOGAWA Nozomu, SATO Masao, OHTSUKI Tatsuo
電子情報通信学会技術研究報告 VLD97;42 ( 141 ) 191 - 198 1997.06
システム設計仕様部分的変更を実現する概略配線径路を考慮したFPGA向けレイアウト再構成手法
電子情報通信学会第10回回路とシステム軽井沢ワークショップ論文集 1997.04
A circuit partitioning algorithm with path delay constraints for multi-FPGA systems
N Togawa, M Sato, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E80A ( 3 ) 494 - 505 1997.03
A circuit partitioning algorithm with path delay constraints for multi-FPGA systems
N Togawa, M Sato, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E80A ( 3 ) 494 - 505 1997.03
スケッチレイアウトシステムにおけるBGAパッケージ配線手法
電子情報通信学会VLSI設計技術研究会 VLD96;96 1997.03
接続コストの最小化を目的とした高速アロケーション手法
KATO Kenkichi, TOGAWA Nozomu, SATO Masao, OHTSUKI Tatsuo
電子情報通信学会VLSI設計技術研究会 VLD96;96 ( 556 ) 1 - 8 1997.03
A Circuit Partitioning Alglrithm with Replication Capability for Multi-FPGA Systems
IEICE Trans,on Fundementals of Eledtronics,Communications and Computer Sciences E78-A/13 1118 - 1123 1997
Simultaneous placement and global routing for transport-processing FPGA layout
N Togawa, M Sato, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E79A ( 12 ) 2140 - 2150 1996.12
Dharmaアーキテクチャに基づくFPGAチップの試作
マイクロエレクトロニクス研究開発機構第15回研究交流会 1996.12
Scheduling and Allocation Algorithms for Entropy CODEC
SUZUKI K.
Proceedings of the Sixth Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'96) 149 - 154 1996.11
パス長制約を考慮した通信処理用FPGA向け配置・概略配線同時処理手法
TOGAWA Nozomu, SATO Masao, OHTSUKI Tatsuo
情報処理学会設計自動化研究会 DA96;81 ( 299 ) 9 - 16 1996.10
高位合成システムを用いた画像符号化アルゴリズムのハードウェア合成法
情報処理学会DAシンポジウム'96論文集 1996.08
安藤研究所第9回安藤博記念学術奨励賞
1996.06
通信処理用FPGAを対象とした配置・概略配線同時処理手法
TOGAWA Nozomu, SATO Masao, OHTSUKI Tatsuo
情報処理学会設計自動化研究会 DA96;80 15 - 22 1996.05
電子情報通信学会第8回回路とシステム軽井沢ワークショップ研究奨励賞
1996.04
A simultaneous technology mapping, placement, and global routing algorithm for FPGAs with path delay constraints
N Togawa, M Sato, T Ohtsuki
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E79A ( 3 ) 321 - 329 1996.03 [Refereed]
N Togawa, M Sato, T Ohtsuki
PROCEEDINGS OF THE ASP-DAC '97 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1997 569 - 578 1996 [Refereed]
A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs
N Togawa, M Sato, T Ohtsuki
PROCEEDINGS OF THE ASP-DAC '97 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1997 569 - 578 1996
A performance-oriented circuit partitioning algorithm with logic-block replication for multi-FPGA systems
N Togawa, M Sato, T Ohtsuki
APCCAS '96 - IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS '96 294 - 297 1996
Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29 - September 1, 1995 319 - 327 1995 [Refereed]
MAPLE - A SIMULTANEOUS TECHNOLOGY MAPPING, PLACEMENT, AND GLOBAL ROUTING ALGORITHM FOR FIELD-PROGRAMMABLE GATE ARRAYS
N TOGAWA, M SATO, T OHTSUKI
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E77A ( 12 ) 2028 - 2038 1994.12 [Refereed]
MAPLE - A SIMULTANEOUS TECHNOLOGY MAPPING, PLACEMENT, AND GLOBAL ROUTING ALGORITHM FOR FPGAS
N TOGAWA, M SATO, T OHTSUKI
APCCAS '94 - 1994 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS 554 - 559 1994 [Refereed]
A SIMULTANEOUS PLACEMENT AND GLOBAL ROUTING ALGORITHM FOR FPGAS
N TOGAWA, M SATO, T OHTSUKI
1994 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1 A483 - A486 1994 [Refereed]
Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994 156 - 163 1994 [Refereed]
CMOS VLSI 回路設計 応用編
ウェスト,ハリス著, 宇佐美公良, 池田誠, 小林和淑監訳, 戸川望他分担共訳( Part: Joint translator)
丸善出版 2014.01 ISBN: 9784621087206
組込みシステム概論
戸川望編著
CQ出版 2008.02 ISBN: 9784789845502
佐伯, 越志, 鮑, 思雅, 高山, 敏典, 戸川, 望
マルチメディア,分散,協調とモバイルシンポジウム2022論文集 2022 1556 - 1569 2022.07
Hardware-Trojan Classification at Practical Trojan Netlists Utilizing Random Forests
コンピュータセキュリティシンポジウム2021論文集 9 - 16 2021.10
コンピュータセキュリティシンポジウム2021論文集 17 - 24 2021.10
Hardware-Trojan Detection Utilizing Graph Neural Networks at Gate-Level Netlists
コンピュータセキュリティシンポジウム2021論文集 1 - 8 2021.10
スマートフォンとスマートウォッチを併用したPDRによる屋内位置推定
若泉 朋弥, 戸川 望
マルチメディア,分散協調とモバイルシンポジウム2205論文集 ( 2020 ) 1290 - 1302 2020.06
モンテカルロ木探索を用いたユーザ個人の嗜好を考慮した経路推薦手法の高速化
石崎 雄太, 高山 敏典, 戸川 望
マルチメディア,分散協調とモバイルシンポジウム2206論文集 ( 2020 ) 1303 - 1310 2020.06
メタヒューリスティクスの制約なし二次形式二値変数最適化問題への適用 (システム数理と応用)
多和田 雅師, 戸川 望
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 119 ( 470 ) 43 - 48 2020.03
イジング計算機による3次元直方体パッキング問題の解法 (VLSI設計技術)
金丸 翔, 寺田 晃太朗, 川村 一志, 田中 宗, 富田 憲範, 戸川 望
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 119 ( 443 ) 173 - 178 2020.03
トリガ回路の性質にもとづく特徴量を利用したニューラルネットワークによるハードウェアトロイ識別 (VLSI設計技術)
井上 智貴, 長谷川 健人, 戸川 望
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 119 ( 443 ) 227 - 232 2020.03
イジングマシンを用いたアミューズメントパークの経路最適化手法 (VLSI設計技術)
武笠 陽介, 若泉 朋弥, 田中 宗, 戸川 望
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 119 ( 443 ) 167 - 172 2020.03
乱数化関数を用いた乱数生成回路を共有するストカスティック数生成器 (VLSI設計技術)
多和田 雅師, 戸川 望
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 119 ( 443 ) 163 - 166 2020.03
イジングモデルによる類似誘導部分グラフ同型問題の解法 (VLSI設計技術) -- (デザインガイア2019 : VLSI設計の新しい大地)
吉村 夏一, 多和田 雅師, 田中 宗, 新井 淳也, 巴 徳瑪, 八木 哲志, 内山 寛之, 戸川 望
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 119 ( 282 ) 103 - 108 2019.11
ストカスティック計算におけるステップ関数の実装と評価 (VLSI設計技術) -- (デザインガイア2019 : VLSI設計の新しい大地)
石川 遼太, 多和田 雅師, 柳澤 政生, 戸川 望
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 119 ( 282 ) 69 - 74 2019.11
低密度パリティ検査符号復号問題を制約なし二次形式二値変数最適化問題に変換した解法
多和田 雅師, 田中 宗, 戸川 望
DAシンポジウム2019論文集 ( 2019 ) 45 - 50 2019.08
スリープ状態をもつ組込みシステムを対象とした電力解析にもとづく異常動作検知とその実証的評価
長谷川 健人, 近松 聖, 戸川 望
DAシンポジウム2019論文集 ( 2019 ) 93 - 98 2019.08
ストカスティック数を用いた再帰的分割による解像度解釈可変な画像形式 (VLSI設計技術)
石川 遼太, 多和田 雅師, 柳澤 政生, 戸川 望
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 119 ( 154 ) 71 - 76 2019.07
モンテカルロ木探索によるユーザ個人の嗜好を考慮した経路推薦手法とその評価
石崎 雄太, 高山 敏典, 戸川 望
マルチメディア,分散協調とモバイルシンポジウム2019論文集 ( 2019 ) 854 - 862 2019.06
動的な歩幅更新をベースとするマップマッチングによるPDR手法
西村 天晴, 高山 敏典, 柳澤 政生, 戸川 望
マルチメディア,分散協調とモバイルシンポジウム2019論文集 ( 2019 ) 1663 - 1669 2019.06
宇佐見 友理, 石川 和明, 高山 敏典, 柳澤 政生, 戸川 望
マルチメディア,分散協調とモバイルシンポジウム2019論文集 ( 2019 ) 1670 - 1675 2019.06
2ⁿRRR : 高度な並び替えにより誤り耐性を強化したストカスティック数複製器 (VLSI設計技術) -- (デザインガイア2018 : VLSI設計の新しい大地)
石川 遼太, 多和田 雅師, 柳澤 政生, 戸川 望
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 118 ( 334 ) 95 - 100 2018.12
高位合成時のモジュール分割におけるバッファコスト最小化問題とその解法
大場 諒介, 川村 一志, 田宮 豊, 柳澤 政生, 戸川 望
DAシンポジウム2018論文集 ( 2018 ) 63 - 68 2018.08
西澤 誠人, 長谷川 健人, 柳澤 政生, 戸川 望
DAシンポジウム2018論文集 ( 2018 ) 112 - 117 2018.08
マイクロコントローラのスリープ状態に着目した消費電力にもとづく悪意のある機能の発現検知
長谷川 健人, 柳澤 政生, 戸川 望
DAシンポジウム2018論文集 ( 2018 ) 118 - 123 2018.08
スマートフォン搭載3軸加速度センサと3軸ジャイロセンサを用いた自転車の挙動認識
宇佐見 友理, 石川 和明, 高山 敏典, 柳澤 政生, 戸川 望
マルチメディア,分散協調とモバイルシンポジウム2018論文集 ( 2018 ) 32 - 42 2018.06
西村 天晴, 石川 和明, 高山 敏典, 柳澤 政生, 戸川 望
マルチメディア,分散協調とモバイルシンポジウム2018論文集 ( 2018 ) 1612 - 1621 2018.06
再収斂による計算誤りに耐性を持つストカスティック数複製器を用いた活性化関数の実装と評価
石川遼太, 多和田雅師, 柳澤政生, 戸川望
電子情報通信学会技術研究報告 118 ( 83 ) 167 - 172 2018.06
金丸翔, 於久太祐, 多和田雅師, 田中宗, 田中宗, 林真人, 山岡雅直, 柳澤政生, 戸川望
電子情報通信学会技術研究報告 118 ( 85(MSS2018 1-36) ) 161‐166 2018.06
亜種ハードウェアトロイの設計とそのニューラルネットワークを用いた検出
井上智貴, 長谷川健人, 小林悠記, 柳澤政生, 戸川望
電子情報通信学会技術研究報告 118 ( 85(MSS2018 1-36) ) 173‐178 2018.06
リーク削減による低消費電力SRAMの設計—A low power SRAM design with leakage power reduction
伊藤 卓, 戸川 望, 柳澤 政生, 史 又華
回路とシステムワークショップ論文集 Workshop on Circuits and Systems 31 197 - 202 2018.05
低周波圧電エネルギーハーベスティングにおけるMOSs SP-SSHI手法—MOSs SP-SSHI for low frequency piezoelectric energy harvesting
杉山 貴紀, 戸川 望, 柳澤 政生, 史 又華
回路とシステムワークショップ論文集 Workshop on Circuits and Systems 31 86 - 91 2018.05
CNNに対する概算加算器の適用と評価—Application and evaluation of CNN with approximate adders
井上 雄太, 戸川 望, 柳澤 政生, 史 又華
回路とシステムワークショップ論文集 Workshop on Circuits and Systems 31 191 - 196 2018.05
鍵長128ビット,192ビット,256ビットの軽量暗号CLEFIAに対するスキャンベース攻撃手法
於久太祐, 多和田雅師, 柳澤政生, 戸川望
電子情報通信学会技術研究報告 117 ( 480 ) 251 - 256 2018.03
鍵長128ビット,192ビット,256ビットの軽量暗号CLEFIAに対するスキャンベース攻撃手法 (コンピュータシステム) -- (組込み技術とネットワークに関するワークショップETNET2018)
於久 太祐, 多和田 雅師, 柳澤 政生, 戸川 望
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 117 ( 479 ) 251 - 256 2018.03
複数エリアへの近接度を用いたパーティクルフィルタによる屋内測位手法の適用
百瀬凌也, 石川和明, 柳澤政生, 戸川望
電子情報通信学会大会講演論文集(CD-ROM) 2018 ROMBUNNO.A‐14‐7 2018.03
凍結ビットパタンの偏りを利用した高速Polar符号復号器とそのハードウェア実装の検討
多和田雅師, 神谷典史, 井手口裕太, 井上浩明, 戸川望
電子情報通信学会大会講演論文集(CD-ROM) 2018 ROMBUNNO.A‐1‐12 2018.03
LSIの配線問題―DAシンポジウムの配線問題解法コンテスト―2 機械学習とFPGAを用いた配線問題解法への取り組み
川村一志, 長谷川健人, 多和田雅師, 戸川望
情報処理 59 ( 3 ) 228‐231 2018.02
低周波圧電エネルギーハーベスティングにおけるMOSs SP‐SSHI手法
杉山貴紀, 戸川望, 柳澤政生, SHI Youhua
回路とシステムワークショップ論文集(CD-ROM) 31st ROMBUNNO.A2‐1 2018
伊藤卓, 戸川望, 柳澤政生, SHI Youhua
回路とシステムワークショップ論文集(CD-ROM) 31st ROMBUNNO.C4‐3 2018
トリガ条件の異なるハードウェアトロイの設計とSVMを用いた検出 (VLSI設計技術) -- (デザインガイア2017 : VLSI設計の新しい大地)
井上 智貴, 長谷川 健人, 小林 悠記, 柳澤 政生, 戸川 望
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 117 ( 273 ) 133 - 138 2017.11
暗号回路に挿入されたハードウェアトロイとその抑止回路のFPGA実装 (VLSI設計技術) -- (デザインガイア2017 : VLSI設計の新しい大地)
長谷川 健人, 柳澤 政生, 戸川 望
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 117 ( 273 ) 139 - 144 2017.11
Stochastic logic circuit using static constant as coefficient without random number generator
117 ( 273 ) 121 - 124 2017.11
スキャンシグネチャを用いた周辺回路を含む軽量暗号CLEFIAに対するスキャンベース攻撃
於久 太祐, 多和田 雅師, 柳澤 政生, 戸川 望
DAシンポジウム2017論文集 ( 2017 ) 116 - 121 2017.08
20KスピンCMOSアニーリングマシンを対象とした完全結合イジングモデルマッピング手法と評価
寺田 晃太朗, 田中 宗, 林 真人, 山岡 雅直, 柳澤 政生, 戸川 望
DAシンポジウム2017論文集 ( 2017 ) 163 - 168 2017.08
平井 勇也, 川村 一志, 柳澤 政生, 戸川 望
DAシンポジウム2017論文集 ( 2017 ) 180 - 185 2017.08
石川 遼太, 多和田 雅師, 柳澤 政生, 戸川 望
DAシンポジウム2017論文集 ( 2017 ) 169 - 174 2017.08
百瀬 凌也, 新田 知之, 柳澤 政生, 戸川 望
マルチメディア,分散協調とモバイルシンポジウム2017論文集 ( 2017 ) 514 - 522 2017.06
疎な GPS 測位情報を対象にした測位精度と短時間滞在除去に基づく滞在地推定手法
岩田 紗瑛, 新田 知之, 高山 敏典, 柳澤 政生, 戸川 望
マルチメディア,分散協調とモバイルシンポジウム2017論文集 ( 2017 ) 523 - 531 2017.06
連続してハッシュ値を出力しないHMAC-SHA-256回路へのスキャンベース攻撃手法 (ディペンダブルコンピューティング) -- (組込み技術とネットワークに関するワークショップETNET2017)
於久 太祐, 柳澤 政生, 戸川 望
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 116 ( 511 ) 129 - 134 2017.03
ネットの特徴量を用いた多層ニューラルネットワークによるハードウェアトロイ識別 (ディペンダブルコンピューティング) -- (組込み技術とネットワークに関するワークショップETNET2017)
長谷川 健人, 柳澤 政生, 戸川 望
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 116 ( 511 ) 135 - 140 2017.03
連続してハッシュ値を出力しないHMAC-SHA-256回路へのスキャンベース攻撃手法 (コンピュータシステム) -- (組込み技術とネットワークに関するワークショップETNET2017)
於久 太祐, 柳澤 政生, 戸川 望
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 116 ( 510 ) 129 - 134 2017.03
ネットの特徴量を用いた多層ニューラルネットワークによるハードウェアトロイ識別 (コンピュータシステム) -- (組込み技術とネットワークに関するワークショップETNET2017)
長谷川 健人, 柳澤 政生, 戸川 望
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 116 ( 510 ) 135 - 140 2017.03
A Design Technique for Approximate Circuits based on Artificial Neural Network
116 ( 478 ) 25 - 30 2017.03
PDRの測位誤差補正のためのマルチシナリオ化マップマッチング手法 (画像工学)
岩名地 良太, 新田 知之, 柳澤 政生, 戸川 望
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 116 ( 464 ) 387 - 392 2017.02
岩名地 良太, 新田 知之, 柳澤 政生, 戸川 望
映像情報メディア学会技術報告 = ITE technical report 41 ( 5 ) 387 - 392 2017.02
Finite state machine design for high accurate stochastic computing
116 ( 415 ) 171 - 174 2017.01
An Evaluation Method of Road Illuminance Levels Using Road Lights and Landmarks
BAO Siya, YANAGISAWA Masao, TOGAWA Nozomu
電子情報通信学会大会講演論文集(CD-ROM) 2017 2017
Proposal of pH-sensor device capable of operating only with NFC energy harvesting
MIYABAYASHI Shun, OSAKA Tetsuya, TAWADA Masashi, TOGAWA Nozomu, KATAOKA Kosuke, ASAHI Toru, IWATA Hiroyasu, HAYATA Hiroki, IWASE Eiji, FUJIE Toshinori, TAKEOKA Shinji, OHASHI Keishi, SATO Shin, KUROIWA Shigeki, MOMMA Toshiyuki
The Proceedings of JSME annual Conference on Robotics and Mechatronics (Robomec) 2017 ( 0 ) 1A1 - L10 2017
セレクタ論理に帰着させたバタフライ演算器のFPGA実装評価 (VLSI設計技術) -- (デザインガイア2016 : VLSI設計の新しい大地)
伊東 光希, 柳澤 政生, 戸川 望
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 116 ( 330 ) 67 - 72 2016.11
動作中のIoTデバイスに対する電気容量変化の測定を用いた不正改変検知装置の設計 (VLSI設計技術) -- (デザインガイア2016 : VLSI設計の新しい大地)
北山 遼育, 竹中 崇, 柳澤 政生, 戸川 望
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 116 ( 330 ) 129 - 134 2016.11
経年劣化を考慮したフロアプラン統合化高位合成手法 (VLSI設計技術) -- (デザインガイア2016 : VLSI設計の新しい大地)
井川 昂輝, 柳澤 政生, 戸川 望
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 116 ( 330 ) 141 - 146 2016.11
スキャンシグネチャを用いたスキャンデータ解析に基づくHMAC-SHA-256ハッシュ回路のスキャンベース攻撃
於久 太祐, 多和田 雅師, 柳澤 政生, 戸川 望
DAシンポジウム2016論文集 2016 ( 2 ) 2 - 7 2016.09
Random Forestを用いたネットリスト特徴選択と機械学習によるハードウェアトロイ識別
長谷川 健人, 柳澤 政生, 戸川 望
DAシンポジウム2016論文集 2016 ( 3 ) 8 - 13 2016.09
リードソロモン符号に基づいたマルチレベルセル不揮発性メモリ書き込み削減
多和田 雅師, 柳澤 政生, 戸川 望
DAシンポジウム2016論文集 2016 ( 31 ) 163 - 168 2016.09
歩行者の方向判断基準を用いた腕時計型ウェアラブル端末向け略地図生成手法
河野 圭亮, 新田 知之, 石川 和明, 柳澤 政生, 戸川 望
マルチメディア,分散協調とモバイルシンポジウム2016論文集 ( 2016 ) 411 - 418 2016.07
眼鏡型ウェアラブル端末を用いたランドマーク確認に基づく屋外歩行者ナビゲーション
矢野 椋也, 新田 知之, 石川 和明, 柳澤 政生, 戸川 望
マルチメディア,分散協調とモバイルシンポジウム2016論文集 ( 2016 ) 419 - 427 2016.07
岩名地 良太, 新田 知之, 石川 和明, 柳澤 政生, 戸川 望
マルチメディア,分散協調とモバイルシンポジウム2016論文集 ( 2016 ) 1748 - 1756 2016.07
Verification Experiment of Scan-based Attack against a Trivium Cipher Circuit
116 ( 96 ) 7 - 12 2016.06
Hardware Trojan Identification based on Netlist Features using Neural Networks
116 ( 96 ) 1 - 6 2016.06
Hardware Trojan Identification based on Netlist Features using Neural Networks
116 ( 95 ) 1 - 6 2016.06
Verification Experiment of Scan-based Attack against a Trivium Cipher Circuit
116 ( 95 ) 7 - 12 2016.06
A-6-4 Improvement and Evaluation of Selector-logic-based Volume Rendering Circuits for FPGAs
Igarashi Keita, Yanagisawa Masao, Togawa Nozomu
Proceedings of the IEICE Engineering Sciences Society/NOLTA Society Conference 2016 78 - 78 2016.03
A-6-5 Evaluation of A Floorplan-aware High-level Synthesis Algorithm Optimizing Critical Path for FPGA Designs
Fujiwara Koichi, Kawamura Kazushi, Yanagisawa Masao, Togawa Nozomu
Proceedings of the IEICE Engineering Sciences Society/NOLTA Society Conference 2016 79 - 79 2016.03
FPGA Design and Evaluation of Volume Rendering Circuits Using Selector Logic
115 ( 465 ) 119 - 124 2016.02
A floorplan-driven high-level synthesis algorithm resilient to dynamic delay variations
115 ( 398 ) 209 - 214 2016.01
115 ( 338 ) 183 - 188 2015.12
A-3-7 Worst-case Bit-Write-Reducing and Error-Correcting Code Generation by One-to-many Mapping for Non-Volatile Memories
Kojo Tatsuro, Tawada Masashi, Yanagisawa Masao, Togawa Nozomu
Proceedings of the IEICE Engineering Sciences Society/NOLTA Society Conference 2015 52 - 52 2015.08
A-9-2 Low-power soft-error tolerant New-SEH latch scheme
TAJIMA Saki, SHI Youhua, TOGAWA Nozomu, YANAGISAWA Masao
Proceedings of the IEICE Engineering Sciences Society/NOLTA Society Conference 2015 106 - 106 2015.08
Field-Data Extractor Construction Based on Rotator-Based Multiplexer Network
( 2015 ) 29 - 34 2015.08
( 2015 ) 143 - 148 2015.08
Scalable and Small Power Analyzer Design with Noise Redcution for Low-Power IoT Devices
( 2015 ) 161 - 166 2015.08
製造ばらつきと配線遅延を同時に考慮した低レイテンシ指向のマルチシナリオ高位合成の評価 (ディペンダブルコンピューティング)
井川 昂輝, 阿部 晋矢, 柳澤 政生, 戸川 望
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 114 ( 507 ) 155 - 160 2015.03
Improved scan-based side-channel attack on the LED block cipher
FUJISHIRO MIKA, YANAGISAWA MASAO, TOGAWA NOZOMU
IEICE technical report. Dependable computing 114 ( 507 ) 149 - 154 2015.03
Improved scan-based side-channel attack on the LED block cipher
FUJISHIRO MIKA, YANAGISAWA MASAO, TOGAWA NOZOMU
IEICE technical report. Computer systems 114 ( 506 ) 149 - 154 2015.03
A Score-Based Hardware-Trojan Identification Method for Gate-Level Netlists
OYA Masaru, SHI Youhua, YANAGISAWA Masao, TOGAWA Nozomu
Technical report of IEICE. VLD 114 ( 476 ) 165 - 170 2015.03
製造ばらつきと配線遅延を同時に考慮した低レイテンシ指向のマルチシナリオ高位合成の評価
井川 昂輝, 阿部 晋矢, 柳澤 政生, 戸川 望
情報処理学会研究報告. SLDM, [システムLSI設計技術] 2015 ( 48 ) 1 - 6 2015.02
A-3-1 Interconnection Delay Modeling for Floorplan-Driven High-Level Synthesis Targeting FPGAs
Fujiwara Koichi, Yanagisawa Masao, Togawa Nozomu
Proceedings of the IEICE General Conference 2015 80 - 80 2015.02
A-3-8 Implementation and Evaluation of Selector-logic-based Alpha Blending Circuits for FPGAs
Igarashi Keita, Yanagisawa Masao, Togawa Nozomu
Proceedings of the IEICE General Conference 2015 87 - 87 2015.02
A Hardware Trojan Detection Method based on Trojan Net Features
OYA Masaru, SHI Youhua, YANAGISAWA Masao, TOGAWA Nozomu
Technical report of IEICE. VLD 114 ( 426 ) 157 - 162 2015.01
A Hardware Trojan Detection Method based on Trojan Net Features
OYA Masaru, SHI Youhua, YANAGISAWA Masao, TOGAWA Nozomu
IEICE technical report. Computer systems 114 ( 427 ) 157 - 162 2015.01
A Hardware Trojan Detection Method based on Trojan Net Features
大屋 優, 史 又華, 柳澤 政生, 戸川 望
情報処理学会研究報告. SLDM, [システムLSI設計技術] 2015 ( 28 ) 1 - 6 2015.01
A Field Data Extractor Configuration Based on Multiplexer Tree Partitioning
ITO Koki, KAWAMURA Kazushi, YANAGISAWA Masao, TOGAWA Nozomu, TAMIYA Yutaka
Technical report of IEICE. VLD 114 ( 328 ) 197 - 202 2014.11
YOSHIDA Shinnosuke, SHI Youhua, YANAGISAWA Masao, TOGAWA Nozomu
Technical report of IEICE. VLD 114 ( 328 ) 57 - 62 2014.11
ABE Shin-ya, SHI Youhua, USAMI Kimiyoshi, YANAGISAWA Masao, TOGAWA Nozomu
Technical report of IEICE. VLD 114 ( 328 ) 203 - 208 2014.11
IGAWA Koki, ABE Shinya, YANAGISAWA Masao, TOGAWA Nozomu
Technical report of IEICE. VLD 114 ( 328 ) 105 - 110 2014.11
KOJO Tatsuro, TAWADA Masashi, YANAGISAWA Masao, TOGAWA Nozomu
Technical report of IEICE. VLD 114 ( 328 ) 221 - 226 2014.11
Small-Sized Encoder/Decoder Circuit Design for Bit-Write Reduction Targeting Non-Volatile Memories
TAWADA Masashi, KIMURA Shinji, YANAGISAWA Masao, TOGAWA Nozomu
Technical report of IEICE. VLD 114 ( 328 ) 227 - 232 2014.11
KAWAMURA Kazushi, ABE Shinya, SHI Youhua, YANAGISAWA Masao, TOGAWA Nozomu
Technical report of IEICE. VLD 114 ( 328 ) 51 - 56 2014.11
Design of Flip-Flop with Timing Error Tolerance
SUZUKI Taito, SHI Youhua, TOGAWA Nozomu, USAMI Kimiyoshi, YANAGISAWA Masao
Technical report of IEICE. VLD 114 ( 328 ) 45 - 50 2014.11
A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay Characteristics in FPGA Designs
FUJIWARA Koichi, YANAGISAWA Masao, TOGAWA Nozomu
Technical report of IEICE. VLD 114 ( 328 ) 99 - 104 2014.11
High speed design of sub-threshold circuit by using DTMOS
FUKUDOME Yuji, SHI Youhua, TOGAWA Nozomu, USAMI Kimiyoshi, YANAGISAWA Masao
Technical report of IEICE. VLD 114 ( 328 ) 117 - 121 2014.11
A Hardware Trojans Detection Method focusing on Nets in Hardware Trojans in Gate-Level Netlists
OYA Masaru, SHI Youhua, YANAGISAWA Masao, TOGAWA Nozomu
Technical report of IEICE. VLD 114 ( 328 ) 135 - 140 2014.11
A High-level Synthesis Algorithm with Delay Variation Tolerance Optimization for RDR Architectures
HAGIO Yuta, YANAGISAWA Masao, TOGAWA Nozomu
Technical report of IEICE. VLD 114 ( 328 ) 209 - 214 2014.11
Design of Flip-Flop with Timing Error Tolerance
SUZUKI Taito, SHI Youhua, TOGAWA Nozomu, USAMI Kimiyoshi, YANAGISAWA Masao
IEICE technical report. Dependable computing 114 ( 329 ) 45 - 50 2014.11
A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay Characteristics in FPGA Designs
FUJIWARA Koichi, YANAGISAWA Masao, TOGAWA Nozomu
IEICE technical report. Dependable computing 114 ( 329 ) 99 - 104 2014.11
Citation count denotes the number of citations in papers published for a particular year.