This article introduces an SRAM-based physically unclonable function (PUF) that employs hybrid-mode operations in the enhancement-enhancement (EE) SRAM mode and CMOS SRAM mode to achieve both high native stability and low power. A data latching scheme based on the hybrid structure enables operations under low supply voltage (VDD). Furthermore, the proposed hybrid SRAM PUF is compatible with hot carrier injection (HCI) burn-in stabilization, which can reinforce PUF stability to ~100% without the requirements of bitcell redundancy, visible oxide damages, additional fabrication processes, helper data storage, or error-correcting code (ECC) circuits. The proposed PUF is fabricated in 130-nm standard CMOS, and the experimental results show that it achieves 0.29% native bit error rate (BER) at the nominal condition of 0.6 V/25 °C. The operating VDD scales down to 0.5 V, with a core energy efficiency of 2.07 fJ/b. After HCI burn-in, no bit errors are found across all VDD/temperature (VT) corners from 0.5 to 0.7 V and from -40 °C to 120 °C (5120 bits x 500 evaluations tested at each condition). Long-term reliability is verified by using an accelerated aging test equivalent to approximately 21 years of operation, where the reinforced PUF shows no bit errors even at the worst VT corner of 0.5 V/120 °C during the test. The introduced hybrid SRAM PUF also passes all applicable NIST SP 800-22 randomness tests. It has a compact bitcell with an area of 497 F².

This paper presents an Enhancement-Enhancement (EE) SRAM physically unclonable function (PUF) with a dark-bit detection technique based on an integrated Vss-bias generator. The EE SRAM PUF cell improves native stability to 0.21% bit-error rate (BER). Bit cells that are potentially unstable due to environmental variations or aging are detected via the lightweight bias generator to ensure stability, and the effectiveness is verified with experimental results of dark-bit detection performed at room temperature. Measurement results of 10 chips in 130-nm CMOS show that after masking the detected dark bits, 1.3×10 BER is achieved across 0.8-1.4 V/-40-120 °C VT corners. The nMOS-only bit cell is also highly compact (i.e., 373 F ). Moreover, a 2D power-gating scheme is implemented for low operation energy, low standby power, and high attack tolerance. -6 2

This article proposes a mismatch self-compensation latch-based true random number generator (TRNG) that harvests a metastable region's enhanced random noise. The proposed TRNG exhibits high randomness across a wide voltage (0.3-1.0 V) and temperature (-20 degrees C-100 degrees C) range by employing XOR of only four entropy sources (ESs). To achieve a full entropy output, an 8-bit von Neumann post-processing with waiting (VN8W) is used. The randomness of the TRNG's output is verified by NIST SP 800-22 and NIST SP 800-90B tests. The proposed TRNG, fabricated in 130-nm CMOS, achieves state-of-the-art energy of 0.186 pJ/bit at 0.3 V with a core (four ESs + XOR circuits) area of 661 mu m(2) and a total area of 5561 mu m(2), including VN8W. The robustness against power noise injection attacks is also demonstrated. An accelerating aging test revealed that the TRNG achieves a stable operation after 19 h of aging, which is equivalent to the 11-year life reliability. The mismatch-to-noise ratio analysis revealed that the XOR-OUT of TRNG core has more than 6 sigma robustness against random mismatch variations.

This paper presents a latch-based TRNG that achieves high raw entropy generation (>0.9) across wide voltage and temperature (0.31.0 V, -40110 °C) in a single latch-based entropy source by static inverter selection and noise enhancement techniques. In a 130 nm CMOS technology, the TRNG occupies 5343 μm2 and consumes 0.116pJ/bit at 0.3 V including an on-chip Von Neumann post-processing circuit. The crypto-graphically-secure randomness of TRNG's output is verified by NIST SP 800-22 and 800-90B tests. An equivalent 20-year life at 0.3 V, 25°C is confirmed by an accelerated aging test.

This paper proposes a small-area low-power inverter-based true random number generator (I-TRNG) which harvests entropy from thermal noise. A single CMOS inverter is used for noise amplification. Clock-feedthrough (CLFT) compensation and body-bias technique provide robustness across a wide range of supply voltage 0.7~1.0 V and temperature -40~100 °C. An on-chip 4-bit Von-Neumann post-processing circuit is implemented for maximum entropy harvesting. I-TRNG is fabricated in 130-nm CMOS technology. It occupies 1495 µm2 (0.08846 MF2) and consumes 0.6585 pJ/bit with a throughput of 0.4456 Mbps (0.1308 Mbits/µW). The random bits generated by I- TRNG pass all FIPS 140-2 and NIST 800-22 tests.