Strong physically unclonable functions (Strong PUFs) are expected to meet the low-energy and low-latency authentication requirements of IoT applications, owing to their exponential number of challenge-response pairs (CRPs). However, Strong PUFs suffer from vulnerability to modeling attacks and a high bit-error rate (BER). The first Strong PUF, known as the arbiter PUF, has little tolerance against modeling attacks because of the linear summation of path-delay times in its response [1]. Several studies have been conducted to improve immunity by introducing non-linearity in the response-generation procedure [2] -[6]. Out of these, only look-up-table (LUT)-based solutions [2], [6] achieved a high machine-learning (ML) robustness against more than 0.1M training CRPs. However, the design in [2] requires 112K bits of entropy, and that in [6] uses many AES S-boxes, as well as entropy sources. The complex response procedures cause high native BER in Strong PUFs, although zero error is not essential because cryptography is not needed in the authentication procedure. CRP filtering [3], [5], [6], a popular countermeasure, not only reduces usable CRPs, but it also requires the server to perform additional tasks in both enrollment and authentication. Taking advantage of a LUT, one can apply SRAM-PUF stabilization techniques. Hot-carrier-injection (HCI) burn-in [7] does not reduce the number of usable bitcells. However, conventionally, it requires the inverse data to be written back before HCI burn-in. Although this could be done on-chip, it provides a potential attack point to an adversary.

This article presents a highly stable SRAM-based physically unclonable function (PUF) using enhancement-enhancement (EE)-structure bit cells for native stability improvement. The PUF bit cells are power-gated 2-D and are normally in the OFF state, which largely reduces power and is beneficial to attack tolerance. In addition, a dark-bit detection technique based on a lightweight integrated {V}_{\text {SS } } -bias generator is implemented in order to screen out potentially unstable bit cells (dark bits) induced by supply voltage/temperature (VT) variations and other factors. Measured native bit error rate (BER) of prototype chips fabricated in 130-nm standard CMOS is 0.21% at 0.8 V and 23 °C, which is 14 \times better compared with the conventional SRAM-based PUF. After masking the detected dark bits, no bit error (3339 bits \times 500 evaluations) appeared at the worst VT corner across 0.8 to 1.4 V and -40 °C to 120 °C. This technique also eliminated all unstable bits in the accelerated aging test. Both the data before and after dark-bit masking have passed all applicable NIST SP 800-22 randomness tests. The measured operational energy at 0.8 V is 128 fJ/bit and the standby power is 0.44 pW/bit, thanks to the 2-D power-gating scheme. The nMOS-only bit cell is highly compact, with a normalized bit cell area of 373 F 2

This paper presents a bit-error free SRAM-based physically unclonable function (PUF) in 130-nm standard CMOS. The PUF has a compact bitcell, with a bitcell area of 497 F2. It switches from EE SRAM to CMOS SRAM mode during evaluation, achieving high native stability, low-voltage evaluation, and low-power operation. Its stability is reinforced to 100% through hot carrier injection (HCI) burn-in on the alternate-direction nMOS load, which causes no visible oxide damage and does not require additional fabrication processes or extra transistors in the bitcell. Experimental results show that the prototype chips achieved actual zero bit error across 0.5-0.7 V and -40°C to 120 °C, as well as zero error (<1E-7 BER) at the worst VT corner after accelerated aging test equivalent to 21 years of operation. The PUF functions stably down to 0.5 V, with an energy of 2.07 fJ/b, which includes both the evaluation and read-out power. The secure, compact, low-power and 100% stable features of the PUF make it an excellent candidate for the resource-constrained Internet of Things security.

This article introduces an SRAM-based physically unclonable function (PUF) that employs hybrid-mode operations in the enhancement-enhancement (EE) SRAM mode and CMOS SRAM mode to achieve both high native stability and low power. A data latching scheme based on the hybrid structure enables operations under low supply voltage (VDD). Furthermore, the proposed hybrid SRAM PUF is compatible with hot carrier injection (HCI) burn-in stabilization, which can reinforce PUF stability to ~100&#x0025; without the requirements of bitcell redundancy, visible oxide damages, additional fabrication processes, helper data storage, or error-correcting code (ECC) circuits. The proposed PUF is fabricated in 130-nm standard CMOS, and the experimental results show that it achieves 0.29&#x0025; native bit error rate (BER) at the nominal condition of 0.6 V/25 &#x00B0;C. The operating VDD scales down to 0.5 V, with a core energy efficiency of 2.07 fJ/b. After HCI burn-in, no bit errors are found across all VDD/temperature (VT) corners from 0.5 to 0.7 V and from -40 &#x00B0;C to 120 &#x00B0;C (5120 bits x 500 evaluations tested at each condition). Long-term reliability is verified by using an accelerated aging test equivalent to approximately 21 years of operation, where the reinforced PUF shows no bit errors even at the worst VT corner of 0.5 V/120 &#x00B0;C during the test. The introduced hybrid SRAM PUF also passes all applicable NIST SP 800-22 randomness tests. It has a compact bitcell with an area of 497 F&#x00B2;.

This paper presents an Enhancement-Enhancement (EE) SRAM physically unclonable function (PUF) with a dark-bit detection technique based on an integrated Vss-bias generator. The EE SRAM PUF cell improves native stability to 0.21% bit-error rate (BER). Bit cells that are potentially unstable due to environmental variations or aging are detected via the lightweight bias generator to ensure stability, and the effectiveness is verified with experimental results of dark-bit detection performed at room temperature. Measurement results of 10 chips in 130-nm CMOS show that after masking the detected dark bits, 1.3×10 BER is achieved across 0.8-1.4 V/-40-120 °C VT corners. The nMOS-only bit cell is also highly compact (i.e., 373 F ). Moreover, a 2D power-gating scheme is implemented for low operation energy, low standby power, and high attack tolerance. -6 2