HEVC achieves a better coding efficiency relative to prior standards, but also involves dramatically increased complexity. The complexity increase for intra prediction is especially intensive due to a highly flexible quad-tree coding structure and a large number of prediction modes. The encoder employs rate-distortion optimization (RDO) to select the optimal coding mode. And RDO takes a great portion of intra encoding complexity.Moreover HEVC has stronger dependency on RDO than H.264/AVC. To reduce the computational complexity and to implement a real-time system,this paper presents two low-complexity RDO algorithms for HEVC intra prediction. The structure of RDO is simplified by the proposed rate and distortion estimators, and some hardware-unfriendly modules are facilitated. Compared with the original RDO procedure, the two proposed algorithms reduce RDO time by 46% and 64% respectively with acceptable coding efficiency loss. © 2014 Springer International Publishing.

HEVC achieves a better coding efficiency relative to prior standards, but also involves dramatically increased complexity. The complexity increase for intra prediction is especially intensive due to a highly flexible quad-tree coding structure and a large number of prediction modes. The encoder employs rate-distortion optimization (RDO) to select the optimal coding mode. And RDO takes a great portion of intra encoding complexity.Moreover HEVC has stronger dependency on RDO than H.264/AVC. To reduce the computational complexity and to implement a real-time system,this paper presents two low-complexity RDO algorithms for HEVC intra prediction. The structure of RDO is simplified by the proposed rate and distortion estimators, and some hardware-unfriendly modules are facilitated. Compared with the original RDO procedure, the two proposed algorithms reduce RDO time by 46% and 64% respectively with acceptable coding efficiency loss. © 2014 Springer International Publishing.

High efficiency video coding (HEVC) is the next generation video compression standard. In-loop filter is an important component of HEVC which is composed of two parts, deblocking filter (DBF) and sample adaptive offset (SAO). In this article, we propose a high performance in-loop filter architecture for HEVC which integrate both deblocking filter and SAO. To achieve it, several ideas are adopted. Firstly, SAO is processed based on drifted block, which suits the output pattern of deblocking filter and ease the coupling of deblocking filter and SAO. Secondly, luma and chroma samples of each 4 x 4 block are organized in same memory storage unit and they are processed simultaneously to raise the parallelism. Thirdly, in both deblocking filter and SAO, calculation core is implemented in combinational logic and data storage is implemented in register groups. Calculation core keeps processing data continually, which greatly raises the utilization of DBF core and SAO core. Fourthly, task level pipeline in processing 8 x 8 block is employed between deblocking filter and SAO. By these means, a high performance in-loop filter including both deblocking filter and SAO is achieved without any intermediate storage or circuit. It takes only four cycles to finish the deblocking filter and SAO of one 8x8 block. The implementation results show that the proposed solution can be synthesized to 240 MHz with 65 nm technology. Thus this solution can process 3.84G pixels/s at maximum. UHDTV 4320p (7680 x 4320) @ 60 fps decoding can be realized with 124.4 MHz working frequency by the proposed architecture.

High efficiency video coding (HEVC) is the next generation video compression standard. In-loop filter is an important component of HEVC which is composed of two parts, deblocking filter (DBF) and sample adaptive offset (SAO). In this article, we propose a high performance in-loop filter architecture for HEVC which integrate both deblocking filter and SAO. To achieve it, several ideas are adopted. Firstly, SAO is processed based on drifted block, which suits the output pattern of deblocking filter and ease the coupling of deblocking filter and SAO. Secondly, luma and chroma samples of each 4 x 4 block are organized in same memory storage unit and they are processed simultaneously to raise the parallelism. Thirdly, in both deblocking filter and SAO, calculation core is implemented in combinational logic and data storage is implemented in register groups. Calculation core keeps processing data continually, which greatly raises the utilization of DBF core and SAO core. Fourthly, task level pipeline in processing 8 x 8 block is employed between deblocking filter and SAO. By these means, a high performance in-loop filter including both deblocking filter and SAO is achieved without any intermediate storage or circuit. It takes only four cycles to finish the deblocking filter and SAO of one 8x8 block. The implementation results show that the proposed solution can be synthesized to 240 MHz with 65 nm technology. Thus this solution can process 3.84G pixels/s at maximum. UHDTV 4320p (7680 x 4320) @ 60 fps decoding can be realized with 124.4 MHz working frequency by the proposed architecture.

As the successive video compression standard of H.264/AVC, High Efficiency Video Codec (HEVC) will play an important role in video coding area. In the deblocking filter part, HEVC inherits the basic property of H.264/AVC and gives some new features. Based on this variation, this paper introduces a novel dual-mode deblocking filter architecture which could support both of the HEVC and H.264/AVC standards. For HEVC standard, the proposed symmetric unified-cross unit (SUCU) based filtering scheme greatly reduces the design complexity. As a result, processing a 16 x 16 block needs 24 clock cycles. For H.264/AVC standard, it takes 48 clock cycles for a 16 x 16 macro-block (MB). In synthesis result, the proposed architecture occupies 41.6k equivalent gate count at frequency of 200 MHz in SMIC 65 nm library, which could satisfy the throughput requirement of super hi-vision (SHV) on 60 fps. With filter reusing scheme, the universal design for the two standards saves 30% gate counts than the dedicated ones in filter part. In addition, the total power consumption could be reduced by 57.2% with skipping mode when the edges need not be filtered.

Multi-view video can provide users with three-dimensional (3-D) and virtual reality perception through multiple viewing angles. In recent years, depth image-based rendering (DIBR) has been generally used to synthesize virtual view images in free viewpoint television (FTV) and 3-D video. To conceal the zero-region more accurately and improve the quality of a virtual view synthesized frame, an integrated hole-filling algorithm for view synthesis is proposed in this paper. The proposed algorithm contains five parts: an algorithm for distinguishing different regions, foreground and background boundary detection, texture image isophotes detection, a textural and structural isophote prediction algorithm, and an in-painting algorithm with gradient priority order. Based on the texture isophote prediction with a geometrical principle and the in-painting algorithm with a gradient priority order, the boundary information of the foreground is considerably clearer and the texture information in the zero-region can be concealed much more accurately than in previous works. The vision quality mainly depends on the distortion of the structural information. Experimental results indicate that the proposed algorithm improves not only the objective quality of the virtual image, but also its subjective quality considerably; human vision is also clearly improved based on the subjective results. In particular, the algorithm ensures the boundary contours of the foreground objects and the textural and structural information.

Multi-view video can provide users with three-dimensional (3-D) and virtual reality perception through multiple viewing angles. In recent years, depth image-based rendering (DIBR) has been generally used to synthesize virtual view images in free viewpoint television (FTV) and 3-D video. To conceal the zero-region more accurately and improve the quality of a virtual view synthesized frame, an integrated hole-filling algorithm for view synthesis is proposed in this paper. The proposed algorithm contains five parts: an algorithm for distinguishing different regions, foreground and background boundary detection, texture image isophotes detection, a textural and structural isophote prediction algorithm, and an in-painting algorithm with gradient priority order. Based on the texture isophote prediction with a geometrical principle and the in-painting algorithm with a gradient priority order, the boundary information of the foreground is considerably clearer and the texture information in the zero-region can be concealed much more accurately than in previous works. The vision quality mainly depends on the distortion of the structural information. Experimental results indicate that the proposed algorithm improves not only the objective quality of the virtual image, but also its subjective quality considerably; human vision is also clearly improved based on the subjective results. In particular, the algorithm ensures the boundary contours of the foreground objects and the textural and structural information.

High Efficiency Video Coding (HEVC) outperforms H.264 High Profile with bitrate saving of about 43%, mostly because block sizes for hybrid prediction and residual encoding are recursively chosen using a quadtree structure. Nevertheless, the exhaustive quadtree-based partition is not always necessary. This paper takes advantage of all-zero residual blocks at every quadtree depth to accelerate the prediction and residual encoding processes. First, we derive a near-sufficient condition to detect variable-sized all-zero blocks (AZBs). For these blocks, discrete cosine transform (DCT) and quantization can be skipped. Next, using the derived condition, we propose an early termination technique to reduce the complexity for motion estimation (ME). More significantly, we present a two-dimensional pruning technique based on AZBs to constrain prediction units (PU) that contribute negligibly to rate-distortion (RD) performance. Experiments on a wide range of videos with resolution ranging from 416 x 240 to 4k x 2k, show that the proposed scheme can reduce computational complexity for the HEVC encoder by up to 70.46% (50.34% on average), with slight loss in terms of the peak signal-to-noise ratio (PSNR) and bitrate. The proposal also outperforms other state-of-the-art methods by achieving greater complexity reduction and improved bitrate performance.

High Efficiency Video Coding (HEVC) outperforms H.264 High Profile with bitrate saving of about 43%, mostly because block sizes for hybrid prediction and residual encoding are recursively chosen using a quadtree structure. Nevertheless, the exhaustive quadtree-based partition is not always necessary. This paper takes advantage of all-zero residual blocks at every quadtree depth to accelerate the prediction and residual encoding processes. First, we derive a near-sufficient condition to detect variable-sized all-zero blocks (AZBs). For these blocks, discrete cosine transform (DCT) and quantization can be skipped. Next, using the derived condition, we propose an early termination technique to reduce the complexity for motion estimation (ME). More significantly, we present a two-dimensional pruning technique based on AZBs to constrain prediction units (PU) that contribute negligibly to rate-distortion (RD) performance. Experiments on a wide range of videos with resolution ranging from 416 x 240 to 4k x 2k, show that the proposed scheme can reduce computational complexity for the HEVC encoder by up to 70.46% (50.34% on average), with slight loss in terms of the peak signal-to-noise ratio (PSNR) and bitrate. The proposal also outperforms other state-of-the-art methods by achieving greater complexity reduction and improved bitrate performance.

An H.264/AVC intra-frame video encoder is implemented in 65nm CMOS. With an efficient intra prediction design, its maximum throughput reaches 1991Mpixels/s for 7680×4320p 60fps video, 9.4x to 32x faster than previous designs. The encoder also incorporates a 1.41Gbins/s CABAC architecture that has been enhanced by 31%. Moreover, low energy consumption is achieved by the high parallelism and hardware efficiency of this design. 1080p 30fps encoding dissipates only 2mW at 0.8V and 9MHz. © 2013 IEEE.

This paper proposes a low power video decoding with adaptive granularity in temporal scalability. This proposal can be applied to reduce the computational complexity of H.264/AVC decoder with acceptable loss of the video quality, and make the single layer bit stream sources much more flexible for various terminal devices. Proposed low power decoding process consists of four proposed algorithms, the reference frame index decision algorithm, motion vector composition algorithm, block-partition decision algorithm and the adaptive selecting algorithm for skipped frames. The experiment results show that the reduction rate of the decoding time decreases when the number of skipped frames increases, and the loss of the video quality increases at the same time. The PSNR loss in the B frame skipping is much smaller than the PSNR loss in the P frame skipping. In the fixed frame skipping cases, the 2/3 P frame is skipped with 60% decoding time reduction and 2.73 dB average PSNR loss in the all filling comparison or 1.59 dB average PSNR loss in the corresponding comparison. Analyzing the relation between motion vector information and the video quality loss of the corresponding frames in probability shows that the proposed adaptive skipping scheme reduces quality loss by skipping the frames with slight movements and keeping the frames with strong movements. Based on the adaptive skipping scheme, the average PSNR is improved 0.68 dB in the all filling comparison or 0.60 dB in the corresponding comparison compared with the fixed frame skipping scheme with almost the same reduction rate of the decoding time.

The up-coming video compression standard, high efficiency video coding (HEVC), reduces 50% bit rates in encoding video sequences with same picture quality compared to H.264/AVC. In the in-loop filter (LF) part of HEVC, sample adaptive offset (SAO) is newly added and de-blocking filter (DBF) has been changed a lot. Thus how to construct a high speed and low cost VLSI architecture for HEVC SAO and de-blocking filter is a challenge.
In this article, we propose a HEVC LF architecture composed of fully utilized de-blocking filter and SAO. Block based SAO and DBF are employed in this architecture to achieve seamless pipeline between them. The implementation results show that it can be synthesized to 240MHz with 65nm technology. Thus this solution can process 3.84G pixels/s and support 4320p(7680x4320)@ 120fps decoding.

In the high efficiency video coding (HEVC), motion estimation (ME) is an essential process for inter prediction. Compared to integer ME (IME), fractional ME (FME) occupies much more encoding time in the fast search case. To reduce the computational complexity of FME, we propose a fast algorithm based on mode filtering. In the proposal, according to results of IME and neighboring largest coding units (LCU), 1 or 2 levels are selected from the original 4-level quad-tree structure, and only the selected levels will process FME. Specifically, quad-tree separation is adopted to remove the interdependence between IME and FME. Experiments on a wide range of video sequences show that the proposed algorithm can reduce up to 42.9% and an average of 33.4% total encoding time for HEVC with little loss in PSNR and rate. © 2013 IEEE.

An H.264/AVC intra-frame video encoder is implemented in 65nm CMOS. With an efficient intra prediction design, its maximum throughput reaches 1991Mpixels/s for 7680×4320p 60fps video, 9.4x to 32x faster than previous designs. The encoder also incorporates a 1.41Gbins/s CABAC architecture that has been enhanced by 31%. Moreover, low energy consumption is achieved by the high parallelism and hardware efficiency of this design. 1080p 30fps encoding dissipates only 2mW at 0.8V and 9MHz. © 2013 IEEE.

This paper proposes a low power video decoding with adaptive granularity in temporal scalability. This proposal can be applied to reduce the computational complexity of H.264/AVC decoder with acceptable loss of the video quality, and make the single layer bit stream sources much more flexible for various terminal devices. Proposed low power decoding process consists of four proposed algorithms, the reference frame index decision algorithm, motion vector composition algorithm, block-partition decision algorithm and the adaptive selecting algorithm for skipped frames. The experiment results show that the reduction rate of the decoding time decreases when the number of skipped frames increases, and the loss of the video quality increases at the same time. The PSNR loss in the B frame skipping is much smaller than the PSNR loss in the P frame skipping. In the fixed frame skipping cases, the 2/3 P frame is skipped with 60% decoding time reduction and 2.73 dB average PSNR loss in the all filling comparison or 1.59 dB average PSNR loss in the corresponding comparison. Analyzing the relation between motion vector information and the video quality loss of the corresponding frames in probability shows that the proposed adaptive skipping scheme reduces quality loss by skipping the frames with slight movements and keeping the frames with strong movements. Based on the adaptive skipping scheme, the average PSNR is improved 0.68 dB in the all filling comparison or 0.60 dB in the corresponding comparison compared with the fixed frame skipping scheme with almost the same reduction rate of the decoding time.

In the high efficiency video coding (HEVC), motion estimation (ME) is an essential process for inter prediction. Compared to integer ME (IME), fractional ME (FME) occupies much more encoding time in the fast search case. To reduce the computational complexity of FME, we propose a fast algorithm based on mode filtering. In the proposal, according to results of IME and neighboring largest coding units (LCU), 1 or 2 levels are selected from the original 4-level quad-tree structure, and only the selected levels will process FME. Specifically, quad-tree separation is adopted to remove the interdependence between IME and FME. Experiments on a wide range of video sequences show that the proposed algorithm can reduce up to 42.9% and an average of 33.4% total encoding time for HEVC with little loss in PSNR and rate. © 2013 IEEE.

In this paper, a feature named multi-scale bidirectional local template patterns (MBLTP) is proposed for human detection. As an extension of bidirectional local template patterns (BLTP), MBLTP not only integrates the textural and gradient information according to the four predefined templates but also calculates information for additional feature vectors by adjusting the scale of the training samples. These additional feature vectors contain multi-scale information on the samples, which can make the feature more discriminative than its original form. Experimental results for an INRIA dataset show that the detection rate of our proposed MBLTP feature outperforms those of other features such as the multi-level histogram of orientated gradient (multi-level HOG), multi scale block histogram of template (MB-HOT), and HOG-LBP. Moreover, in order to make our feature meet real-time requirements, an implementation based on a graphic process unit (GPU) is adopted to accelerate the calculation.

The quadtree-based variable block sized prediction makes the biggest contribution for dramatically improved coding efficiency in the new video coding standard named HEVC. However, this technique takes about 75-80% computational complexity of an HEVC encoder. This paper brings forward an adaptive scheme that exploits temporal, spatial and transform-domain features to speed up the original quadtree-based prediction, targeting at high resolution videos. Before encoding starts, analysis on utilization ratio of each coding depth is performed to skip rarely adopted coding depths at frame level. Then, texture complexity (TC) measurement is applied to filter out none-contributable coding blocks for each largest coding unit (LCU). In this step, a dynamic threshold setting approach is proposed to make filtering adaptable to videos and coding parameters. Thirdly, during encoding process, sum of absolute quantized residual coefficient (SAQC) is used as criterion to prune useless coding blocks for both LCUs and 32 × 32 blocks. By using proposed scheme, motion estimation is performed for prediction blocks within a narrowed range. Experiments show that proposed scheme outperforms existing works and speeds up original HEVC by a factor of up to 61.89% and by an average of 33.65% for 4kx2k video sequences. Meanwhile, the peak signal-to-noise ratio (PSNR) degradation and bit increment are trivial. Copyright © 2013 The Institute of Electronics, Information and Communication Engineers.

A combined hole-filling approach with spatial and temporal prediction is presented in this paper. Depth image-based rendering (DIBR) is generally used to synthesize virtual view images in free viewpoint television (FTV) and threedimensional (3-D) video. Limited original camera views and depth maps are used to generate the additional virtual views in the synthesizing process. One of the main problems in DIBR is that there are some regions are occluded by the foreground objects in the original views, and they will be some holes in the generated additional virtual views, especially for the view extrapolation cases. Therefore, the proposed algorithm is introduced and it can be used to fill the holes which caused by disocclusion regions and inaccurate depth values. The proposed algorithm combines the spatial and temporal prediction, and the performance is much better and more stable than the previous work. The experimental results show that the proposed method can improve the quality of the virtual views a lot compared with the previous work. The improvement is not only obvious in the objective comparison, but also in the subjective comparison.

The up-coming video compression standard, high efficiency video coding (HEVC), reduces 50% bit rates in encoding video sequences with same picture quality compared to H.264/AVC. In the in-loop filter (LF) part of HEVC, sample adaptive offset (SAO) is newly added and de-blocking filter (DBF) has been changed a lot. Thus how to construct a high speed and low cost VLSI architecture for HEVC SAO and de-blocking filter is a challenge.
In this article, we propose a HEVC LF architecture composed of fully utilized de-blocking filter and SAO. Block based SAO and DBF are employed in this architecture to achieve seamless pipeline between them. The implementation results show that it can be synthesized to 240MHz with 65nm technology. Thus this solution can process 3.84G pixels/s and support 4320p(7680x4320)@ 120fps decoding.

This paper presents a fractional motion estimation (FME) design in high efficiency video coding (HEVC) for ultrahigh definition video (Ultra-HD). To reduce complexity and achieve high throughput, the design is co-optimized in algorithm and hardware architecture. Bilinear quarter pixel approximation, together with a 5T12S search pattern is proposed to reduce the complexity of the interpolation and search process. Furthermore, we introduce an exhaustive size-hadamard transform (ES-HAD), to improve coding quality, and determine the best transform size rather than using complex transform coding. Besides, a data reuse method of ES-HAD is applied to reduce the hardware overhead. This design is implemented in 65nm CMOS chip and verified by FPGA based evaluation system. It achieves 995Mpixels/s for 7680×4320 30fps encoding, at least 4.7 times faster than previous designs. Its power dissipation is 198.6mW at 188MHz, with 0.2nJ/pixel power efficiency. Despite high complexity in HEVC, the chip achieves 56% improvement on power efficiency than previous works in H.264. © 2013 IEEE.

The quadtree-based variable block sized prediction makes the biggest contribution for dramatically improved coding efficiency in the new video coding standard named HEVC. However, this technique takes about 75-80% computational complexity of an HEVC encoder. This paper brings forward an adaptive scheme that exploits temporal, spatial and transform-domain features to speed up the original quadtree-based prediction, targeting at high resolution videos. Before encoding starts, analysis on utilization ratio of each coding depth is performed to skip rarely adopted coding depths at frame level. Then, texture complexity (TC) measurement is applied to filter out none-contributable coding blocks for each largest coding unit (LCU). In this step, a dynamic threshold setting approach is proposed to make filtering adaptable to videos and coding parameters. Thirdly, during encoding process, sum of absolute quantized residual coefficient (SAQC) is used as criterion to prune useless coding blocks for both LCUs and 32 × 32 blocks. By using proposed scheme, motion estimation is performed for prediction blocks within a narrowed range. Experiments show that proposed scheme outperforms existing works and speeds up original HEVC by a factor of up to 61.89% and by an average of 33.65% for 4kx2k video sequences. Meanwhile, the peak signal-to-noise ratio (PSNR) degradation and bit increment are trivial. Copyright © 2013 The Institute of Electronics, Information and Communication Engineers.

A combined hole-filling approach with spatial and temporal prediction is presented in this paper. Depth image-based rendering (DIBR) is generally used to synthesize virtual view images in free viewpoint television (FTV) and threedimensional (3-D) video. Limited original camera views and depth maps are used to generate the additional virtual views in the synthesizing process. One of the main problems in DIBR is that there are some regions are occluded by the foreground objects in the original views, and they will be some holes in the generated additional virtual views, especially for the view extrapolation cases. Therefore, the proposed algorithm is introduced and it can be used to fill the holes which caused by disocclusion regions and inaccurate depth values. The proposed algorithm combines the spatial and temporal prediction, and the performance is much better and more stable than the previous work. The experimental results show that the proposed method can improve the quality of the virtual views a lot compared with the previous work. The improvement is not only obvious in the objective comparison, but also in the subjective comparison.

In recent years, local pattern based features have attracted increasing interest in object detection and recognition systems. Local Binary Pattern (LBP) feature is widely used in texture classification and face detection. But the original definition of LBP is not suitable for human detection. In this paper, we propose a novel feature set named gradient local binary patterns (GLBP), Original GLBP and Improved GLBP, for human detection. Experiments are performed on INRIA dataset, which shows the proposal GLBP feature is more discriminative than histogram of orientated gradient (HOG), histogram of template (HOT) and Semantic Local Binary Patterns (S-LBP), under the same training method. In our experiments, the window size is fixed. That means the performance can be improved by boosting and cascade methods. And the computation of GLBP feature is parallel, which make it easy for hardware acceleration. These factors make GLBP feature possible for real-time human detection.

Electromagnetic emissions leak confidential data of cryptographic devices. Electromagnetic Analysis (EMA) exploits such emission for cryptanalysis. The performance of EMA dramatically decreases when correlated noise, which is caused by the interference of clock network and exhibits strong correlation with encryption signal, is present in the acquired EM signal. In this paper, three techniques are proposed to reduce the correlated noise. Based on the observation that the clock signal has a high variance at the signal edges, the first technique: single-sample Singular Value Decomposition (SVD), extracts the clock signal with only one EM sample. The second technique: multi-sample SVD is capable of suppressing the clock signal with short sampling length. The third one: averaged subtraction is suitable for estimation of correlated noise when background samplings are included. Experiments on the EM signal during AES encryption on the FPGA and ASIC implementation demonstrate that the proposed techniques increase SNR as much as 22.94 dB, and the success rates of EMA show that the data-independent information is retained and the performance of EMA is improved.

In recent years, local pattern based features have attracted increasing interest in object detection and recognition systems. Local Binary Pattern (LBP) feature is widely used in texture classification and face detection. But the original definition of LBP is not suitable for human detection. In this paper, we propose a novel feature set named gradient local binary patterns (GLBP), Original GLBP and Improved GLBP, for human detection. Experiments are performed on INRIA dataset, which shows the proposal GLBP feature is more discriminative than histogram of orientated gradient (HOG), histogram of template (HOT) and Semantic Local Binary Patterns (S-LBP), under the same training method. In our experiments, the window size is fixed. That means the performance can be improved by boosting and cascade methods. And the computation of GLBP feature is parallel, which make it easy for hardware acceleration. These factors make GLBP feature possible for real-time human detection.

Electromagnetic emissions leak confidential data of cryptographic devices. Electromagnetic Analysis (EMA) exploits such emission for cryptanalysis. The performance of EMA dramatically decreases when correlated noise, which is caused by the interference of clock network and exhibits strong correlation with encryption signal, is present in the acquired EM signal. In this paper, three techniques are proposed to reduce the correlated noise. Based on the observation that the clock signal has a high variance at the signal edges, the first technique: single-sample Singular Value Decomposition (SVD), extracts the clock signal with only one EM sample. The second technique: multi-sample SVD is capable of suppressing the clock signal with short sampling length. The third one: averaged subtraction is suitable for estimation of correlated noise when background samplings are included. Experiments on the EM signal during AES encryption on the FPGA and ASIC implementation demonstrate that the proposed techniques increase SNR as much as 22.94 dB, and the success rates of EMA show that the data-independent information is retained and the performance of EMA is improved.

Adverse weather, such as rain or snow, can cause difficulties in the processing of video streams. Because the appearance of raindrops can affect the performance of human tracking and reduce the efficiency of video compression, the detection and removal of rain is a challenging problem in outdoor surveillance systems. In this paper, we propose a new algorithm for rain detection and removal based on both spatial and wavelet domain features. Our system involves fewer frames during detection and removal, and is robust to moving objects in the rain. Experimental results demonstrate that the proposed algorithm outperforms existing approaches in terms of subjective and objective quality. Copyright © 2013 The Institute of Electronics, Information and Communication Engineers.

Adverse weather, such as rain or snow, can cause difficulties in the processing of video streams. Because the appearance of raindrops can affect the performance of human tracking and reduce the efficiency of video compression, the detection and removal of rain is a challenging problem in outdoor surveillance systems. In this paper, we propose a new algorithm for rain detection and removal based on both spatial and wavelet domain features. Our system involves fewer frames during detection and removal, and is robust to moving objects in the rain. Experimental results demonstrate that the proposed algorithm outperforms existing approaches in terms of subjective and objective quality. Copyright © 2013 The Institute of Electronics, Information and Communication Engineers.

Electromagnetic emissions leak confidential data of cryptographic devices. Electromagnetic Analysis (EMA) exploits such emission for cryptanalysis. The performance of EMA dramatically decreases when correlated noise, which is caused by the interference of clock network and exhibits strong correlation with encryption signal, is present in the acquired EM signal. In this paper, three techniques are proposed to reduce the correlated noise. Based on the observation that the clock signal has a high variance at the signal edges, the first technique: single-sample Singular Value Decomposition (SVD), extracts the clock signal with only one EM sample. The second technique: multi-sample SVD is capable of suppressing the clock signal with short sampling length. The third one: averaged subtraction is suitable for estimation of correlated noise when background samplings are included. Experiments on the EM signal during AES encryption on the FPGA and ASIC implementation demonstrate that the proposed techniques increase SNR as much as 22.94 dB, and the success rates of EMA show that the data-independent information is retained and the performance of EMA is improved.

Electromagnetic emissions leak confidential data of cryptographic devices. Electromagnetic Analysis (EMA) exploits such emission for cryptanalysis. The performance of EMA dramatically decreases when correlated noise, which is caused by the interference of clock network and exhibits strong correlation with encryption signal, is present in the acquired EM signal. In this paper, three techniques are proposed to reduce the correlated noise. Based on the observation that the clock signal has a high variance at the signal edges, the first technique: single-sample Singular Value Decomposition (SVD), extracts the clock signal with only one EM sample. The second technique: multi-sample SVD is capable of suppressing the clock signal with short sampling length. The third one: averaged subtraction is suitable for estimation of correlated noise when background samplings are included. Experiments on the EM signal during AES encryption on the FPGA and ASIC implementation demonstrate that the proposed techniques increase SNR as much as 22.94 dB, and the success rates of EMA show that the data-independent information is retained and the performance of EMA is improved.

This paper presents a high-performance context adaptive binary arithmetic coding (CABAC) architecture for the next-generation UHDTV applications. Its maximum throughput has been enhanced by 31%∼34% with the proposed pre-normalization (prenorm.), hybrid path coverage (HPC), bypass bin splitting (BPBS) and state dual-transition (SDT) schemes. Both the HEVC and H.264/AVC formats can be supported with our architecture by applying a dualstandard binarization design. The proposed CABAC architecture has been silicon proven in a 65nm video encoder chip. It delivers 4.27∼4.40 bins/cycle with synthesized and measured clock rates of 401.5MHz and 330MHz, respectively. Therefore a high performance of 1.452Gbin/s is achieved for real-time UHDTV encoding. © 2013 IEEE.

In this paper, a feature named multi-scale bidirectional local template patterns (MBLTP) is proposed for human detection. As an extension of bidirectional local template patterns (BLTP), MBLTP not only integrates the textural and gradient information according to the four predefined templates but also calculates information for additional feature vectors by adjusting the scale of the training samples. These additional feature vectors contain multi-scale information on the samples, which can make the feature more discriminative than its original form. Experimental results for an INRIA dataset show that the detection rate of our proposed MBLTP feature outperforms those of other features such as the multi-level histogram of orientated gradient (multi-level HOG), multi scale block histogram of template (MB-HOT), and HOG-LBP. Moreover, in order to make our feature meet real-time requirements, an implementation based on a graphic process unit (GPU) is adopted to accelerate the calculation.

Structured quasi-cyclic low-density parity-check (QC-LDPC) codes have been adopted in many wireless communication standards, such as WiMAX, Wi-Fi and WPAN. To completely support the variable code rate (multi-rate) and variable code length (multi-length) implementation for universal applications, the partial-parallel layered LDPC decoder architecture is straightforward and widely used in the decoder design. In this paper, we propose a high parallel LDPC decoder architecture for WiMAX system with dedicated ASIC design. Different from the block by block decoding schedule in most partial-parallel layered architectures, all the messages within each layer are updated simultaneously in the proposed fully-parallel layered decoder architecture. Meanwhile, the message updating is separated into bit-serial style to reduce hardware complexity. A 6-bit implementation is adopted in the decoder chip, since simulations demonstrate that 6-bit quantization is the best trade-off between performance and complexity. Moreover, the two-layer concurrent processing technique is proposed to further increase the parallelism for low code rates. Implementation results show that the decoder chip saves 22.2% storage bits and only takes 24 similar to 48 clock cycles per iteration for all the code rates defined in WiMAX standard. It occupies 3.36 mm(2) in SMIC 65 nm CMOS process, and realizes 1056 Mbps throughput at 1.2 V, 110 MHz and 10 iterations with 115 mW power occupation, which infers a power efficiency of 10.9 pJ/bit/iteration. The power efficiency is improved 63.6% in normalized comparison with the state-of-art WiMAX LDPC decoder.

Structured quasi-cyclic low-density parity-check (QC-LDPC) codes have been adopted in many wireless communication standards, such as WiMAX, Wi-Fi and WPAN. To completely support the variable code rate (multi-rate) and variable code length (multi-length) implementation for universal applications, the partial-parallel layered LDPC decoder architecture is straightforward and widely used in the decoder design. In this paper, we propose a high parallel LDPC decoder architecture for WiMAX system with dedicated ASIC design. Different from the block by block decoding schedule in most partial-parallel layered architectures, all the messages within each layer are updated simultaneously in the proposed fully-parallel layered decoder architecture. Meanwhile, the message updating is separated into bit-serial style to reduce hardware complexity. A 6-bit implementation is adopted in the decoder chip, since simulations demonstrate that 6-bit quantization is the best trade-off between performance and complexity. Moreover, the two-layer concurrent processing technique is proposed to further increase the parallelism for low code rates. Implementation results show that the decoder chip saves 22.2% storage bits and only takes 24 similar to 48 clock cycles per iteration for all the code rates defined in WiMAX standard. It occupies 3.36 mm(2) in SMIC 65 nm CMOS process, and realizes 1056 Mbps throughput at 1.2 V, 110 MHz and 10 iterations with 115 mW power occupation, which infers a power efficiency of 10.9 pJ/bit/iteration. The power efficiency is improved 63.6% in normalized comparison with the state-of-art WiMAX LDPC decoder.

Structured quasi-cyclic low-density parity-check (QC-LDPC) codes have been adopted in many wireless communication standards, such as WiMAX, Wi-Fi and WPAN. To completely support the variable code rate (multi-rate) and variable code length (multi-length) implementation for universal applications, the partial-parallel layered LDPC decoder architecture is straightforward and widely used in the decoder design. In this paper, we propose a high parallel LDPC decoder architecture for WiMAX system with dedicated ASIC design. Different from the block by block decoding schedule in most partial-parallel layered architectures, all the messages within each layer are updated simultaneously in the proposed fully-parallel layered decoder architecture. Meanwhile, the message updating is separated into bit-serial style to reduce hardware complexity. A 6-bit implementation is adopted in the decoder chip, since simulations demonstrate that 6-bit quantization is the best trade-off between performance and complexity. Moreover, the two-layer concurrent processing technique is proposed to further increase the parallelism for low code rates. Implementation results show that the decoder chip saves 22.2% storage bits and only takes 24 similar to 48 clock cycles per iteration for all the code rates defined in WiMAX standard. It occupies 3.36 mm(2) in SMIC 65 nm CMOS process, and realizes 1056 Mbps throughput at 1.2 V, 110 MHz and 10 iterations with 115 mW power occupation, which infers a power efficiency of 10.9 pJ/bit/iteration. The power efficiency is improved 63.6% in normalized comparison with the state-of-art WiMAX LDPC decoder.

In recent years, local pattern based features have attracted increasing interest in object detection and recognition systems. Local Binary Pattern (LBP) feature is widely used in texture classification and face detection. But the original definition of LBP is not suitable for human detection. In this paper, we propose a novel feature named gradient local binary patterns (GLBP) for human detection. In this feature, original 256 local binary patterns are reduced to 56 patterns. These 56 patterns named uniform patterns are used for generating a 56-bin histogram. And gradient value of each pixel is set as the weight which is always same in LBP based features in histogram calculation to computing the values in 56 bins for histogram. Experiments are performed on INRIA dataset, which shows the proposal GLBP feature is discriminative than histogram of orientated gradient (HOG), Semantic Local Binary Patterns (S-LBP) and histogram of template (HOT). In our experiments, the window size is fixed. That means the performance can be improved by boosting methods. And the computation of GLBP feature is parallel, which make it easy for hardware acceleration. These factors make GLBP feature possible for real-time pedestrian detection.

Stereo-view and multi-view video formats are heavily investigated topics given their vast application potential. Depth Image Based Rendering (DIBR) system has been developed to improve Multiview Video Coding (MVC). Depth image is introduced to synthesize virtual views on the decoder side in this system. Depth image is a piecewise image, which is filled with sharp contours and smooth interior. Contours in a depth image show more importance than interior in view synthesis process. In order to improve the quality of the synthesized views and reduce the bitrate of depth image, a contour based coding strategy is proposed. First, depth image is divided into layers by different depth value intervals. Then regions, which are defined as the basic coding unit in this work, are segmented from each layer. The region is further divided into the contour and the interior. Two different procedures are employed to code contours and interiors respectively. A vector-based strategy is applied to code the contour lines. Straight lines in contours cost few of bits since they are regarded as vectors. Pixels, which are out of straight lines, are coded one by one. Depth values in the interior of a region are modeled by a linear or nonlinear formula. Coefficients in the formula are retrieved by regression. This process is called interior painting. Unlike conventional block based coding method, the residue between original frame and reconstructed frame (by contour rebuilt and interior painting) is not sent to decoder. In this proposal, contour is coded in a lossless way whereas interior is coded in a lossy way. Experimental results show that the proposed Contour Based Depth map Coding (CBDC) achieves a better performance than JMVC (reference software of MVC) in the high quality scenarios.

In recent years, local pattern based features have attracted increasing interest in object detection and recognition systems. Local Binary Pattern (LBP) feature is widely used in texture classification and face detection. But the original definition of LBP is not suitable for human detection. In this paper, we propose a novel feature named gradient local binary patterns (GLBP) for human detection. In this feature, original 256 local binary patterns are reduced to 56 patterns. These 56 patterns named uniform patterns are used for generating a 56-bin histogram. And gradient value of each pixel is set as the weight which is always same in LBP based features in histogram calculation to computing the values in 56 bins for histogram. Experiments are performed on INRIA dataset, which shows the proposal GLBP feature is discriminative than histogram of orientated gradient (HOG), Semantic Local Binary Patterns (S-LBP) and histogram of template (HOT). In our experiments, the window size is fixed. That means the performance can be improved by boosting methods. And the computation of GLBP feature is parallel, which make it easy for hardware acceleration. These factors make GLBP feature possible for real-time pedestrian detection.

High-definition (HD) videos become more and more popular on portable devices these years. Due to the resolution mismatch between the HD video sources and the relative low-resolution screens of portable devices, the HD videos are usually fully decoded and then down-sampled (FDDS) for the displays, which not only increase the cost of both computational power and memory bandwidth, but also lose the details of video contents. In this paper, an encoder-unconstrained partial decoding scheme for H.264/AVC is presented to solve the problem by only decoding the object of interest (001) related region, which is defined by users. A simplified compression domain tracking method is utilized to ensure that the 001 locates in the center of the display area. The decoded partial area (DPA) adaptation, the reference block relocation (RBR) and co-located temporal Intra prediction (CTIP) methods are proposed to improve the visual quality for the DPA with low complexity. The simulation results show that the proposed partial decoding scheme provides an average of 50.16% decoding time reduction comparing to the fully decoding process. The displayed region also presents the original HD granularity of OOI. The proposed partial decoding scheme is especially useful for displaying HD video on the devices of which the battery life is a crucial factor.

In recent years, local pattern based features have attracted increasing interest in object detection and recognition systems. Local Binary Pattern (LBP) feature is widely used in texture classification and face detection. But the original definition of LBP is not suitable for human detection. In this paper, we propose a novel feature named gradient local binary patterns (GLBP) for human detection. In this feature, original 256 local binary patterns are reduced to 56 patterns. These 56 patterns named uniform patterns are used for generating a 56-bin histogram. And gradient value of each pixel is set as the weight which is always same in LBP based features in histogram calculation to computing the values in 56 bins for histogram. Experiments are performed on INRIA dataset, which shows the proposal GLBP feature is discriminative than histogram of orientated gradient (HOG), Semantic Local Binary Patterns (S-LBP) and histogram of template (HOT). In our experiments, the window size is fixed. That means the performance can be improved by boosting methods. And the computation of GLBP feature is parallel, which make it easy for hardware acceleration. These factors make GLBP feature possible for real-time pedestrian detection.

High-definition (HD) videos become more and more popular on portable devices these years. Due to the resolution mismatch between the HD video sources and the relative low-resolution screens of portable devices, the HD videos are usually fully decoded and then down-sampled (FDDS) for the displays, which not only increase the cost of both computational power and memory bandwidth, but also lose the details of video contents. In this paper, an encoder-unconstrained partial decoding scheme for H.264/AVC is presented to solve the problem by only decoding the object of interest (001) related region, which is defined by users. A simplified compression domain tracking method is utilized to ensure that the 001 locates in the center of the display area. The decoded partial area (DPA) adaptation, the reference block relocation (RBR) and co-located temporal Intra prediction (CTIP) methods are proposed to improve the visual quality for the DPA with low complexity. The simulation results show that the proposed partial decoding scheme provides an average of 50.16% decoding time reduction comparing to the fully decoding process. The displayed region also presents the original HD granularity of OOI. The proposed partial decoding scheme is especially useful for displaying HD video on the devices of which the battery life is a crucial factor.

Stereo-view and multi-view video formats are heavily investigated topics given their vast application potential. Depth Image Based Rendering (DIBR) system has been developed to improve Multiview Video Coding (MVC). Depth image is introduced to synthesize virtual views on the decoder side in this system. Depth image is a piecewise image, which is filled with sharp contours and smooth interior. Contours in a depth image show more importance than interior in view synthesis process. In order to improve the quality of the synthesized views and reduce the bitrate of depth image, a contour based coding strategy is proposed. First, depth image is divided into layers by different depth value intervals. Then regions, which are defined as the basic coding unit in this work, are segmented from each layer. The region is further divided into the contour and the interior. Two different procedures are employed to code contours and interiors respectively. A vector-based strategy is applied to code the contour lines. Straight lines in contours cost few of bits since they are regarded as vectors. Pixels, which are out of straight lines, are coded one by one. Depth values in the interior of a region are modeled by a linear or nonlinear formula. Coefficients in the formula are retrieved by regression. This process is called interior painting. Unlike conventional block based coding method, the residue between original frame and reconstructed frame (by contour rebuilt and interior painting) is not sent to decoder. In this proposal, contour is coded in a lossless way whereas interior is coded in a lossy way. Experimental results show that the proposed Contour Based Depth map Coding (CBDC) achieves a better performance than JMVC (reference software of MVC) in the high quality scenarios.

Transmission of compressed video over error-prone channels may result in packet losses or errors, which can significantly degrade the image quality. Such degradation becomes even worse in 1Seg video broadcasting, which is widely used in Japan and Brazil for mobile phone TV services recently, where errors are drastically increased and the lost areas are contiguous. Therefore, the errors in the earlier concealed MBs (macro blocks) may propagate to the MBs later to be concealed inside the same frame (spatial domain). The error concealment (EC) is used to recover the lost data by the redundancy in videos. Aiming at spatial error propagation (SEP) reduction, this paper proposes an SEP-reduction-based EC (SEPEC). In SEPEC, besides the mismatch distortion in the current MB, the potential propagated mismatch distortion in the following to be concealed MBs is also minimized. Also, two extensions of SEPEC, i.e. SEPEC with refined search and SEPEC with multiple layer match, are discussed. Compared with previous work, the experiments show SEPEC achieves much better performance of video recovery and excellent trade-off between quality and computation in 1Seg broadcasting. (C) 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

With the popularity of mobile devices with embedded video cameras, real-time video encoding on hand-held devices becomes increasingly popular. Reducing the power consumption during real-time video encoding to suspend the battery life with the same encoding performance is very important to improve the quality of service. Although some workload estimation techniques have been developed for video decoding to reduce power consumption for video playback applications, they present inefficiency in being transferred to video encoding directly because the compressed information cannot be retrieved before encoding and the future input video content is often nondeterministic. In this paper, a workload estimation scheme targeting video encoding applications is proposed. Based on the definition of video encoding workload and the analysis of the features, a Hilbert transform-based workload estimation model is proposed to predict the overall variation trend in the encoding workload to overcome the workload fluctuations and the nondeterministic content variations, e. g., burst motion. The effectiveness of the proposed algorithm is demonstrated on two H.264/AVC encoders on PC and an embedded platform by encoding different video contents at different bit-rates. The proposed algorithm provides a negligible deadline missing ratio around 4.8%, which is much lower than the previous solutions, together with platform and content robustness. Compared with the previous solutions, the proposed algorithm provides up to 61.69% power reduction under the same performance constraint.

Transmission of compressed video over error-prone channels may result in packet losses or errors, which can significantly degrade the image quality. Such degradation becomes even worse in 1Seg video broadcasting, which is widely used in Japan and Brazil for mobile phone TV services recently, where errors are drastically increased and the lost areas are contiguous. Therefore, the errors in the earlier concealed MBs (macro blocks) may propagate to the MBs later to be concealed inside the same frame (spatial domain). The error concealment (EC) is used to recover the lost data by the redundancy in videos. Aiming at spatial error propagation (SEP) reduction, this paper proposes an SEP-reduction-based EC (SEPEC). In SEPEC, besides the mismatch distortion in the current MB, the potential propagated mismatch distortion in the following to be concealed MBs is also minimized. Also, two extensions of SEPEC, i.e. SEPEC with refined search and SEPEC with multiple layer match, are discussed. Compared with previous work, the experiments show SEPEC achieves much better performance of video recovery and excellent trade-off between quality and computation in 1Seg broadcasting. (C) 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

With the popularity of mobile devices with embedded video cameras, real-time video encoding on hand-held devices becomes increasingly popular. Reducing the power consumption during real-time video encoding to suspend the battery life with the same encoding performance is very important to improve the quality of service. Although some workload estimation techniques have been developed for video decoding to reduce power consumption for video playback applications, they present inefficiency in being transferred to video encoding directly because the compressed information cannot be retrieved before encoding and the future input video content is often nondeterministic. In this paper, a workload estimation scheme targeting video encoding applications is proposed. Based on the definition of video encoding workload and the analysis of the features, a Hilbert transform-based workload estimation model is proposed to predict the overall variation trend in the encoding workload to overcome the workload fluctuations and the nondeterministic content variations, e. g., burst motion. The effectiveness of the proposed algorithm is demonstrated on two H.264/AVC encoders on PC and an embedded platform by encoding different video contents at different bit-rates. The proposed algorithm provides a negligible deadline missing ratio around 4.8%, which is much lower than the previous solutions, together with platform and content robustness. Compared with the previous solutions, the proposed algorithm provides up to 61.69% power reduction under the same performance constraint.

Network-on-Chips (NoCs) have been proposed as a solution for addressing the global communication challenges in System-on-Chip (SoC) architectures that are implemented in nanoscale technologies. For the use of NoCs to be feasible in today's industrial designs, a custom-tailored, power- efficient NoC topology that satisfies the application characteristics is required. In this work, we present a design methodology that automates the synthesis of such application-specific NoC topologies. We present a method which integrates partitioning into floorplanning phase to explore optimal clustering of cores during floorplanning with minimized link and switch power consumption. Based on the size of applications, we also present an Integer Linear Programming and a heuristic method to place switches and network interfaces on the floorplan. Then, a power and timing aware path allocation algorithm is carried out to determine the connectivity across different switches. We perform experiments on several SoC benchmarks and present a comparison with the latest work. For small applications, the NoC topologies synthesized by our method show large improvements in power consumption (27,54%), hop-count (4%) and running time (66%) on average. And for large applications, the synthesized topologies result in large power (31.77%), hop-count (29%) and running time (94.18%) on average.

In this paper, we present a hardware-efficient fast algorithm with a lossless frame recompression scheme and early-level termination strategy for large search range (SR) motion estimation (ME) utilized in beyond high-definition video encoder. To achieve high ME quality for hierarchical motion search, we propose an advanced hierarchical ME scheme which processes the multiresolution motion search with an efficient refining stage. This enables high data and hardware reuse for much lower bandwidth and memory cost, while achieving higher ME quality than previous works. In addition, a lossless frame recompression scheme based on this ME algorithm is presented to further reduce bandwidth. A hierarchical memory organization as well as a leveling two-step data fetching strategy is applied to meet constraint of random access for hierarchical motion search structure. Also, the leveling compression strategy by allowing a lower level to refer to a higher one for compression is proposed to efficiently reduce the bandwidth. Furthermore, an early-level termination method suitable for hierarchical ME structure is also applied. This method terminates high-level redundant motion searches by establishing thresholds based on current block mode and motion search level
it also applies the early refinement termination in order to avoid unnecessary refinement for high levels. Experimental results show that the total scheme has a much lower bit rate increasing compared with previous works especially for high motion sequences, while achieving a considerable saving of memory and bandwidth cost for large SR of [-128,127]. © 2011 IEEE.

In this paper, we present a hardware-efficient fast algorithm with a lossless frame recompression scheme and early-level termination strategy for large search range (SR) motion estimation (ME) utilized in beyond high-definition video encoder. To achieve high ME quality for hierarchical motion search, we propose an advanced hierarchical ME scheme which processes the multiresolution motion search with an efficient refining stage. This enables high data and hardware reuse for much lower bandwidth and memory cost, while achieving higher ME quality than previous works. In addition, a lossless frame recompression scheme based on this ME algorithm is presented to further reduce bandwidth. A hierarchical memory organization as well as a leveling two-step data fetching strategy is applied to meet constraint of random access for hierarchical motion search structure. Also, the leveling compression strategy by allowing a lower level to refer to a higher one for compression is proposed to efficiently reduce the bandwidth. Furthermore, an early-level termination method suitable for hierarchical ME structure is also applied. This method terminates high-level redundant motion searches by establishing thresholds based on current block mode and motion search level; it also applies the early refinement termination in order to avoid unnecessary refinement for high levels. Experimental results show that the total scheme has a much lower bit rate increasing compared with previous works especially for high motion sequences, while achieving a considerable saving of memory and bandwidth cost for large SR of [-128, 127]..

In this paper, we present a hardware-efficient fast algorithm with a lossless frame recompression scheme and early-level termination strategy for large search range (SR) motion estimation (ME) utilized in beyond high-definition video encoder. To achieve high ME quality for hierarchical motion search, we propose an advanced hierarchical ME scheme which processes the multiresolution motion search with an efficient refining stage. This enables high data and hardware reuse for much lower bandwidth and memory cost, while achieving higher ME quality than previous works. In addition, a lossless frame recompression scheme based on this ME algorithm is presented to further reduce bandwidth. A hierarchical memory organization as well as a leveling two-step data fetching strategy is applied to meet constraint of random access for hierarchical motion search structure. Also, the leveling compression strategy by allowing a lower level to refer to a higher one for compression is proposed to efficiently reduce the bandwidth. Furthermore, an early-level termination method suitable for hierarchical ME structure is also applied. This method terminates high-level redundant motion searches by establishing thresholds based on current block mode and motion search level
it also applies the early refinement termination in order to avoid unnecessary refinement for high levels. Experimental results show that the total scheme has a much lower bit rate increasing compared with previous works especially for high motion sequences, while achieving a considerable saving of memory and bandwidth cost for large SR of [-128,127]. © 2011 IEEE.

Network-on-Chips (NoCs) have been proposed as a solution for addressing the global communication challenges in System-on-Chip (SoC) architectures that are implemented in nanoscale technologies. For the use of NoCs to be feasible in today's industrial designs, a custom-tailored, power- efficient NoC topology that satisfies the application characteristics is required. In this work, we present a design methodology that automates the synthesis of such application-specific NoC topologies. We present a method which integrates partitioning into floorplanning phase to explore optimal clustering of cores during floorplanning with minimized link and switch power consumption. Based on the size of applications, we also present an Integer Linear Programming and a heuristic method to place switches and network interfaces on the floorplan. Then, a power and timing aware path allocation algorithm is carried out to determine the connectivity across different switches. We perform experiments on several SoC benchmarks and present a comparison with the latest work. For small applications, the NoC topologies synthesized by our method show large improvements in power consumption (27,54%), hop-count (4%) and running time (66%) on average. And for large applications, the synthesized topologies result in large power (31.77%), hop-count (29%) and running time (94.18%) on average.

In this paper, we present a hardware-efficient fast algorithm with a lossless frame recompression scheme and early-level termination strategy for large search range (SR) motion estimation (ME) utilized in beyond high-definition video encoder. To achieve high ME quality for hierarchical motion search, we propose an advanced hierarchical ME scheme which processes the multiresolution motion search with an efficient refining stage. This enables high data and hardware reuse for much lower bandwidth and memory cost, while achieving higher ME quality than previous works. In addition, a lossless frame recompression scheme based on this ME algorithm is presented to further reduce bandwidth. A hierarchical memory organization as well as a leveling two-step data fetching strategy is applied to meet constraint of random access for hierarchical motion search structure. Also, the leveling compression strategy by allowing a lower level to refer to a higher one for compression is proposed to efficiently reduce the bandwidth. Furthermore, an early-level termination method suitable for hierarchical ME structure is also applied. This method terminates high-level redundant motion searches by establishing thresholds based on current block mode and motion search level; it also applies the early refinement termination in order to avoid unnecessary refinement for high levels. Experimental results show that the total scheme has a much lower bit rate increasing compared with previous works especially for high motion sequences, while achieving a considerable saving of memory and bandwidth cost for large SR of [-128, 127]..

In this paper we focus on the resolution of the message updating conflict problem in layered algorithm for DVB-T2 LDPC decoders. Unlike the previous resolutions, we directly implement the layered algorithm without modifying the parity-check matrices (PCM) or the decoding algorithm. DVB-T2 LDPC decoder architecture is also proposed in this paper with two new techniques which guarantee conflict-free layered decoding. The PCM Rearrange technique reduces the number of conflicts and eliminates all of data dependency problems between layers to ensure high pipeline efficiency. The Layer Division technique deals with all remaining conflicts with a well-designed decoding schedule. Experiment results show that compared to state-of-the-art works we achieve a slight error-correcting performance gain for DVB-T2 LDPC codes. © 2012 IEEE.

Electromagnetic emissions leak confidential data of cryptographic devices. The electromagnetic emission has been reported as an important side channel for cryptanalysis. Electromagnetic Analysis (EMA) exploits the external radiation of cryptographic devices during encryption to reveal secret keys. The performance of EMA depends on the acquired signals to a large extent. To protect the devices from attacks, noises are introduced in the side channel either by unintentional interference from surroundings or elaborate design from engineers. Thus the secret recovery becomes difficult and even unavailable. In this paper, we propose two signal processing techniques to counteract both of these noises. The bandpass filtering and independent component analysis are widely used in other areas. We demonstrate their applications to EMA against the encryption algorithms on application-specific integrated circuit. With these techniques, the secret keys are extracted successfully and rapidly. © 2012 American Scientific Publishers. All Rights Reserved.

An H.264/AVC intra-frame video encoder is implemented in 65nm CMOS. With an efficient intra prediction design, its maximum throughput reaches 1991Mpixels/s for 7680x4320p 60fps video, 9.4x to 32x faster than previous designs. The encoder also incorporates a 1.41Gbins/s CABAC architecture that has been enhanced by 31%. Moreover, low energy consumption is achieved by the high parallelism and hardware efficiency of this design. 1080p30 encoding dissipates only 2mW at 0.8V and 9MHz. © 2012 IEEE.

Multi-view video can provide users a 3-D and virtual reality perception by its multiple viewing angles. In recent years, the depth image-based rendering (DIBR) is generally used to synthesize virtual view images in free viewpoint television (FTV) and three-dimensional (3-D) video. In order to conceal the zero-region more accurately and improve the quality of virtual view synthesized frame, an integrated Hole-filling Algorithm for View Synthesis is proposed in this paper. It contains five parts: the different regions distinguishing algorithm, foreground and background boundary detection, the texture image isophotes detection, the textural and structural isophotes prediction algorithm, the in-painting algorithm with gradient priority order. Based on the texture isophotes prediction with geometrical principle and the in-painting algorithm with gradient priority order, the boundary information of the foreground is much clearer and the texture information in the zero-region can be concealed much more accurately than the previous work. The vision quality mainly depends on the distortion of the structural information. Through the experimental results, the proposed algorithm not only improves the objective quality of the virtual image, but also improves the subjective quality of the virtual image a lot, and the human vision quality is also improved obviously based on the subjective results. Especially, it ensures the boundary contours of the foreground objects and the textural and the structural information. © 2012 Springer-Verlag.

In this paper we focus on the resolution of the message updating conflict problem in layered algorithm for DVB-T2 LDPC decoders. Unlike the previous resolutions, we directly implement the layered algorithm without modifying the parity-check matrices (PCM) or the decoding algorithm. DVB-T2 LDPC decoder architecture is also proposed in this paper with two new techniques which guarantee conflict-free layered decoding. The PCM Rearrange technique reduces the number of conflicts and eliminates all of data dependency problems between layers to ensure high pipeline efficiency. The Layer Division technique deals with all remaining conflicts with a well-designed decoding schedule. Experiment results show that compared to state-of-the-art works we achieve a slight error-correcting performance gain for DVB-T2 LDPC codes. © 2012 IEEE.

Multi-view video can provide users a 3-D and virtual reality perception by its multiple viewing angles. In recent years, the depth image-based rendering (DIBR) is generally used to synthesize virtual view images in free viewpoint television (FTV) and three-dimensional (3-D) video. In order to conceal the zero-region more accurately and improve the quality of virtual view synthesized frame, an integrated Hole-filling Algorithm for View Synthesis is proposed in this paper. It contains five parts: the different regions distinguishing algorithm, foreground and background boundary detection, the texture image isophotes detection, the textural and structural isophotes prediction algorithm, the in-painting algorithm with gradient priority order. Based on the texture isophotes prediction with geometrical principle and the in-painting algorithm with gradient priority order, the boundary information of the foreground is much clearer and the texture information in the zero-region can be concealed much more accurately than the previous work. The vision quality mainly depends on the distortion of the structural information. Through the experimental results, the proposed algorithm not only improves the objective quality of the virtual image, but also improves the subjective quality of the virtual image a lot, and the human vision quality is also improved obviously based on the subjective results. Especially, it ensures the boundary contours of the foreground objects and the textural and the structural information. © 2012 Springer-Verlag.

In this paper, a novel envelope detection based workload prediction is proposed. The workload estimation is based on the envelope of the difference value between the previous adjacent actual-workloads, and the envelope is obtained by an absolute value and low pass filter method. To further improve the performance of the envelope detection, the negative truncation is introduced by ignoring the negative difference. This workload prediction method is proposed for the partial decoding scheme and works together with the Dynamic Voltage Frequency Scaling (DVFS) to reduce the power consumption of H.264/AVC video decoding. It provides accurate estimation results with only 0.66% deadline missing rate, which is much lower than previous methods. The power consumption results on the evaluation board show that, with the proposed envelope detection based workload prediction and DVFS, the power reduction achieves about 41.65%, the energy reduction is about 10.16%. The energy reduction of the partial decoding together with proposed workload prediction and DVFS is about 61.15% compare to the fully decoding without DVFS. © 2012 IEEE.

Weather such as rain and snow cause difficulties in processing the videos captured. Since the appearance of rain drops can affect the performance of human tracking and reduce the efficiency of video compression, detection and removal of rain is a challenging problem in outdoor surveillance systems. In this paper, we propose a new algorithm for rain detection, which is based on joint spatial and wavelet domain features. This approach is robust to the videos with moving objects in the rain. Experimental results demonstrated its better performance in comparison with the existing approaches in the subjective quality.

Multi-view video can provide users a 3-D and virtual reality perception by its multiple viewing angles. In recent years, the depth image-based rendering (DIBR) is generally used to synthesize virtual view images in free viewpoint television (FTV) and three-dimensional (3-D) video. In order to conceal the zero-region more accurately and improve the quality of virtual view synthesized frame, an integrated Hole-filling Algorithm for View Synthesis is proposed in this paper. It contains five parts: the different regions distinguishing algorithm, foreground and background boundary detection, the texture image isophotes detection, the textural and structural isophotes prediction algorithm, the in-painting algorithm with gradient priority order. Based on the texture isophotes prediction with geometrical principle and the in-painting algorithm with gradient priority order, the boundary information of the foreground is much clearer and the texture information in the zero-region can be concealed much more accurately than the previous work. The vision quality mainly depends on the distortion of the structural information. Through the experimental results, the proposed algorithm not only improves the objective quality of the virtual image, but also improves the subjective quality of the virtual image a lot, and the human vision quality is also improved obviously based on the subjective results. Especially, it ensures the boundary contours of the foreground objects and the textural and the structural information. © 2012 Springer-Verlag.

In the High Efficiency Video Coding (HEVC), block sizes for hybrid-prediction and residual encoding are recursively selected by using a quadtree structure. This technique requires enormous computational complexity. Nevertheless, the exhaustive quadtree-based partition is not always necessary. This paper fully utilizes all-zero residual blocks to accelerate HEVC encoding process. A near-sufficient condition is derived to detect variable-sized all-zero blocks. For these blocks, DCT and quantization can be skipped. Moreover, a novel PU pruning technique based on allzero block is presented to constrain prediction units (PU) which have little contribution to RD performance. Experiments on a wide range of videos show that proposed scheme can reduce up to 73.42% and an average of 53.37% computational complexity for HEVC encoder with only trivial loss in PSNR and rate. © 2012 IEEE.

Bidirectional motion estimation significantly enhances video coding efficiency, but its huge complexity is also a critical problem for implementation. This paper presents an interlaced asymmetric search range assignment (IASRA) algorithm. By applying a large and a small search ranges to two reference directions and switching the assignment of these two search ranges once per macroblock, total complexity for bidirectional motion estimation can be reduced by near half with slight coding efficiency drop. IASRA also has the flexibility to be combined with existing fast algorithms and architectures for further complexity saving. We demonstrate this feature by combining IASRA with the state-of-the-art IMNPDR and PMRME architectures, which results in 33% to 42% complexity reduction with less than 1% bit rate increase. © 2012 IEEE.

Because of the limitation in the imaging system, videos captured by mobile devices are usually noisy. In this paper, a noise robust fast video encoding scheme is proposed based on Retinex theory. The reflectance image is estimated in a co-analysis module by Retinex theory, within which the content similarity is detected to conduct the encoding process. Experimental results demonstrate that the proposed encoding scheme provides an average of 18.42 times higher encoding speed relative to the existing approaches without sacrificing the subjective quality.

This paper presents a majority-logic based message-passing algorithm for decoding non-binary LDPC codes. Recently, many majority-logic decoding (MLGD) algorithms make huge efforts on reducing the computational complexity for decoding non-binary LDPC codes. Inspired by one step majority-logic decoding and q-ary sum-product algorithm, we devise a novel iterative double-reliability- based (IDRB) MLGD algorithm which carries out an efficient trade-off between decoding computational complexity and error performance. The proposed algorithm achieves a remarkable enhancement on error correct ability and yet requires only integer operations and finite field operations. Simulation results on two NB-LDPC codes show that we succeed in achieving significant coding gain compared with IHRB-and ISRB-MLGD with limited complexity increase. © 2012 IEEE.

Electromagnetic emissions leak confidential data of cryptographic devices. The electromagnetic emission has been reported as an important side channel for cryptanalysis. Electromagnetic Analysis (EMA) exploits the external radiation of cryptographic devices during encryption to reveal secret keys. The performance of EMA depends on the acquired signals to a large extent. To protect the devices from attacks, noises are introduced in the side channel either by unintentional interference from surroundings or elaborate design from engineers. Thus the secret recovery becomes difficult and even unavailable. In this paper, we propose two signal processing techniques to counteract both of these noises. The bandpass filtering and independent component analysis are widely used in other areas. We demonstrate their applications to EMA against the encryption algorithms on application-specific integrated circuit. With these techniques, the secret keys are extracted successfully and rapidly. © 2012 American Scientific Publishers. All Rights Reserved.

An H.264/AVC intra-frame video encoder is implemented in 65nm CMOS. With an efficient intra prediction design, its maximum throughput reaches 1991Mpixels/s for 7680x4320p 60fps video, 9.4x to 32x faster than previous designs. The encoder also incorporates a 1.41Gbins/s CABAC architecture that has been enhanced by 31%. Moreover, low energy consumption is achieved by the high parallelism and hardware efficiency of this design. 1080p30 encoding dissipates only 2mW at 0.8V and 9MHz. © 2012 IEEE.

HEVC achieves a better coding efficiency relative to prior standards, but also involves increased complexity. For intra prediction, complexity is especially intensive due to a highly flexible coding unit structure and a large number of prediction modes. This paper presents a low-complexity intra prediction algorithm for HEVC. A fast preprocessing stage based on a simplified cost model is proposed. Based on its results, a level filtering scheme reduces the number of prediction unit levels that requires fine processing from 5 to 2. To supply level filtering decision with appropriate thresholds, a fast training method is also designed. A mode filtering scheme further reduces the maximum number of angular modes to be evaluated from 34 to 9. Complexity reduction from HM 3.0 is over 50% and stable for various sequences, which makes the proposed algorithm suitable for real-time applications. The corresponding bit rate increase is lower than 2.5%. © 2012 IEEE.

Weather such as rain and snow cause difficulties in processing the videos captured. Since the appearance of rain drops can affect the performance of human tracking and reduce the efficiency of video compression, detection and removal of rain is a challenging problem in outdoor surveillance systems. In this paper, we propose a new algorithm for rain detection, which is based on joint spatial and wavelet domain features. This approach is robust to the videos with moving objects in the rain. Experimental results demonstrated its better performance in comparison with the existing approaches in the subjective quality.

Multi-view video can provide users a 3-D and virtual reality perception by its multiple viewing angles. In recent years, the depth image-based rendering (DIBR) is generally used to synthesize virtual view images in free viewpoint television (FTV) and three-dimensional (3-D) video. In order to conceal the zero-region more accurately and improve the quality of virtual view synthesized frame, an integrated Hole-filling Algorithm for View Synthesis is proposed in this paper. It contains five parts: the different regions distinguishing algorithm, foreground and background boundary detection, the texture image isophotes detection, the textural and structural isophotes prediction algorithm, the in-painting algorithm with gradient priority order. Based on the texture isophotes prediction with geometrical principle and the in-painting algorithm with gradient priority order, the boundary information of the foreground is much clearer and the texture information in the zero-region can be concealed much more accurately than the previous work. The vision quality mainly depends on the distortion of the structural information. Through the experimental results, the proposed algorithm not only improves the objective quality of the virtual image, but also improves the subjective quality of the virtual image a lot, and the human vision quality is also improved obviously based on the subjective results. Especially, it ensures the boundary contours of the foreground objects and the textural and the structural information. © 2012 Springer-Verlag.

Occlusions significantly affect the result during human tracking. This paper proposes a novel occlusion detection and handling algorithm which is mainly based on the KLT (Kanade-Lucas-Tomasi) method. Instead of using KLT as a tracker, we apply it for occlusion detection to enhance tracking stability. In this paper, a combinational method of particle filter tracking and occlusion detection is proposed. Depending on the detection result, our method makes decisions that whether to update the appearance model and use the occlusion handling strategy. Our occlusion detector associates color information, KLT feature tracker and directions of feature points. Additional, the occlusion handling strategy is based on the information from detection. Moreover, the algorithm also can solve the drift problem. Experimental results on famous datasets prove that our method has better performance and robustness on occlusion detection and handling.

In this paper, a voltage island aware framework is proposed for low power design of application specific NoC (LPASNoC). Through a three-phase processing including voltage island generation, VI-driven floorplanning and post-floorplan processing, the total power consumption, design cost and total wire length can be optimized. Experimental results show that compared to traditional ASNoC, the proposed method can reduce total core power by about 34.5% and chip area by about 26.8% without increasing communication power. Copyright 2012 ACM.

As the successor of H.264/AVC, HEVC inherits the basic property of H.264/AVC and gives some new features. This paper introduces a novel dual-standard de-blocking filter architecture which could support both of the HEVC and H.264/AVC standards. It takes 48 clock cycles for H.264/AVC and 24 cycles for HEVC for every 16×16 block. The proposed unified-cross based processing order greatly reduces the design complexity. The proposed architecture occupies 43.3k equivalent gate count at frequency of 200MHz in SMIC 65nm library, which could satisfy the throughput requirement of quad-full high definition (QFHD) on 60fps for H.264/AVC and super hi-vision (SHV) on 60fps for HEVC. In addition, the total power consumption could be reduced by 37.8% in skipping mode when the edges need not be filtered. © 2012 Springer-Verlag.

We considered the one-sided single-detour untangling twisted nets problem for printed circuit board bus routing. A previous optimal dynamic programming based O(n 3) algorithm was proposed in a previous work, where n is the number of nets. In this paper, we propose an optimal O(n) untangling algorithm without considering capacity, and this algorithm is further modified to consider capacity. Experimental results show that our algorithms runs much faster than the previous work due to its low time complexity. © 2012 IEEE.

Occlusions significantly affect the result during human tracking. This paper proposes a novel occlusion detection and handling algorithm which is mainly based on the KLT (Kanade-Lucas-Tomasi) method. Instead of using KLT as a tracker, we apply it for occlusion detection to enhance tracking stability. In this paper, a combinational method of particle filter tracking and occlusion detection is proposed. Depending on the detection result, our method makes decisions that whether to update the appearance model and use the occlusion handling strategy. Our occlusion detector associates color information, KLT feature tracker and directions of feature points. Additional, the occlusion handling strategy is based on the information from detection. Moreover, the algorithm also can solve the drift problem. Experimental results on famous datasets prove that our method has better performance and robustness on occlusion detection and handling.

In this paper, a voltage island aware framework is proposed for low power design of application specific NoC (LPASNoC). Through a three-phase processing including voltage island generation, VI-driven floorplanning and post-floorplan processing, the total power consumption, design cost and total wire length can be optimized. Experimental results show that compared to traditional ASNoC, the proposed method can reduce total core power by about 34.5% and chip area by about 26.8% without increasing communication power. Copyright 2012 ACM.

This paper presents a majority-logic based message-passing algorithm for decoding non-binary LDPC codes. Recently, many majority-logic decoding (MLGD) algorithms make huge efforts on reducing the computational complexity for decoding non-binary LDPC codes. Inspired by one step majority-logic decoding and q-ary sum-product algorithm, we devise a novel iterative double-reliability- based (IDRB) MLGD algorithm which carries out an efficient trade-off between decoding computational complexity and error performance. The proposed algorithm achieves a remarkable enhancement on error correct ability and yet requires only integer operations and finite field operations. Simulation results on two NB-LDPC codes show that we succeed in achieving significant coding gain compared with IHRB-and ISRB-MLGD with limited complexity increase. © 2012 IEEE.

8Kx4K Super Hi-Vision (SHV) offers a significantly enhanced visual experience relative to 1080p, and is on its way to being the next digital TV standard. In addition, advanced 3DTV specifications involving a large number of camera views are targeted by emerging applications such as free-viewpoint TV (FTV). This paper presents a single-chip design that supports real-time H.264 decoding of SHV or up to 32 HD views. The design of the chip involved 3 key challenges: 1) Data dependencies of video coding algorithms restrict the degree of hardware parallelism. For SHV, each macroblock (MB) should be processed in less than 40 cycles at 300MHz, which is difficult to meet with a single pipeline
2) due to the massive design and verification effort for video decoders, a scalable architecture that allows the maximum reuse of existing IP is desirable
and 3) the DRAM bandwidth requirements are always a bottleneck in high-throughput video decoders. © 2012 IEEE.

8Kx4K Super Hi-Vision (SHV) offers a significantly enhanced visual experience relative to 1080p, and is on its way to being the next digital TV standard. In addition, advanced 3DTV specifications involving a large number of camera views are targeted by emerging applications such as free-viewpoint TV (FTV). This paper presents a single-chip design that supports real-time H.264 decoding of SHV or up to 32 HD views. The design of the chip involved 3 key challenges: 1) Data dependencies of video coding algorithms restrict the degree of hardware parallelism. For SHV, each macroblock (MB) should be processed in less than 40 cycles at 300MHz, which is difficult to meet with a single pipeline
2) due to the massive design and verification effort for video decoders, a scalable architecture that allows the maximum reuse of existing IP is desirable
and 3) the DRAM bandwidth requirements are always a bottleneck in high-throughput video decoders. © 2012 IEEE.

Because of the limitation in the imaging system, videos captured by mobile devices are usually noisy. In this paper, a noise robust fast video encoding scheme is proposed based on Retinex theory. The reflectance image is estimated in a co-analysis module by Retinex theory, within which the content similarity is detected to conduct the encoding process. Experimental results demonstrate that the proposed encoding scheme provides an average of 18.42 times higher encoding speed relative to the existing approaches without sacrificing the subjective quality.

As the successor of H.264/AVC, HEVC inherits the basic property of H.264/AVC and gives some new features. This paper introduces a novel dual-standard de-blocking filter architecture which could support both of the HEVC and H.264/AVC standards. It takes 48 clock cycles for H.264/AVC and 24 cycles for HEVC for every 16×16 block. The proposed unified-cross based processing order greatly reduces the design complexity. The proposed architecture occupies 43.3k equivalent gate count at frequency of 200MHz in SMIC 65nm library, which could satisfy the throughput requirement of quad-full high definition (QFHD) on 60fps for H.264/AVC and super hi-vision (SHV) on 60fps for HEVC. In addition, the total power consumption could be reduced by 37.8% in skipping mode when the edges need not be filtered. © 2012 Springer-Verlag.

This paper presents a majority-logic based message-passing algorithm for decoding non-binary LDPC codes. Recently, many majority-logic decoding (MLGD) algorithms make huge efforts on reducing the computational complexity for decoding non-binary LDPC codes. Inspired by one step majority-logic decoding and q-ary sum-product algorithm, we devise a novel iterative double-reliability- based (IDRB) MLGD algorithm which carries out an efficient trade-off between decoding computational complexity and error performance. The proposed algorithm achieves a remarkable enhancement on error correct ability and yet requires only integer operations and finite field operations. Simulation results on two NB-LDPC codes show that we succeed in achieving significant coding gain compared with IHRB-and ISRB-MLGD with limited complexity increase. © 2012 IEEE.

This paper presents a high-performance dual-issue 32-core SIMD platform for image and video processing. The SIMD cores support 8/16 bits SIMD MAC instructions, and vertical vector access. Eight cores with a 4-ports L2 cache are connected by CIB bus as a cluster. Four clusters are connected by mesh network. This hierarchical network can provide more than 192 GB/s low latency inter-core BW in average. The 4-ports L2 cache architecture is also designed to provide 192 GB/s L2 cache BW. To reduce coherence operation in large-scale SMP, an application specified protocol is proposed. Compared with MOESI, 67.8% of L1 cache energy can be saved in 32 cores case. The whole system including 32 vector cores, 256 KB L2 cache, 64-bit DDRII PHY and two PLL units, occupy 25 mm(2) in 65 nm CMOS. It can achieve a peak performance of 375 GMACs and 98 GMACs/W at 1.2 V.

In this paper, we introduce an LDPC decoder design for decoding a length-672 multi-rate code adopted in IEEE 802.15.3c standard. The proposed decoder features high performances in both data rate and power efficiency. A macro-layer level fully parallel layered decoding architecture is proposed to support the throughput requirement in the standard. For the proposed decoder, it takes only 4 clock cycles to process one decoding iteration. While parallelism increases, the chip routing congestion problem becomes more severe because a more complicated interconnection network is needed for message passing during the decoding process. This problem is nicely solved by our proposed efficient message permutation scheme utilizing exploited parity check matrix features. The proposed message permutation network features high compatibility and zero-logic-gate VLSI implementation, which contribute to the remarkable improvements in both area utilization ratio and total gate count. Meanwhile, frame-level pipeline decoding is applied in the design to shorten the critical path. To verify the above techniques, the proposed decoder is implemented on a chip fabricated using Fujitsu 65 nm 1P12L LVT CMOS process. The chip occupies a core area of 1.30 mm(2) with area utilization ratio 86.3%. According to the measurement results, working at 1.2 V, 400 MHz and 10 iterations the proposed decoder delivers a 6.72 Gb/s data throughput and dissipates a power of 537.6 mW, resulting in an energy efficiency 8.0 pJ/bit/iteration. Moreover, a decoder of the same architecture but with no pipeline stage for low-profile application is also implemented and evaluated at post-layout level.

In this paper, we introduce an LDPC decoder design for decoding a length-672 multi-rate code adopted in IEEE 802.15.3c standard. The proposed decoder features high performances in both data rate and power efficiency. A macro-layer level fully parallel layered decoding architecture is proposed to support the throughput requirement in the standard. For the proposed decoder, it takes only 4 clock cycles to process one decoding iteration. While parallelism increases, the chip routing congestion problem becomes more severe because a more complicated interconnection network is needed for message passing during the decoding process. This problem is nicely solved by our proposed efficient message permutation scheme utilizing exploited parity check matrix features. The proposed message permutation network features high compatibility and zero-logic-gate VLSI implementation, which contribute to the remarkable improvements in both area utilization ratio and total gate count. Meanwhile, frame-level pipeline decoding is applied in the design to shorten the critical path. To verify the above techniques, the proposed decoder is implemented on a chip fabricated using Fujitsu 65 nm 1P12L LVT CMOS process. The chip occupies a core area of 1.30 mm(2) with area utilization ratio 86.3%. According to the measurement results, working at 1.2 V, 400 MHz and 10 iterations the proposed decoder delivers a 6.72 Gb/s data throughput and dissipates a power of 537.6 mW, resulting in an energy efficiency 8.0 pJ/bit/iteration. Moreover, a decoder of the same architecture but with no pipeline stage for low-profile application is also implemented and evaluated at post-layout level.

In this paper, we introduce an LDPC decoder design for decoding a length-672 multi-rate code adopted in IEEE 802.15.3c standard. The proposed decoder features high performances in both data rate and power efficiency. A macro-layer level fully parallel layered decoding architecture is proposed to support the throughput requirement in the standard. For the proposed decoder, it takes only 4 clock cycles to process one decoding iteration. While parallelism increases, the chip routing congestion problem becomes more severe because a more complicated interconnection network is needed for message passing during the decoding process. This problem is nicely solved by our proposed efficient message permutation scheme utilizing exploited parity check matrix features. The proposed message permutation network features high compatibility and zero-logic-gate VLSI implementation, which contribute to the remarkable improvements in both area utilization ratio and total gate count. Meanwhile, frame-level pipeline decoding is applied in the design to shorten the critical path. To verify the above techniques, the proposed decoder is implemented on a chip fabricated using Fujitsu 65 nm 1P12L LVT CMOS process. The chip occupies a core area of 1.30 mm(2) with area utilization ratio 86.3%. According to the measurement results, working at 1.2 V, 400 MHz and 10 iterations the proposed decoder delivers a 6.72 Gb/s data throughput and dissipates a power of 537.6 mW, resulting in an energy efficiency 8.0 pJ/bit/iteration. Moreover, a decoder of the same architecture but with no pipeline stage for low-profile application is also implemented and evaluated at post-layout level.

In this paper, we introduce an LDPC decoder design for decoding a length-672 multi-rate code adopted in IEEE 802.15.3c standard. The proposed decoder features high performances in both data rate and power efficiency. A macro-layer level fully parallel layered decoding architecture is proposed to support the throughput requirement in the standard. For the proposed decoder, it takes only 4 clock cycles to process one decoding iteration. While parallelism increases, the chip routing congestion problem becomes more severe because a more complicated interconnection network is needed for message passing during the decoding process. This problem is nicely solved by our proposed efficient message permutation scheme utilizing exploited parity check matrix features. The proposed message permutation network features high compatibility and zero-logic-gate VLSI implementation, which contribute to the remarkable improvements in both area utilization ratio and total gate count. Meanwhile, frame-level pipeline decoding is applied in the design to shorten the critical path. To verify the above techniques, the proposed decoder is implemented on a chip fabricated using Fujitsu 65 nm 1P12L LVT CMOS process. The chip occupies a core area of 1.30 mm(2) with area utilization ratio 86.3%. According to the measurement results, working at 1.2 V, 400 MHz and 10 iterations the proposed decoder delivers a 6.72 Gb/s data throughput and dissipates a power of 537.6 mW, resulting in an energy efficiency 8.0 pJ/bit/iteration. Moreover, a decoder of the same architecture but with no pipeline stage for low-profile application is also implemented and evaluated at post-layout level.

This paper presents a high-performance dual-issue 32-core SIMD platform for image and video processing. The SIMD cores support 8/16 bits SIMD MAC instructions, and vertical vector access. Eight cores with a 4-ports L2 cache are connected by CIB bus as a cluster. Four clusters are connected by mesh network. This hierarchical network can provide more than 192 GB/s low latency inter-core BW in average. The 4-ports L2 cache architecture is also designed to provide 192 GB/s L2 cache BW. To reduce coherence operation in large-scale SMP, an application specified protocol is proposed. Compared with MOESI, 67.8% of L1 cache energy can be saved in 32 cores case. The whole system including 32 vector cores, 256 KB L2 cache, 64-bit DDRII PHY and two PLL units, occupy 25 mm(2) in 65 nm CMOS. It can achieve a peak performance of 375 GMACs and 98 GMACs/W at 1.2 V.

With the progress of process technology in recent years, low voltage power supplies have become quite predominant. With this, the voltage margin has decreased and therefore the on-chip decoupling capacitance optimization that satisfies the voltage drop constraint becomes more important. In addition, the reduction of the on-chip decoupling capacitance area will reduce the chip area and, therefore, manufacturing costs. Hence, we propose an algorithm that satisfies the voltage drop constraint and at the same time, minimizes the total on-chip decoupling capacitance area. The proposed algorithm uses the idea of the network algorithm where the path which has the most influence on voltage drop is found. Voltage drop is improved by adding the on-chip capacitance to the node on the path. The proposed algorithm is efficient and effectively adds the on-chip capacitance to the greatest influence on the voltage drop. Experimental results demonstrate that, with the proposed algorithm, real size power/ground network could be optimized in just a few minutes which are quite practical. Compared with the conventional algorithm, we confirmed that the total on-chip decoupling capacitance area of the power/ground network was reducible by about 40 similar to 50%.

With the progress of process technology in recent years, low voltage power supplies have become quite predominant. With this, the voltage margin has decreased and therefore the on-chip decoupling capacitance optimization that satisfies the voltage drop constraint becomes more important. In addition, the reduction of the on-chip decoupling capacitance area will reduce the chip area and, therefore, manufacturing costs. Hence, we propose an algorithm that satisfies the voltage drop constraint and at the same time, minimizes the total on-chip decoupling capacitance area. The proposed algorithm uses the idea of the network algorithm where the path which has the most influence on voltage drop is found. Voltage drop is improved by adding the on-chip capacitance to the node on the path. The proposed algorithm is efficient and effectively adds the on-chip capacitance to the greatest influence on the voltage drop. Experimental results demonstrate that, with the proposed algorithm, real size power/ground network could be optimized in just a few minutes which are quite practical. Compared with the conventional algorithm, we confirmed that the total on-chip decoupling capacitance area of the power/ground network was reducible by about 40 similar to 50%.

The state-of-the-art median prediction scheme is widely used for predicting motion vectors (MVs) in recent video standards. By exploiting the spatial correlations among MVs, median prediction scheme predicts MV for current block from three neighboring blocks. When MV is obtained from motion estimation, MV difference (MVD) is calculated and then transmitted. This process for predicting MV and calculating MVD is known as MV coding process. For MV coding, the performance depends on how efficient both the spatial and the temporal correlations among MVs are being exploited. Median prediction scheme applies a sophisticated way including some special rules to exploit the spatial correlations, however the temporal correlations among successive MVs are not exploited. In this paper, a new algorithm named MV pattern matching (MV-PM) exploiting both the spatial and temporal correlations is proposed. Various kinds of experimental results show that the proposed MV-PM algorithm outperforms the median prediction and the other related prediction schemes. (C) 2011 Elsevier Inc. All rights reserved.

The state-of-the-art median prediction scheme is widely used for predicting motion vectors (MVs) in recent video standards. By exploiting the spatial correlations among MVs, median prediction scheme predicts MV for current block from three neighboring blocks. When MV is obtained from motion estimation, MV difference (MVD) is calculated and then transmitted. This process for predicting MV and calculating MVD is known as MV coding process. For MV coding, the performance depends on how efficient both the spatial and the temporal correlations among MVs are being exploited. Median prediction scheme applies a sophisticated way including some special rules to exploit the spatial correlations, however the temporal correlations among successive MVs are not exploited. In this paper, a new algorithm named MV pattern matching (MV-PM) exploiting both the spatial and temporal correlations is proposed. Various kinds of experimental results show that the proposed MV-PM algorithm outperforms the median prediction and the other related prediction schemes. (C) 2011 Elsevier Inc. All rights reserved.

High Dynamic Range (HDR) images have been widely applied in daily applications. However, HDR image is a special format, which needs to be pre-processed known as tone mapping operators for display. Since the visual quality of HDR images is very sensitive to luminance value variations, conventional watermarking methods for low dynamic range (LDR) images are not suitable and may even cause catastrophic visible distortion. Currently, few methods for HDR image watermarking are proposed. In this paper, two watermarking schemes targeting HDR images are proposed, which are based on p-Law and bilateral filtering, respectively. Both of the subjective and objective qualities of watermarked images are greatly improved by the two methods. What's more, these proposed methods also show higher robustness against tone mapping operations.

High Dynamic Range (HDR) images have been widely applied in daily applications. However, HDR image is a special format, which needs to be pre-processed known as tone mapping operators for display. Since the visual quality of HDR images is very sensitive to luminance value variations, conventional watermarking methods for low dynamic range (LDR) images are not suitable and may even cause catastrophic visible distortion. Currently, few methods for HDR image watermarking are proposed. In this paper, two watermarking schemes targeting HDR images are proposed, which are based on p-Law and bilateral filtering, respectively. Both of the subjective and objective qualities of watermarked images are greatly improved by the two methods. What's more, these proposed methods also show higher robustness against tone mapping operations.

During video transmission, errors may happen normally. Addressing error resiliency, the reference modification (RM) approach at video compression encoder is used to modify the original reference to a modified one, which is less sensitive to errors. Apparently it is a bit rate overhead compared to original reference based conventional encoder. Therefore to reduce such bit rate overhead while still keep the error resilience performance is a big issue. A low bit rate overhead based RM approach is proposed in this paper, where the decoder information is exploited to perform encoding. In the proposal, the modified reference has more correlation to original reference, thus can reduce the bit rate overhead. In addition, the proposal can achieve better image recovery compared to existing works, and still be compatible to standard decoder. Overall, the proposal provides the best trade-off among the error resiliency, coding efficiency, and standard compatibility.

During video transmission, errors may happen normally. Addressing error resiliency, the reference modification (RM) approach at video compression encoder is used to modify the original reference to a modified one, which is less sensitive to errors. Apparently it is a bit rate overhead compared to original reference based conventional encoder. Therefore to reduce such bit rate overhead while still keep the error resilience performance is a big issue. A low bit rate overhead based RM approach is proposed in this paper, where the decoder information is exploited to perform encoding. In the proposal, the modified reference has more correlation to original reference, thus can reduce the bit rate overhead. In addition, the proposal can achieve better image recovery compared to existing works, and still be compatible to standard decoder. Overall, the proposal provides the best trade-off among the error resiliency, coding efficiency, and standard compatibility.

Because of the outstanding contribution in improving compression efficiency, block-based quantization has been widely accepted in state-of-the-art image/video coding standards. However, false contour artifacts are introduced, which result in reducing the fidelity of the decoded image/video especially in terms of subjective quality. In this paper, a block-based decontouring method is proposed to reduce the false contour artifacts in the decoded image/video by automatically dithering its direct current (DC) value according to a composite model established between gradient smoothness and block-edge smoothness. Feature points on the model with the corresponding criteria in suppressing contour artifacts are compared to show a good consistency between the model and the actual processing effects. Discrete cosine transform (DCT)-based block level contour artifacts detection mechanism ensures the blocks within the texture region are not affected by the DC dithering. Both the implementation method and the algorithm complexity are analyzed to present the feasibility in integrating the proposed method into an existing video decoder on an embedded platform or system-on-chip (SoC). Experimental results demonstrate the effectiveness of the proposed method both in terms of subjective quality and processing complexity in comparison with the previous methods.

Because of the outstanding contribution in improving compression efficiency, block-based quantization has been widely accepted in state-of-the-art image/video coding standards. However, false contour artifacts are introduced, which result in reducing the fidelity of the decoded image/video especially in terms of subjective quality. In this paper, a block-based decontouring method is proposed to reduce the false contour artifacts in the decoded image/video by automatically dithering its direct current (DC) value according to a composite model established between gradient smoothness and block-edge smoothness. Feature points on the model with the corresponding criteria in suppressing contour artifacts are compared to show a good consistency between the model and the actual processing effects. Discrete cosine transform (DCT)-based block level contour artifacts detection mechanism ensures the blocks within the texture region are not affected by the DC dithering. Both the implementation method and the algorithm complexity are analyzed to present the feasibility in integrating the proposed method into an existing video decoder on an embedded platform or system-on-chip (SoC). Experimental results demonstrate the effectiveness of the proposed method both in terms of subjective quality and processing complexity in comparison with the previous methods.

This paper proposes a region-of-interest (ROI) based H.264 encoder and the VLSI architecture of the ROI detection algorithm. In ROI based video coding system, pre-processing unit to detect ROI should only introduce low computational complexity overhead due to the low power requirement. The Macroblocks (MBs) in ROIs are detected sequentially in the same order of H.264 encoding to satisfy the MB level pipelining of ROI detector and H.264 encoder. ROI detection is performed in a novel estimation-and-verification process with an ROT contour template. Proposed architecture can be configured to detect either single ROI or multiple ROIs in each frame and the throughput of single detection mode is 5.5 times of multiple detection mode. 98.01% and 97.89% of MBs in ROIs can be detected in single and multiple detection modes respectively. Hardware cost of proposed architecture is only 4.68k gates. Detection speed is 753 fps for CIF format video at the operation frequency of 200 MHz in multiple detection mode with power consumption of 0.47 mW. Compared with previous fast ROI detection algorithms for video coding application, the proposed architecture obtains more accurate and smaller ROI. Therefore, more efficient ROT based computation complexity and compression efficiency optimization can be implemented in H.264 encoder.

The increased resolution of Quad Full High Definition (QFHD) offers significantly enhanced visual experience. However, the corresponding huge data throughput of up to 530 Mpixels/s greatly challenges the design of real-time video decoder VLSI with the extensive requirement on both DRAM bandwidth and computational power. In this work, a lossless frame recompression technique and a partial MB reordering scheme are proposed to save the DRAM access of a QFHD video decoder chip. Besides, pipelining and parallelization techniques such as NAL/slice-parallel entropy decoding are implemented to efficiently enhance its computational power. The chip supporting H.264/AVC high profile is fabricated in 90 nm CMOS and verified. It delivers a maximum throughput of 4096x2160@60fps, which is at least 4.3 times higher than the state-of-the-art. DRAM bandwidth requirement is reduced by typically 51%, which fits the design into a 64-bit LPDDR SDRAM interface and results in 58% DRAM power saving. Meanwhile, the core energy is saved by 54% by pipelining and parallelization.

With the process technological progress in recent years, low voltage power supplies have become quite predominant. With this, the voltage margin has decreased and therefore the power/ground design that satisfies the voltage drop constraint becomes more important. In addition, the reduction of the power/ground total wiring area and the number of layers will reduce manufacturing and designing costs. So, we propose an algorithm that satisfies the voltage drop constraint and at the same time, minimizes the power/ground total wiring area. The proposed algorithm uses the idea of a network algorithm [I] where the edge which has the most influence on voltage drop is found. Voltage drop is improved by changing the resistance of the edge. The proposed algorithm is efficient and effectively updates the edge with the greatest influence on the voltage drop. From experimental results, compared with the conventional algorithm, we confirmed that the total wiring area of the power/ground was reducible by about 1/3. Also, the experimental data shows that the proposed algorithm satisfies the voltage drop constraint in the data whereas the conventional algorithm cannot.

Integer Motion Estimation (IME) costs much computation in H.264/AVC video encoder. 2-D SAD tree IME architecture provides very high performance for encoder, and it has been used by many video codec designs. This paper proposes an optimized hardware design of 2-D SAD tree IME. Firstly, a new hardware architecture is proposed to reduce on-chip memory size. Secondly, a new search pattern is proposed to fully use memory bandwidth and reduce external memory access. Thirdly, the data-path is redesigned, and the performance is greatly improved. In order to compare with other IME designs, an IME design support D1 size, 30 fps with search range [+/- 32, +/- 32] is implemented. The hardware cost of this design includes 118 KGates and 8 Kb SRAM, the maximum clock frequency is 200 MHz. Compared to the original 2-D SAD tree IME, our design saves 87.5% on-chip memory, and achieves 3 times performance than original one. Our design provides a new way to design a low cost and high performance IME for H.264/AVC encoder.

The increased resolution of Quad Full High Definition (QFHD) offers significantly enhanced visual experience. However, the corresponding huge data throughput of up to 530 Mpixels/s greatly challenges the design of real-time video decoder VLSI with the extensive requirement on both DRAM bandwidth and computational power. In this work, a lossless frame recompression technique and a partial MB reordering scheme are proposed to save the DRAM access of a QFHD video decoder chip. Besides, pipelining and parallelization techniques such as NAL/slice-parallel entropy decoding are implemented to efficiently enhance its computational power. The chip supporting H.264/AVC high profile is fabricated in 90 nm CMOS and verified. It delivers a maximum throughput of 4096x2160@60fps, which is at least 4.3 times higher than the state-of-the-art. DRAM bandwidth requirement is reduced by typically 51%, which fits the design into a 64-bit LPDDR SDRAM interface and results in 58% DRAM power saving. Meanwhile, the core energy is saved by 54% by pipelining and parallelization.

With the process technological progress in recent years, low voltage power supplies have become quite predominant. With this, the voltage margin has decreased and therefore the power/ground design that satisfies the voltage drop constraint becomes more important. In addition, the reduction of the power/ground total wiring area and the number of layers will reduce manufacturing and designing costs. So, we propose an algorithm that satisfies the voltage drop constraint and at the same time, minimizes the power/ground total wiring area. The proposed algorithm uses the idea of a network algorithm [I] where the edge which has the most influence on voltage drop is found. Voltage drop is improved by changing the resistance of the edge. The proposed algorithm is efficient and effectively updates the edge with the greatest influence on the voltage drop. From experimental results, compared with the conventional algorithm, we confirmed that the total wiring area of the power/ground was reducible by about 1/3. Also, the experimental data shows that the proposed algorithm satisfies the voltage drop constraint in the data whereas the conventional algorithm cannot.

In this paper, we present a cache based motion compensation (MC) architecture for Quad-HD H.264/AVC video decoder. With the significantly increased throughput requirement. VLSI design for MC is greatly challenged by the huge area cost and power consumption. Moreover, the long memory system latency leads to performance drop of the MC pipeline. To solve these problems, three optimization schemes are proposed in this work. Firstly, a high-performance interpolator based on Horizontal-Vertical Expansion and Luma-Chroma Parallelism (HVE-LCP) is proposed to efficiently increase the processing throughput to at least over 4 times as the previous designs. Secondly, an efficient cache memory organization scheme (4Sx4) is adopted to improve the on-chip memory utilization, which contributes to memory area saving of 25% and memory power saving of 39 similar to 49%. Finally, by employing a Split Task Queue (STQ) architecture, the cache system is capable of tolerating much longer latency of the memory system. Consequently, the cache idle time is saved by 90%, which contributes to reducing the overall processing time by 24 similar to 40%. When implemented with SMIC 90 nm process, this design costs a logic gate count and on-chip memory of 108.8k and 3.1kB respectively. The proposed MC architecture can support real-time processing of 3840x2160@60 fps with less than 166 MHz.

Integer Motion Estimation (IME) costs much computation in H.264/AVC video encoder. 2-D SAD tree IME architecture provides very high performance for encoder, and it has been used by many video codec designs. This paper proposes an optimized hardware design of 2-D SAD tree IME. Firstly, a new hardware architecture is proposed to reduce on-chip memory size. Secondly, a new search pattern is proposed to fully use memory bandwidth and reduce external memory access. Thirdly, the data-path is redesigned, and the performance is greatly improved. In order to compare with other IME designs, an IME design support D1 size, 30 fps with search range [+/- 32, +/- 32] is implemented. The hardware cost of this design includes 118 KGates and 8 Kb SRAM, the maximum clock frequency is 200 MHz. Compared to the original 2-D SAD tree IME, our design saves 87.5% on-chip memory, and achieves 3 times performance than original one. Our design provides a new way to design a low cost and high performance IME for H.264/AVC encoder.

This paper proposes a region-of-interest (ROI) based H.264 encoder and the VLSI architecture of the ROI detection algorithm. In ROI based video coding system, pre-processing unit to detect ROI should only introduce low computational complexity overhead due to the low power requirement. The Macroblocks (MBs) in ROIs are detected sequentially in the same order of H.264 encoding to satisfy the MB level pipelining of ROI detector and H.264 encoder. ROI detection is performed in a novel estimation-and-verification process with an ROT contour template. Proposed architecture can be configured to detect either single ROI or multiple ROIs in each frame and the throughput of single detection mode is 5.5 times of multiple detection mode. 98.01% and 97.89% of MBs in ROIs can be detected in single and multiple detection modes respectively. Hardware cost of proposed architecture is only 4.68k gates. Detection speed is 753 fps for CIF format video at the operation frequency of 200 MHz in multiple detection mode with power consumption of 0.47 mW. Compared with previous fast ROI detection algorithms for video coding application, the proposed architecture obtains more accurate and smaller ROI. Therefore, more efficient ROT based computation complexity and compression efficiency optimization can be implemented in H.264 encoder.

Intra coding in H.264/AVC significantly enhances video compression efficiency. However, due to the high data dependency of intra prediction in H.264, both pipelining and parallel processing techniques are limited to be applied. Moreover, it is difficult to get high hardware utilization and throughput because of the long block/MB-level reconstruction loops. This paper proposes a high-performance intra prediction architecture that can support H.264/AVC high profile. The proposed MB/block co-reordering can avoid data dependency and improve pipeline utilization. Therefore, the timing constraint of real-time 4096 x 2160 encoding can be achieved with negligible quality loss. 16 x 16 prediction engine and 8 x 8 prediction engine work parallel for prediction and coefficients generating. A reordering interlaced reconstruction is also designed for fully pipelined architecture. It takes only 160 cycles to process one macroblock (MB). Hardware utilization of prediction and reconstruction modules is almost 100%. Furthermore, PE-reusable 8 x 8 intra predictor and hybrid SAD & SAID mode decision are proposed to save hardware cost. The design is implemented by 90 nm CMOS technology with 113.2k gates and can encode 4096 x 2160 video sequences at 60 fps with operation frequency of 332 MHz.

In this paper, we present a cache based motion compensation (MC) architecture for Quad-HD H.264/AVC video decoder. With the significantly increased throughput requirement. VLSI design for MC is greatly challenged by the huge area cost and power consumption. Moreover, the long memory system latency leads to performance drop of the MC pipeline. To solve these problems, three optimization schemes are proposed in this work. Firstly, a high-performance interpolator based on Horizontal-Vertical Expansion and Luma-Chroma Parallelism (HVE-LCP) is proposed to efficiently increase the processing throughput to at least over 4 times as the previous designs. Secondly, an efficient cache memory organization scheme (4Sx4) is adopted to improve the on-chip memory utilization, which contributes to memory area saving of 25% and memory power saving of 39 similar to 49%. Finally, by employing a Split Task Queue (STQ) architecture, the cache system is capable of tolerating much longer latency of the memory system. Consequently, the cache idle time is saved by 90%, which contributes to reducing the overall processing time by 24 similar to 40%. When implemented with SMIC 90 nm process, this design costs a logic gate count and on-chip memory of 108.8k and 3.1kB respectively. The proposed MC architecture can support real-time processing of 3840x2160@60 fps with less than 166 MHz.

Intra coding in H.264/AVC significantly enhances video compression efficiency. However, due to the high data dependency of intra prediction in H.264, both pipelining and parallel processing techniques are limited to be applied. Moreover, it is difficult to get high hardware utilization and throughput because of the long block/MB-level reconstruction loops. This paper proposes a high-performance intra prediction architecture that can support H.264/AVC high profile. The proposed MB/block co-reordering can avoid data dependency and improve pipeline utilization. Therefore, the timing constraint of real-time 4096 x 2160 encoding can be achieved with negligible quality loss. 16 x 16 prediction engine and 8 x 8 prediction engine work parallel for prediction and coefficients generating. A reordering interlaced reconstruction is also designed for fully pipelined architecture. It takes only 160 cycles to process one macroblock (MB). Hardware utilization of prediction and reconstruction modules is almost 100%. Furthermore, PE-reusable 8 x 8 intra predictor and hybrid SAD & SAID mode decision are proposed to save hardware cost. The design is implemented by 90 nm CMOS technology with 113.2k gates and can encode 4096 x 2160 video sequences at 60 fps with operation frequency of 332 MHz.

As a state-of-the-art video compression technique, H.264/AVC has been deployed in many surveillance cameras to improve the compression efficiency. However, it induces very high coding complexity, and thus high power consumption. In this paper, a difference detection algorithm is proposed to reduce the computational complexity and power consumption in surveillance video compression by automatically distributing the video data to different modules of the video encoder according to their content similarity features. Without any requirement in changing the encoder hardware, the proposed algorithm provides high adaptability to be integrated into the existing H.264 video encoders. An average of over 82% of overall encoding complexity can be reduced regardless of whether or not the H.264 encoder itself has employed fast algorithms. No loss is observed in both subjective and objective video quality. (C) 2011 Elsevier B.V. All rights reserved.

As a state-of-the-art video compression technique, H.264/AVC has been deployed in many surveillance cameras to improve the compression efficiency. However, it induces very high coding complexity, and thus high power consumption. In this paper, a difference detection algorithm is proposed to reduce the computational complexity and power consumption in surveillance video compression by automatically distributing the video data to different modules of the video encoder according to their content similarity features. Without any requirement in changing the encoder hardware, the proposed algorithm provides high adaptability to be integrated into the existing H.264 video encoders. An average of over 82% of overall encoding complexity can be reduced regardless of whether or not the H.264 encoder itself has employed fast algorithms. No loss is observed in both subjective and objective video quality. (C) 2011 Elsevier B.V. All rights reserved.

This paper introduces an adaptive low power decoding process with temporal prediction method for common video. This method can be used to reduce the decoding time and reduce the decoding power consumption by skipping the decoding process of some frames and reducing the frame rate. With the temporal prediction, it is different from the certain frame skipping scheme in the temporal scalable decoding process with frame rate down conversion method (TSDP) [2]. This method considers the video quality loss when the current frame is skipped and chooses the skipping scheme which causes minimum cost, so this method can be also used in the common video cases. And compares with the temporal scalable decoding process with frame rate down conversion method, the video quality (PSNR) is improved about 0.01 - 2.4 dB in the experimental common video cases by using the temporal prediction method. And can reduce the decoding time based on the number of the skipped frames, and it can get about 65% - 86% reduction which compares with the frame rate reduction in the experimental cases. © 2011 IEEE.

Frame-compatible format, packing two neighbouring views into one frame, is considered as a promising solution for 3D distribution in the existing system. In this paper, a fast Infra encoder is designed for frame-compatible format coding based on the content similarity and proposed to reduce the computation complexity. With a relative shift, statistics analysis proves the high prediction correlation between the two packed views and qualifies the first coded view provide prediction mode as the reference for the second view prediction. The proposed scheme enables the prediction of the second view's MB only perform candidate Infra modes and candidate directions of each, according to the reference MB in the first view. An average of 75.69% complexity reduction of encoding the second view can be achieved with comparable compression efficiency. With no requirement to change the decoder of existing system and there is little effort for this encouraging format, this proposed algorithm improves the efficiency of frame-compatible format coding, and contributes to the delivery of 3D service.

As the future of digital photography, high dynamic range imaging (HDRI) has been widely applied in daily applications. However, since the visual quality of HDR images is very sensitive to luminance value variations, the conventional watermarking methods present inefficiency because of introducing many visible image distortions. In this paper, a watermarking scheme targeting HDR images is proposed, which is based on bilateral filtering. Watermarks are embedded into detail part of HDR image which is the residual image between the HDR image and the bilateral filtered image. The objective quality of the watermarked images can be significantly improved by an average of 20dB in PSNR with corresponding improvement in subjective quality. It also shows higher robustness against tone mapping operations. © 2011 IEEE.

Depth Image Based Rendering (DIBR) is a coding strategy for Multiview Video Coding (MVC). Depth video is involved to DIBR to represent another dimensional of the traditional 2D video (texture video). The physics meaning of depth video is different from texture video. But the traditional block based coding system use the same procedure to code both depth video and texture video. A new coding system that dedicate to depth video coding is proposed in this paper, which is called Contour Based Depth map Coding system (CBDC). To meet the feature of sharp-edge and smooth-interior, the proposed CBDC performs contour coding and interior coding separately. This paper focus on introduce the interior coding part. Linear painting modes and non-linear painting mode are introduced and compared. Experimental results indicate that proposed painting method performs an equivalent PSNR performance to the block based coding strategy (JMVC). © 2011 IEEE.

In this paper, a novel approach is proposed to achieve the multi-object tracking in video surveillance system using a combination of tracking by detection method. For the foreground objects detection part, we implement a modified codebook model. First, the block-based model upgrades the pixel-based codebook model to block level, thus improving the processing speed and reducing memory. Moreover, by adding the orientation and magnitude of the block gradient, the codebook model contains not only information of color, but also the texture feature in order to further reduce noises and refine more entire foreground regions. For the tracking aspect, we further utilize the data from the foreground detection that a color-edgetexture histogram is used by calculate the local binary pattern of the edge of the foreground objects which could have a good performance in describing the shape and texture of the objects. Finally, occlusion solutions strategies are applies to order to overcome the occlusion problems during tracking. Experimental results on different data sets prove that our method has better performance and good real-time ability. © 2011 IEEE.

1 As technology advances, 3-D stacking of silicon layers is emerging as a promising approach to address the integration challenges faced by current System-on-Chips (SoCs). Designing efficient Network-on-Chips (NoCs) is necessary to handle the 3-D interconnect complexity. In this paper, we present a four-stage synthesis approach to determine the power-performance efficient 3-D NoC topology for the application. First, we propose an algorithm to explore optimal clustering of cores during 3-D floorplanning. Then, an Integer Linear Programming (ILP) algorithm is proposed to place switches and network interfaces on the 3-D floorplan. Thirdly, a power and timing aware path allocation algorithm is carried out to determine the connectivity across different switches. Last, a min-cost max-flow based algorithm is proposed for Through-Silicon Via (TSV) assignment to minimize the link power consumption. Experimental results show the effectiveness of the proposed algorithm. © 2011 IEEE.

In this paper, a low power parallel surveillance video encoding system based on joint power-speed scheduling is proposed. The relative relationships among the CPU statuses, total power consumption and encoding speed are analyzed and modeled for multi-core processors. Based on the power directional graph and the relative encoding speed model, the working statuses of the cores are controlled jointly adapting to video encoding workload to minimize the total power consumption. It provides more than 20% power reduction compared with the latest existing system without a penalty on the encoding speed. © 2011 IEEE.

As the future of digital photography, high dynamic range imaging (HDRI) has been widely applied in daily applications. However, since the visual quality of HDR images is very sensitive to luminance value variations, the conventional watermarking methods present inefficiency because of introducing many visible image distortions. In this paper, a watermarking scheme targeting HDR images is proposed, which is based on bilateral filtering. Watermarks are embedded into detail part of HDR image which is the residual image between the HDR image and the bilateral filtered image. The objective quality of the watermarked images can be significantly improved by an average of 20dB in PSNR with corresponding improvement in subjective quality. It also shows higher robustness against tone mapping operations. © 2011 IEEE.

In this paper, we propose a full hardware encoder architecture for context-based adaptive binary arithmetic coding (CABAC) for Super Hi-vision data that tries to enlarge the throughput of the encoder. CABAC is a crucial part in H.264/AVC main profile that provides a great compression ratio at the expense of high computational complexity. Due to the data dependence between bit-wise processing, the throughput of the encoder is limited. Some techniques have been proposed in the latest encoder architecture designs to improve the speed to meet the need of QFHD or 3DHD applications. While for Super Hi-vision (4320p) case, a throughput of more than 1Gbps is required. While the current designs can only reach a throughput of around 660Mbps. As a result, frame parallelism is a usual but hardware costing way to solve the throughput gap. What's more, frame parallel will also cost frame delay problem, which is crucial in real-time system. This design tries to avoid the frame parallelism and save the power by encoding 4 bins per cycle using only one core, while working at a frequency of 264MHz. The technology used for synthesis is SMIC 90nm. Two main ideas are applied in this design to realize this high throughput. © 2011 IEEE.

Turbo code and Low Density Parity Check (LDPC) code are both recommended as FEC code in many communication standards owing to their impressive error correcting performance. Aiming at the common architecture which can decode both of the two codes, this paper describes the method of decoding turbo codes with message passing algorithm which is conventionally used for LDPC codes. In this method, turbo codes are viewed as block codes and the sparse parity check matrices are constructed through Smith Decomposition or GBT (Generator matrix based transformation). In order to guarantee decoding performance, we propose the criterion of turbo codes with no 4-cycles, which is mathematically proved and demonstrated by the simulation results. © 2011 IEEE.

In this paper, we propose a full hardware encoder architecture for context-based adaptive binary arithmetic coding (CABAC) for Super Hi-vision data that tries to enlarge the throughput of the encoder. CABAC is a crucial part in H.264/AVC main profile that provides a great compression ratio at the expense of high computational complexity. Due to the data dependence between bit-wise processing, the throughput of the encoder is limited. Some techniques have been proposed in the latest encoder architecture designs to improve the speed to meet the need of QFHD or 3DHD applications. While for Super Hi-vision (4320p) case, a throughput of more than 1Gbps is required. While the current designs can only reach a throughput of around 660Mbps. As a result, frame parallelism is a usual but hardware costing way to solve the throughput gap. What's more, frame parallel will also cost frame delay problem, which is crucial in real-time system. This design tries to avoid the frame parallelism and save the power by encoding 4 bins per cycle using only one core, while working at a frequency of 264MHz. The technology used for synthesis is SMIC 90nm. Two main ideas are applied in this design to realize this high throughput. © 2011 IEEE.

During the depth image based rendering (DIBR), depth map is a new type of video sequence to be compressed. The synthesized result of DIBR is highly related to the quality of the depth map. Depth map also has some new features than color maps. It occurs to us that some improvement is required. Higher efficiency and keeping the edge quality is two critical issues for depth compression. In this paper, region of interest (ROI) detection is introduced to meet these requirements. We adopt an ROI detection method which can distinguish the moving and relatively complexity part (foreground) from each frame. By using different mode decision strategy in ROI and non-ROI, computing burden is reduced and performance is kept. Experimental results show that the proposed strategy saves 40% computation of ME on average with an acceptable performance lost. © 2011 IEEE.

This paper presents a high-performance dual-issue 32-core SIMD platform for image and video processing. Eight cores with a 4-ports L2 cache are connected by CIB bus as a cluster. Four clusters are connected by mesh network. The proposed hierarchical network can provide 192 GB/sintercore communication BW in average. To reduce coherence operation in large-scale SMP, an application specified protocol is proposed. Comparing with MOESI, 67.8% of L1 Cache energy can be saved in 32 cores case. It can achieve a peak performance of 375 GMACs and 98 GMACs/W in 65 nm CMOS. © 2011 IEEE.

Power analysis attacks are based on analyzing the power consumption of the cryptographic devices while they perform the encryption operation. Correlation Power Analysis (CPA) attacks exploit the linear relation between the known power consumption and the predicted power consumption of cryptographic devices to recover keys. It has been one of the effective side channel attacks that threaten the security of CMOS circuits. However, few works consider the leakage of glitches at the logic gates. In this paper, we present a new power consumption model, namely Switching Glitch (SG) power leakage model, which not only considers the data dependent switching activities but also including glitch power consumptions in CMOS circuits. Additionally, from a theoretical point of view, we show how to estimate the glitch factor. The experiments against AES implementation validate the proposed model. Compared with CPA based on Hamming Distance model, the power traces of recovering keys have been decreased by as much as 28.9%. © 2011 ACADEMY PUBLISHER.

Structured quasi-cyclic low-density parity-check (QC-LDPC) code is a part of many emerging wireless communication standards, such as WiMAX, WiFi and WPAN. This paper presents a high parallel decoder architecture for the QC-LDPC codes and the corresponding decoder ASIC for WiMAX system. Through utilizing the proposed fully parallel layered scheduling architecture, the decoder chip saves 22.2% memory bits and takes 24-48 clock cycles per iteration for different code rates. It occupies 3.36 mm 2 in SMIC 65nm CMOS, and realizes 1Gbps (1056Mbps) throughput at 1.2V, 110MHz and 10 iterations with the power 115mW and power efficiency 10.9pJ/bit/iteration. The energy/bit/iteration reduces 63.6% in normalized comparison with the state-of-art publication. © 2011 IEEE.

Depth Image Based Rendering (DIBR) is a coding strategy for Multiview Video Coding (MVC). Depth video is involved to DIBR to represent another dimensional of the traditional 2D video (texture video). The physics meaning of depth video is different from texture video. But the traditional block based coding system use the same procedure to code both depth video and texture video. A new coding system that dedicate to depth video coding is proposed in this paper, which is called Contour Based Depth map Coding system (CBDC). To meet the feature of sharp-edge and smooth-interior, the proposed CBDC performs contour coding and interior coding separately. This paper focus on introduce the interior coding part. Linear painting modes and non-linear painting mode are introduced and compared. Experimental results indicate that proposed painting method performs an equivalent PSNR performance to the block based coding strategy (JMVC). © 2011 IEEE.

In this paper, a novel approach is proposed to achieve the multi-object tracking in video surveillance system using a combination of tracking by detection method. For the foreground objects detection part, we implement a modified codebook model. First, the block-based model upgrades the pixel-based codebook model to block level, thus improving the processing speed and reducing memory. Moreover, by adding the orientation and magnitude of the block gradient, the codebook model contains not only information of color, but also the texture feature in order to further reduce noises and refine more entire foreground regions. For the tracking aspect, we further utilize the data from the foreground detection that a color-edgetexture histogram is used by calculate the local binary pattern of the edge of the foreground objects which could have a good performance in describing the shape and texture of the objects. Finally, occlusion solutions strategies are applies to order to overcome the occlusion problems during tracking. Experimental results on different data sets prove that our method has better performance and good real-time ability. © 2011 IEEE.

Turbo code and Low Density Parity Check (LDPC) code are both recommended as FEC code in many communication standards owing to their impressive error correcting performance. Aiming at the common architecture which can decode both of the two codes, this paper describes the method of decoding turbo codes with message passing algorithm which is conventionally used for LDPC codes. In this method, turbo codes are viewed as block codes and the sparse parity check matrices are constructed through Smith Decomposition or GBT (Generator matrix based transformation). In order to guarantee decoding performance, we propose the criterion of turbo codes with no 4-cycles, which is mathematically proved and demonstrated by the simulation results. © 2011 IEEE.

In this paper, a novel approach is proposed for face detection in still image based on the AdaBoost algorithm. First, face candidates are detected by AdaBoost Algorithm. Since a lot of influence might exist, such as size of the image, illumination and noise, some non-faces windows might also be detected as face candidates, or some faces might be missed. In order to solve these problems and get better performances, we take use of skin color information in the YCbCr color space together with the edge information of the color image. In this way, we are able to remove some non-faces that have been wrongly detected as faces and add some possible missed faces as well. Experimental results show that the hit rate could be improved and false alarm could also be reduced by this method.

Leakage power is growing comparable to dynamic power dissipation as a result of technology trends, and thus it has become an important issue in low-power circuit design. As a popular technique for standby power reduction, power gating is applied to high-parallel LDPC decoder for WiMAX standard. The clustered-block processing engine (CBPE) array are divided into 9 power domains, and they are switched on or off according to different code lengths of LDPC code defined in WiMAX standard. As CBPE array occupies about 70% of the decoder system, the dedicated power gating strategy is very effective in shorter code length case since more power domains can be switched off. At shortest code length, power gating design brings about 55% power reduction compared to that of longest code length. © 2011 IEEE.

In this paper, a low power parallel surveillance video encoding system based on joint power-speed scheduling is proposed. The relative relationships among the CPU statuses, total power consumption and encoding speed are analyzed and modeled for multi-core processors. Based on the power directional graph and the relative encoding speed model, the working statuses of the cores are controlled jointly adapting to video encoding workload to minimize the total power consumption. It provides more than 20% power reduction compared with the latest existing system without a penalty on the encoding speed. © 2011 IEEE.

Structured quasi-cyclic low-density parity-check (QC-LDPC) code is a part of many emerging wireless communication standards, such as WiMAX, WiFi and WPAN. This paper presents a high parallel decoder architecture for the QC-LDPC codes and the corresponding decoder ASIC for WiMAX system. Through utilizing the proposed fully parallel layered scheduling architecture, the decoder chip saves 22.2% memory bits and takes 24-48 clock cycles per iteration for different code rates. It occupies 3.36 mm 2 in SMIC 65nm CMOS, and realizes 1Gbps (1056Mbps) throughput at 1.2V, 110MHz and 10 iterations with the power 115mW and power efficiency 10.9pJ/bit/iteration. The energy/bit/iteration reduces 63.6% in normalized comparison with the state-of-art publication. © 2011 IEEE.

This paper introduces an adaptive temporal scalable decoding scheme with temporal and spatial prediction method. This method can be used to reduce the decoding time and reduce the decoding power consumption by skipping the decoding process of some frames and reducing the frame rate. With the spatial prediction and the temporal prediction, it is different from the certain frame skipping scheme in the temporal scalable decoding process with frame rate down conversion method (TSDP) [2]. This method chooses the skipping scheme which causes minimum cost by considering the video quality loss when the current frame is skipped and the movements of the current frame, so this method can be also used in the common video cases well. It is compared with the process which only used the temporal prediction method [3], the video quality (PSNR) is improved about 0.94.6 dB in the experimental common video cases by using the combined method. It can reduce the decoding time based on the number of the skipped frames, and can also get about 65%-86% reduction which compares with the frame rate reduction in the experimental cases. © 2011 IEEE.

In recent years, LBP feature based svm detector and Haar feature based cascade detector are the two types of efficient detectors for face detection. In this paper, we proposed to improve the performance on Haar feature based cascade detector. First, we describe a new feature for cascade detector. The feature is called Separate Haar Feature. Secondly, we describe a new decision algorithm in cascade detection to improve the detection rate. There are three key contributions. The first is "Separate Haar Feature", which adds a don't-care area between the rectangles of Haar Feature. The second is the algorithm for selecting the best width for this don't-care area. Finally, we proposed a new decision algorithm which makes the decision by not only a stage result in cascade detection process to improve the detection rate. © 2011 IEEE.

Frame-compatible format, packing two neighbouring views into one frame, is considered as a promising solution for 3D distribution in the existing system. In this paper, a fast Infra encoder is designed for frame-compatible format coding based on the content similarity and proposed to reduce the computation complexity. With a relative shift, statistics analysis proves the high prediction correlation between the two packed views and qualifies the first coded view provide prediction mode as the reference for the second view prediction. The proposed scheme enables the prediction of the second view's MB only perform candidate Infra modes and candidate directions of each, according to the reference MB in the first view. An average of 75.69% complexity reduction of encoding the second view can be achieved with comparable compression efficiency. With no requirement to change the decoder of existing system and there is little effort for this encouraging format, this proposed algorithm improves the efficiency of frame-compatible format coding, and contributes to the delivery of 3D service.

1 As technology advances, 3-D stacking of silicon layers is emerging as a promising approach to address the integration challenges faced by current System-on-Chips (SoCs). Designing efficient Network-on-Chips (NoCs) is necessary to handle the 3-D interconnect complexity. In this paper, we present a four-stage synthesis approach to determine the power-performance efficient 3-D NoC topology for the application. First, we propose an algorithm to explore optimal clustering of cores during 3-D floorplanning. Then, an Integer Linear Programming (ILP) algorithm is proposed to place switches and network interfaces on the 3-D floorplan. Thirdly, a power and timing aware path allocation algorithm is carried out to determine the connectivity across different switches. Last, a min-cost max-flow based algorithm is proposed for Through-Silicon Via (TSV) assignment to minimize the link power consumption. Experimental results show the effectiveness of the proposed algorithm. © 2011 IEEE.

In recent years, LBP feature based svm detector and Haar feature based cascade detector are the two types of efficient detectors for face detection. In this paper, we proposed to improve the performance on Haar feature based cascade detector. First, we describe a new feature for cascade detector. The feature is called Separate Haar Feature. Secondly, we describe a new decision algorithm in cascade detection to improve the detection rate. There are three key contributions. The first is "Separate Haar Feature", which adds a don't-care area between the rectangles of Haar Feature. The second is the algorithm for selecting the best width for this don't-care area. Finally, we proposed a new decision algorithm which makes the decision by not only a stage result in cascade detection process to improve the detection rate. © 2011 IEEE.

During the depth image based rendering (DIBR), depth map is a new type of video sequence to be compressed. The synthesized result of DIBR is highly related to the quality of the depth map. Depth map also has some new features than color maps. It occurs to us that some improvement is required. Higher efficiency and keeping the edge quality is two critical issues for depth compression. In this paper, region of interest (ROI) detection is introduced to meet these requirements. We adopt an ROI detection method which can distinguish the moving and relatively complexity part (foreground) from each frame. By using different mode decision strategy in ROI and non-ROI, computing burden is reduced and performance is kept. Experimental results show that the proposed strategy saves 40% computation of ME on average with an acceptable performance lost. © 2011 IEEE.

Power analysis attacks are based on analyzing the power consumption of the cryptographic devices while they perform the encryption operation. Correlation Power Analysis (CPA) attacks exploit the linear relation between the known power consumption and the predicted power consumption of cryptographic devices to recover keys. It has been one of the effective side channel attacks that threaten the security of CMOS circuits. However, few works consider the leakage of glitches at the logic gates. In this paper, we present a new power consumption model, namely Switching Glitch (SG) power leakage model, which not only considers the data dependent switching activities but also including glitch power consumptions in CMOS circuits. Additionally, from a theoretical point of view, we show how to estimate the glitch factor. The experiments against AES implementation validate the proposed model. Compared with CPA based on Hamming Distance model, the power traces of recovering keys have been decreased by as much as 28.9%. © 2011 ACADEMY PUBLISHER.

In this paper, new raster scan orders other than the conventional horizontal scan from the top-left corner of the image/slice are proposed to fully exploit content correlation from the regions right to and below the current coding unit. By being applied to each slice/frame adaptively with the conventional one, features influencing the scan order selection are investigated. Different adaptive scan schemes are tested and compared. Up to 3.4% bit-rate reduction can be achieved for Intra coding with limited increase in complexity. © 2011 IEEE.

This paper introduces an adaptive low power decoding process with temporal prediction method for common video. This method can be used to reduce the decoding time and reduce the decoding power consumption by skipping the decoding process of some frames and reducing the frame rate. With the temporal prediction, it is different from the certain frame skipping scheme in the temporal scalable decoding process with frame rate down conversion method (TSDP) [2]. This method considers the video quality loss when the current frame is skipped and chooses the skipping scheme which causes minimum cost, so this method can be also used in the common video cases. And compares with the temporal scalable decoding process with frame rate down conversion method, the video quality (PSNR) is improved about 0.01 - 2.4 dB in the experimental common video cases by using the temporal prediction method. And can reduce the decoding time based on the number of the skipped frames, and it can get about 65% - 86% reduction which compares with the frame rate reduction in the experimental cases. © 2011 IEEE.

In this paper, a novel approach is proposed for face detection in still image based on the AdaBoost algorithm. First, face candidates are detected by AdaBoost Algorithm. Since a lot of influence might exist, such as size of the image, illumination and noise, some non-faces windows might also be detected as face candidates, or some faces might be missed. In order to solve these problems and get better performances, we take use of skin color information in the YCbCr color space together with the edge information of the color image. In this way, we are able to remove some non-faces that have been wrongly detected as faces and add some possible missed faces as well. Experimental results show that the hit rate could be improved and false alarm could also be reduced by this method.

Leakage power is growing comparable to dynamic power dissipation as a result of technology trends, and thus it has become an important issue in low-power circuit design. As a popular technique for standby power reduction, power gating is applied to high-parallel LDPC decoder for WiMAX standard. The clustered-block processing engine (CBPE) array are divided into 9 power domains, and they are switched on or off according to different code lengths of LDPC code defined in WiMAX standard. As CBPE array occupies about 70% of the decoder system, the dedicated power gating strategy is very effective in shorter code length case since more power domains can be switched off. At shortest code length, power gating design brings about 55% power reduction compared to that of longest code length. © 2011 IEEE.

In this paper, new raster scan orders other than the conventional horizontal scan from the top-left corner of the image/slice are proposed to fully exploit content correlation from the regions right to and below the current coding unit. By being applied to each slice/frame adaptively with the conventional one, features influencing the scan order selection are investigated. Different adaptive scan schemes are tested and compared. Up to 3.4% bit-rate reduction can be achieved for Intra coding with limited increase in complexity. © 2011 IEEE.

This paper introduces an adaptive temporal scalable decoding scheme with temporal and spatial prediction method. This method can be used to reduce the decoding time and reduce the decoding power consumption by skipping the decoding process of some frames and reducing the frame rate. With the spatial prediction and the temporal prediction, it is different from the certain frame skipping scheme in the temporal scalable decoding process with frame rate down conversion method (TSDP) [2]. This method chooses the skipping scheme which causes minimum cost by considering the video quality loss when the current frame is skipped and the movements of the current frame, so this method can be also used in the common video cases well. It is compared with the process which only used the temporal prediction method [3], the video quality (PSNR) is improved about 0.94.6 dB in the experimental common video cases by using the combined method. It can reduce the decoding time based on the number of the skipped frames, and can also get about 65%-86% reduction which compares with the frame rate reduction in the experimental cases. © 2011 IEEE.

Permutation network plays an important role in the reconfigurable QC LDPC decoder for most modem wireless communication systems with multiple code rates and various code lengths This paper presents the generic permutation network (GPN) for the reconfigurable QC LDPC decoder Compared with conventional permutation networks this proposal could break through the input number restriction such as power of 2 and other limited number and optimize the network for any application in demand Moreover the proposed scheme could greatly reduce the latency because of less stages and efficient control signal generating algorithm In addition the proposed network processes the nature of high parallelism which could enable several groups of data to be cyclically shifted simultaneously The synthesis results using the 90 nm technology demonstrate that this architecture can be implemented with the gate count of 18 3k for WiMAX standard at the frequency of 600 MHz and 10 9k for WiFi standard at the frequency of 800 MHz

Permutation network plays an important role in the reconfigurable QC LDPC decoder for most modem wireless communication systems with multiple code rates and various code lengths This paper presents the generic permutation network (GPN) for the reconfigurable QC LDPC decoder Compared with conventional permutation networks this proposal could break through the input number restriction such as power of 2 and other limited number and optimize the network for any application in demand Moreover the proposed scheme could greatly reduce the latency because of less stages and efficient control signal generating algorithm In addition the proposed network processes the nature of high parallelism which could enable several groups of data to be cyclically shifted simultaneously The synthesis results using the 90 nm technology demonstrate that this architecture can be implemented with the gate count of 18 3k for WiMAX standard at the frequency of 600 MHz and 10 9k for WiFi standard at the frequency of 800 MHz

In this paper, a human detection method is developed. An appearance based detector and a motion based detector are proposed respectively. A multi scale block histogram of template feature (MB-HOT) is used to detect human by the appearance. It integrates the gray value information and the gradient value information, and represents the relationship of three blocks. Experiment on INRIA dataset shows that this feature is more discriminative than other features, such as histogram of orientation gradient (HOG). A motion based feature is also proposed to capture the relative motion of human body. This feature is calculated in optical flow domain and experimental result in our dataset shows that this feature outperforms other motion based features. The detection responses obtained by two features are combined to reduce the false detection. Graphic process unit (GPU) based implementation is proposed to accelerate the calculation of two features, and make it suitable for real time applications.

In this paper, a human detection method is developed. An appearance based detector and a motion based detector are proposed respectively. A multi scale block histogram of template feature (MB-HOT) is used to detect human by the appearance. It integrates the gray value information and the gradient value information, and represents the relationship of three blocks. Experiment on INRIA dataset shows that this feature is more discriminative than other features, such as histogram of orientation gradient (HOG). A motion based feature is also proposed to capture the relative motion of human body. This feature is calculated in optical flow domain and experimental result in our dataset shows that this feature outperforms other motion based features. The detection responses obtained by two features are combined to reduce the false detection. Graphic process unit (GPU) based implementation is proposed to accelerate the calculation of two features, and make it suitable for real time applications.

In this paper, a novel self-adjustable offset min-sum LDPC decoding algorithm is proposed for ISDB-S2 application. We present for the first time a uniform approximation of the check node operation through mathematical induction on Jacobian logarithm and theoretically shows that the offset value is mainly dependent on the difference of the two most unreliable inputs from the bit nodes, which makes the offset value adjustable during the iterative decoding procedure. Simulation results for all 11 code rates of ISDB-S2 demonstrate that the proposed method can achieve an average of 0.15 dB gain compared to the Min-sum based algorithms, and consumes only 1.21% computation complexity compared to BP-based algorithms in the best case.

In this paper, a novel self-adjustable offset min-sum LDPC decoding algorithm is proposed for ISDB-S2 application. We present for the first time a uniform approximation of the check node operation through mathematical induction on Jacobian logarithm and theoretically shows that the offset value is mainly dependent on the difference of the two most unreliable inputs from the bit nodes, which makes the offset value adjustable during the iterative decoding procedure. Simulation results for all 11 code rates of ISDB-S2 demonstrate that the proposed method can achieve an average of 0.15 dB gain compared to the Min-sum based algorithms, and consumes only 1.21% computation complexity compared to BP-based algorithms in the best case.

In this paper, VLSI architecture of a joint parameter decoder is proposed to realize the calculation of motion vector (MV), intra prediction mode (IPM) and boundary strength (BS) for ultra high definition H.264/AVC applications. For this architecture, a 64-cycle-per-MB pipeline with simplified control modes is designed to increase system throughput and reduce hardware cost. Moreover, in order to save memory bandwidth, the data which includes the motion information for the co-located picture and the last decoded line, is pre-processed before being stored to DRAM. A partition based storage format is applied to condense the MB level data, while variable length coding based compression method is utilized to reduce the data size in each partition. Experimental results show our design is capable of real-time 3840 x 2160@60 fps decoding at less than 133 MHz, with 37.2k logic gates. Meanwhile, by applying the proposed scheme, 85-98% bandwidth saving is achieved, compared with storing the original information for every 4 x 4 block to DRAM.

In this paper, VLSI architecture of a joint parameter decoder is proposed to realize the calculation of motion vector (MV), intra prediction mode (IPM) and boundary strength (BS) for ultra high definition H.264/AVC applications. For this architecture, a 64-cycle-per-MB pipeline with simplified control modes is designed to increase system throughput and reduce hardware cost. Moreover, in order to save memory bandwidth, the data which includes the motion information for the co-located picture and the last decoded line, is pre-processed before being stored to DRAM. A partition based storage format is applied to condense the MB level data, while variable length coding based compression method is utilized to reduce the data size in each partition. Experimental results show our design is capable of real-time 3840 x 2160@60 fps decoding at less than 133 MHz, with 37.2k logic gates. Meanwhile, by applying the proposed scheme, 85-98% bandwidth saving is achieved, compared with storing the original information for every 4 x 4 block to DRAM.

In this paper, we propose a novel feature named histogram of template (HOT) for human detection in still images. For every pixel of an image, various templates are defined, each of which contains the pixel itself and two of its neighboring pixels. If the texture and gradient values of the three pixels satisfy a pre-defined formula, the central pixel is regarded to meet the corresponding template for this formula. Histograms of pixels meeting various templates are calculated for a set of formulas, and combined to be the feature for detection. Compared to the other features, the proposed feature takes texture as well as the gradient information into consideration. Besides, it reflects the relationship between 3 pixels, instead of focusing on only one. Experiments for human detection are performed on INRIA dataset, which shows the proposed HOT feature is more discriminative than histogram of orientated gradient (HOG) feature, under the same training method.

In this paper, we propose a novel feature named histogram of template (HOT) for human detection in still images. For every pixel of an image, various templates are defined, each of which contains the pixel itself and two of its neighboring pixels. If the texture and gradient values of the three pixels satisfy a pre-defined formula, the central pixel is regarded to meet the corresponding template for this formula. Histograms of pixels meeting various templates are calculated for a set of formulas, and combined to be the feature for detection. Compared to the other features, the proposed feature takes texture as well as the gradient information into consideration. Besides, it reflects the relationship between 3 pixels, instead of focusing on only one. Experiments for human detection are performed on INRIA dataset, which shows the proposed HOT feature is more discriminative than histogram of orientated gradient (HOG) feature, under the same training method.

Since the structured quasi-cyclic low-density parity-check (QC-LDPC) codes tor most modern wireless communication systems include multiple code rates, various block lengths. and the corresponding different sizes of submatrices in parity check matrix (PCM), the reconfigurable LDPC decoder is desirable and the permutation network is needed to accommodate any Input number (IN) and shift number (SN) for cyclic shift In this paper we propose a novel permutation network architecture for the reconfigurable QC-LDPC decoders based on Banyan network We prove that Banyan network ha, the nonblocking property or cyclic shift when the IN is power of 2, and give the control signal generating algorithm Through introducing the bypass network, we put forward the nonblocking scheme for any IN and SN In addition, we present the hardware design of the control signal generator. which can greatly reduce the hardware complexity and latency The synthesis results using the TSMC 0 mu m pin library demonstrate that the proposed permutation network can be implemented with the area of 0 546 mm(2) and the frequency of 292 MHz

Motion compensation is widely used in many video coding standards Due to its bandwidth requirement and complexity. motion compensation is One of the most challenging parts in the design of high definition video decoder In this paper, we propose a high performance and low bandwidth motion compensation design which supports H 264/AVC. MPEG-1/2 and Chinese AVS standards We introduce a 2-Dimensional cache that can greatly reduce the external bandwidth requirement Similarities among the 3 standards are also explored to reduce hardware cost We also propose a block-pipelining strategy to conceal the long latency of external memory access Experimental results show that our motion compensation design can reduce the bandwidth by 74% in average and it can teal-tune decode 1920x1088@30 fps video stream at 80 MHz

Since the structured quasi-cyclic low-density parity-check (QC-LDPC) codes tor most modern wireless communication systems include multiple code rates, various block lengths. and the corresponding different sizes of submatrices in parity check matrix (PCM), the reconfigurable LDPC decoder is desirable and the permutation network is needed to accommodate any Input number (IN) and shift number (SN) for cyclic shift In this paper we propose a novel permutation network architecture for the reconfigurable QC-LDPC decoders based on Banyan network We prove that Banyan network ha, the nonblocking property or cyclic shift when the IN is power of 2, and give the control signal generating algorithm Through introducing the bypass network, we put forward the nonblocking scheme for any IN and SN In addition, we present the hardware design of the control signal generator. which can greatly reduce the hardware complexity and latency The synthesis results using the TSMC 0 mu m pin library demonstrate that the proposed permutation network can be implemented with the area of 0 546 mm(2) and the frequency of 292 MHz

Motion compensation is widely used in many video coding standards Due to its bandwidth requirement and complexity. motion compensation is One of the most challenging parts in the design of high definition video decoder In this paper, we propose a high performance and low bandwidth motion compensation design which supports H 264/AVC. MPEG-1/2 and Chinese AVS standards We introduce a 2-Dimensional cache that can greatly reduce the external bandwidth requirement Similarities among the 3 standards are also explored to reduce hardware cost We also propose a block-pipelining strategy to conceal the long latency of external memory access Experimental results show that our motion compensation design can reduce the bandwidth by 74% in average and it can teal-tune decode 1920x1088@30 fps video stream at 80 MHz

As a state-of-the-art video compression technique, H.264/AVC has been deployed in many surveillance cameras to improve the compression efficiency. However, it induces very high coding complexity, and thus high power consumption. In this paper, an early skip mode decision algorithm is proposed to reduce the computational complexity and power consumption in surveillance video compression by detecting the content similarity using chrominance and motion features. The overall computational complexity of the whole video encoding system is significantly reduced by 84%. No loss is observed in both of subjective and objective video quality. ©2010 IEEE.

In this paper, a region of interest (ROI) oriented partial H.264/AVC decoding scheme is proposed to enable low-power and low-complexity HD video content display on low resolution screens. The proposed scheme is a macroblock level based partial decoding, which employs several strategies to maintain the good video quality in the ROI The simulation results show that, the proposed scheme provides better visual quality, and very limited PSNR loss quality in the ROI, but it achieves much lower computational complexity and power consumption. On average, it reduces the decoding time by about 40.66% with the PSNR loss up to O.77dB in the ROI among the test cases. The partially decoded sequences maintain more details in the ROI, thus provide better user experience. This proposal is especially useful for the portable devices. © 2010 IEEE.

Depth map coding is a new topic in multiview video coding (MVC) following the development of depth-image-based rendering (DIBR). Since depth map is monochromatic and has less texture than color map, fast algorithm is necessary and possible to reduce the computation burden of the encoder. This paper proposed difference detection based early mode termination strategy. The difference detection (DD) algorithms are categorized to reconstructed frame based (RDD) and original frame based (ODD). A simplified ODD (sODD) strategy is also proposed. Early mode termination based on these three DD algorithms are implemented and evaluated in the reference software of Joint Multiview Video Coding (JMVC) version 8.0 respectively. Simulation results indicate that RDD based one has no performance lost and reduce 25% runtime on average. ODD and sODD based ones can save 54.3% and 43.6% runtime respectively and have an acceptable R-D performance lost. © 2010 IEEE.

This paper proposes a high-performance intra prediction architecture that can support H.264/AVC high profile. The proposed MB/block co-reordering can avoid data dependency and improve pipeline utilization. Therefore, the timing constraint of real-time 4kx2k encoding can be achieved with negligible quality loss. 16×16 prediction engine and 8×8 prediction engine work parallel for prediction and coefficients generating. A reordering interlaced reconstruction is also designed for fully pipelined architecture. It takes only 160 cycles to process one macroblock (MB). Hardware utilization of prediction and reconstruction modules is almost 100%. Furthermore, PE-reusable 8×8 intra predictor and hybrid SAD &amp
SATD mode decision are proposed to save hardware cost. The design is implemented by 90nm CMOS technology with 113.2k gates and can encode 4kx2k video sequences at 60 fps with operation frequency of 310MHz. © 2010 IEEE.

As a state-of-the-art video compression technique, H.264/AVC has been deployed in many surveillance cameras to improve the compression efficiency. However, it induces very high coding complexity, and thus high power consumption. In this paper, an early skip mode decision algorithm is proposed to reduce the computational complexity and power consumption in surveillance video compression by detecting the content similarity using chrominance and motion features. The overall computational complexity of the whole video encoding system is significantly reduced by 84%. No loss is observed in both of subjective and objective video quality. ©2010 IEEE.

In this paper, we propose a novel feature named histogram of template (HOT) for human detection in still images. For every pixel of an image, various templates are defined, each of which contains the pixel itself and two of its neighboring pixels. If the intensity and gradient values of the three pixels satisfy a pre-defined function, the central pixel is regarded to meet the corresponding template for this function. Histograms of pixels meeting various templates are calculated for a set of functions, and combined to be the feature for detection. Compared to the other features, the proposed feature takes intensity as well as the gradient information into consideration. Besides, it reflects the relationship between 3 pixels, instead of focusing on only one. Experiments for human detection are performed on INRIA dataset, which shows the proposed HOT feature is more discriminative than histogram of orientated gradient (HOG) feature, under the same training method. ©2010 IEEE.

In surveillance systems, ultra low bit rate video coding is necessary to reduce the storage and bandwidth consumption, especially for high definition video coding. This paper proposes a new architecture to further reduce the bit rate than H.264/AVC. The algorithm of detecting the difference of the adjacent frames and skipping the static frames in the original video is proposed. Moreover, this paper presents an adaptive coding method to code the active regions with traditional slices and background with the proposed S slice respectively. The S slice contains less syntax elements than the conventional P slice. The simulation results demonstrate that great bit reduction is achieved by these two schemes. © 2010 IEEE.

Advanced Encryption Standard (AES) is a widely used symmetric cryptographic algorithm. Differential power analysis attack (DPA) is a powerful side-channel attack method which has been successfully used to attack AES. As a lot of people focus on revealing the key, more and more people become interested in how to defend DPA attack. In this paper, we propose a method by adding a set of register and a random generator to defend DPA attack. The proposed method has been implemented on SASEBO board. It can process data with 2.56Gbps at 200MHz frequency. And we use the DPA attack to prove it can effectively defend the normal DPA attack. © 2010 IEEE.

This paper presents a new architecture for high profile intra prediction in H.264/AVC video coding standard. Our goal is to design an Intra prediction engine for 4Kx2K@60fps Ultra High Definition (UHD) Decoder. The proposed architecture can provide very stable throughput, which can predict any H.264 intra prediction mode within 66 cycles. Compared with previous design, this feature can guarantee the whole decoding pipeline to work efficiently. The intra prediction engine is divided into two parallel pipelines, one is used for 4x4 block prediction loops and the other is used to prepare data for MB loops. It can overlap data preparing time with prediction time, which can finish data loading and storing within 2 cycles. Comparing with MB pipeline only architecture, it can achieve more than 3.2 times higher throughput with 29.8 K gates cost. The proposed architecture is verified to work at 175 MHz for our UHD Decoder by using TSMC 90 G. © 2010 Information Processing Society of Japan.

This paper proposes an adaptive solution of temporal scalable decoding process with frame rate conversion method for surveillance video. It realizes the adaptive skipping scheme in the temporal scalable decoding process [2] based on the content of the pictures. By analyzing the relationship between motion vector energy and the video quality loss of the same frame in probability, chooses the suitable form of the motion vector value to qualify the video quality loss which is caused by the skipping process in a frame. And uses a selecting algorithm based on the energy accumulation principle to realize the adaptive frame skipping. By using this frame rate-down conversion algorithm, the PSNR is improved about 0.2-1.4 dB (compared with the certain frame skipping scheme [2]) in different skipping cases. And the loss of the decoding time reduction is less than 5% in the worst case, but in the most of the cases it is only 0 ∼ 2%. © 2010 IEEE.

Advanced Encryption Standard (AES) is a widely used symmetric cryptographic algorithm. Differential power analysis attack (DPA) is a powerful side-channel attack method which has been successfully used to attack AES. As a lot of people focus on revealing the key, more and more people become interested in how to defend DPA attack. In this paper, we propose a method by adding a set of register and a random generator to defend DPA attack. The proposed method has been implemented on SASEBO board. It can process data with 2.56Gbps at 200MHz frequency. And we use the DPA attack to prove it can effectively defend the normal DPA attack. © 2010 IEEE.

This paper presents a new architecture for high profile intra prediction in H.264/AVC video coding standard. Our goal is to design an Intra prediction engine for 4Kx2K@60fps Ultra High Definition (UHD) Decoder. The proposed architecture can provide very stable throughput, which can predict any H.264 intra prediction mode within 66 cycles. Compared with previous design, this feature can guarantee the whole decoding pipeline to work efficiently. The intra prediction engine is divided into two parallel pipelines, one is used for 4x4 block prediction loops and the other is used to prepare data for MB loops. It can overlap data preparing time with prediction time, which can finish data loading and storing within 2 cycles. Comparing with MB pipeline only architecture, it can achieve more than 3.2 times higher throughput with 29.8 K gates cost. The proposed architecture is verified to work at 175 MHz for our UHD Decoder by using TSMC 90 G. © 2010 Information Processing Society of Japan.

In this paper we propose a synthesizable LDPC decoder IP core for WiMax and WiFi applications. Two new techniques are applied in the proposed decoder to improve the decoding performance. Firstly, a high parallelism permutation network (PN) is proposed to perform the circulant shift according to the parity check matrix (PCM) defined in WiMax and WiFi standards. By using the proposed PN, at most, four independent code frames with small code length are decoded concurrently, which largely improves the decoding throughput (2-4 times). Secondly, a fast early stopping criterion specialized for WiMax and WiFi LDPC code is proposed to reduce the average iteration number. Unlike the early works, by utilizing our proposed stopping criterion, the decoding will be stopped when all the information bits of a code frame are corrected even if there are still some errors in redundant part. Experiment results show that, it can reduce up to 20% iteration numbers compared to popular used stopping criterion. © 2010 Information Processing Society of Japan.

H.264/AVC achieves low bit-rate video stream which meets the requirement of video communication. The problem of H.264/AVC is the large computation burden. Thus fast algorithm should be adopted to reduce the computation burden to meet the limited power of the mobile device. This paper uses region-of-interest (ROI) detector to locate an “important” region and apply unequally coding in the encoder engine according ROI. Several coding parameters including quantization parameter (QP), candidates for mode decision, number of referencing frames and the search range of motion estimation are adaptively adjusted at the macroblock (MB) level. This design is decoding-friendly. Experimental result shows a large amount computation is saved and the subjective visual quality is kept or even improved. © 2010, The Institute of Image Electronics Engineers of Japan. All rights reserved.

H.264/AVC introduces the variable block size motion estimation (VBSME), which brings huge computational cost of the encoder. In this paper, a novel fast inter mode decision algorithm for H.264/AVC has been proposed. The proposed algorithm evaluates the modes based on residual feature. The residual is obtained after the motion search of P16 X 16 mode or P8 X 8 mode. And then basing on the extracted residual feature, the complexity and similarity are evaluated for the inter mode decision. According to the evaluation of similarity between different sub-blocks and the complexity of each sub-block, the most possible inter modes for current block is chosen to be conducted. In the worst case, the proposed whole scheme of inter mode decision algorithm only conducts 4 modes, which is much more effective than conducting all the 8 modes in conventional approach. The simulation results show that, comparing to JM14.1, on average, the proposed algorithm achieves 57.98% and 55.72% time-saving on CIF and 720p sequences respectively, with equivalent 0.219 dB PSNR drop and 5.55% bit rate increase for CIF and 0.107dB PSNR drop and 3.53% bit rate increase for 720p. Compared to existing inter mode decision algorithm, proposed algorithm achieves 10.68% and 13.26% timing-reduction on CIF and 720p sequences respectively with less performance loss. © 2010, The Institute of Image Electronics Engineers of Japan. All rights reserved.

The variable block sizes for intra and inter coding in H.264/AVC achieves significant coding gain compared with coding a macroblock (MB) with fixed size. However, extremely heavy computational burden is required when Rate Distortion Optimization (RDO) process runs in brutal force searching manner for selecting the optimal coding block. This paper proposes an MB homogeneity detection method to accelerate H.264/AVC intra and inter coding. All the luminance values of pixels in an MB are taken to calculate their entropy feature, which is defined as MB's spatial homogeneity. Based on homogeneity judgment, 16 X 16 or 4 X 4 block size is appropriately selected for intra coding
Meanwhile, either the large blocks in {16 X 16, 16 X 8, 8 X 16} or sub-blocks in {8 X 8, 8 X 4, 4 X 8, 4 X 4} are chosen for inter coding. Especially, a cost function is defined to select near optimal threshold for selecting optimal block size. Proposed methods are verified on a wide range of video sequences with different spatial-/motion characteristics. Sufficient simulations demonstrate that consistent encoding gain is achieved for all videos with different motion and spatial features. Encoding complexity for intra coding alone can be reduced by 31%- 34% and time savings for inter mode decision is 43.7%-58.7%, both with negligible loss in bitrate and PSNR. © 2010, The Institute of Image Electronics Engineers of Japan. All rights reserved.

Transmission of compressed video over error prone channels may result in packet losses or errors, which can significantly degrade the image quality. Such degradation even becomes worse in 1Seg video broadcasting, which is widely used in Japan and Brazil for mobile phone TV service recently, where errors are drastically increased and lost areas are contiguous. Therefore the errors in earlier concealed MBs (macro blocks) may propagate to the MBs later to be concealed inside the same frame (spatial domain). The error concealment (EC) is used to recover the lost data by the redundancy in videos. Aiming at spatial error propagation (SEP) reduction, this paper proposes a SEP reduction based EC (SEPEC). In SEPEC, besides the mismatch distortion in current MB, the potential propagated mismatch distortion in the following to be concealed MBs is also minimized. Also, 2 extensions of SEPEC, that SEPEC with refined search and SEPEC with multiple layer match are discussed. Compared with previous work, the experiments show SEPEC achieves much better performance of video recovery and excellent trade-off between quality and computation in 1Seg broadcasting in terms of computation cost. ©2010 IEEE.

In this paper, an encoding system is proposed to further reduce the power consumption in parallel video encoding based on difference detection and Hilbert transform based workload estimation (HTWE). The proposed parallel encoding system provides an average of 40% computational complexity reduction for parallel encoding without objective performance loss. For the multi-core platform with frequency and voltage scalability, up to 78% of power reduction can be achieved. ©2010 IEEE.

In this paper, firstly, we describe a new feature for fast and accurate face detection. The feature is called Separate Haar Feature. Secondly, we describe a multi-mode detection algorithm to improve the detection rate. There are three key contributions. The first is "Separate Haar Feature", which adds a don't-care area between the rectangles of Haar Feature. We can get some more efficient features by this algorithm. The second is the algorithm for selecting the best width for this don't-care area and the False Alarm Rate for each stage in "Learning". This algorithm for width selecting is proposed to reduce the total number of learning features for reducing the memory used. And we use a smaller false alarm rate for each stage and less number of stages training the detector to improve the hit rate within the same detection time consuming. Finally, we proposed a multi-mode detection algorithm in cascade detection process to improve the detection rate. © 2010 IEEE.

As a global interconnection, bus is critical for chip performance in deep submicron technology. Reducing bus routing vias will facilitate the lithography and give bus routing a higher yield and also a higher performance. In this paper, we present a floorplan revising method to minimize the number of reducible routing vias with a controllable loss on the chip area and wirelength. Therefore, it is easy to make a proper tradeoff between via reduction and revising loss. Experiments show that our method reaches a 96.2% and 93.5% reduction of routing vias, which is close to 100% and runs fast. Besides, our revising is friendly to all third-party floorplanners, which can be applied to any existing floorplans to reduce vias. It is also scalable to larger benchmarks. © 2010 ACM.

H.264/AVC introduces the variable block size motion estimation (VBSME), which brings huge computational cost of the encoder. In this paper, a novel fast inter mode decision algorithm for H.264/AVC has been proposed. The proposed algorithm evaluates the modes based on residual feature. The residual is obtained after the motion search of P16 X 16 mode or P8 X 8 mode. And then basing on the extracted residual feature, the complexity and similarity are evaluated for the inter mode decision. According to the evaluation of similarity between different sub-blocks and the complexity of each sub-block, the most possible inter modes for current block is chosen to be conducted. In the worst case, the proposed whole scheme of inter mode decision algorithm only conducts 4 modes, which is much more effective than conducting all the 8 modes in conventional approach. The simulation results show that, comparing to JM14.1, on average, the proposed algorithm achieves 57.98% and 55.72% time-saving on CIF and 720p sequences respectively, with equivalent 0.219 dB PSNR drop and 5.55% bit rate increase for CIF and 0.107dB PSNR drop and 3.53% bit rate increase for 720p. Compared to existing inter mode decision algorithm, proposed algorithm achieves 10.68% and 13.26% timing-reduction on CIF and 720p sequences respectively with less performance loss. © 2010, The Institute of Image Electronics Engineers of Japan. All rights reserved.

The variable block sizes for intra and inter coding in H.264/AVC achieves significant coding gain compared with coding a macroblock (MB) with fixed size. However, extremely heavy computational burden is required when Rate Distortion Optimization (RDO) process runs in brutal force searching manner for selecting the optimal coding block. This paper proposes an MB homogeneity detection method to accelerate H.264/AVC intra and inter coding. All the luminance values of pixels in an MB are taken to calculate their entropy feature, which is defined as MB's spatial homogeneity. Based on homogeneity judgment, 16 X 16 or 4 X 4 block size is appropriately selected for intra coding
Meanwhile, either the large blocks in {16 X 16, 16 X 8, 8 X 16} or sub-blocks in {8 X 8, 8 X 4, 4 X 8, 4 X 4} are chosen for inter coding. Especially, a cost function is defined to select near optimal threshold for selecting optimal block size. Proposed methods are verified on a wide range of video sequences with different spatial-/motion characteristics. Sufficient simulations demonstrate that consistent encoding gain is achieved for all videos with different motion and spatial features. Encoding complexity for intra coding alone can be reduced by 31%- 34% and time savings for inter mode decision is 43.7%-58.7%, both with negligible loss in bitrate and PSNR. © 2010, The Institute of Image Electronics Engineers of Japan. All rights reserved.

Transmission of compressed video over error prone channels may result in packet losses or errors, which can significantly degrade the image quality. Such degradation even becomes worse in 1Seg video broadcasting, which is widely used in Japan and Brazil for mobile phone TV service recently, where errors are drastically increased and lost areas are contiguous. Therefore the errors in earlier concealed MBs (macro blocks) may propagate to the MBs later to be concealed inside the same frame (spatial domain). The error concealment (EC) is used to recover the lost data by the redundancy in videos. Aiming at spatial error propagation (SEP) reduction, this paper proposes a SEP reduction based EC (SEPEC). In SEPEC, besides the mismatch distortion in current MB, the potential propagated mismatch distortion in the following to be concealed MBs is also minimized. Also, 2 extensions of SEPEC, that SEPEC with refined search and SEPEC with multiple layer match are discussed. Compared with previous work, the experiments show SEPEC achieves much better performance of video recovery and excellent trade-off between quality and computation in 1Seg broadcasting in terms of computation cost. ©2010 IEEE.

In this paper, an encoding system is proposed to further reduce the power consumption in parallel video encoding based on difference detection and Hilbert transform based workload estimation (HTWE). The proposed parallel encoding system provides an average of 40% computational complexity reduction for parallel encoding without objective performance loss. For the multi-core platform with frequency and voltage scalability, up to 78% of power reduction can be achieved. ©2010 IEEE.

In this paper, a region of interest (ROI) oriented partial H.264/AVC decoding scheme is proposed to enable low-power and low-complexity HD video content display on low resolution screens. The proposed scheme is a macroblock level based partial decoding, which employs several strategies to maintain the good video quality in the ROI The simulation results show that, the proposed scheme provides better visual quality, and very limited PSNR loss quality in the ROI, but it achieves much lower computational complexity and power consumption. On average, it reduces the decoding time by about 40.66% with the PSNR loss up to O.77dB in the ROI among the test cases. The partially decoded sequences maintain more details in the ROI, thus provide better user experience. This proposal is especially useful for the portable devices. © 2010 IEEE.

Depth map coding is a new topic in multiview video coding (MVC) following the development of depth-image-based rendering (DIBR). Since depth map is monochromatic and has less texture than color map, fast algorithm is necessary and possible to reduce the computation burden of the encoder. This paper proposed difference detection based early mode termination strategy. The difference detection (DD) algorithms are categorized to reconstructed frame based (RDD) and original frame based (ODD). A simplified ODD (sODD) strategy is also proposed. Early mode termination based on these three DD algorithms are implemented and evaluated in the reference software of Joint Multiview Video Coding (JMVC) version 8.0 respectively. Simulation results indicate that RDD based one has no performance lost and reduce 25% runtime on average. ODD and sODD based ones can save 54.3% and 43.6% runtime respectively and have an acceptable R-D performance lost. © 2010 IEEE.

As a global interconnection, bus is critical for chip performance in deep submicron technology. Reducing bus routing vias will facilitate the lithography and give bus routing a higher yield and also a higher performance. In this paper, we present a floorplan revising method to minimize the number of reducible routing vias with a controllable loss on the chip area and wirelength. Therefore, it is easy to make a proper tradeoff between via reduction and revising loss. Experiments show that our method reaches a 96.2% and 93.5% reduction of routing vias, which is close to 100% and runs fast. Besides, our revising is friendly to all third-party floorplanners, which can be applied to any existing floorplans to reduce vias. It is also scalable to larger benchmarks. © 2010 ACM.

In surveillance systems, ultra low bit rate video coding is necessary to reduce the storage and bandwidth consumption, especially for high definition video coding. This paper proposes a new architecture to further reduce the bit rate than H.264/AVC. The algorithm of detecting the difference of the adjacent frames and skipping the static frames in the original video is proposed. Moreover, this paper presents an adaptive coding method to code the active regions with traditional slices and background with the proposed S slice respectively. The S slice contains less syntax elements than the conventional P slice. The simulation results demonstrate that great bit reduction is achieved by these two schemes. © 2010 IEEE.

As one of the effective side-channel attacks that threaten the security of cryptographic devices, Correlation Power Analysis (CPA) attacks exploit the linear relation between the known power consumption and the predicted power consumption of cryptographic devices to recover keys. A robust cryptographic algorithm should endure both the cryptanalysis from software and hardware implementations. Researches have focused on the security examination of AES (Advanced Encryption Standard). In this paper, we present the CPA attack with the Switching Distance model against an AES implementation on ASIC. Compared with the leakage model of Hamming Distance, the power traces of recovering keys have been decreased by as much as 25%. These should cause more attention of security experts. © 2010 IEEE.

Layered LDPC decoding algorithm is known to achieve high Bit Error Rate (BER) performance and high throughput for LDPC decoders. However, for ISDB-S2 (Integrated Services Digital Broadcasting via Satellite - Second Generation) LDPC decoder, applying layered algorithm directly will result in data conflict problem. In this paper, a novel selective recalculation method is proposed to solve the data conflict problem. It determines the inaccurately calculated values based on a recalculation decision rule, and correct them accordingly. By applying this selective recalculation method, the layered algorithm can achieve conflict free BER performance. Simulation results demonstrate that the proposed method can achieve 0.1dB gain for the code with most conflicts in ISDB-S2, under the same BER performance compared to the previous strategy to solve data conflict problem. ©2010 IEEE.

With development of multi-core system, parallel encoder with fast algorithm is widely used to improve video encoding speed. In this paper, a dynamic slice-resize algorithm is proposed to balance workload and increase encoding speed for slice-level parallel encoder. This algorithm retrieves encoding workload from previous encoded frames and dynamically changes the slice size for the following frames to balance the encoding workload among slices. By applying the proposed algorithm, an average of 21 % encoding speed improvement can be achieved for parallel video encoder without loss in objective performance. © 2010 IEEE.

As one of the effective side-channel attacks that threaten the security of cryptographic devices, Correlation Power Analysis (CPA) attacks exploit the linear relation between the known power consumption and the predicted power consumption of cryptographic devices to recover keys. A robust cryptographic algorithm should endure both the cryptanalysis from software and hardware implementations. Researches have focused on the security examination of AES (Advanced Encryption Standard). In this paper, we present the CPA attack with the Switching Distance model against an AES implementation on ASIC. Compared with the leakage model of Hamming Distance, the power traces of recovering keys have been decreased by as much as 25%. These should cause more attention of security experts. © 2010 IEEE.

In this paper we propose a synthesizable LDPC decoder IP core for WiMax and WiFi applications. Two new techniques are applied in the proposed decoder to improve the decoding performance. Firstly, a high parallelism permutation network (PN) is proposed to perform the circulant shift according to the parity check matrix (PCM) defined in WiMax and WiFi standards. By using the proposed PN, at most, four independent code frames with small code length are decoded concurrently, which largely improves the decoding throughput (2-4 times). Secondly, a fast early stopping criterion specialized for WiMax and WiFi LDPC code is proposed to reduce the average iteration number. Unlike the early works, by utilizing our proposed stopping criterion, the decoding will be stopped when all the information bits of a code frame are corrected even if there are still some errors in redundant part. Experiment results show that, it can reduce up to 20% iteration numbers compared to popular used stopping criterion. © 2010 Information Processing Society of Japan.

H.264/AVC achieves low bit-rate video stream which meets the requirement of video communication. The problem of H.264/AVC is the large computation burden. Thus fast algorithm should be adopted to reduce the computation burden to meet the limited power of the mobile device. This paper uses region-of-interest (ROI) detector to locate an “important” region and apply unequally coding in the encoder engine according ROI. Several coding parameters including quantization parameter (QP), candidates for mode decision, number of referencing frames and the search range of motion estimation are adaptively adjusted at the macroblock (MB) level. This design is decoding-friendly. Experimental result shows a large amount computation is saved and the subjective visual quality is kept or even improved. © 2010, The Institute of Image Electronics Engineers of Japan. All rights reserved.

Layered LDPC decoding algorithm is known to achieve high Bit Error Rate (BER) performance and high throughput for LDPC decoders. However, for ISDB-S2 (Integrated Services Digital Broadcasting via Satellite - Second Generation) LDPC decoder, applying layered algorithm directly will result in data conflict problem. In this paper, a novel selective recalculation method is proposed to solve the data conflict problem. It determines the inaccurately calculated values based on a recalculation decision rule, and correct them accordingly. By applying this selective recalculation method, the layered algorithm can achieve conflict free BER performance. Simulation results demonstrate that the proposed method can achieve 0.1dB gain for the code with most conflicts in ISDB-S2, under the same BER performance compared to the previous strategy to solve data conflict problem. ©2010 IEEE.

High-definition (HD) and super-high-definition (SHD) videos become more and more popular for various video applications, including video capture and playback on portable devices. Because of the resolution mismatch between HD/SHD video and the low resolution screen of portable devices, the video is fully decoded and then sown-sampled for the display, which causes a waste of both computational power and memory bandwidth. In this paper, a user-defined region of interest (ROI) oriented partial decoding scheme for H.264/AVC is proposed to achieve low-power and good subjective visual quality of decoding/display for viewing resolution adaptation. The proposed partial decoding scheme works basing on the adaptive ROI tracking. The motion-vector (MV) adaptation is adopted for maintaining the visual quality in ROI. The simulation results show that, the displayed partial decoded sequence provides better subjective visual quality, more details, and very small PSNR drop in ROI compare to original one. And the partial decoder achieves about 48.34% decoding time reduction averagely, which means lower computational complexity and power consumption. The proposal is especially useful for displaying HD video on the portable devices in which the battery life is a crucial factor. ©2010 IEEE.

With development of multi-core system, parallel encoder with fast algorithm is widely used to improve video encoding speed. In this paper, a dynamic slice-resize algorithm is proposed to balance workload and increase encoding speed for slice-level parallel encoder. This algorithm retrieves encoding workload from previous encoded frames and dynamically changes the slice size for the following frames to balance the encoding workload among slices. By applying the proposed algorithm, an average of 21 % encoding speed improvement can be achieved for parallel video encoder without loss in objective performance. © 2010 IEEE.

We revisit voltage partitioning problem when the mapped voltages of functional units are predetermined. If energy consumption is estimated by formulation E=CV2, a published work claimed this problem was NP-hard. We clarify that it is polynomial solvable, then propose an optimal algorithm, its time complexity is O(nk+k2d) which is best so far, where n, k, and d are respectively the numbers of functional units, available supply voltages, and voltages employed in the final design. In reality, considering leakage power the energy-voltage curve is not simply monotonically increasing and there is still no optimal polynomal polynomial time algorithm. However, under the assumption that energy-voltage curve is quasiconvex, which is also a good approximation to actual situation, the optimal solution can be got in time O(nk2). Experimental results show that our algorithms are more efficient than previous works. © 2010 ACM.

This paper presents a novel early termination scheme for layered LDPC decoder. By solving the bit error rate (BER) performance degradation which will occur when other early termination schemes are applied in layered LDPC decoder, the proposed method achieves very fast termination speed without BER performance loss. It is the best solution for BER performance-aware layered LDPC decoders, such as satellite video broadcasting applications. ©2010 IEEE.

High-definition (HD) and super-high-definition (SHD) videos become more and more popular for various video applications, including video capture and playback on portable devices. Because of the resolution mismatch between HD/SHD video and the low resolution screen of portable devices, the video is fully decoded and then sown-sampled for the display, which causes a waste of both computational power and memory bandwidth. In this paper, a user-defined region of interest (ROI) oriented partial decoding scheme for H.264/AVC is proposed to achieve low-power and good subjective visual quality of decoding/display for viewing resolution adaptation. The proposed partial decoding scheme works basing on the adaptive ROI tracking. The motion-vector (MV) adaptation is adopted for maintaining the visual quality in ROI. The simulation results show that, the displayed partial decoded sequence provides better subjective visual quality, more details, and very small PSNR drop in ROI compare to original one. And the partial decoder achieves about 48.34% decoding time reduction averagely, which means lower computational complexity and power consumption. The proposal is especially useful for displaying HD video on the portable devices in which the battery life is a crucial factor. ©2010 IEEE.

We revisit voltage partitioning problem when the mapped voltages of functional units are predetermined. If energy consumption is estimated by formulation E=CV2, a published work claimed this problem was NP-hard. We clarify that it is polynomial solvable, then propose an optimal algorithm, its time complexity is O(nk+k2d) which is best so far, where n, k, and d are respectively the numbers of functional units, available supply voltages, and voltages employed in the final design. In reality, considering leakage power the energy-voltage curve is not simply monotonically increasing and there is still no optimal polynomal polynomial time algorithm. However, under the assumption that energy-voltage curve is quasiconvex, which is also a good approximation to actual situation, the optimal solution can be got in time O(nk2). Experimental results show that our algorithms are more efficient than previous works. © 2010 ACM.

This paper presents a novel early termination scheme for layered LDPC decoder. By solving the bit error rate (BER) performance degradation which will occur when other early termination schemes are applied in layered LDPC decoder, the proposed method achieves very fast termination speed without BER performance loss. It is the best solution for BER performance-aware layered LDPC decoders, such as satellite video broadcasting applications. ©2010 IEEE.

In this paper, firstly, we describe a new feature for fast and accurate face detection. The feature is called Separate Haar Feature. Secondly, we describe a multi-mode detection algorithm to improve the detection rate. There are three key contributions. The first is "Separate Haar Feature", which adds a don't-care area between the rectangles of Haar Feature. We can get some more efficient features by this algorithm. The second is the algorithm for selecting the best width for this don't-care area and the False Alarm Rate for each stage in "Learning". This algorithm for width selecting is proposed to reduce the total number of learning features for reducing the memory used. And we use a smaller false alarm rate for each stage and less number of stages training the detector to improve the hit rate within the same detection time consuming. Finally, we proposed a multi-mode detection algorithm in cascade detection process to improve the detection rate. © 2010 IEEE.

Low Power Design has become a significant requirement when the CMOS technology entered the nanometer era. Multiple-Supply Voltage (MSV) is a popular and effective method for both dynamic and static power reduction while maintaining performance. Level shifters may cause area and Interconnect Length Overhead (ILO), and should be considered at both floorplanning and post-floorplanning stages. In this paper, we propose a two phases algorithm framework, called VLSAF, to solve voltage and level shifter assignment problem. At floorplanning phase, we use a convex cost network flow algorithm to assign voltage and a minimum cost flow algorithm to handle level-shifter assignment. At post-floorplanning phase, a heuristic method is adopted to redistribute white spaces and calculate the positions and shapes of level shifters. The experimental results show VLSAF is effective.

Low Power Design has become a significant requirement when the CMOS technology entered the nanometer era. Multiple-Supply Voltage (MSV) is a popular and effective method for both dynamic and static power reduction while maintaining performance. Level shifters may cause area and Interconnect Length Overhead (ILO), and should be considered at both floorplanning and post-floorplanning stages. In this paper, we propose a two phases algorithm framework, called VLSAF, to solve voltage and level shifter assignment problem. At floorplanning phase, we use a convex cost network flow algorithm to assign voltage and a minimum cost flow algorithm to handle level-shifter assignment. At post-floorplanning phase, a heuristic method is adopted to redistribute white spaces and calculate the positions and shapes of level shifters. The experimental results show VLSAF is effective.

In this paper, a highly parallel deblocking filter architecture for H.264/AVC is proposed to process one macroblock in 48 clock cycles and give real-time support to QFHD@60 fps sequences at less than 100 MHz. 4 edge filters organized in 2 groups for simultaneously processing vertical and horizontal edges are applied in this architecture to enhance its throughput. While parallelism increases, pipeline hazards arise owing to the latency of edge filters and data dependency of deblocking algorithm. To solve this problem, a zig-zag processing schedule is proposed to eliminate the pipeline bubbles. Data path of the architecture is then derived according to the processing schedule and optimized through data flow merging, so as to minimize the cost of logic and internal buffer. Meanwhile, the architecture's data input rate is designed to be identical to its throughput, while the transmission order of input data can also match the zig-zag processing schedule. Therefore no intercommunication buffer is required between the deblocking filter and its previous component for speed matching or data reordering. As a result, only one 24x64 two-port SRAM as internal buffer is required in this design. When synthesized with SMIC 130 not process, the architecture costs a gate count of 30.2 k, which is competitive considering its high performance.

In this paper, a highly parallel deblocking filter architecture for H.264/AVC is proposed to process one macroblock in 48 clock cycles and give real-time support to QFHD@60 fps sequences at less than 100 MHz. 4 edge filters organized in 2 groups for simultaneously processing vertical and horizontal edges are applied in this architecture to enhance its throughput. While parallelism increases, pipeline hazards arise owing to the latency of edge filters and data dependency of deblocking algorithm. To solve this problem, a zig-zag processing schedule is proposed to eliminate the pipeline bubbles. Data path of the architecture is then derived according to the processing schedule and optimized through data flow merging, so as to minimize the cost of logic and internal buffer. Meanwhile, the architecture's data input rate is designed to be identical to its throughput, while the transmission order of input data can also match the zig-zag processing schedule. Therefore no intercommunication buffer is required between the deblocking filter and its previous component for speed matching or data reordering. As a result, only one 24x64 two-port SRAM as internal buffer is required in this design. When synthesized with SMIC 130 not process, the architecture costs a gate count of 30.2 k, which is competitive considering its high performance.

In the latest video coding frameworks, efficiency of motion vector (MV) coding is becoming increasingly important because of the growing bit rate portion of motion information. However, neither the conventional median predictor, nor the newer schemes such as the minimum bit rate prediction scheme and the hybrid scheme, can effectively eliminate the local redundancy of motion vectors. In this paper, we present the prioritized reference decision scheme for efficient motion vector coding, based on the H.264/AVC framework. This scheme makes use of a boolean indicator to specify whether the median predictor is to be used for the current MV or not. If not, the median prediction is considered not suitable for the current MV, and this information is used for refining the possible space of a group of reference MVs including 4 neighboring MVs and the zero MV. This group of MVs is organized to be a prioritized list so that the reference MV with highest priority is to be selected as the prediction value. Furthermore, the boolean indicators are coded into the modified code words of nib-type and sub_mb_type, so as to reduce the overhead. By applying the proposed scheme, the structure and the applicability problems with the state-of-the-art MBP scheme have been overcome. Experimental result shows that the proposed scheme achieves a considerable reduction of bits for MVDs. compared with the conventional median prediction algorithm. It also achieves a better and much stabler performance than MBP-based MV coding.

Motion estimation (ME) is a computation and data intensive module in video coding system. The search window reuse methods play a critical role in bandwidth reduction by exploiting the data locality in video coding system. In this paper, a search window reuse method (Level C+) is proposed for MPEG-2 to H.264/AVC transcoding. The proposed method is designed for ultra-low bandwidth application, while the on-chip memory is not a main constraining factor. By loading search window for the motion estimation unit (MEU) and applying motion vector clipping processing, each MB in MEU can utilize both horizontal and vertical search reuse. A very low bandwidth level (R-alpha < 2) can be achieved with an acceptable on-chip memory.

A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30 fps is proposed in this paper. On the basis of the specifications and algorithm optimizations, the dedicated hardware engines and one 32-bit Media embedded Processor (MeP) equipped with hardware extensions are mapped into the three-stage macroblock pipelining system architecture. This paper describes the design considerations for chief components, including high throughput integer motion estimation, data reusing fractional motion estimation, and hardware friendly mode reduction for intra prediction. The 11.5 Gbps 64 Mb System-in-Silicon DRAM is embedded to alleviate the external memory bandwidth. Using TSMC one-poly six-metal 0.18 mu m CMOS technology, the prototype chip is implemented with 1140 k logic gates and 108.3 KB internal SRAM. The SoC core occupies 27.1 mm(2) die area and consumes 1.41 W at 200 MHz execution speed in typical work conditions.

A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30 fps is proposed in this paper. On the basis of the specifications and algorithm optimizations, the dedicated hardware engines and one 32-bit Media embedded Processor (MeP) equipped with hardware extensions are mapped into the three-stage macroblock pipelining system architecture. This paper describes the design considerations for chief components, including high throughput integer motion estimation, data reusing fractional motion estimation, and hardware friendly mode reduction for intra prediction. The 11.5 Gbps 64 Mb System-in-Silicon DRAM is embedded to alleviate the external memory bandwidth. Using TSMC one-poly six-metal 0.18 mu m CMOS technology, the prototype chip is implemented with 1140 k logic gates and 108.3 KB internal SRAM. The SoC core occupies 27.1 mm(2) die area and consumes 1.41 W at 200 MHz execution speed in typical work conditions.

As technology scales, low power design has become a significant requirement for soc designers. Among the existing techniques, Multiple-Supply Voltage (MSV) is a popular and effective method to reduce both dynamic and static power. Besides, level shifters consume area and delay, and should be considered during floorplanning. In this paper, we present a new floorplanning system, called MVLSAF, to solve multi-voltage and level shifter assignment problem. We use a convex cost network flow algorithm to assign arbitrary number of legal working voltages and a minimum cost flow algorithm to handle level-shifter assignment. The experimental results show MVLSAF is effective. ©2009 IEEE.

H.264/AVC introduces the variable block size macroblock mode for motion estimation, which brings huge computational cost. In this paper, a novel fast inter macroblock mode decision algorithm for H.264/AVC has been proposed. The proposed algorithm evaluates the modes based on residual information. The residual is obtained after the motion search of P16x16 mode or P8x8 mode. Then the characteristic of the blocks are extracted by the defined conversion, and the complexity and similarity are calculated for the decision the next conducting mode. The mode with the minimal R-D cost is chosen as the final mode. The simulation results show that, the proposed algorithm achieves 65.95% time-saving, which is 1.5 times than that of other algorithm with less PSNR loss and bit rate increase. ©2009 IEEE.

Motion estimation (ME) is a computation and data intensive module in video coding system. The search window reuse methods play a critical role in bandwidth reduction by exploiting the data locality in video coding system. In this paper, a search window reuse method (Level C+) is proposed for MPEG-2 to H.264/AVC transcoding. The proposed method is designed for ultra-low bandwidth application, while the on-chip memory is not a main constraining factor. By loading search window for the motion estimation unit (MEU) and applying motion vector clipping processing, each MB in MEU can utilize both horizontal and vertical search reuse. A very low bandwidth level (Rα &lt
2) can be achieved with an acceptable on-chip memory. Copyright © 2009 The Institute of Electronics, Information and Communication Engineers.

For many applications like video surveillance and digital cinema, it is desirable to encode video content with constant video quality. However, although constant quantization parameter is used in video encoder, quality fluctuation in macroblock level is still very large and standard deviation of PSNR is typically about 1.8dB. Since distortion is introduced in the process of quantization of DCT coefficients, we propose a new DCT-domain distortion model which utilizes the truncated tailing bits in quantization to estimate distortion in macroblock level, and QP of each block is determined by the estimated PSNR. Experimental results show that our proposed model can accurately estimate distortion of each MB before implementing quantization and the corresponding RMSE is only about 0.3dB (less than 1% of the actual value). Compared with previous works, our proposed algorithm can achieve 0.57dB enhancement in quality stabilization.

In this paper, we propose a partially-parallel irregular LDPC decoder for IEEE 802.11n standard targeting high throughput applications. The proposed decoder has several merits: (i) The decoder is designed based on a novel deltavalue based message passing algorithm which facilitates the decoding throughput by redundant computation removal. (ii) Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message-passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder can achieve 8 times increasement in throughput, reaching 418 Mbps at the frequency of 200 MHz. © 2009 Information Processing Society of Japan.

An approach to detect moving and standing human from video is proposed in this paper. Human detection from videos is a difficult problem because of motion of human, camera and background. In order to detect moving human, the dense optical flow is calculated by two consecutive frames, to represent the motion of human. Motion based feature is extracted from optical flow field. It not only represents the global motion caused by the boundary of human body, but also contains local motion caused by the limbs. Motion based feature is combined with histogram of template feature, which is designed to detect standing human, as final feature for detection. Experiment on CAS dataset shows that this feature has more discriminative ability than other motion based feature. Besides, this feature is easier for hardware acceleration, which makes it suitable for real time application. ©2009 IEEE.

H.264/AVC introduces the variable block size macroblock mode for motion estimation, which brings huge computational cost. In this paper, a novel fast inter macroblock mode decision algorithm for H.264/AVC has been proposed. The proposed algorithm evaluates the modes based on residual information. The residual is obtained after the motion search of P16x16 mode or P8x8 mode. Then the characteristic of the blocks are extracted by the defined conversion, and the complexity and similarity are calculated for the decision the next conducting mode. The mode with the minimal R-D cost is chosen as the final mode. The simulation results show that, the proposed algorithm achieves 65.95% time-saving, which is 1.5 times than that of other algorithm with less PSNR loss and bit rate increase. ©2009 IEEE.

An approach to detect moving and standing human from video is proposed in this paper. Human detection from videos is a difficult problem because of motion of human, camera and background. In order to detect moving human, the dense optical flow is calculated by two consecutive frames, to represent the motion of human. Motion based feature is extracted from optical flow field. It not only represents the global motion caused by the boundary of human body, but also contains local motion caused by the limbs. Motion based feature is combined with histogram of template feature, which is designed to detect standing human, as final feature for detection. Experiment on CAS dataset shows that this feature has more discriminative ability than other motion based feature. Besides, this feature is easier for hardware acceleration, which makes it suitable for real time application. ©2009 IEEE.

For many applications like video surveillance and digital cinema, it is desirable to encode video content with constant video quality. However, although constant quantization parameter is used in video encoder, quality fluctuation in macroblock level is still very large and standard deviation of PSNR is typically about 1.8dB. Since distortion is introduced in the process of quantization of DCT coefficients, we propose a new DCT-domain distortion model which utilizes the truncated tailing bits in quantization to estimate distortion in macroblock level, and QP of each block is determined by the estimated PSNR. Experimental results show that our proposed model can accurately estimate distortion of each MB before implementing quantization and the corresponding RMSE is only about 0.3dB (less than 1% of the actual value). Compared with previous works, our proposed algorithm can achieve 0.57dB enhancement in quality stabilization.

In the latest video coding frameworks, efficiency of motion vector (MV) coding is becoming increasingly important because of the growing bit rate portion of motion information. However, neither the conventional median predictor, nor the newer schemes such as the minimum bit rate prediction scheme and the hybrid scheme, can effectively eliminate the local redundancy of motion vectors. In this paper, we present the prioritized reference decision scheme for efficient motion vector coding, based on the H.264/AVC framework. This scheme makes use of a boolean indicator to specify whether the median predictor is to be used for the current MV or not. If not, the median prediction is considered not suitable for the current MV, and this information is used for refining the possible space of a group of reference MVs including 4 neighboring MVs and the zero MV. This group of MVs is organized to be a prioritized list so that the reference MV with highest priority is to be selected as the prediction value. Furthermore, the boolean indicators are coded into the modified code words of mb-type and sub-mb-type, so as to reduce the overhead. By applying the proposed scheme, the structure and the applicability problems with the state-of-the-art MBP scheme have been overcome. Experimental result shows that the proposed scheme achieves a considerable reduction of bits for MVDs, compared with the conventional median prediction algorithm. It also achieves a better and much stabler performance than MBP-based MV coding. Copyright © 2009 The Institute of Electronics, Information and Communication Engineers.

In this paper, we propose a partially-parallel irregular LDPC decoder for IEEE 802.11n standard targeting high throughput applications. The proposed decoder has several merits: (i) The decoder is designed based on a novel deltavalue based message passing algorithm which facilitates the decoding throughput by redundant computation removal. (ii) Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message-passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder can achieve 8 times increasement in throughput, reaching 418 Mbps at the frequency of 200 MHz. © 2009 Information Processing Society of Japan.

The inter motion estimation and intra motion estimation are most important and widely used prediction techniques in various kinds of video standards. However, inter and intra predictions are rarely considered together since the contents used for reference by these 2 predictions are different. As most of the previous works focus on either inter or intra or reluctantly combining inter/intra together, this paper proposes a fast mode decision algorithms that considers both inter and intra organically, by taking advantage of that both inter and intra have hierarchical partition sizes. Moreover, in contrast to traditional mode decision algorithms that either enable or disable one specific mode, this paper proposes a fuzzy variable called "effort" which can adaptively adjust the computation paid to each inter or intra mode. This "effort" is defined as a fractional value ranges from 0 to 1. In this paper, firstly the correlation between partition-size selection and QP is related, then by describing how to calculate and implement this "effort" the proposed algorithm is present. Experimental result shows that about 42 67% computational complexity can be saved by adopting the proposed fast mode decision algorithm. ©2009 IEEE.

In this paper, a high speed deblocking filter architecture for H.264/AVC is proposed to process one macroblock in 48 clock cycles and give real-time support to QFHD (3840x2160)@60fps sequences at less than 100MHz. 4 edge filters organized in 2 groups for simultaneously processing vertical and horizontal edges are applied in this architecture to enhance its throughput. While parallelism increases, pipeline hazards arise owing to the latency of edge filters and data dependency of deblocking algorithm. To solve this problem, a zig-zag processing schedule is proposed to eliminate the pipeline bubbles. Data path of the architecture is then derived according to the processing schedule and optimized through data flow merging, so as to minimize the cost of logic and internal buffer. Meanwhile, the architecture's data input rate is designed to be identical to its throughput, while the transmission order of input data can also match the zig-zag processing schedule. Therefore no intercommunication buffer is required between the deblocking filter and its previous component for speed matching or data reordering. As a result, only one 24x64 two-port SRAM as internal buffer is required in this design. When synthesized with SMIC 130nm process, the architecture costs a gate count of 30.2k, which is competitive considering its high performance. ©2009 IEEE.

In this paper, VLSI architecture of a joint parameter decoder is proposed to realize the calculation of motion vector (MV), intra prediction mode (IPM) and boundary strength (BS) for ultra high definition H.264/AVC applications. To achieve an efficient design, compact data storage formats are proposed for SRAM size saving and DRAM bandwidth reduction. Moreover, a 64-cycle-per-MB pipeline with simplified control modes is designed to enhance the throughput. Experimental results show the proposed architecture is capable of real-time QFHD@60fps decoding at less than 133MHz, with 26.7k logic gates and 3.6kB SRAM. ©2009 IEEE.

In this paper, we propose a partially-parallel irregular LDPC decoder based on IEEE 802.1 In standard targeting high throughput and small area applications. The design is based on a novel sum-delta message passing algorithm characterized as follows: (i) Decoding throughput is greatly improved by utilizing the difference value between the updated and the original value to remove redundant computations. (H) Registers and memory are optimized to store only the frequently used messages to decrease the hardware cost. (iii) Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed lip the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200 MHz, with 11% area reduction. The synthesis result also demonstrates the competitiveness to the fully-parallel regular LDPC decoders in terms of the tradeoff between throughput, area and power.

In this paper, we propose a partially-parallel irregular LDPC decoder based on IEEE 802.1 In standard targeting high throughput and small area applications. The design is based on a novel sum-delta message passing algorithm characterized as follows: (i) Decoding throughput is greatly improved by utilizing the difference value between the updated and the original value to remove redundant computations. (H) Registers and memory are optimized to store only the frequently used messages to decrease the hardware cost. (iii) Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed lip the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200 MHz, with 11% area reduction. The synthesis result also demonstrates the competitiveness to the fully-parallel regular LDPC decoders in terms of the tradeoff between throughput, area and power.

Transmission of compressed video over error prone channels may result in packet losses or errors, which can significantly degrade the image quality. Therefore an error concealment scheme is applied at the video receiver side to mask the damaged video. Considering there are 3 types of MBs (Macro Blocks) in natural video frame, i.e., Textural MB. Edged MB, and Smooth MB, this paper proposes an adaptive spatial error concealment which can choose 3 different methods for these 3 different MBs. For criteria of choosing appropriate method, 2 factors are taken into consideration. Firstly, standard deviation of our proposed edge statistical model is exploited. Secondly, some new features of latest video compression standard H.264/AVC. i.e.. intra prediction mode is also considered for criterion formulation. Compared with previous works. which are only based on deterministic measurement, proposed method achieves the best image recovery. Subjective and objective image quality evaluations in experiments confirmed this.

Transmission of compressed video over error prone channels may result in packet losses or errors, which can significantly degrade the image quality. Therefore an error concealment scheme is applied at the video receiver side to mask the damaged video. Considering there are 3 types of MBs (Macro Blocks) in natural video frame, i.e., Textural MB. Edged MB, and Smooth MB, this paper proposes an adaptive spatial error concealment which can choose 3 different methods for these 3 different MBs. For criteria of choosing appropriate method, 2 factors are taken into consideration. Firstly, standard deviation of our proposed edge statistical model is exploited. Secondly, some new features of latest video compression standard H.264/AVC. i.e.. intra prediction mode is also considered for criterion formulation. Compared with previous works. which are only based on deterministic measurement, proposed method achieves the best image recovery. Subjective and objective image quality evaluations in experiments confirmed this.

In the state-of-the-art video coding standard', H.264/AVC, the encoder is allowed to search for its prediction signals among a large number of reference pictures that have been decoded and stored in the decoder to enhance its coding efficiency. Therefore, the computation complexity of the motion estimation (ME) increases linearly with the number of reference picture. Many fast multiple reference frame ME algorithms have been proposed, whose performance, however, will be considerably degraded in the hardwired encoder design due to the macroblock (MB) pipelining architecture. Considering the limitations of the traditional four-stage MB pipelining architecture, two fast multiple reference frame ME algorithms are proposed here. First, on the basis of mathematical analysis, which reveals that the efficiency of multiple reference frames will be degraded by the relative motion between the camera and the objects, for the slow-moving MB, the authors adopt the multiple reference frames but reduce their search range. On the other hand, for the fast-moving MB, the first previous reference frame is used with the full search range during the ME processing. The mutually exclusive feature between the large search range and the multiple reference frames makes the computation saving performance of the proposed algorithm insensitive to the nature of video sequence. Second, following the Hadamard transform coefficient-based all_zeros block early detection algorithm, two early termination criteria are proposed. These methods ensure the pronounced computation saving efficiency when the encoded video has strong spatial homogeneity or temporal stationarity. Experimental results show that 72.7%-93.7% computation can be saved by the proposed fast algorithms with an average of 0.0899 dB coding quality degradation. Moreover, these fast algorithms can be combined with fast block matching algorithms to further improve their speedup performance.

In the state-of-the-art video coding standard', H.264/AVC, the encoder is allowed to search for its prediction signals among a large number of reference pictures that have been decoded and stored in the decoder to enhance its coding efficiency. Therefore, the computation complexity of the motion estimation (ME) increases linearly with the number of reference picture. Many fast multiple reference frame ME algorithms have been proposed, whose performance, however, will be considerably degraded in the hardwired encoder design due to the macroblock (MB) pipelining architecture. Considering the limitations of the traditional four-stage MB pipelining architecture, two fast multiple reference frame ME algorithms are proposed here. First, on the basis of mathematical analysis, which reveals that the efficiency of multiple reference frames will be degraded by the relative motion between the camera and the objects, for the slow-moving MB, the authors adopt the multiple reference frames but reduce their search range. On the other hand, for the fast-moving MB, the first previous reference frame is used with the full search range during the ME processing. The mutually exclusive feature between the large search range and the multiple reference frames makes the computation saving performance of the proposed algorithm insensitive to the nature of video sequence. Second, following the Hadamard transform coefficient-based all_zeros block early detection algorithm, two early termination criteria are proposed. These methods ensure the pronounced computation saving efficiency when the encoded video has strong spatial homogeneity or temporal stationarity. Experimental results show that 72.7%-93.7% computation can be saved by the proposed fast algorithms with an average of 0.0899 dB coding quality degradation. Moreover, these fast algorithms can be combined with fast block matching algorithms to further improve their speedup performance.

With the increase of key length used in public cryptographic algorithms such as RSA and ECC, the speed of Montgomery multiplication becomes a bottleneck. This paper proposes a high speed design of Montgomery multiplier. Firstly, a modified scalable high-radix Montgomery algorithm is proposed to reduce critical path. Secondly, a high-radix clock-saving dataflow is proposed to support high-radix operation and one clock cycle delay in dataflow. Finally, a hardware-reused architecture is proposed to reduce the hardware cost and a parallel radix-16 design of data path is proposed to accelerate the speed. By using HHNEC 0.25 mu m standard cell library, the implementation results show that the total cost of Montgomery multiplier is 130 KGates, the clock frequency is 180 MHz and the throughput of 1024-bit RSA encryption is 352 kbps. This design is suitable to be used in high speed RSA or ECC encryption/decryption. As a scalable design, it supports any key-length encryption/decryption up to the size of OD-chip memory.

Comparing with search pattern motion estimation (ME) algorithms, adaptive search range (ASR) algorithms are more fundamental, regular and flexible. In variable block size motion estimation (VBSME), ASR algorithms can be applied whether on a whole frame (frame level), or on an entire macroblock which includes up to forty-one blocks (macroblock level), or just on a single block (block level). In the other hand, in H.264/AVC, not the motion vectors (MVs) but the motion vector differences (MVDs) are coded and the median motion vector predictors (median-MVPs) are used to place the search centers. In this sense, it can be thought that the search windows (SWs) are centered at the positions pointed by median-MVPs, the search ranges (SRs) play the role of limiting MVDs. Thus it is reasonable for considering using MVDs to predict SRs. In this paper, one of the MB level and two of the block level, at all three MVD based SR prediction algorithms are proposed. VBSME based experiments are carried out to assess the proposed algorithms. Comparisons between the proposed three algorithms and the previously proposed one given in [8] are done in terms of encoding quality and computational complexity.

Comparing with search pattern motion estimation (ME) algorithms, adaptive search range (ASR) algorithms are more fundamental, regular and flexible. In variable block size motion estimation (VBSME), ASR algorithms can be applied whether on a whole frame (frame level), or on an entire macroblock which includes up to forty-one blocks (macroblock level), or just on a single block (block level). In the other hand, in H.264/AVC, not the motion vectors (MVs) but the motion vector differences (MVDs) are coded and the median motion vector predictors (median-MVPs) are used to place the search centers. In this sense, it can be thought that the search windows (SWs) are centered at the positions pointed by median-MVPs, the search ranges (SRs) play the role of limiting MVDs. Thus it is reasonable for considering using MVDs to predict SRs. In this paper, one of the MB level and two of the block level, at all three MVD based SR prediction algorithms are proposed. VBSME based experiments are carried out to assess the proposed algorithms. Comparisons between the proposed three algorithms and the previously proposed one given in [8] are done in terms of encoding quality and computational complexity.

With the increase of key length used in public cryptographic algorithms such as RSA and ECC, the speed of Montgomery multiplication becomes a bottleneck. This paper proposes a high speed design of Montgomery multiplier. Firstly, a modified scalable high-radix Montgomery algorithm is proposed to reduce critical path. Secondly, a high-radix clock-saving dataflow is proposed to support high-radix operation and one clock cycle delay in dataflow. Finally, a hardware-reused architecture is proposed to reduce the hardware cost and a parallel radix-16 design of data path is proposed to accelerate the speed. By using HHNEC 0.25 mu m standard cell library, the implementation results show that the total cost of Montgomery multiplier is 130 KGates, the clock frequency is 180 MHz and the throughput of 1024-bit RSA encryption is 352 kbps. This design is suitable to be used in high speed RSA or ECC encryption/decryption. As a scalable design, it supports any key-length encryption/decryption up to the size of OD-chip memory.

Variable Block Size Motion Estimation (VBSME) costs a lot of computation during video coding. Search range reduction algorithm is widely used to reduce computational cost of motion estimation. Current VBSME designs are not suitable for this algorithm. This paper proposes a reconfigurable design of VBSME which can be efficiently used with search range reduction algorithm. While using proposed design, n x m reference MBs form an MB array which can be processed in parallel. n and m can be configured according to the new search range shape calculated by algorithm. In this way, the parallelism of proposed design is very flexible and can be adapted to any search range shape. The hardware resource is also fully used while performing VBSME. There are two primary reconfigurable modules in this design: PEGA (PE Group Array) and SAD comparator. By using TSMC 0.18 mu m standard cell library, the implementation results show that the hardware cost of design which uses 16 PEGs (PE Groups) is about 179 K Gates, the clock frequency is 167 MHz.

Motion estimation (ME) is a computation-intensive module in video coding system. In MPEG-2 to H.264 transcoding, motion vector (MV) from MPEG-2 reused as search center in H.264 encoder is a simple but effective technique to simplify ME processing. However, directly applying MPEG-2 MV as search center will bring difficulties on application of data reuse method in hardware design, because the irregular overlapping of search windows between successive macro block (MB). In this paper, we propose a search window reuse scheme for transcoding, especially for HDTV application. By utilizing the similarity between neighboring MV, overlapping area of search windows can be regularized. Experiment results show that our method achieves average 93.1% search window reuse-rate in HDTV720p sequence with almost no video quality degradation. Compared to transcoding method without any data reuse scheme, bandwidth of the proposed method can be reduced to 40.6% of that.

Motion estimation (ME) is a computation-intensive module in video coding system. In MPEG-2 to H.264 transcoding, motion vector (MV) from MPEG-2 reused as search center in H.264 encoder is a simple but effective technique to simplify ME processing. However, directly applying MPEG-2 MV as search center will bring difficulties on application of data reuse method in hardware design, because the irregular overlapping of search windows between successive macro block (MB). In this paper, we propose a search window reuse scheme for transcoding, especially for HDTV application. By utilizing the similarity between neighboring MV, overlapping area of search windows can be regularized. Experiment results show that our method achieves average 93.1% search window reuse-rate in HDTV720p sequence with almost no video quality degradation. Compared to transcoding method without any data reuse scheme, bandwidth of the proposed method can be reduced to 40.6% of that.

This paper presents a compact hardware architecture of Context-Based Adaptive Binary Arithmetic Coding (CABAC) codec for H.264/AVC. The similarities between encoding algorithm and decoding algorithm are explored to achieve remarkable hardware reuse. System-level hardware/software partition is conducted to improve overall performance. Meanwhile, the characteristics of CABAC algorithm are utilized to implement dynamic pipeline scheme, which increases the processing throughput with very small hardware overhead. Proposed architecture is implemented under 0.18 mu m technology. Results show that the core area of proposed design is 0.496 mm(2) when the maximum clock frequency is 230 MHz. It is estimated that the proposed architecture can support CABAC encoding or decoding for HD1080i resolution at a speed of 30 frame/s.

Variable Block Size Motion Estimation (VBSME) costs a lot of computation during video coding. Search range reduction algorithm is widely used to reduce computational cost of motion estimation. Current VBSME designs are not suitable for this algorithm. This paper proposes a reconfigurable design of VBSME which can be efficiently used with search range reduction algorithm. While using proposed design, n x m reference MBs form an MB array which can be processed in parallel. and m can be configured according to the new search range shape calculated by algorithm. In this way, the parallelism of proposed design is very flexible and can be adapted to any search range shape. The hardware resource is also fully used while performing VBSME. There are two primary reconfigurable modules in this design: PEGA (PE Group Array) and SAD comparator. By using TSMC 0.18 pm standard cell library, the implementation results show that the hardware cost of design which uses 16 PEGs (PE Groups) is about 179 K Gates, the clock frequency is 167 MHz. Copyright © 2008 The Institute of Electronics, Information and Communication Engineers.

Intra coding in H.264/AVC has significantly enhanced the video compression efficiency. However, computation complexity increases due to the rate-distortion (RD) based mode decision. This paper proposes a new fast mode decision algorithm in H.264/AVC intra prediction and its VLSI architecture. A new edge-detection pattern is proposed and both edge-detection technique and spatial mode prediction technique are combined together to reduce intra 4x4 candidate mode number from 9 to an average of 2.42. This algorithm is the only hardware-oriented algorithm which can reduce the number of 4x4 candidate mode to less than 4. VLSI architecture of intra mode decision module is designed with TSMC 0.18 mu m CMOS technology. The maximum frequency of 285MHz is achieved and 13.1k gates are required. High frequency, efficient processing cycle reduction and small area make this design to be an excellent accelerator for HDTV 1080p@30fps real time encoder.

Rate distortion optimization (RDO) based spatial intra prediction is an important new feature in H.264/AVC. It chooses the best mode for each MB by exhaustively examining all possible modes. Thus, drastically increased computation complexity is involved. This paper proposes an efficient fast intra mode decision algorithm. Prewitt operator is used to extract each block's two most dominant edge directions. Based on these two directions, only few modes are chosen as candidates. In this way, computational load caused by RDO can be reduced remarkably. Experimental results show that more than 70% computation reduction can be achieved, with little loss of visual quality. Moreover, only addition and comparison operations are used, which makes proposed algorithm friendly enough to be implemented in hardware.

A partially-parallel decoder architecture for irregular LDPC code targeting high throughput and low cost applications is proposed. The design is based on a novel sum-delta message passing algorithm that facilitates the decoding throughput by removing redundant computations and decreases the hardware cost by optimizing the storage. Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction. Copyright 2008 ACM.

This paper presents an efficient hybrid memory access optimization system called HyMacs, which integrates the hardware and software optimization strategies in the embedded system design. First, HyMacs features a pre-configuration stage which is equipped with a memory configuration algorithm to satisfy area constraints. Then a custom instruction generation process is integrated in the system via a seedgrowth algorithm under the intelligent guide functions. The custom instruction benefits to the reduction of the whole memory access latency and thus relieves the burden of system through hardware mode. Finally, a data-dependencydriven scheduling algorithm is also integrated to compress the whole latency through access mode conversion. We have tested the system on a set of commonly used benchmarks, and compared the results with the previous memory access system MACCESS-opt proposed in DAC'05. The experimental results indicate 20% enhancement obtained for the total memory access latency reduction compared with MACCESS-opt, where the custom instruction generation and scheduling contribute about 15% and 5% respectively. Copyright 2008 ACM.

This paper presents a compact hardware architecture of Context-Based Adaptive Binary Arithmetic Coding (CABAC) codec for H.264/AVC. The similarities between encoding algorithm and decoding algorithm are explored to achieve remarkable hardware reuse. System-level hardware/software partition is conducted to improve overall performance. Meanwhile, the characteristics of CABAC algorithm are utilized to implement dynamic pipeline scheme, which increases the processing throughput with very small hardware overhead. Proposed architecture is implemented under 0.18 mu m technology. Results show that the core area of proposed design is 0.496 mm(2) when the maximum clock frequency is 230 MHz. It is estimated that the proposed architecture can support CABAC encoding or decoding for HD1080i resolution at a speed of 30 frame/s.

A partially-parallel decoder architecture for irregular LDPC code targeting high throughput and low cost applications is proposed. The design is based on a novel sum-delta message passing algorithm that facilitates the decoding throughput by removing redundant computations and decreases the hardware cost by optimizing the storage. Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction. Copyright 2008 ACM.

This paper presents an efficient hybrid memory access optimization system called HyMacs, which integrates the hardware and software optimization strategies in the embedded system design. First, HyMacs features a pre-configuration stage which is equipped with a memory configuration algorithm to satisfy area constraints. Then a custom instruction generation process is integrated in the system via a seedgrowth algorithm under the intelligent guide functions. The custom instruction benefits to the reduction of the whole memory access latency and thus relieves the burden of system through hardware mode. Finally, a data-dependencydriven scheduling algorithm is also integrated to compress the whole latency through access mode conversion. We have tested the system on a set of commonly used benchmarks, and compared the results with the previous memory access system MACCESS-opt proposed in DAC'05. The experimental results indicate 20% enhancement obtained for the total memory access latency reduction compared with MACCESS-opt, where the custom instruction generation and scheduling contribute about 15% and 5% respectively. Copyright 2008 ACM.

The well known Rate-Distortion (RD) curve and the average Peak Signal to Noise Ratio (PSNR) difference between two RD curves (Delta PSNR) are frequently and widely used for evaluating how well a fast motion estimation (ME) algorithm performs in encoding efficiency. Besides this one for encoding efficiency, there usually exists another parameter, such as ME executing time or average search point number for processing one macroblock (ASP/MB), to evaluate the complexity of this fast ME algorithm. In the other hand, adaptive search range (ASR) ME algorithms are proved to be more fundamental, regular and controllable than normal fixed search pattern (FSP) ME algorithms. Thus for especially evaluating ASR ME algorithms, an Efficiency-Complexity (EC) curve based method is proposed and discussed in this paper.

H.264 is the latest international video coding standard. It is a joint work by the ITUT Video Coding Experts Group and the ISO/IEC Moving Picture Experts Group. H.264 contains a number of new features which make it compress video sequences much more effectively than previous standards and can provide more flexibility for application to a wide variety of network environments. But the H.264 standard also brings much more computations, especially when the rate-distortion optimization function is on. In order to reduce the complexity of rate-distortion cost of the rate part, we propose al rate estimation methods to avoid doing the real entropy coding method. The estimation method proposed is based on the notification of CAVLC tables, and is changed adoptively according to total_coeff. The final result shows that the proposed estimation method can reduce the encoding computation by 50% through the intra coding with ignorable degradation of coding performance. ©2008 IEEE.

This paper proposes a novel computational structure for Sum of Absolute Difference (SAD) in Fast Full Search (FFS) algorithm to ellipsis part of the SAD value dependency. This structure adopts an SAD Accumulating Termination Algorithm (SAD-ATA) and an Early Loop Termination Decision (ELTD). SAD-ATA is used to analyze and determine whether to skip the following operation of successive SAD accumulation or not, and ELTD is for the control and reduction of SAD comparison loops' degree in FFS ME. The Ratio Distortion (RD) based simulation results show that the proposed algorithm achieves an acceleration in ME processing speed by averagely more than 92% and 20% reduction compared with Full Search (FS) and Fast Full Search (FFS) in H.264 JM12.4, respectively. Meanwhile, the impact on video quality is negligible. © 2008 IEEE.

Intra coding in H.264/AVC has significantly enhanced the video compression efficiency. However, computation complexity increases due to the rate-distortion (RD) based mode decision. This paper proposes a new fast mode decision algorithm in H.264/AVC intra prediction and its VLSI architecture. A new edge-detection pattern is proposed and both edge-detection technique and spatial mode prediction technique are combined together to reduce intra 4x4 candidate mode number from 9 to an average of 2.42. This algorithm is the only hardware-oriented algorithm which can reduce the number of 4x4 candidate mode to less than 4. VLSI architecture of intra mode decision module is designed with TSMC 0.18 mu m CMOS technology. The maximum frequency of 285MHz is achieved and 13.1k gates are required. High frequency, efficient processing cycle reduction and small area make this design to be an excellent accelerator for HDTV 1080p@30fps real time encoder.

H.264 is the latest international video coding standard. It is a joint work by the ITUT Video Coding Experts Group and the ISO/IEC Moving Picture Experts Group. H.264 contains a number of new features which make it compress video sequences much more effectively than previous standards and can provide more flexibility for application to a wide variety of network environments. But the H.264 standard also brings much more computations, especially when the rate-distortion optimization function is on. In order to reduce the complexity of rate-distortion cost of the rate part, we propose al rate estimation methods to avoid doing the real entropy coding method. The estimation method proposed is based on the notification of CAVLC tables, and is changed adoptively according to total_coeff. The final result shows that the proposed estimation method can reduce the encoding computation by 50% through the intra coding with ignorable degradation of coding performance. ©2008 IEEE.

This paper proposes a novel computational structure for Sum of Absolute Difference (SAD) in Fast Full Search (FFS) algorithm to ellipsis part of the SAD value dependency. This structure adopts an SAD Accumulating Termination Algorithm (SAD-ATA) and an Early Loop Termination Decision (ELTD). SAD-ATA is used to analyze and determine whether to skip the following operation of successive SAD accumulation or not, and ELTD is for the control and reduction of SAD comparison loops' degree in FFS ME. The Ratio Distortion (RD) based simulation results show that the proposed algorithm achieves an acceleration in ME processing speed by averagely more than 92% and 20% reduction compared with Full Search (FS) and Fast Full Search (FFS) in H.264 JM12.4, respectively. Meanwhile, the impact on video quality is negligible. © 2008 IEEE.

The well known Rate-Distortion (RD) curve and the average Peak Signal to Noise Ratio (PSNR) difference between two RD curves (Delta PSNR) are frequently and widely used for evaluating how well a fast motion estimation (ME) algorithm performs in encoding efficiency. Besides this one for encoding efficiency, there usually exists another parameter, such as ME executing time or average search point number for processing one macroblock (ASP/MB), to evaluate the complexity of this fast ME algorithm. In the other hand, adaptive search range (ASR) ME algorithms are proved to be more fundamental, regular and controllable than normal fixed search pattern (FSP) ME algorithms. Thus for especially evaluating ASR ME algorithms, an Efficiency-Complexity (EC) curve based method is proposed and discussed in this paper.

Rate distortion optimization (RDO) based spatial intra prediction is an important new feature in H.264/AVC. It chooses the best mode for each MB by exhaustively examining all possible modes. Thus, drastically increased computation complexity is involved. This paper proposes an efficient fast intra mode decision algorithm. Prewitt operator is used to extract each block's two most dominant edge directions. Based on these two directions, only few modes are chosen as candidates. In this way, computational load caused by RDO can be reduced remarkably. Experimental results show that more than 70% computation reduction can be achieved, with little loss of visual quality. Moreover, only addition and comparison operations are used, which makes proposed algorithm friendly enough to be implemented in hardware.

Rectangular shape object detection in color images is a critical step of many image recognition systems. However, there are few reports on this matter. In this paper, we proposed a hierarchical approach, which combines a global contour-based line segment detection algorithm and an Markov random field (MRF) model, to extract rectangular shape objects from real color images. Firstly, we use an elaborate edge detection algorithm to obtain image edge map and accurate edge pixel gradient information (magnitude and direction). Then line segments are extracted from the edge map and some neighboring parallel segments are merged into a single line segment. Finally all segments lying on the boundary of unknown rectangular shape objects are labeled via an MRF model built on line segments. Experimental results show that our method is robust in locating multiple rectangular shape objects simultaneously with respect to different size, orientation and color. (c) 2007 Elsevier BN. All rights reserved.

Rectangular shape object detection in color images is a critical step of many image recognition systems. However, there are few reports on this matter. In this paper, we proposed a hierarchical approach, which combines a global contour-based line segment detection algorithm and an Markov random field (MRF) model, to extract rectangular shape objects from real color images. Firstly, we use an elaborate edge detection algorithm to obtain image edge map and accurate edge pixel gradient information (magnitude and direction). Then line segments are extracted from the edge map and some neighboring parallel segments are merged into a single line segment. Finally all segments lying on the boundary of unknown rectangular shape objects are labeled via an MRF model built on line segments. Experimental results show that our method is robust in locating multiple rectangular shape objects simultaneously with respect to different size, orientation and color. (c) 2007 Elsevier BN. All rights reserved.

In this paper we introduce an area and power efficient fully-parallel LDPC decoder design, which keeps the BER performance while consuming less hardware resources and lower power compared with conventional decoders. For this decoder, we firstly propose two improved simplified min-sum algorithms, which enable the decoder to reduce the hardware implementation complexity and area: hardware consumption of check operation module is reduced by 40%, while achieving a negligible performance loss compared with the general min-sum algorithm. To reduce the power dissipation of the decoder, we also proposed a power-saved strategy according to which the message evolution halts as the parity-check condition is satisfied. This strategy reduces more than 50% power under food channel condition. The synthesis result in 0.18 mu m CMOS technology shows our decoder based on (648,540) irregular LDPC code of WLAN (802.11n) protocol achieves 8 10 [Mbps] throughput with 283 [mW] power consumption.

In this paper we introduce an area and power efficient fully-parallel LDPC decoder design, which keeps the BER performance while consuming less hardware resources and lower power compared with conventional decoders. For this decoder, we firstly propose two improved simplified min-sum algorithms, which enable the decoder to reduce the hardware implementation complexity and area: hardware consumption of check operation module is reduced by 40%, while achieving a negligible performance loss compared with the general min-sum algorithm. To reduce the power dissipation of the decoder, we also proposed a power-saved strategy according to which the message evolution halts as the parity-check condition is satisfied. This strategy reduces more than 50% power under food channel condition. The synthesis result in 0.18 mu m CMOS technology shows our decoder based on (648,540) irregular LDPC code of WLAN (802.11n) protocol achieves 8 10 [Mbps] throughput with 283 [mW] power consumption.

Fractional Motion Estimation (FME) is an advanced feature adopted in H.264/AVC video compression standard with quarter-pixel accuracy. Although FME could gain considerably higher encoding efficiency, sub-pixel interpolation and sum of absolute transformed difference (SATD) computation, as main parts of FME, increase the computation complexity a lot. To reduce the complexity of FME, this paper proposes a full computation reusable VLSI oriented algorithm. Through exploiting the similarity among motion vectors (MVs) of partitions in the same macroblock (MB), temporary computation results can be fully reused. Furthermore, a simple and effective searching method is adopted to make the proposed method more suitable for VLSI implementation. Experiment results show that up to 80% add operations and 85% internal reference frame memory access operations are saved without any degradation in the coding quality.

This paper presents simple and effective method to further reduce the search points in multilevel successive elimination algorithm (MSEA). Because the calculated sea values of those best matching search points are much smaller than the current minimum SAD, we can simply increase the calculated sea values to increase the elimination ratio without much affecting the coding quality. Compared with the original MSEA algorithm, the proposed strict MSEA algorithm (SMSEA) can provide average 6.52 times speedup. Compared with other lossy fast ME algorithms such as TSS and DS, the proposed SMSEA can maintain more stable image quality. In practice, the proposed technique can also be used in the fine granularity SEA (FGSEA) algorithm and the calculation process is almost the same.

Fractional Motion Estimation (FME) is an advanced feature adopted in H.264/AVC video compression standard with quarter-pixel accuracy. Although FME could gain considerably higher encoding efficiency, sub-pixel interpolation and sum of absolute transformed difference (SATD) computation, as main parts of FME, increase the computation complexity a lot. To reduce the complexity of FME, this paper proposes a full computation reusable VLSI oriented algorithm. Through exploiting the similarity among motion vectors (MVs) of partitions in the same macroblock (MB), temporary computation results can be fully reused. Furthermore, a simple and effective searching method is adopted to make the proposed method more suitable for VLSI implementation. Experiment results show that up to 80% add operations and 85% internal reference frame memory access operations are saved without any degradation in the coding quality.

This paper presents simple and effective method to further reduce the search points in multilevel successive elimination algorithm (MSEA). Because the calculated sea values of those best matching search points are much smaller than the current minimum SAD, we can simply increase the calculated sea values to increase the elimination ratio without much affecting the coding quality. Compared with the original MSEA algorithm, the proposed strict MSEA algorithm (SMSEA) can provide average 6.52 times speedup. Compared with other lossy fast ME algorithms such as TSS and DS, the proposed SMSEA can maintain more stable image quality. In practice, the proposed technique can also be used in the fine granularity SEA (FGSEA) algorithm and the calculation process is almost the same.

A 1-D full search variable block sizes motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the add operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is required to store the search area and then reduces 72.7% hardware cost of SRAM. The design is realized with TSMC 0.18μm 1P6M technology with a hardware cost of 67.6K gates. In typical working condition (1.8V, 25°C), a clock frequency of 266MHz can be achieved. © 2006 IEEE.

The intra-frame coding in H.264/AVC has made significant contribution to the enhancement of coding efficiency. However it brings about a heavy computation burden in the rate distortion based (RD) mode decision (MD) process. Although the real-time encoding of 1280-720p signals is realized in recent works with existing algorithms, for higher resolution e.g. 1920-1088p some hardware-oriented fast algorithms are necessary. Yet so far few of the many proposed fast MD algorithms have seen successful hardware implementation. This paper presents a novel VLSI design (15.8k gates@200MHz, with TSMC CMOS 0.18m technology) of an edge based fast intra MD algorithm which can constantly reduce about 66% of the RD related computation with a negligible quality loss. It is expected to be utilized as a favorable accelerator hardware module in a real-time HDTV (1920-1088p) H.264 encoder or MPEG2-H.264 transcoder. Copyright 2007 ACM.

A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30fps is implemented with the dedicated hardware engines and one 32-bit Media embedded Processor (MeP) equipped with hardware extensions. The 11.5Gbps 64Mb Svstem-in-Silicon DRAMA is embedded to alleviate the external memory bandwidth. With TSMC 0.18 mu m CMOS technology, the SoC core occupies 27.1mm(2) die area and consumes 1.41W at 200MHz in typical work conditions.

Fractional Motion Estimation (FME) is an advanced feature adopted in H.264/AVC video compression standard with quarter-pixel accuracy. Although FME could gain considerably higher encoding efficiency, sub-pixel interpolation and sum of absolute transformed difference (SATD) computation, as main parts of FME, increase the computation complexity a lot. To reduce the complexity of FME, this paper proposes a full computation reusable VLSI oriented algorithm. Through exploiting the similarity among motion vectors (MVs) of partitions in the same macroblock (MB), temporary computation results can be fully reused. Furthermore, a simple and effective searching method is adopted to make the proposed method more suitable for VLSI implementation. Experiment results show that up to 80 add operations and 85 internal reference frame memory access operations are saved without any degradation in the coding quality. Copyright © 2007 The Institute of Electronics, Information and Communication Engineers.

In MPEG-2 to H.264 transcoding, MPEG-2 motion vector (MV) is often reused as search center to simplify H.264 motion estimation (ME) module. In this paper, we show that motion vector predictor (MVP) from neighboring sub-blocks is more accurate than MPEG-2 MV as search center when MPEG-2 MV field is non-smooth. A criterion based on relative motion is proposed to evaluate smoothness of MPEG-2 MV field. And a hardware oriented MV prediction scheme is also proposed. Experiment results show that the proposed MV prediction scheme with a relative small search range can approach the performance of full search algorithm. Comparing with the method only utilizing MPEG-2 MV, the proposed approach can achieve significant improvement on accuracy of motion prediction, especially in sequences with fast motion and complicate background.

There are many encryption algorithms for general data such as text data. But they are unsuitable for the encryption of the video data because of the real time constraint of the video applications. In this paper, a partial scramble scheme is proposed. The main feature of this scheme is making use of the characteristics of a H.264/AVC video. In stead of encrypting all the video data, some important parameters of the H.264/AVC video such as motion vector difference (MVD) and trailing ones (T1) of CAVLC module are scrambled in this scheme. There are 3 scramble levels in this scheme. For different scramble levels, MVDs and T1s of different MBs in a frame are scrambled according to different part of the key stream generated by a stream cipher. The advantage of this scheme is that it adds very small computional overhead to H.264/AVC coding process. Hence it is fast enough to be used for real time video applications. This scheme can be utilized in mobile and entertainment applications. © 2007 IEEE.

This paper proposes the power-efficient LDPC decoder architecture which features (1) a FIFO buffering based rapid convergence schedule which enables the decoder to accelerate the decoding throughput without increasing the required number of memory bits, (2) an intermediate message compression technique based on a clock gated shift register which reduces the read and write, power dissipation for the intermediate messages. Simulation results show that the proposed decoder achieves 1.66 times faster decoding throughput, and improves the power efficiency (which is defined by the power dissipation per Mbps) up to 52% compared to the decoder based on the conventional overlapped schedule.

Contour detection is a fundamental step to scene analysis and interpretation. However, because contours often locate in rich texture background it is still a difficult task in realistic vision. Through multi-scale analysis, it becomes clear that edge responses of real object contours are relatively stable across scales, while those from noise or texture background are not. In this paper, a salient contour detection method is proposed based on the scale invariance of piecewise linear approximation of real object contours. Firstly, an image pyramid is efficiently constructed by repeatedly smoothing and sub-sampling the image. Secondly, the piecewise linear approximation of contours in multiple scales are extracted and then a collinear line grouping process is implemented to improve the connectivity of the contours. Thirdly, the new salient line segments are generated based on the analysis on the stability of line segments across scales. Experimental results show that the proposed method can effectively improve the connectivity and saliency of the contour detection compared with the former method. © 2007, The Institute of Image Electronics Engineers of Japan. All rights reserved.

A 1-D full search variable block sizes motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the add operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is required to store the search area and then reduces 72.7% hardware cost of SRAM. The design is realized with TSMC 0.18μm 1P6M technology with a hardware cost of 67.6K gates. In typical working condition (1.8V, 25°C), a clock frequency of 266MHz can be achieved. © 2006 IEEE.

This paper proposes the power-efficient LDPC decoder architecture which features (1) a FIFO buffering based rapid convergence schedule which enables the decoder to accelerate the decoding throughput without increasing the required number of memory bits, (2) an intermediate message compression technique based on a clock gated shift register which reduces the read and write, power dissipation for the intermediate messages. Simulation results show that the proposed decoder achieves 1.66 times faster decoding throughput, and improves the power efficiency (which is defined by the power dissipation per Mbps) up to 52% compared to the decoder based on the conventional overlapped schedule.

The latest video coding standard H.264/AVC covers a wide range of applications from QCIF to HDTV. In case of HDTV, subsampling technique is widely adopted to reduce hardware cost with little video quality degradation. Moreover, experiments show that contribution of small inter search modes to video quality is trivial so that mode reduction can help to further reduce hardware cost. This paper proposes a cost efficient Propagate Partial SAD architecture for HDTV application. The highly pipelined feature of proposed architecture makes it robust to high speed impact. Compared with widely used SAD Tree structure, the proposed cost efficient structure which adopts subsampling and inter search mode reduction can reduce averagely 23.88% hardware cost with negligible video quality loss. With TSMC 0.18μm CMOS 1P6M standard cell library, the maximum clock speed of this design is 233 MHz in worst work condition (1.62, 125°C). © 2007 IEEE.

The coexistence of MPEG-2 and its powerful successor H.264/AVC has created a huge need for MPEG-2/H.264 video transcoding. However, a traditional transcoder where an MPEG-2 decoder is simply cascaded to an H.264 encoder requires huge computational power due to the adoption of a complicated rate-distortion based mode decision process in H.264. This paper proposes a 2-D Sobel filter based motion vector domain method and a DCT domain method to measure macroblock complexity and realize content-based H.264 candidate mode decision. A new local edge based fast INTRA prediction mode decision method is also adopted to boost the encoding efficiency. Simulation results confirm that with the proposed methods the computational burden of a traditional transcoder can be reduced by 20 ∼ 30 with only a negligible bit-rate increase for a wide range of video sequences. Copyright © 2007 The Institute of Electornics, Information and Communication Engineers.

One hardware efficient and high speed architecture for variableblock size motion estimation in H.264 is presented in this paper. Through compressing the propagated data and optimizing theprocessing element and adder tree circuits in pipeline, this architecture gets more hardware efficient datapath logic. Compared with the original Propagate Partial SAD structure, 12.1% hardware cost can be saved. With TSMC 0.18m CMOS 1P6M standard celllibrary, the maximum clock speed of this design is 227MHz in worstwork conditions (1.62V, 125°C). With the 48x32 search range, the maximum throughput of our design is 147786 MB/S, which can be used in the real-time encoding of VGA resolution frame with 4 reference frames at 30Hz. Copyright 2007 ACM.

The latest video coding standard H.264/AVC covers a wide range of applications from QCIF to HDTV. In case of HDTV, subsampling technique is widely adopted to reduce hardware cost with little video quality degradation. Moreover, experiments show that contribution of small inter search modes to video quality is trivial so that mode reduction can help to further reduce hardware cost. This paper proposes a cost efficient Propagate Partial SAD architecture for HDTV application. The highly pipelined feature of proposed architecture makes it robust to high speed impact. Compared with widely used SAD Tree structure, the proposed cost efficient structure which adopts subsampling and inter search mode reduction can reduce averagely 23.88% hardware cost with negligible video quality loss. With TSMC 0.18μm CMOS 1P6M standard cell library, the maximum clock speed of this design is 233 MHz in worst work condition (1.62, 125°C). © 2007 IEEE.

This paper presents two hardware-friendly low-power oriented fast motion estimation (ME) algorithms and their VLSI implementations. The basic idea of the proposed partial distortion sorting (PDS) algorithm is to disable the search points which have larger partial distortions during the ME process, and only keep those search points with smaller ones. To further reduce the computation overhead, a simplified local PDS (LPDS) algorithm is also presented. Experiments show that the PDS and LPDS algorithms can provide almost the same image quality as full search only with 36.7 computation complexity. The proposed two algorithms can be integrated into different FSBMA architectures to save power consumption. In this paper, the 1-D inter ME architecture [12] is used as an detailed example. Under the worst working conditions (1.62 V, 125°C) and 166 MHz clock frequency, the PDS algorithm can reduce 33.3 power consumption with 4.05 K gates extra hardware cost, and the LPDS can reduce 37.8 power consumption with 1.73 K gates overhead. Copyright © 2007 The Institute of Electornics, Information and Communication Engineers.

A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30fps is implemented with the dedicated hardware engines and one 32-bit Media embedded Processor (MeP) equipped with hardware extensions. The 11.5Gbps 64Mb Svstem-in-Silicon DRAMA is embedded to alleviate the external memory bandwidth. With TSMC 0.18 mu m CMOS technology, the SoC core occupies 27.1mm(2) die area and consumes 1.41W at 200MHz in typical work conditions.

In H.264/AVC standard, motion estimation can be processed on multiple reference frames (MRF) to improve the video coding performance. For the VLSI real-time encoder, the heavy computation of fractional motion estimation (FME) makes the integer motion estimation (IME) and FME must be scheduled in two macro block (MB) pipeline stages, which makes many fast MRF algorithms inefficient for the computation reduction. In this paper, two algorithms are provided to reduce the computation of FME and IME. First, through analyzing the block's Hadamard transform coefficients, all-zero case after quantization can be accurately detected. The FME processing in the remaining frames for the block, detected as all-zero one, can be eliminated. Second, because the fast motion object blurs its edges in image, the effect of MRF to aliasing is weakened. The first reference frame is enough for fast motion MBs and MRF is just processed on those slow motion MBs with a small search range. The computation of IME is also highly reduced with this algorithm. Experimental results show that 61.4%-76.7% computation can be saved with the similar coding quality as the reference software. Moreover, the provided fast algorithms can be combined with fast block matching algorithms to further improve the performance.

In MPEG-2 to H.264 transcoding, MPEG-2 motion vector (MV) is often reused as search center to simplify H.264 motion estimation (ME) module. In this paper, we show that motion vector predictor (MVP) from neighboring sub-blocks is more accurate than MPEG-2 MV as search center when MPEG-2 MV field is non-smooth. A criterion based on relative motion is proposed to evaluate smoothness of MPEG-2 MV field. And a hardware oriented MV prediction scheme is also proposed. Experiment results show that the proposed MV prediction scheme with a relative small search range can approach the performance of full search algorithm. Comparing with the method only utilizing MPEG-2 MV, the proposed approach can achieve significant improvement on accuracy of motion prediction, especially in sequences with fast motion and complicate background.

The coexistence of MPEG-2 and its powerful successor H.264/AVC has created a huge need for MPEG-2/H.264 video transcoding. However, a traditional transcoder where an MPEG-2 decoder is simply cascaded to an H.264 encoder requires huge computational power due to the adoption of a complicated rate-distortion based mode decision process in H.264. This paper proposes a 2-D Sobel filter based motion vector domain method and a DCT domain method to measure macroblock complexity and realize content-based H.264 candidate mode decision. A new local edge based fast INTRA prediction mode decision method is also adopted to boost the encoding efficiency. Simulation results confirm that with the proposed methods the computational burden of a traditional transcoder can be reduced by 20 ∼ 30 with only a negligible bit-rate increase for a wide range of video sequences. Copyright © 2007 The Institute of Electornics, Information and Communication Engineers.

Fractional Motion Estimation (FME) is an advanced feature adopted in H.264/AVC video compression standard with quarter-pixel accuracy. Although FME could gain considerably higher encoding efficiency, sub-pixel interpolation and sum of absolute transformed difference (SATD) computation, as main parts of FME, increase the computation complexity a lot. To reduce the complexity of FME, this paper proposes a full computation reusable VLSI oriented algorithm. Through exploiting the similarity among motion vectors (MVs) of partitions in the same macroblock (MB), temporary computation results can be fully reused. Furthermore, a simple and effective searching method is adopted to make the proposed method more suitable for VLSI implementation. Experiment results show that up to 80 add operations and 85 internal reference frame memory access operations are saved without any degradation in the coding quality. Copyright © 2007 The Institute of Electronics, Information and Communication Engineers.

One hardware efficient and high speed architecture for variableblock size motion estimation in H.264 is presented in this paper. Through compressing the propagated data and optimizing theprocessing element and adder tree circuits in pipeline, this architecture gets more hardware efficient datapath logic. Compared with the original Propagate Partial SAD structure, 12.1% hardware cost can be saved. With TSMC 0.18m CMOS 1P6M standard celllibrary, the maximum clock speed of this design is 227MHz in worstwork conditions (1.62V, 125°C). With the 48x32 search range, the maximum throughput of our design is 147786 MB/S, which can be used in the real-time encoding of VGA resolution frame with 4 reference frames at 30Hz. Copyright 2007 ACM.

This paper presents a hardware architecture for Context-Based Adaptive Binary Arithmetic Coding (CABAC) codec in H.264/AVC main profile. The similarities between encoding algorithm and decoding algorithm are explored to fulfill hardware reuse. Meanwhile, dynamic pipeline scheme is adopted, to speedup the throughput. The characteristics of CABAC algorithm are utilized to reduce pipeline latency. Proposed codec design is implemented under TSMC 0.18 μm technology. Results show that the equivalent gate counts is 33.2k when the maximum frequency is 230MHz. It is estimated that the proposed CABAC, codec can process the input binary symbol at 135Mb/s for encoding and 90Mb/s for decoding. © 2007 IEEE.

In H.264/AVC standard, motion estimation can be processed on multiple reference frames (MRF) to improve the video coding performance. For the VLSI real-time encoder, the heavy computation of fractional motion estimation (FME) makes the integer motion estimation (IME) and FME must be scheduled in two macro block (MB) pipeline stages, which makes many fast MRF algorithms inefficient for the computation reduction. In this paper, two algorithms are provided to reduce the computation of FME and IME. First, through analyzing the block's Hadamard transform coefficients, all-zero case after quantization can be accurately detected. The FME processing in the remaining frames for the block, detected as all-zero one, can be eliminated. Second, because the fast motion object blurs its edges in image, the effect of MRF to aliasing is weakened. The first reference frame is enough for fast motion MBs and MRF is just processed on those slow motion MBs with a small search range. The computation of IME is also highly reduced with this algorithm. Experimental results show that 61.4%-76.7% computation can be saved with the similar coding quality as the reference software. Moreover, the provided fast algorithms can be combined with fast block matching algorithms to further improve the performance.

Contour detection is a fundamental step to scene analysis and interpretation. However, because contours often locate in rich texture background it is still a difficult task in realistic vision. Through multi-scale analysis, it becomes clear that edge responses of real object contours are relatively stable across scales, while those from noise or texture background are not. In this paper, a salient contour detection method is proposed based on the scale invariance of piecewise linear approximation of real object contours. Firstly, an image pyramid is efficiently constructed by repeatedly smoothing and sub-sampling the image. Secondly, the piecewise linear approximation of contours in multiple scales are extracted and then a collinear line grouping process is implemented to improve the connectivity of the contours. Thirdly, the new salient line segments are generated based on the analysis on the stability of line segments across scales. Experimental results show that the proposed method can effectively improve the connectivity and saliency of the contour detection compared with the former method. © 2007, The Institute of Image Electronics Engineers of Japan. All rights reserved.

A one-dimensional (1-D) full search variable block size motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the addition operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is used to store the search area data. The design is realized in TSMC 0.18 mu m 1P6M technology with a hardware cost of 67.6K gates. In typical working conditions (1.8 V, 25 degrees C), a clock frequency of 266 MHz can be achieved.

One full search variable block size motion estimation (VBSME) architecture with integer pixel accuracy is proposed in this paper. This proposed architecture has following features: (1) Through widening data path from the search area memories, m processing element groups (PEG) could be scheduled to work in parallel and fully utilized, where m is a factor of sixteen. Each PEG has sixteen processing elements (PE) and just costs 8.5K gates. This feature provides users more flexibility to make tradeoff between the hardware cost and the performance. (2) Based on pipelining and multi-cycle data path techniques, this architecture can work at high clock frequency. (3) The memory partition number is greatly reduced. When sixteen PEGs are adopted, only two memory partitions are required for the search area data storage. Therefore, both the system hardware cost and power consumption can be saved. A 16-PEG design with 48 x 32 search range has been implemented with TSMC 0.18 mu m CMOS technology. In typical work conditions, its maximum clock frequency is 261 MHz. Compared with the previous 2-D architecture [9], about 13.4% hardware cost and 5.7% power consumption can be saved.

In this paper, we propose a power-efficient LDPC decoder architecture based on an accelerated message-passing schedule. The proposed decoder architecture is characterized as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port SRAMs. (H) FIFO-based buffering reduces the number of SRAM banks and words of the LDPC. decoder based on the accelerated message-passing schedule.. The proposed LDPC decoder keeps a single message for each non-zero bit in a parity check matrix as well as a classical schedule while achieving the accelerated message-passing schedule. Implementation results in 0.18 [mu m] CMOS technology show that the proposed decoder architecture reduces an area of the LDPC decoder by 43% and a power dissipation by 29% compared to the conventional architecture based on the accelerated message-passing schedule.

In this paper, we propose a power-efficient LDPC decoder architecture based on an accelerated message-passing schedule. The proposed decoder architecture is characterized as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port SRAMs. (H) FIFO-based buffering reduces the number of SRAM banks and words of the LDPC. decoder based on the accelerated message-passing schedule.. The proposed LDPC decoder keeps a single message for each non-zero bit in a parity check matrix as well as a classical schedule while achieving the accelerated message-passing schedule. Implementation results in 0.18 [mu m] CMOS technology show that the proposed decoder architecture reduces an area of the LDPC decoder by 43% and a power dissipation by 29% compared to the conventional architecture based on the accelerated message-passing schedule.

A one-dimensional (1-D) full search variable block size motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the addition operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is used to store the search area data. The design is realized in TSMC 0.18 mu m 1P6M technology with a hardware cost of 67.6K gates. In typical working conditions (1.8 V, 25 degrees C), a clock frequency of 266 MHz can be achieved.

One full search variable block size motion estimation (VBSME) architecture with integer pixel accuracy is proposed in this paper. This proposed architecture has following features: (1) Through widening data path from the search area memories, m processing element groups (PEG) could be scheduled to work in parallel and fully utilized, where m is a factor of sixteen. Each PEG has sixteen processing elements (PE) and just costs 8.5K gates. This feature provides users more flexibility to make tradeoff between the hardware cost and the performance. (2) Based on pipelining and multi-cycle data path techniques, this architecture can work at high clock frequency. (3) The memory partition number is greatly reduced. When sixteen PEGs are adopted, only two memory partitions are required for the search area data storage. Therefore, both the system hardware cost and power consumption can be saved. A 16-PEG design with 48 x 32 search range has been implemented with TSMC 0.18 mu m CMOS technology. In typical work conditions, its maximum clock frequency is 261 MHz. Compared with the previous 2-D architecture [9], about 13.4% hardware cost and 5.7% power consumption can be saved.

In this paper, we propose a partially-parallel LDPC decoder which achieves a high-efficiency message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) The column operations follow the row operations in a pipelined architecture to ensure that the row and column operations are performed concurrently. (ii) The proposed parallel pipelined bit functional unit enables the column operation module to compute every message in each bit node which is updated by the row operations. These column operations can be performed without extending the single iterative decoding delay when the row and column operations are performed concurrently. Therefore, the proposed decoder performs the column operations more frequently in a single iterative decoding, and achieves a high-efficiency message-passing schedule within the limited decoding delay time. Hardware implementation on an FPGA and simulation results show that the proposed partially-parallel LDPC decoder improves the decoding throughput and bit error performance with a small hardware overhead.

Power efficiency and real-time processing capability are two major issues in today's mobile video applications. We proposed a novel Motion Estimation (ME) engine for power-efficient real-time MPEG-4 video coding based on our previously proposed content-based ME algorithm [8],[13]. By adopting Full Search (FS) and Three Step Search (TSS) alternatively according to the nature of video contents, this algorithm keeps the visual quality very close to that of FS with only 3% of its computational power. We designed a flexible Block Matching (BM) Unit with 16-PE SIMD data path so that the adaptive ME can be performed at a much lower clock frequency and hardware cost as compared with previous FS based work. To reduce the energy cost caused by excessive external memory access, on-chip SRAM is also utilized and optimized for parallel processing in the BM Unit. The ME engine is fabricated with TSMC 0.18 mu m technology. When processing QCEF (15 fps) video, the estimated power is 2.88 mW@4.16 MHz (supply voltage: 1.62 V). It is believed to be a favorable contribution to the video encoder LSI design for mobile applications.

Because of the data correlation in the motion estimation (ME) algorithm of H.264/AVC reference software, it is difficult to implement an efficient ME hardware architecture. In order to make parallel processing feasible, four modified hardware friendly ME workflows are proposed in this paper. Based on these workflows, a scalable full search ME architecture is presented, which has following characteristics: (1) The sum of absolute differences (SAD) results of 4 x 4 sub-blocks is accumulated and reused to calculate SADs of bigger sub-blocks. (2) The number of PE groups is configurable. For a search range of MxN pixels, where M is width and N is height, up to M PE groups can be configured to work in parallel with a peak processing speed of N x 16 clock cycles to fulfill a full search variable block size ME (VBSME). (3) Only conventional single port SRAM is required, which makes this architecture suitable for standard-cell-based implementation. A design with 8 PE groups has been realized with TSMC 0.18 mu m CMOS technology. The core area is 2.13 mm x 1.60 mm and clock frequency is 228 MHz in typical condition (1.8 V, 25 degrees C).

In this paper, we propose a partially-parallel LDPC decoder which achieves a high-efficiency message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) The column operations follow the row operations in a pipelined architecture to ensure that the row and column operations are performed concurrently. (ii) The proposed parallel pipelined bit functional unit enables the column operation module to compute every message in each bit node which is updated by the row operations. These column operations can be performed without extending the single iterative decoding delay when the row and column operations are performed concurrently. Therefore, the proposed decoder performs the column operations more frequently in a single iterative decoding, and achieves a high-efficiency message-passing schedule within the limited decoding delay time. Hardware implementation on an FPGA and simulation results show that the proposed partially-parallel LDPC decoder improves the decoding throughput and bit error performance with a small hardware overhead.

Because of the data correlation in the motion estimation (ME) algorithm of H.264/AVC reference software, it is difficult to implement an efficient ME hardware architecture. In order to make parallel processing feasible, four modified hardware friendly ME workflows are proposed in this paper. Based on these workflows, a scalable full search ME architecture is presented, which has following characteristics: (1) The sum of absolute differences (SAD) results of 4 x 4 sub-blocks is accumulated and reused to calculate SADs of bigger sub-blocks. (2) The number of PE groups is configurable. For a search range of MxN pixels, where M is width and N is height, up to M PE groups can be configured to work in parallel with a peak processing speed of N x 16 clock cycles to fulfill a full search variable block size ME (VBSME). (3) Only conventional single port SRAM is required, which makes this architecture suitable for standard-cell-based implementation. A design with 8 PE groups has been realized with TSMC 0.18 mu m CMOS technology. The core area is 2.13 mm x 1.60 mm and clock frequency is 228 MHz in typical condition (1.8 V, 25 degrees C).

Power efficiency and real-time processing capability are two major issues in today's mobile video applications. We proposed a novel Motion Estimation (ME) engine for power-efficient real-time MPEG-4 video coding based on our previously proposed content-based ME algorithm [8],[13]. By adopting Full Search (FS) and Three Step Search (TSS) alternatively according to the nature of video contents, this algorithm keeps the visual quality very close to that of FS with only 3% of its computational power. We designed a flexible Block Matching (BM) Unit with 16-PE SIMD data path so that the adaptive ME can be performed at a much lower clock frequency and hardware cost as compared with previous FS based work. To reduce the energy cost caused by excessive external memory access, on-chip SRAM is also utilized and optimized for parallel processing in the BM Unit. The ME engine is fabricated with TSMC 0.18 mu m technology. When processing QCEF (15 fps) video, the estimated power is 2.88 mW@4.16 MHz (supply voltage: 1.62 V). It is believed to be a favorable contribution to the video encoder LSI design for mobile applications.

Text detection in color images has become an active research area in the past few decades. In this paper, we present a novel approach to accurately detect text in color images possibly with a complex background. The proposed algorithm is based on the combination of connected component and texture feature analysis of unknown text region contours. First, we utilize an elaborate color image edge detection algorithm to extract all possible text edge pixels. Connected component analysis is performed oil these edge pixels to detect the external contour and possible internal contours of potential text regions. The gradient and geometrical characteristics of each region contour are carefully examined to construct candidate text regions and classify part non-text regions. Then each candidate text region is verified with texture features derived from wavelet domain. Finally, the Expectation maximization algorithm is introduced to binarize each text region to prepare data for recognition. In contrast to previous approach, our algorithm combines both the efficiency of connected component based method and robustness Of texture based analysis. Experimental results show that our proposed algorithm is robust ill text detection with respect to different character size, orientation. color and language and can provide reliable text binarization result.

Text detection in color images has become an active research area in the past few decades. In this paper, we present a novel approach to accurately detect text in color images possibly with a complex background. The proposed algorithm is based on the combination of connected component and texture feature analysis of unknown text region contours. First, we utilize an elaborate color image edge detection algorithm to extract all possible text edge pixels. Connected component analysis is performed oil these edge pixels to detect the external contour and possible internal contours of potential text regions. The gradient and geometrical characteristics of each region contour are carefully examined to construct candidate text regions and classify part non-text regions. Then each candidate text region is verified with texture features derived from wavelet domain. Finally, the Expectation maximization algorithm is introduced to binarize each text region to prepare data for recognition. In contrast to previous approach, our algorithm combines both the efficiency of connected component based method and robustness Of texture based analysis. Experimental results show that our proposed algorithm is robust ill text detection with respect to different character size, orientation. color and language and can provide reliable text binarization result.

This paper proposes a memory-efficient accelerating schedule for LDPC decoder. Important properties of the proposed techniques are as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port memories. (ii) FIFO-based buffering reduces the number of memory banks and words for the decoder based on the accelerated message-passing schedule. The proposed decoder reduces the memories for intermediate messages by half compared to the conventional one based on the accelerated message-passing schedule. ©2006 IEEE.

This paper proposes a memory-efficient accelerating schedule for LDPC decoder. Important properties of the proposed techniques are as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port memories. (ii) FIFO-based buffering reduces the number of memory banks and words for the decoder based on the accelerated message-passing schedule. The proposed decoder reduces the memories for intermediate messages by half compared to the conventional one based on the accelerated message-passing schedule. ©2006 IEEE.

This paper presents an object-oriented unequal loss protection scheme for robust wireless scalable 3D-SPIHT encoded video transmission using product codes. In our proposed OOULP system, the embedded video bitstream of all concerned video objects are packetized independently for transmission over wireless network. The scheme employs regular LDPC codes and Reed-Solomon codes to deal effectively with burst errors over wireless network. For optimal unequal loss protection, a coarse-to-fine strategy has been used to assign unequal rate allocation to each object within the video:(a) coarse allocation: the inter-object rate allocation assign the rate budget among different objects according to their priority level
(b) fine allocation: intra-object rate allocation provides byte-wise protection to the embedded bitstream of each object to minimize its individual mean distortion. Our proposed framework allows the users to independently access and manipulates the objects with their interests. The simulation experiment shows that the proposed framework is robust in hostile network conditions and therefore can provide reasonable visual qualities for different video objects according to their importance.

This paper presents an object-oriented unequal loss protection scheme for robust wireless scalable 3D-SPIHT encoded video transmission using product codes. In our proposed OOULP system, the embedded video bitstream of all concerned video objects are packetized independently for transmission over wireless network. The scheme employs regular LDPC codes and Reed-Solomon codes to deal effectively with burst errors over wireless network. For optimal unequal loss protection, a coarse-to-fine strategy has been used to assign unequal rate allocation to each object within the video:(a) coarse allocation: the inter-object rate allocation assign the rate budget among different objects according to their priority level
(b) fine allocation: intra-object rate allocation provides byte-wise protection to the embedded bitstream of each object to minimize its individual mean distortion. Our proposed framework allows the users to independently access and manipulates the objects with their interests. The simulation experiment shows that the proposed framework is robust in hostile network conditions and therefore can provide reasonable visual qualities for different video objects according to their importance.

With the increase of commercial multimedia applications using digital video, the security of video data becomes more and more important. Although several techniques have been proposed in order to protect these video data, they provide limited security or introduce significant overhead. This paper proposes a video security scheme for MPEG video compression standard, which includes two methods: DCEA (DC Coefficient Encryption Algorithm) and "Event Shuffle." DCEA is aim to encrypt group of codewords of DC coefficients. The feature of this method is the usage of data permutation to scatter the ciphertexts of additional codes in DC codewords. These additional codes are encrypted by block cipher previously. With the combination of these algorithms, the method provides enough security for important DC component of MPEG video data. "Event Shuffle" is aim to encrypt the AC coefficients. The prominent feature of this method is a shuffling of AC events generated after DCT transformation and quantization stages. Experimental results show that these methods introduce no bit overhead to MPEG bit stream while achieving low processing overhead to MPEG codec.

Color image segmentation is probably the most important task in image analysis and understanding. In this paper, we present a novel approach to segment color images by integrating region clustering result with edge detection result. In contrast to existing region-based clustering method, we do not cluster all pixels in an image at one time. We divide clustering process into two steps. First we only cluster those reliable pixels, whose colors are not affected by shadow or highlight, to get more reasonable initial clustering results. Then we cluster left unreliable pixels into classes obtained in previous step or new classes. To avoid over-segmenting an image, edge detection result and spatial information are utilized to merge some neighboring regions, a significant part of whose common boundary consists of weak edges, together as a whole. Experimental results demonstrate the efficacy of our algorithm to segment color images without any prior knowledge. ©2006 IEEE.

With the increase of commercial multimedia applications using digital video, the security of video data becomes more and more important. Although several techniques have been proposed in order to protect these video data, they provide limited security or introduce significant overhead. This paper proposes a video security scheme for MPEG video compression standard, which includes two methods: DCEA (DC Coefficient Encryption Algorithm) and "Event Shuffle." DCEA is aim to encrypt group of codewords of DC coefficients. The feature of this method is the usage of data permutation to scatter the ciphertexts of additional codes in DC codewords. These additional codes are encrypted by block cipher previously. With the combination of these algorithms, the method provides enough security for important DC component of MPEG video data. "Event Shuffle" is aim to encrypt the AC coefficients. The prominent feature of this method is a shuffling of AC events generated after DCT transformation and quantization stages. Experimental results show that these methods introduce no bit overhead to MPEG bit stream while achieving low processing overhead to MPEG codec.

Motion estimation (ME) is a key processing in video encoding systems. Since it requires huge computational complexity, many algorithms and LSI architectures have been proposed to reduce it. Conventional LSIs, however, are not sufficient for mobile applications which require both flexibility and low power dissipation. This paper describes an application specific instruction processor (ASIP) LSI for ME processing. It has a dedicated unit for SAD (sum of absolute difference) operations. By applying our proposed ultra-low ME algorithm named ULCMEA, it can reduce power while keeping high flexibility. A chip capable of operating at 80 MHz was fabricated using TSMC 0.18-μm CMOS technology. 15K logic gates and 32 Kbit SRAM have been integrated into 1.4 mm2 chip. Typical power dissipation is 0.3-mW for QCIF 15 frame/sec ME processing. © 2006 IEEE.