他学部・他研究科等兼任情報

理工学術院 基幹理工学部
2022/11/29 更新
理工学術院 基幹理工学部
理工学術院総合研究所 兼任研究員
筑波大学 博士（工学）
計算機システム
CoDesign of Binary Processing in Memory ReRAM Array and DNN Model Optimization Algorithm
Yue Guan, Takashi Ohsawa
IEICE TRANSACTIONS ON ELECTRONICS E103C ( 11 ) 685  692 2020年11月
Cell Array Design with RowDriven Source Line in Block Shunt Architecture Applicable to Future 6F(2) 1T1MTJ Memory
Tongshuang Huang, Takashi Ohsawa
2019 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSITSA) 2019年
UserFriendly Compact Model of Magnetic Tunnel Junctions for Circuit Simulation Based on Switching Probability
Haoyan Liu, Takashi Ohsawa
2019 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSIDAT) 2019年
A new read scheme for highdensity emerging memories
Takashi Ohsawa
IEICE Transactions on Electronics E101C ( 6 ) 423  429 2018年06月
Hiroki Koike, Takashi Ohsawa, Sadahiko Miura, Hiroaki Honjo, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
JAPANESE JOURNAL OF APPLIED PHYSICS 54 ( 4 ) 2015年04月
A 500ps/8.5ns Array Read/Write Latency 1Mb Twin 1T1MTJ STTMRAM designed in 90nm CMOS/40nm MTJ Process with Novel Positive Feedback S/A Circuit
T. Ohsawa, S. Miura, H. Honjo, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh
International Conference on Solid State Dvices and Materails (SSDM) A83 2014年09月 [査読有り]
磁気ランダムアクセスメモリ（MRAM）の最新技術動向
小池洋紀, 大澤隆, 池田正二, 羽生貴弘, 大野英男, 遠藤哲郎
電子情報通信学会2014年ソサイエティ大会 エレクトロニクス講演論文集2 CT13 SS69 2014年09月 [招待有り]
T. Ohsawa, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh
JOURNAL OF APPLIED PHYSICS 115 ( 17 ) 2014年05月
1.5ns/2.1nsのランダム読出／書込サイクル時間を達成した不揮発性混載メモリ用1Mb STTMRAM －6T2MTJセルにバックグラウンド書き込み（BGW）方式を適用
大澤隆, 小池洋紀, 三浦貞彦, 木下啓藏, 本庄弘明, 池田正二, 羽生貴弘, 大野英男, 遠藤哲郎
信学技報 114 ( 13 ) 33  38 2014年04月 [査読有り] [招待有り]
MTJベース不揮発フリップフロップを用いた3μsecEntry/Exit 遅延時間のマイクロプロセッサ
小池洋紀, 崎村昇, 根橋竜介, 辻幸秀, 森岡あゆ香, 三浦貞彦, 本庄弘明, 杉林直彦, 大澤隆, 池田正二, 羽生貴弘, 大野英男, 遠藤哲郎
信学技報 114 ( 13 ) 85  90 2014年04月 [査読有り] [招待有り]
Hiroki Koike, Takashi Ohsawa, Sadahiko Miura, Hiroaki Honjo, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
JAPANESE JOURNAL OF APPLIED PHYSICS 53 ( 4 ) 2014年04月
Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
JAPANESE JOURNAL OF APPLIED PHYSICS 53 ( 4 ) 2014年04月
A twotransistor bootstrap type selective device for spintransfertorque magnetic tunnel junctions
Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
JAPANESE JOURNAL OF APPLIED PHYSICS 53 ( 4 ) 2014年04月
A PowerGated MPU with 3microsecond Entry/Exit Delay using MTJBased Nonvolatile FlipFlop
Hiroki Koike, Takashi Ohsawa, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Katsuya Miura, Hiroaki Honjo, Tadahiko Sugibayashi, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
IEEE Asian SolidState Circuits Conference (ASSCC2013) 317  320 2013年11月 [査読有り]
Trend of TMR and Variation in Vth for Keeping Data Load Robustness of MOS/MTJ Hybrid Latches
Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
The 58th Annual Magnetism and Magnetic Materials Conference (MMM2013) GT10 693  693 2013年11月 [査読有り]
MTJ resistance distribution and its bit error rate of 1kbit 1T1MTJ STTMRAM cell arrays fabricated on a 300mm wafer
H. Koike, T. Ohsawa, S. Miura, H. Honjo, S. Ikeda, T. Hanyu, H. Ohno
58th Annual Conference on Magnetism & Magnetic Materials Abstract 2013年11月 [査読有り]
Strategy of STTMRAM Cell Design and Its Power Gating Technique for LowVoltage and LowPower Cache Memories
Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetuso Endoh
2013 International Conference on Solid State Devices and Materials (SSDM) M71 1090  1091 2013年09月 [査読有り]
Studies on Selective Devices for SpinTransferTorque Magnetic Tunnel Junctions
Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetuso Endoh
2013 International Conference on Solid State Devices and Materials (SSDM) M84 1104  1105 2013年09月 [査読有り]
A 4x4 Nonvolatile Multiplier Using Novel MTJCMOS Hybrid Latch and FlipFlop
Takashi Ohsawa, Sadahiro Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetuso Endoh
2013 International Conference on Solid State Devices and Materials (SSDM) M63 1086  1087 2013年09月 [査読有り]
Wide Operational Margin Capability of 1kbit STTMRAM Array Chip with 1PMOS and 1BottomPinMTJ Type Cell
Hiroki Koike, Takashi Ohsawa, Sadahiro Miura, Hiroaki Honjo, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetuso Endoh
2013 International Conference on Solid State Devices and Materials (SSDM) M73 1094  1095 2013年09月 [査読有り]
IEEE Journal of SolidState Circuits
T. Ohsawa, H. Koike, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh
A 1 Mb nonvolatile embedded memory using 4T2MTJ cell with 32 b finegrained power gating scheme 48 ( 6 ) 1511  1520 2013年06月 [査読有り]
Takashi Ohsawa, Sadahiro Miura, Keizo Kinoshita, Hiroaki Honjo, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetuso Endoh
2013 Symposium on VLSI Technology (VLSIT) & 2013 Symposium on VLSI Cricuit (VLSIC) Digest of Technical Papers C110  C111 2013年06月 [査読有り]
Verification of Simulation Time Improvement for SPICE Simulator Using Builtin MTJ Model
Hiroki Koike, Takashi Ohsawa, Tetsuo Endoh
16th International Workshop on Computational Electronics (IWCE) 246  247 2013年06月 [査読有り]
A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b FineGrained Power Gating Scheme
Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 48 ( 6 ) 1511  1520 2013年06月
不揮発性STTMRAMの開発と今後の展望
遠藤哲郎, 大澤隆, 伊賀文崇, 池田正二, 羽生貴弘, 大野英男
応用物理学会・特別シンポジウム 2013年03月 [招待有り]
Twostep writing method for STTMTJ to improve switching probability and writespeed
Fumitaka Iga, Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
The 3nd CSIS International Symposium on Spintronicsbased VLSIs 2013年01月 [査読有り]
A finegrained power gating architecture for MTJbased embedded memories
Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keiichi Tokutome, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
The 3nd CSIS International Symposium on Spintronicsbased VLSIs 2013年01月 [査読有り]
A New Sensing Scheme with High Signal Margin Suitable for SpinTransfer Torque RAM
Hiroki Koike, Takashi Ohsawa, Tetsuo Endoh
The 3nd CSIS International Symposium on Spintronicsbased VLSIs 2013年01月 [査読有り]
600MHz Nonvolatile Latch Based on a New MTJ/CMOS Hybrid Circuit Concept
Tetsuo Endoh, Shuta Togashi, Fumitaka Iga, Yasuhiro Yoshida, Takashi Ohsawa, Hiroki Koike, Shunsuke Fukami, Shoji Ikeda, Naoki Kasai, Noboru Sakimura, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
The 3nd CSIS International Symposium on Spintronicsbased VLSIs 2013年01月 [査読有り]
省エネシステムのためのSTTMRAMと、そのロジック応用
遠藤哲郎, 小池洋紀, 大澤隆, 羽生貴弘, 笠井直記, 大野英男
ゲートスタック研究会 2013年01月 [招待有り]
MTJ based Non Volatile Logic for Ultimate Power Management
Tetsuo Endoh, Takashi Ohsawa, Takahiro Hanyu, Hideo Ohno
the 19th International Conference on Magnetism with Strongly Correlated Electron Systems (ICM2012 with SCES) Session BI02 5  7 2012年06月 [査読有り] [招待有り]
1Mb 4T2MTJ Nonvolatile STTRAM for Embedded Memories Using 32b FineGrained Power Gating Technique with 1.0ns/200ps Wakeup/Poweroff Times
T. Ohsawa, H. Koike, S. Miura, H. Honjo, K. Tokutome, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh
2012 Symposium on VLSI Circuits, Digest of Technical Papers JC6.3 46  47 2012年06月 [査読有り]
MTJ based non volatile SRAM and low power non volatile logicinmemory architecture
Tetsuo Endoh, Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Naoki Kasai, Hideo Ohno
IEEE International Magnetics Conference (INTERMAG2012) HB06  HB06 2012年05月 [査読有り] [招待有り]
Low Power Nonvolatile Counter Unit with FineGrained Power Gating
Shuta Togashi, Takashi Ohsawa, Tetsuo Endoh
IEICE TRANSACTIONS ON ELECTRONICS E95C ( 5 ) 854  859 2012年05月
Proposal of New MTJBased Nonvolatile Memories
T. Ohsawa, H. Koike, T. Hanyu, S. Ikeda, H. Ohno, T. Endoh
The 2nd CSIS International Symposium on Spintronicsbased VLSIs F6 23  23 2012年02月 [査読有り] [招待有り]
Nonvolatile Low Power 16bit/32bit Binary Counter with MTJ and its Scalability
Shuta Togashi, Takashi Ohsawa, Tetsuo Endoh
The 2nd CSIS International Symposium on Spintronicsbased VLSIs P20 46  46 2012年02月 [査読有り]
A Study for Adopting PMOS Memory Cell for 1T1R STTRAM with Asymmetric Switching Current MTJ
H. Koike, T. Ohsawa, T. Endoh
The 2nd CSIS International Symposium on Spintronicsbased VLSIs P21 47  47 2012年02月 [査読有り]
Nonvolatile Low Power 16bit/32bit Magnetic Tunnel Junction Based Binary Counter and Its Scaling
Shuta Togashi, Takashi Ohsawa, Tetsuo Endoh
JAPANESE JOURNAL OF APPLIED PHYSICS 51 ( 2 ) 2012年02月
Takashi Ohsawa, Fumitaka Iga, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
JAPANESE JOURNAL OF APPLIED PHYSICS 51 ( 2 ) 2012年02月
HighSpeed Simulator including Accurate MTJ Models for Spintronics Integrated Circuit Design
Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012) 1971  1974 2012年 [査読有り]
A 600MHz MTJBased Nonvolatile Latch Making Use of Incubation Time in MTJ Switching
T. Endoh, S. Togashi, F. Iga, Y. Yoshida, T. Ohsawa, H. Koike, S. Fukami, S. Ikeda, N. Kasai, N. Sakimura, T. Hanyu, H. Ohno
International Electron Devices Meeting (IEDM2011) Session No. 4.3 2011年12月 [査読有り]
Nonvolatile Low Power 16bit/32bit MTJ Based Binary Counter and its Scaling
Shuta Togashi, Takashi Ohsawa, Tetsuo Endoh
2011 International Conference on Solid State Devices and Materials (SSDM2011) 166  167 2011年09月 [査読有り]
Studies on Static Noise Margin and Scalability for LowPower and HighDensity Nonvolatile SRAM using Spin Transfer Torque (STT) MTJs
Takashi Ohsawa, Fumitaka Iga, Shoji Ikeda, Takahiro, Hanyu, Hideo Ohno, Testuo Endoh
2011 International Conference on Solid State Devices and Materials (SSDM2011) 959  960 2011年09月 [査読有り]
Novel 2step Writing Method for STTRAM to Improve Switching Probability and Write Speed
Fumitaka. Iga, Yasuhiko Suzuki, Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
2011 International Conference on Solid State Devices and Materials (SSDM2011) 963  964 2011年09月 [査読有り]
Takashi Ohsawa, Kosuke Hatsuda, Katsuyuki Fujita, Fumiyoshi Matsuoka, Tomoki Higashi
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 46 ( 9 ) 2148  2157 2011年09月
Low Power Nonvolatile Counter Circuit with FineGrained Power Gating
Shuta Togashi, Takashi Ohsawa, Tetsuo Endoh
2011 AsiaPacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD 2011) 3B.10 267  270 2011年06月 [査読有り]
Takeshi Hamamoto, Yoshiaki Fukuzumi, Tomoki Higashi, Hiroomi Nakajima, Yoshihiro Minami, Tomoaki Shino, Takashi Ohsawa, Akihiro Nitayama
IEEE TRANSACTIONS ON ELECTRON DEVICES 57 ( 8 ) 1781  1788 2010年08月
Autonomous Refresh of FloatingBody Cell due to Current Anomaly of Impact Ionization
Takashi Ohsawa, Ryo Fukuda, Tomoki Higashi, Katsuyuki Fujita, Fumiyoshi Matsuoka, Tomoaki Shino, Hironobu Furuhashi, Yoshihiro Minami, Hiroomi Nakajima, Takeshi Hamamoto, Yohji Watanabe, Akihiro Nitayama, Tohru Furuyama
IEEE TRANSACTIONS ON ELECTRON DEVICES 56 ( 10 ) 2302  2311 2009年10月
Takeshi Hamamoto, Takashi Ohsawa
SOLIDSTATE ELECTRONICS 53 ( 7 ) 676  683 2009年07月
Array Architecture of Floating Body Cell (FBC) with QuasiShielded Open Bit Line Scheme for sub40nm Node
Katsuyuki Fujita, Takashi Ohsawa, Ryo Fukuda, Fumiyoshi Matsuoka, Tomoki Higashi, Tomoaki Shino, Yohji Watanabe
2008 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS 31  + 2008年 [査読有り]
Scaling Scenario of Floating Body Cell (FBC) Suppressing Vth Variation Due to Random Dopant Fluctuation
Hironobu Furuhashi, Tomoaki Shino, Takashi Ohsawa, Fumiyoshi Matsuoka, Tomoki Higashi, Yoshihiro Minami, Hiroomi Nakajima, Katsuyuki Fujita, Ryo Fukuda, Takeshi Hamamoto, Akihiro Nitayama
2008 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS 33  + 2008年 [査読有り]
Overview and Future Challenges of Floating Body RAM (FBRAM) Technology for 32nm Technology Node and Beyond
Takeshi Hamamoto, Takashi Ohsawa
ESSDERC 2008: PROCEEDINGS OF THE 38TH EUROPEAN SOLIDSTATE DEVICE RESEARCH CONFERENCE 25  29 2008年 [査読有り]
Autonomous Refresh of Floating Body Cell (FBC)
Takashi Ohsawa, Ryo Fukuda, Tomoki Higashi, Katsuyuki Fujita, Fumiyoshi Matsuoka, Tomoaki Shino, Hironobu Furuhashi, Yoshihiro Minami, Hiroomi Nakajima, Takeshi Hamamoto, Yohji Watanabe, Akihiro Nitayama, Tohru Furuyama
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2008, TECHNICAL DIGEST 801  + 2008年 [査読有り]
Takeshi Hamamoto, Yoshihiro Minami, Tomoaki Shino, Naoki Kusunoki, Hiroomi Nakajima, Mutsuo Morikado, Takashi Yamada, Kazumi Inoh, Atsushi Sakamoto, Tomoki Higashi, Katsuyuki Fujita, Kosuke Hatsuda, Takashi Ohsawa, Akihiro Nitayama
IEEE TRANSACTIONS ON ELECTRON DEVICES 54 ( 3 ) 563  571 2007年03月
FBC's potential of 6F(2) single cell operation in multiGbit memories confirmed by a newly developed method for measuring signal sense margin
Fumiyoshi Matsuoka, Takashi Ohsawa, Tomoki Higashi, Hironobu Furuhashi, Kosuke Hatsuda, Katsuyuki Fujita, Ryo Fukuda, Nobuyuki Ikumi, Tomoaki Shino, Yoshihiro Minami, Hiroomi. Nakajima, Takeshi Hamamoto, Akihiro Nitayama, Yohji Watanabe
2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2 39  + 2007年 [査読有り]
Design of a 128Mb SOI DRAM using the floating body cell (FBC)
T Ohsawa, K Fujita, K Hatsuda, T Higashi, T Shino, Y Minami, H Nakajima, M Morikado, K Inoh, T Hamamoto, S Watanabe, S Fujii, T Furuyama
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 41 ( 1 ) 135  145 2006年01月
Floating body RAM technology and its scalability to 32nm node and beyond
Tomoaki Shino, Naoki Kusunoki, Tomoki Higashi, Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda, Nobuyuki Ikumi, Fumiyoshi Matsuoka, Yasuyuki Kajitani, Ryo Fukuda, Yoji Watanabe, Yoshihiro Minami, Atsushi Sakamoto, Jun Nishimura, Hiroomi Nakajima, Mutsuo Morikado, Kazumi Inoh, Takeshi Hamamoto, Akihiro Nitayama
2006 INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2 314  + 2006年 [査読有り]
A Floating Body Cell (FBC) fully compatible with 90nm CMOS Technology Node for Embedded Applications
Takeshi Hamamoto, Yoshihiro Minami, Tomoaki Shino, Atsushi Sakamoto, Tomoki Higashi, Naoki Kusunoki, Katsuyuki Fujita, Kosuke Hatsuda, Takashi Ohsawa, Nobutoshi Aoki, Hiroyoshi Tanimoto, Mutsuo Morikado, Hiroomi Nakajima, Kazumi Inoh, Akihiro Nitayama
2006 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS 30  + 2006年 [査読有り]
Overview and future challenge of Floating Body Cell (FBC) technology for embedded applications
Akihiro Nitayama, Takashi Ohsawa, Takeshi Hamamoto
2006 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSITSA), PROCEEDINGS OF TECHNICAL PAPERS 94  + 2006年 [査読有り]
Operation voltage dependence of memory cell characteristics in fully depleted floatingbody cell
T Shino, T Ohsawa, T Higashi, K Fujita, N Kusunoki, Y Minami, M Morikado, H Nakajima, K Inoh, T Hamamoto, A Nitayama
IEEE TRANSACTIONS ON ELECTRON DEVICES 52 ( 10 ) 2220  2226 2005年10月
A Floating Body Cell (FBC) fully compatible with 90nm CMOS Technology(CMOS IV) for 128Mb SOI DRAM
Y Minami, T Shino, A Sakamoto, T Higashi, N Kusunoki, K Fujita, K Hatsuda, T Ohsawa, N Aoki, H Tanimoto, M Morikado, H Nakajima, K Inoh, T Hamamoto, A Nitayama
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST 317  320 2005年 [査読有り]
Fullydepleted FBC (Floating Body Cell) with enlarged signal window and excellent logic process compatibility
T Shino, T Higashi, N Kusunoki, K Fujita, T Ohsawa, N Aoki, H Tanimoto, Y Minami, T Yamada, M Morikado, H Nakajima, K Inoh, T Hamamoto, A Nitayama
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST 281  284 2004年 [査読有り]
A memory using onetransistor gain cell on SOI(FBC) with performance suitable for embedded DRAM's
T Ohsawa, T Higashi, K Fujita, T Ikehashi, T Kajiyama, Y Fukuzumi, T Shino, H Yamada, H Nakajima, Y Minami, T Yamada, K Inoh, T Hamamoto
2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS 93  96 2003年 [査読有り]
Memory design using a onetransistor gain cell on SOI
T Ohsawa, K Fujita, T Higashi, Y Iwata, T Kajiyama, Y Asao, K Sunouchi
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 37 ( 11 ) 1510  1522 2002年11月
A 250 mV bitline swing scheme for 1V operating gigabit scale DRAMs
T Inaba, D Takashima, Y Oowaki, T Ozaki, S Watanabe, T Ohsawa, K Ohuchi, H Tango
IEICE TRANSACTIONS ON ELECTRONICS E79C ( 12 ) 1699  1706 1996年12月
A 12MHZ DATA CYCLE 4MB DRAM WITH PIPELINE OPERATION
N KUSHIYAMA, Y WATANABE, T OHSAWA, K MURAOKA, Y NAGAHAMA, T FURUYAMA
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 26 ( 4 ) 479  483 1991年04月
A New CRDelay Circuit Technology for HighDensity and HighSpeed DRAM’s
Yohji Watanabe, Takashi Ohsawa, Kiyofumi Sakurai, Tohru Furuyama
IEEE Journal of SolidState Circuits 24 ( 4 ) 905  910 1989年
An Experimental 2bit/Cell Storage DRAM for Macroce11 or MemoryonLogic Application
Tohru Furuyama, Takashi Ohsawa, Yohji Watanabe, Kazuyoshi Muraoka, Kenji Natori, Yousei Nagahama, Tohru Kimura, Hiroto Tanaka
IEEE Journal of SolidState Circuits 24 ( 2 ) 388  393 1989年
A New OnChip Voltage Converter for Submicrometer HighDensity DRAM's
Tohru Furuyama, Yorji Watanabe, Takashi Ohsawa, Shigeyoshi Watanabe
IEEE Journal of SolidState Circuits 22 ( 3 ) 437  441 1987年
A 60ns 4Mbit CMOS DRAM with BuiltIn SelfTest Function
Takashi Ohsawa, Tohru Furuyama, Yohji Watanabe, Hiroto Tanaka, Kenji Natori, Satoshi Shinozaki, Takeshi Tanaka, Satoshi Yamano, Yohsei Nagahama, Natsuki Kushiyama, Kenji Tsuchida
IEEE Journal of SolidState Circuits 22 ( 5 ) 663  668 1987年
An Experimental 4Mbit CMOS DRAM
Tohru Furuyama, Takashi Ohsawa, Yohji Watanabe, Hidemi Ishiuchi, Toshiharu Watanabe, Takeshi Tanaka, Kenji Natori, Osamu Ozawa
IEEE Journal of SolidState Circuits 21 ( 5 ) 605  611 1986年
THERMODYNAMIC THEORY OF LIGHTION BEAM PROPAGATION IN A PLASMA
T KATO, T OHSAWA
JOURNAL OF THE PHYSICAL SOCIETY OF JAPAN 52 ( 8 ) 2720  2726 1983年
AZIMUTHAL CURRENTNEUTRALIZATION OF A ROTATIONAL LIGHTION BEAM BY A PLASMA
T OHSAWA, T KATO
JOURNAL OF THE PHYSICAL SOCIETY OF JAPAN 52 ( 8 ) 2727  2735 1983年
SYNCHRONOUS QUENCHING DUE TO NONLINEAR MODECOUPLING IN BEAMPLASMA SYSTEM
T OHSAWA
JOURNAL OF THE PHYSICAL SOCIETY OF JAPAN 49 ( 6 ) 2340  2348 1980年
Theory of the Parametric Oscillation in an Electron BeamPlasma System
Tomokazu Kato, Takashi Okazaki, Takashi Ohsawa
Journal of the Physical Society of Japan 46 277  284 1979年01月
Floating Body Cell  A Novel Capacitorless DRAM Cell 
大澤 隆( 担当： 共著, 担当範囲: pp. 1111, pp. 113116, pp. 127254 (total 254 pages))
Pan Stanford Publishing Pte. Ltd. 2012年
招待講演 3次元構造とスピントロニクスによる半導体メモリの新展開
遠藤 哲郎, 大澤 隆, 小池 洋紀
半導体・集積回路技術シンポジウム講演論文集 = Proceedings of Symposium on Semiconductors and Integrated Circuits Technology 77 35  40 2013年07月
依頼講演 32ビット細粒度パワーゲーティングを使った不揮発性混載用1Mb 4T2MTJ STTRAM : 1.0ns/200psのWakeup/Poweroff時間を達成 (集積回路)
遠藤 哲郎, 大澤 隆, 小池 洋紀, 三浦 貞彦, 本庄 弘明, 徳留 圭一, 池田 正二, 羽生 貴弘, 大野 英男
電子情報通信学会技術研究報告 : 信学技報 113 ( 1 ) 27  32 2013年04月
シリコン不揮発性メモリ技術の限界を突破するスピントルク注入型磁気メモリの最新動向
遠藤哲郎, 大澤隆, 小池洋紀, 羽生貴弘, 笠井直記, 大野英男
電子情報通信学会誌 ( 平成24年11月号 ) 2012年11月
記事・総説・解説・論説等（その他）
STTMRAM for future high performance Nonvolatile memory
遠藤哲郎, 大澤隆, 小池洋紀, 羽生貴弘, 笠井直記, 大野英男
電子情報通信学会誌 ( 平成24年11月号 ) 2012年11月
記事・総説・解説・論説等（その他）
SSDM Paper Award
2012年09月 International Conference on Solid State Devices and Materials (SSDM)
受賞者： 大澤 隆
The Takuo Sugano Award
2003年02月 IEEE International SolidState Circuits Confenetce
受賞者： 大澤 隆
Codesign of DNN Model Optimization for Binary ReRAM Array Inmemory Processing
Yue Guan, Takashi Ohsawa
Proceedings of Technical Program  IEEE 2019 11th International Memory Workshop, Monterey, USA
発表年月： 2019年05月
UserFriendly Compact Model of Magnetic Tunnel Junctions for Circuit SImulation Based on Switching Probability
Haoyan Liu, Takashi Ohsawa
Proceedings of Technical Program  2019 International Symposium on VLSI Design, Automation and Test, VLSIDAT 2019
発表年月： 2019年04月
Accurate Meassurement of Sneak Current in ReRAM Crossbar Array with Data Storage Pattern Dependencies
Yaqi Shang, Takashi Ohsawa
Proceedings of Technical Program  2019 International Symposium on VLSI Technology, Systems and Applications, VLSITSA 2019
発表年月： 2019年04月
Cell Array Design with RowDriven Source Line in Block Shunt Architecture Applicable to Future 6F2 1T1MTJ Memory
Tongshuang Huang, Takashi Ohsawa
Proceedings of Technical Program  2019 International Symposium on VLSI Technology, Systems and Applications, VLSITSA 2019
発表年月： 2019年04月
Studies on readstability and writeability of fast access STTMRAMs
Takashi Ohsawa, Takashi Ohsawa, Shoji Ikeda, Shoji Ikeda, Takahiro Hanyu, Takahiro Hanyu, Takahiro Hanyu, Hideo Ohno, Hideo Ohno, Hideo Ohno, Tetsuo Endoh, Tetsuo Endoh, Tetsuo Endoh
Proceedings of Technical Program  2014 International Symposium on VLSI Technology, Systems and Application, VLSITSA 2014
発表年月： 2014年01月
A powergated MPU with 3microsecond entry/exit delay using MTJbased nonvolatile flipflop
H. Koike, T. Ohsawa, S. Ikeda, S. Ikeda, T. Hanyu, T. Hanyu, H. Ohno, H. Ohno, T. Endoh, T. Endoh, N. Sakimura, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, S. Miura, H. Honjo, T. Sugibayashi
Proceedings of the 2013 IEEE Asian SolidState Circuits Conference, ASSCC 2013
発表年月： 2013年12月
T. Ohsawa, S. Miura, K. Kinoshita, H. Honjo, S. Ikeda, S. Ikeda, T. Hanyu, T. Hanyu, H. Ohno, H. Ohno, T. Endoh, T. Endoh, T. Endoh
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
発表年月： 2013年09月
Takashi Ohsawa, Shoji Ikeda, Shoji Ikeda, Takahiro Hanyu, Takahiro Hanyu, Hideo Ohno, Hideo Ohno, Tetsuo Endoh, Tetsuo Endoh, Tetsuo Endoh
2013 5th IEEE International Memory Workshop, IMW 2013
発表年月： 2013年09月
T. Ohsawa, S. Miura, K. Kinoshita, H. Honjo, S. Ikeda, S. Ikeda, T. Hanyu, T. Hanyu, H. Ohno, H. Ohno, T. Endoh, T. Endoh, T. Endoh
Digest of Technical Papers  Symposium on VLSI Technology
発表年月： 2013年09月
Highspeed simulator including accurate MTJ models for spintronics integrated circuit design
Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
ISCAS 2012  2012 IEEE International Symposium on Circuits and Systems
発表年月： 2012年09月
T. Ohsawa, H. Koike, S. Miura, H. Honjo, K. Tokutome, S. Ikeda, S. Ikeda, T. Hanyu, T. Hanyu, H. Ohno, H. Ohno, T. Endoh, T. Endoh, T. Endoh
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
発表年月： 2012年09月
Restructuring of memory hierarchy in computing system with spintronicsbased technologies
Tetsuo Endoh, Tetsuo Endoh, Tetsuo Endoh, Takashi Ohsawa, Hiroki Koike, Takahiro Hanyu, Takahiro Hanyu, Hideo Ohno, Hideo Ohno
Digest of Technical Papers  Symposium on VLSI Technology
発表年月： 2012年09月
A 600MHz MTJbased nonvolatile latch making use of incubation time in MTJ switching
T. Endoh, T. Endoh, T. Endoh, S. Togashi, S. Togashi, F. Iga, F. Iga, Y. Yoshida, Y. Yoshida, T. Ohsawa, H. Koike, S. Fukami, S. Ikeda, S. Ikeda, N. Kasai, N. Sakimura, T. Hanyu, T. Hanyu, H. Ohno, H. Ohno
Technical Digest  International Electron Devices Meeting, IEDM
発表年月： 2011年12月
Katsuyuki Fujita, Takashi Ohsawa, Ryo Fukuda, Fumiyoshi Matsuoka, Tomoki Higashi, Tomoaki Shino, Yohji Watanabe
Proceedings  IEEE International SOI Conference
発表年月： 2008年12月
Hironobu Furuhashi, Tomoaki Shino, Takashi Ohsawa, Fumiyoshi Matsuoka, Tomoki Higashi, Yoshihiro Minami, Hiroomi Nakajima, Katsuyuki Fujita, Ryo Fukuda, Takeshi Hamamoto, Akihiro Nitayama
Proceedings  IEEE International SOI Conference
発表年月： 2008年12月
Autonomous refresh of floating body cell (FBC)
Takashi Ohsawa, Ryo Fukuda, Tomoki Higashi, Katsuyuki Fujita, Fumiyoshi Matsuoka, Tomoaki Shino, Hironobu Furuhashi, Yoshihiro Minami, Hiroomi Nakajima, Takeshi Hamamoto, Yohji Watanabe, Akihiro Nitayama, Tohru Furuyama
Technical Digest  International Electron Devices Meeting, IEDM
発表年月： 2008年12月
Takeshi Hamamoto, Takashi Ohsawa
ESSDERC 2008  Proceedings of the 38th European SolidState Device Research Conference
発表年月： 2008年01月
Fumiyoshi Matsuoka, Takashi Ohsawa, Tomoki Higashi, Hironobu Furuhashi, Kosuke Hatsuda, Katsuyuki Fujita, Ryo Fukuda, Nobuyuki Ikumi, Tomoaki Shino, Yoshihiro Minami, Hiroomi Nakajima, Takeshi Hamamoto, Akihiro Nitayama, Yohji Watanabe
Technical Digest  International Electron Devices Meeting, IEDM
発表年月： 2007年12月
Floating body RAM technology and its scalability to 32nm node and beyond
Tomoaki Shino, Naoki Kusunoki, Tomoki Higashi, Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda, Nobuyuki Ikumi, Fumiyoshi Matsuoka, Yasuyuki Kajitani, Ryo Fukuda, Yoji Watanabe, Yoshihiro Minami, Atsushi Sakamoto, Jun Nishimura, Hiroomi Nakajima, Mutsuo Morikado, Kazumi Inoh, Takeshi Hamamoto, Akihiro Nitayama
Technical Digest  International Electron Devices Meeting, IEDM
発表年月： 2006年12月
A 128Mb floating body RAM(FBRAM) on SOI with multiaveraging scheme of dummy cell
Takashi Ohsawa, Tomoki Higashi, Katsuyuki Fujita, Kosuke Hatsuda, Nobuyuki Ikumi, Tomoaki Shino, Hiroomi Nakajima, Yoshihiro Minami, Naoki Kusunoki, Atsushi Sakamoto, Jun Nishimura, Takeshi Hamamoto, Shuso Fujii
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
発表年月： 2006年12月
Overview and future challenge of Floating Body Cell (FBC) technology for embedded applications
Akihiro Nitayama, Takashi Ohsawa, Takeshi Hamamoto
International Symposium on VLSI Technology, Systems, and Applications, Proceedings
発表年月： 2006年12月
A Floating Body Cell (FBC) fully compatible with 90nm CMOS technology node for embedded applications
Takeshi Hamamoto, Yoshihiro Minami, Tomoaki Shino, Atsushi Sakamoto, Tomoki Higashi, Naoki Kusunoki, Katsuyuki Fujita, Kosuke Hatsuda, Takashi Ohsawa, Nobutoshi Aoki, Hiroyoshi Tanimoto, Mutsuo Morikado, Hiroomi Nakajima, Kazumi Inoh, Akihiro Nitayama
2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06
発表年月： 2006年12月
An 18.5ns 128Mb SOI DRAM with a floating body cell
Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda, Tomoki Higashi, Mutsuo Morikado, Yoshihiro Minami, Tomoaki Shino, Hiroomi Nakajima, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe
Digest of Technical Papers  IEEE International SolidState Circuits Conference
発表年月： 2005年12月
An 18.5ns 128Mb SOI DRAM with a floating body cell
Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda, Tomoki Higashi, Mutsuo Morikado, Yoshihiro Minami, Tomoaki Shino, Hiroomi Nakajima, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe
Digest of Technical Papers  IEEE International SolidState Circuits Conference
発表年月： 2005年12月
A Floating Body Cell (FBC) fully compatible with 90nm CMOS technology(CMOS IV) for 128Mb SOI DRAM
Yoshihiro Minami, Tomoaki Shino, Atsushi Sakamoto, Tomoki Higashi, Naoki Kusunoki, Katsuyuki Fujita, Kosuke Hatsuda, Takashi Ohsawa, Nobutoshi Aoki, Hiroyoshi Tanimoto, Mutsuo Morikado, Hiroomi Nakajima, Kazumi Inoh, Takeshi Hamamoto, Akihiro Nitayama
Technical Digest  International Electron Devices Meeting, IEDM
発表年月： 2005年12月
A 333MHz random cycle DRAM using the floating body cell
Kosuke Hatsuda, Katsuyuki Fujita, Takashi Ohsawa
Proceedings of the Custom Integrated Circuits Conference
発表年月： 2005年12月
Tomoaki Shino, Tomoki Higashi, Naoki Kusunoki, Katsuyuki Fujita, Takashi Ohsawa, Nobutoshi Aoki, Hiroyoshi Tanimoto, Yoshihiro Minami, Takashi Yamada, Mutsuo Morikado, Hiroomi Nakajima, Kazumi Inoh, Takeshi Hamamoto, Akihiro Nitayama
Technical Digest  International Electron Devices Meeting, IEDM
発表年月： 2004年12月
Highly scalable FBC (floating body cell) with 25nm BOX structure for embedded DRAM applications
Tomoaki Shino, Tomoki Higashi, Katsuyuki Fujita, Takashi Ohsawa, Yoshihiro Minami, Takashi Yamada, Mutsuo Morikado, Hiroomi Nakajima, Kazumi Inoh, Takeshi Hamamoto, Akihiro Nitayama
Digest of Technical Papers  Symposium on VLSI Technology
発表年月： 2004年10月
FBC (Floating Body Cell) for Embedded DRAM on SOI
Kazumi Inoh, Tomoaki Shino, Hiroaki Yamada, Hiroomi Nakajima, Yoshihiro Minami, Takashi Yamada, Takashi Ohsawa, Tomoki Higashi, Katsuyuki Fujita, Tamio Ikehashi, Takeshi Kajiyama, Yoshiaki Fukuzumi, Takeshi Hamamoto, Hidemi Ishiuchi
Digest of Technical Papers  Symposium on VLSI Technology
発表年月： 2003年10月
A Memory Using Onetransistor Gain Cell on SOI(FBC) with Performance Suitable for Embedded DRAM's
Takashi Ohsawa, Tomoki Higashi, Katsuyuki Fujita, Tamio Ikehashi, Takeshi Kajiyama, Yoshiaki Fukuzumi, Tomoaki Shino, Hiroaki Yamada, Hiroomi Nakajima, Yoshihiro Minami, Takashi Yamada, Kazumi Inoh, Takeshi Hamamoto
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
発表年月： 2003年10月
Memory design using onetransistor gain cell on SOI
Takashi Ohsawa, Katsuyuki Fujita, Tomoki Higashi, Yoshihisa Iwata, Takeshi Kajiyama, Yoshiaki Asao, Kazumasa Sunouchi
Digest of Technical Papers  IEEE International SolidState Circuits Conference
発表年月： 2002年01月
Memory design using onetransistor gain cell on SOI
Takashi Ohsawa, Katsuyuki Fujita, Tomoki Higashi, Yoshihisa Iwata, Takeshi Kajiyama, Yoshiaki Asao, Kazumasa Sunouchi
Digest of Technical Papers  IEEE International SolidState Circuits Conference
発表年月： 2002年01月
A high randomaccessdatarate 4MbDRAM with pipeline operation
Tohru Furuyama, Natsuki Kushiyama, Yohji Watanabe, Takashi Ohsawa, Kazuyoshi Muraoka, Yousei Nagahama
1990 Symposium on VLSI Circuits; Honolulu, HI, USA; ; 7 June 1990 through 9 June 1990
発表年月： 1990年12月
Experimental 2bit/cell storage DRAM for macro cell or memoryonlogic application.
Tohru Furuyama, Takashi Ohsawa, Yousei Nagahama, Hiroto Tanaka, Yohji Watanabe, Tohru Kimura, Kazuyoshi Muraoka, Kenji Natori
Proceedings of the Custom Integrated Circuits Conference
発表年月： 1988年12月
New CRdelay circuit technology for highdensity and highspeed DRAMs
Yohji Watanabe, Takashi Ohsawa, Kiyofumi Sakurai, Tohru Furuyama
1988 Symposium on VLSI Circuits  Digest of Technical Papers; Tokyo, Japan; ; 22 August 1988 through 24 August 1988
発表年月： 1988年12月
A 60ns 4Mb DRAM with builtin selftest
大澤 隆
International SolidState Circuits Conference (ISSCC) Digest of Technical Papers, pp. 286287
発表年月： 1987年02月
ONCHIP SUPPLY VOLTAGE CONVERSION SYSTEM AND ITS APPLICATION TO A 4Mb DRAM.
Yohji Watanabe, Shigeyoshi Watanabe, Takashi Ohsawa, Tohru Furuyama, Kazunori Ohuchi
Conference on Solid State Devices and Materials
発表年月： 1986年12月
NEW ONCHIP VOLTAGE CONVERTER FOR SUBMICRON HIGHDENSITY DRAMs.
Tohru Furuyama, Yohji Watanabe, Takashi Ohsawa, Shigeyoshi Watanabe
ESSCIRC '86: Twelfth European SolidState Circuits Conference.; Delft, Neth
発表年月： 1986年12月
An experimental 4Mb CMOS DRAM
大澤 隆
International SolidState Circuits Conference (ISSCC) Digest of Technical Papers, pp. 272273
発表年月： 1986年02月
Citation Countは当該年に発表した論文の被引用数