A spintronic-based power-gated micro-processing unit (MPU) is proposed. It includes a power control circuit activated by the newly supported power-off instruction for the deep-sleep mode. These means enable the power-off procedure for the MPU to be executed appropriately. A test chip was designed and fabricated using 90nm CMOS and an additional 100nm MTJ process; it was successfully operated. The guideline of the energy reduction effects for this MPU was presented, using the estimation based on the measurement results of the test chip. The result shows that a large operation energy reduction of 1/28 can be achieved when the operation duty is 10%, under the condition of a sufficient number of idle clock cycles. (C) 2015 The Japan Society of Applied Physics

The robustness of data load of metal-oxide-semiconductor/magnetic tunnel junction (MOS/MTJ) hybrid latches at power-on is examined by using Monte Carlo simulation with the variations in magnetoresistances for MTJs and in threshold voltages for MOSFETs involved in 90 nm technology node. Three differential pair type spin-transfer-torque-magnetic random access memory cells (4T2MTJ, 6T2MTJ, and 8T2MTJ) are compared for their successful data load at power-on. It is found that the 4T2MTJ cell has the largest pass area in the shmoo plot in TMR ratio (tunnel magnetoresistance ratio) and V-dd in which a whole 256 kb cell array can be powered-on successfully. The minimum TMR ratio for the 4T2MTJ in 0.9V < V-dd < 1.9V is 140%, while the 6T2MTJ and the 8T2MTJ cells require TMR ratio larger than 170%. (C) 2014 AIP Publishing LLC.

This paper discusses the optimal combination of 1 transistor (T) and 1 magnetic tunnel junction (MTJ) type cell for spin transfer torque memory. Taking into consideration of current magnitude for both the T and the MTJ, either PMOS-bottom pin structure or NMOS-top pin structure can be a promising choice. Focusing on the PMOS-bottom pin structure from the viewpoint of avoiding process difficulty, we clarified the condition that the structure would be effective. In order to verify the structure's effectiveness, a stand-alone MTJ test element group and a 1 kbit memory array chip were designed and fabricated with 90nm CMOS/100nm MTJ process. With the pass bit percentage measurement of the memory chip, we successfully demonstrated that 1-PMOS and 1-bottom-pin-MTJ has the wide operation margin of 100% pass at near 1.6V. It will be an effective solution for 1T-1MTJ memories. (C) 2014 The Japan Society of Applied Physics

Array operation currents in spin-transfer-torque magnetic random access memories (STT-MRAMs) that use four differential pair type magnetic tunnel junction (MTJ)-based memory cells (4T2MTJ, two 6T2MTJs and 8T2MTJ) are simulated and compared with that in SRAM. With L3 cache applications in mind, it is assumed that the memories are composed of 32 Mbyte capacity to be accessed in 64 byte in parallel. All the STT-MRAMs except for the 8T2MTJ one are designed with 32 bit fine-grained power gating scheme applied to eliminate static currents in the memory cells that are not accessed. The 8T2MTJ STT-MRAM, the cell's design concept being not suitable for the fine-grained power gating, loads and saves 32 Mbyte data in 64 Mbyte unit per 1 Mbit sub-array in 2 x 10(3) cycles. It is shown that the array operation current of the 4T2MTJ STT-MRAM is 70mA averaged in 15 ns write cycles at V-dd = 0.9V. This is the smallest among the STT-MRAMs, about the half of the low standby power (LSTP) SRAM whose array operation current is totally dominated by the cells' subthreshold leakage. (C) 2014 The Japan Society of Applied Physics

Two-transistor bootstrap type selective device for spin-transfer-torque magnetic tunnel junctions (STT-MTJs) is proposed that is smaller than the conventional ones with equivalent performance. The power supply voltage dependence of the area for the two-NFET bootstrap type selective device that can switch MTJs within 10 ns is compared with those of the conventional single-NFET, single-PFET, and CMOS type selective devices with the same performance in 90nm technology node. It is found that the two-NFET bootstrap type selective device can be smaller than the conventional ones especially for the power supply voltage equal to or lower than 0.9V. The two-NFET bootstrap type selective device is shown to maintain scalability to 32nm node just like the CMOS one, while the conventional single-NFET and single-PFET selective devices fail to be scaled properly. This selective device can be applied to every high-performance MOS/MTJ hybrid circuit for increasing the integration density. (C) 2014 The Japan Society of Applied Physics

A 1 Mb nonvolatile embedded memory using a four transistor and two spin-transfer-torque (STT) magnetic tunnel junction (MTJ) cell is designed and fabricated to demonstrate its zero standby power and high performance. The power supply voltages of 32 cells along a word line (WL) are controlled simultaneously by a power line (PL) driver to eliminate the standby power without impact on the access time. This fine-grained power gating scheme also optimizes the trade-off between macro size and operation power. The butterfly curve for the cell is measured to be asymmetric as predicted, enhancing the cell's static noise margin (SNM) for data retention. The scaling of 1 Mb macro size is compared with that of the 6T SRAM counterpart, indicating that the former will become smaller than the latter at 45 nm technology node and beyond by moderately thinning its tunnel dielectrics (MgO) in accordance with the shrink of the MTJ's cross sectional area. The operation current of the macro is also shown to be almost unchanged over generations, while that of the 6T SRAM increases exponentially due to the degradation of MOSFET off-current as the device scales.

In this paper, we propose a new low power nonvolatile counter unit based on Magnetic Tunnel Junction (MTJ) with fine-grained power gating. The proposed counter unit consists of only a single latch with two MTJs. We verify the basic operation and estimate the power consumption of the proposed counter unit. The operating power consumption of the proposed nonvolatile counter unit is smaller than the conventional one below 140 kHz. The power of the proposed unit is 74.6% smaller than the conventional one at low frequency.

We propose a nonvolatile 16-bit/32-bit magnetic tunnel junction (MTJ) based binary counter with fine-grained power gating scheme suitable for MTJ. We estimate the power consumption of the proposed counter by using simulation program with integrated circuit emphasis (SPICE) simulation. The power of the proposed 16-bit/32-bit counter is 59.1 and 72.5% smaller in case of 45 and 16 nm node, respectively, than that of the conventional complementary metal oxide semiconductor (CMOS) counter at low frequency (100 Hz). The proposed nonvolatile 32-bit counter achieves lower power at operating frequencies up to 49 kHz and 4 MHz in the case of 45 and 16 nm node, respectively, in comparison with the conventional CMOS counter. Moreover, we propose a hybrid 32-bit counter that is constructed with CMOS counter units for the beginning stages and nonvolatile MTJ based counter units for the latter stages. It achieves a lower power at operating frequencies up to 1 GHz than the conventional CMOS counter for 16 nm node. As a result, clear scalability of the proposed MTJ based multi-bit counter is obtained from the viewpoint of suppressing power. (C) 2012 The Japan Society of Applied Physics

A novel nonvolatile static random access memory cell is proposed that consists of four transistors and two spin-transfer-torque magnetic tunnel junctions (STT-MTJs). In the case of the NFET driver cell, the free layers of the magnetic tunnel junctions are connected to the transistors' sources and drains to make the cell read-disturb free. The static power is totally eliminated as the power line is shut down during data hold. The static noise margin of the cell is calculated based on the experimental data on MTJ switching that is enhanced from the resistive load SRAM cell due to the MTJ's switching operation. The cell size is estimated to become smaller than the 6-transistor SRAM cell when it is designed at 45nm node and beyond owing to the MTJ's area shrink as well as the thinning of its tunnel dielectrics (MgO). (C) 2012 The Japan Society of Applied Physics

An extremely practical simulation program with integrated circuits emphasis (SPICE) incorporating model parameters of magnetic tunnel junction (MTJ) was developed. The simulator provides reliable simulation results in spintronics circuit design because it can accurately calculate various MTJ characteristics that actual devices have, that considerably influence the operation margin and power dissipation. It can also accelerate the simulation speed, which makes it possible to simulate three times or more large-scale circuits than when a conventional macro-model is used.

Methods to generate an accurate reference current by averaging multi-pair dummy cells' currents for distinguishing the data in sense amplifiers (S/As) of a large scale memory with resistance change cell is presented and analyzed. The predicted characteristics are confirmed by comparing them with measurement results of the functionalities and the retention time distributions in a floating body random access memory (FBRAM). The methods are found to be especially effective in situations where signals are seriously degraded such as in sensing the signals of tail bit cells in retention time distributions, making the retention time performance of the FBRAM improved drastically. The sense amplifiers which can accommodate the dummy cell averaging methods are identified to find a necessary condition for a S/A to afford the methods.

The cell-to-cell leakage caused by bipolar disturb of the floating-body cell (FBC) has been investigated. In the case of FBC without silicide at the source and drain regions, the change of data "0" to data "1" has been observed in the writing operation to the adjacent cell. However, this leakage can be reduced when the silicide is formed on the thin silicon film at the source and drain regions. It has been clarified that the diffusion of holes inside the n(+) region is restricted by the capture of holes at the silicide/silicon interface when silicon thickness reduces. Based on these experimental results, 6F(2) layout of FBC can be realized with the conventional logic device process platform.

Physics of autonomous refresh is presented, which explains the mechanism of a spontaneous recovery of degraded binary states of the floating-body cell (FBC). Input current to the floating body and output current from the body balance to generate an unstable stationary state that is accompanied by two stable stationary ones. The current anomaly of impact ionization is essential for the instability that brings about the bistability and is realized by positive feedback where impact ionization current input increases as the body voltage increases. Experiments with charge pumping current as output show that the autonomous refresh is possible on a single-cell basis. Necessary conditions for a high-density memory to be autonomously refreshed are derived and assessed for state-of-the-art FBCs. FBC is shown in simulation to become an SRAM cell when the autonomous refresh is applied, which uses gate direct tunneling current as output. This is an SRAM cell that is theoretically expected to have the simplest structure ever reported.

Floating body cell (FBC) is a one-transistor memory cell on SOI substrate aimed at high-density embedded memory on SOC. In order to verify this memory cell technology, a 128 Mb floating body RAM (FBRAM) with FBC has been designed and successfully developed. The memory cell design and the experimental results, including single-cell operation, are reviewed. Based on the experimental results, the scalability of FBC down to 32 nm technology node is also discussed. (C) 2009 Elsevier Ltd. All rights reserved.

Cell array architecture for floating body RAM of 35nm bit line half pitch is described. The quasi-non-destructive-read-out feature of floating body cell contributes to eliminating inter-bit fine coupling noise in open bit line architecture without degrading the cycle time of the RAM.

A scaling scenario of fully-depleted floating body cell (FBC) is demonstrated in view of signal margin for stable array functionality. Measurement and numerical simulation reveal that the V-th variation of cell array transistors is mainly attributed to the random dopant fluctuation In channel region. By setting the channel impurity concentration in the order of 10(16) cm(-3) or lower, Gbit array functionality is guaranteed for the 32nm node and further scaled generations.

Floating Body Cell (FBC) is a one-transistor memory cell on SOI substrate, which aims high density embedded memory on SOC. In order to verify this memory cell technology, a 128Mb Floating Body RAM (FBRAM) with FBC has been designed and successfully developed. The memory cell design and the experimental results, including single cell (1Cell/Bit) operation, are reviewed. Based on the experimental results, the scalability of FBC is also discussed.

Physics of autonomous refresh of FBC is presented. Current input to the floating body by impact ionization and output by charge pumping can balance to make FBC refresh by itself without sense amplifier operation. Thanks to this feature, multiple cells on a 131, can be refreshed simultaneously, leading to a drastic reduction of BL charging current compared to the conventional refresh. 600 mu A refresh current for IG-bit memory is achieved in 32nm technology node with 4ms retention time. If gate direct tunneling current is used as output, FBC can realize static RAM without periodical refresh when retaining data.

A 128-Mb silicon-on-insulator dynamic random access memory with floating-body cell (FBC) has been successfully developed for the first time. Two technologies have been newly implemented, namely: 1) the optimized well structure and 2) Cu wiring. The well design has been optimized both for the array device and the peripheral circuit in order to realize full functionality and good retention characteristics. Cu wiring has been used for the bit line and the source line, which increases the signal of the worst bit in the array and also realizes full compatibility with the standard CMOS process. Scalability of FBC down to 45-nm CMOS technology node has been investigated by a device simulation. The signal and the maximum electric field can be maintained constant with the reduction of the device dimensions and the operation voltage.

A 6F(2) single cell (one-cell-per-bit) operation of the floating body RAM (FBRAM) is successfully demonstrated for the first time with more than 60% yield of 16Mbit area in a wafer The signal sense margin (SSM) at actual read conditions is found to well back up the functional results. The parasitic resistance in the source and drain formed under the FBC's spacers can be optimized for making the SSM as large as 8 mu A at +/-4.5 sigma without sacrificing the retention time.

A 128-Mb SOI DRAM has been developed featuring the floating body cell (FBC). To keep the cell data state from being degraded by the word-line (WL) disturb due to the charge pumping and to reduce the refresh busy rate, a sense amplifier (S/A) is arranged for every bit-line (BL) and replenishes data "1" cells' bodies with holes which are lost by the disturb in every read and write cycle. The power is reduced by operating the S/As asymmetrically between the selected and the unselected thanks to that the number of holes to be replenished in the unselected S/As for charge pumping is two order of magnitude smaller than that required for writing the data "1". The multi-pair averaging of dummy cells generates a very accurate reference current for distinguishing the data "1" and "0" and a Monte Carlo simulation shows that it achieves a sensing scheme robust enough to realize all good parts of the DRAM with a reasonable amount of redundancy. The cell's feature of quasi-nondestructive read-out is also advantageous for making an SRAM interface of the DRAM or hiding refresh from uses without sacrificing the access time.

Technologies and improved performance of the Floating Body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb chip yield of 68% has been obtained. Device simulation proves that the Floating Body Cell is scalable to the 32nm node keeping signal margin (threshold voltage difference) and data retention time constant.

Floating Body Cell (FBC) is a one-transistor memory cell on SOI substrate, which aims high density embedded memory on SOC. In order to verify this memory cell technology, a 128Mb SOI DRAM with FBC has been designed and successfully developed. The memory cell design, and the experimental results, such as the signal and the retention characteristics, are reviewed. The results of the fabricated SOI DRAM and the prospect as embedded memory are also discussed.

A one-transistor memory cell on silicon-on-insulator, called Floating Body Cell (FBC), has been developed for high density embedded DRAM applications. The functionality of a 128Mb FBC DRAM using fully compatible 90mn CMOS technology has been successfully demonstrated. The memory cell design, such as fully-depleted (FD) operation with substrate-bias, and the process integration, such as well and Cu wiring, are reviewed. The scalability and future challenge of FBC technology are discussed as well.

A one-transistor memory cell on silicon-on-insulator, called floating-body cell (FBC), has been developed and demonstrated. Threshold voltage difference between the "0"-state and the "1"-state, which is a key parameter for realizing a larger scale memory by FBCs, is measured and analyzed using a 96 kb array diagnostic monitor (ADM). A function test of the ADM yielded a fail-bit probability of 0.002%. A new metric relating to the fail-bit probability, that is, the ratio of the threshold voltage difference over the total threshold voltage variation, is introduced and applied to the measurement results. Read current distributions are also evaluated for various operation voltages. This paper also investigates substrate bias dependence of the threshold voltage unique to fully-depleted devices. Channel impurity and substrate impurity concentration dependence of the threshold voltage are analyzed based on experimental data and device simulation.

A Monte Carlo simulation shows that a DRAM using the floating body cell (FBC) realizes a 333MHz high-speed random cycle with an introduction of a symmetrical sense amplifier circuit and optimization of its current mirror ratio. Since the FBC DRAM having a superior affinity with logic LSI process is also shown to have its macro size smaller than the conventional 1T-1C DRAM, the FBC is a promising candidate for next generation embedded DRAM cells. © 2005 IEEE.

A 128Mb SOI DRAM with FBC (Floating Body Cell) has been successfully developed for the first time. Two technologies have been newly implemented. (i)In order to realize full functionality and good retention characteristics, the well design has been optimized both for the array device and the peripheral circuit. (ii)Cu wiring has been used for Bit Line(BL) and Source Line(SL), which leads to increasing the signal of the worst bit in the array and also realizes the full compatibility with 90nm CMOS Technology.

Fully-depleted (FD) Floating Body Cell on 55nm SOI featuring excellent logic process compatibility has been successfully developed. For the first time FD operation is reported through significant signal enlargement by negative substrate bias. Using standard salicide process and FD operation, high-density embedded memory on SOI is achievable.

A 288Kbit memory chip featuring a one-transistor gain cell on SOI of the size 0.21 mu m(2) (7F(2) with F=0.175 mu m) which we named the floating body transistor cell(FBC) is presented and basic characteristics of the cell and the memory chip performance are disclosed. The threshold voltages of a cell transistor in the chip for the data "1" and for the data "0" are measured by using a direct access test circuit and a fail bit map for the 96Kbit array is obtained. A sensing scheme which was designed to eliminate the effect of cell characteristics variation due to process and temperature fluctuation as common mode noise is verified to be working and the random access time is measured to be less than 100ns. The characteristics of data hold demonstrate that the FBC can satisfy retention time specifications for some embedded memories. The access time and the data retention time show that the FBC has a potential to be used as a future embedded DRAM memory cell.

A 512-kb memory has been developed featuring a one-transistor gain cell of size 7F(2) (F = 0. 18 mum) on SOI. The cell named the floating body transistor cell (FBC) has the ability to achieve a 4F(2) cell using self-aligned contact technologies and is proved to be scalable with respect to a cell signal. A basic operation was verified by device simulation and hardware measurement. An array driving method is disclosed which makes selective write possible. A cell signal sensing system consisting of a pair of reference cells written opposite data and comparing the combined current with the doubled cell current is shown to be robust against cell parameter variations in process and temperature. A random access time of 40 ns was simulated. Nondestructive readout and C-b/C-s free signal development drastically improve cell efficiency.

This paper proposes a small 1/4 Vcc bit-line swing scheme and a related sense amplifier scheme for low power 1 V operating DRAM. Using the proposed small bit-line swing scheme, the stress bias of memory cell transistor and capacitor is reduced to half that of the conventional DRAM, resulting in improvement of device reliability. The proposed sense amplifier scheme achieves high speed and stable sensing/restoring operation at 250mV bit-line swing, which is much smaller than threshold voltage. The proposed scheme reduces the total power dissipation of bit-line sensing/restoring operation to 40% of the conventional one. This paper also proposes a small 4F(2) size memory cell and a new twisted bit-line scheme. The array noise is reduced to 8.6% of the conventional DRAM.

A 12-MHz data-cycle 4-Mb DRAM with pipeline operation has been designed and fabricated using 0.8-mu-m twin-tub CMOS technology. The pipeline DRAM outputs data corresponding to addresses that were accepted in the previous RAS cycle. The latter half of the previous read operation and the first half of the next read operation take place simultaneously, so the RAS cycle time is reduced. This pipeline DRAM technology needs no additional chip area and no process modification. A 95-ns RAS cycle time was obtained under worst conditions while this value is 125 ns for conventional DRAM's.

A novel capacitance-resistance (CR-) delay circuit technology for high-density DRAM’s has been developed as a method to assure full asynchronicity between memory cell array and peripheral circuits over a wide range of both operating and process conditions, and thus, to realize a fast access time. A unique noise compensation scheme is introduced to the CR-delay circuit to generate a constant delay even under the power supply line noise. This CR-delay circuit was applied to the 4-Mbit DRAM peripheral circuit. As a result, a timing loss as well as a malfunction could be successfully avoided, and 7 ns faster access time and 39 ns shorter cycle time have been achieved, compared with a conventional design using normal inverter chains. © 1989 IEEE

A novel 2-bit (four-level)/cell storage technique is described. This technique saves the RAM area, in particular the cell array area which is highly defect sensitive provides fairly fast access time. An experimental 1-Mbit DRAM has been fabricated and has successfully demon-strated the feasibility of this technique for embedded memory applications. ©1989 IEEE

A new on-chip voltage converter has been developed and its characteristics have been examined. The converter is a feedback-type voltage regulator, and it supplies a reduced voltage to an entire RAM circuit. A novel timing activation method was introduced to save power. The converter has been implemented on an experimental 4-Mbit dynamic RAM. It was found that an even faster access time and higher reliability compared to a conventional design could be achieved by using an on-chip voltage converter and shorter channel transistors. This voltage converter is suitable for high-density, high-speed, and high-reliability DRAM's with submicrometer transistors. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.

A 4-Mbit CMOS DRAM measuring 6.9×16.11 mm2 has been fabricated using a 0.9-µm twin-tub CMOS, triple-poly, single-metal process technology. N-channel depletion-type trench cells, 2.5 × 5.5 µm2 each, are incorporated in a p-well. A novel built-in self-test (BIST) function which enables a simultaneous and automatic test of all the memory devices on a board is introduced to reduce the RAM testing time in a system. This function is effective for system maintenance and a daily start-up test even in a relatively small system. A high-speed low-power 4-Mbit CMOS DRAM with 60-ns access time, 50-mA active current, and 200-µA standby current is realized by widening the DQ line bus which connects the sense amplifiers with the DQ buffers, thereby reducing the parasitic capacitance of the DQ lines. Copyright © 1987 by The Institute of Electrical and Electronics, Inc.

A 4-Mbit dynamic RAM has been designed and fabricated using 1.0-μm twin-tub CMOS technology. The memory array consists of trenched n-channel depletion-type capacitor cells in a p-well. Very high α-particle immunity was achieved with this structure. One cell measures 3.0×5.8 µm2 yielding a chip size of 7.84 x 17.48 mm2. An on-chip voltage converter circuit was implemented as a mask option to investigate a possible solution to the MOSFET reliability problem caused by hot carriers. An 8-bit parallel test mode was introduced to reduce the RAM test time. Metal mask options provide static column mode and fast page mode operation. The chip is usable as ×1 or ×4 with a bonding option. Using an external 5-V power supply, the RAS access time is 80 ns at room temperature. Typical active current is 60 mA at a 220-ns cycle time with a standby current of 0.5 mA. Copyright © 1986 by the Institute of Electrical and Electronics Engineers, Inc.

Propagation of a light ion beam in a plasma is investigated theoretically. The basic principle determining the steady state of the beam transport in a plasma is ascertained from the view points of the theory of the irreversible processes. As a preliminary work to discuss the collisional plasma, we consider a state in which the entropy production vanishes and obtain an extended result of Chen and Davidson to include the current due to the drift of the plasma electrons. Two extreme cases are considered: (i) No rotation of the beam around the axis of symmetry or complete neutralization of azimuthal beam current by the plasma electron. (ii) Complete balancing of the electrostatic repulsive force on a beam ion and the magnetically pinching force due to the axial beam current. It is shown that the distribution of ions in a rotational ion beam is given by the Bennett type, provided the current is over-neutralized azimuthally. © 1983, THE PHYSICAL SOCIETY OF JAPAN. All rights reserved.

The rotational motion of a light ion beam and a plasma immersed in a uniform magnetic field is investigated within the framework of the macroscopic fluid equations including force terms due to radial pressure variations. Drift motion caused by the radial electric and magnetic forces rotates the beam fluid element and the plasma electron fluid element in the same azimuthal direction. The motion leads to the over-neutralization of the azimuthal beam current by the plasma electron current. It is found that the ion beam is compact and never hollowed out in over-neutralized states. The radial density profiles of the beam are obtained and the condition for radially confined equilibria in those over-neutralized states is examined. © 1983, THE PHYSICAL SOCIETY OF JAPAN. All rights reserved.

A nonlinear theory is presented which shows mode-locking of a naturally excited instability by an externally launched wave whose frequency is around that of the instability. A procedure to remove secular solutions leads to a couple of nonlinear equations which describe slow-time evolutions of amplitudes. A stably stationary solution of these equations is investigated to show qualitative agreement with published experiments; the external field strength at which the instability vanishes increases as the frequency discrepancy between the instability and the external wave |Ω-ω0| increases, and a relation Aa2+Bb2=1 is obtained between the amplitude of the instability a and that of the externally excited wave b where the ratio B/A depends on the frequency discrepancy in the form (Ω-ω0)−2. © 1980, THE PHYSICAL SOCIETY OF JAPAN. All rights reserved.

The density oscillations in a system composed of a one-dimensional cold electron plasma and a cold electron beam are considered where the beam is assumed to be modulated sinusoidally and also to be bounded by a repeller in the plasma. A nonlinear differential equation which describes the density oscillations in the beam-plasma system is derived from the Vlasov and Poisson equations. The equation does not take the so-called van der Pol-type, but is, as one of the linear approximations, reduced to a Mathieu-type equation with an inhomogeneous term: d2ρ⁄dt2+ωe2[1−σ cos (ωt)]ρ=σ(ω2−ωe2) cos (ωt). This inhomogeneous Mathieu equation is analyzed by the method of Bogoliubov and Mitropolsky. The spectrum of the characteristic frequency obtained from the analysis is compared with the experimental results. © 1979, THE PHYSICAL SOCIETY OF JAPAN. All rights reserved.