2022/11/29 更新

写真a

オオサワ タカシ
大澤 隆
Scopus 論文情報  
論文数: 0  Citation: 0  h-index: 10

Citation Countは当該年に発表した論文の被引用数

所属
理工学術院 大学院情報生産システム研究科
職名
教授(任期付)

他学部・他研究科等兼任情報

  • 理工学術院   基幹理工学部

学内研究所・附属機関兼任歴

  • 2020年
    -
    2022年

    理工学術院総合研究所   兼任研究員

学位

  • 筑波大学   博士(工学)

 

研究分野

  • 計算機システム

論文

  • Co-Design of Binary Processing in Memory ReRAM Array and DNN Model Optimization Algorithm

    Yue Guan, Takashi Ohsawa

    IEICE TRANSACTIONS ON ELECTRONICS   E103C ( 11 ) 685 - 692  2020年11月

     概要を見る

    In recent years, deep neural network (DNN) has achieved considerable results on many artificial intelligence tasks, e.g. natural language processing. However, the computation complexity of DNN is extremely high. Furthermore, the performance of traditional von Neumann computing architecture has been slowing down due to the memory wall problem. Processing in memory (PIM), which places computation within memory and reduces the data movement, breaks the memory wall. ReRAM PIM is thought to be a available architecture for DNN accelerators. In this work, a novel design of ReRAM neuromorphic system is proposed to process DNN fully in array efficiently. The binary ReRAM array is composed of 2T2R storage cells and current minor sense amplifiers. A dummy BL reference scheme is proposed for reference voltage generation. A binary DNN (BDNN) model is then constructed and optimized on MNIST dataset. The model reaches a validation accuracy of 96.33% and is deployed to the ReRAM PIM system. Co-design model optimization method between hardware device and software algorithm is proposed with the idea of utilizing hardware variance information as uncertainness in optimization procedure. This method is analyzed to achieve feasible hardware design and generalizable model. Deployed with such co-design model, ReRAM array processes DNN with high robustness against fabrication fluctuation.

    DOI

  • Array Design of High-Density Emerging Memories Making Clamped Bit-Line Sense Amplifier Compatible with Dummy Cell Average Read Scheme

    Ziyue Zhang, Takashi Ohsawa

    IEICE TRANSACTIONS ON ELECTRONICS   E103C ( 8 ) 372 - 380  2020年08月

     概要を見る

    Reference current used in sense amplifiers is a crucial factor in a single-end read manner for emerging memories. Dummy cell average read scheme uses multiple pairs of dummy cells inside the array to generate an accurate reference current for data sensing. The previous research adopts current minor sense amplifier (CMSA) which is compatible with the dummy cell average read scheme. However, clamped bit-line sense amplifier (CBLSA) has higher sensing speed and lower power consumption compared with CMSA. Therefore, applying CBLSA to dummy cell average read scheme is expected to enhance the performance. This paper reveals that direct combination of CBLSA and dummy cell average read scheme leads to sense margin degradation. In order to solve this problem, a new array design is proposed to make CBLSA compatible with dummy cell average read scheme. Current minor structure is employed to prevent CBLSA from being short-circuited directly. The simulation result shows that the minimum sensible tunnel magnetoresistance ratio (TMRR) can be extended from 14.3% down to 1%. The access speed of the proposed sensing scheme is less than 2 ns when TMRR is 70% or larger, which is about twice higher than the previous research. And this circuit design just consumes half of the energy in one read cycle compared with the previous research. In the proposed array architecture, all the dummy cells can be always short-circuited in totally isolated area by low-resistance metal wiring instead of using controlling transistors. This structure is able to contribute to increasing the dummy cell averaging effect. Besides, the array-level simulation validates that the array design is accessible to every data cell. This design is generally applicable to any kinds of resistance-variable emerging memories including STT-MRAM.

    DOI

    Scopus

  • Cell Array Design with Row-Driven Source Line in Block Shunt Architecture Applicable to Future 6F(2) 1T1MTJ Memory

    Tongshuang Huang, Takashi Ohsawa

    2019 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA)    2019年

     概要を見る

    In this paper, we propose a new 1T1MTJ cell array architecture with SL parallel to WL to achieve a small cell size, in which page mode write can be realized without performance degradation. We propose a row-driven source line (RSL) 1T1MTJ memory cell array architecture for minimizing the cell size and a corresponding operational waveform. A block shunt architecture (BSA) that shunts lower source line (LSL) and upper source line (USL) is proposed to make page mode write possible. Size of 1T1MTJ cell can be shrunk to 6F(2) when the state-of-the-art design rules are applied.

  • User-Friendly Compact Model of Magnetic Tunnel Junctions for Circuit Simulation Based on Switching Probability

    Haoyan Liu, Takashi Ohsawa

    2019 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)    2019年

     概要を見る

    We propose a new compact MTJ model for circuit simulation which is implemented by Verilog-A and can be easily built in de-facto standard SPICE. The model is based on switching probability of an MTJ with time-varying input current. The transition between the adiabatic precessional model and the thermal activation model is made smooth by using an interpolation function with a technique to predict a switching time from an input current. Simulation results validate that the model is consistent with physical model and effective for MTJ/CMOS hybrid circuit simulation.

  • A new read scheme for high-density emerging memories

    Takashi Ohsawa

    IEICE Transactions on Electronics   E101C ( 6 ) 423 - 429  2018年06月

     概要を見る

    Several new memories are being studied as candidates of future DRAM that seems difficult to be scaled. However, the read signal in these new memories needs to be amplified in a single-end manner with reference signal supplied if they are aimed for being applied to the high-density main memory. This scheme, which is fortunately not necessary in DRAM's 1/2Vdd pre-charge sense amp, can become a serious bottleneck in the new memory development, because the device electrical parameters in these new memory cells are prone to large cell-to-cell variations without exception. Furthermore, the extent to which the parameter fluctuates in data “1” is generally not the same as in data “0”. In these situations, a new sensing scheme is proposed that can minimize the sensing error rate for high-density single-end emerging memories like STT-MRAM, ReRAM and PCRAM. The scheme is based on averaging multiple dummy cell pairs that are written “1” and “0” in a weighted manner according to the fluctuation unbalance between “1” and “0”. A detailed analysis shows that this scheme is effective in designing 128Mb 1T1MTJ STT-MRAM with the results that the required TMR ratio of an MTJ can be relaxed from 130% to 90% for the fluctuation of 6% sigma-to-average ratio of MTJ resistance in a 16 pair-dummy cell averaging case by using this technology when compared with the arithmetic averaging method.

    DOI

    Scopus

    1
    被引用数
    (Scopus)
  • Power-gated 32 bit microprocessor with a power controller circuit activated by deep-sleep-mode instruction achieving ultra-low power operation

    Hiroki Koike, Takashi Ohsawa, Sadahiko Miura, Hiroaki Honjo, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

    JAPANESE JOURNAL OF APPLIED PHYSICS   54 ( 4 )  2015年04月

     概要を見る

    A spintronic-based power-gated micro-processing unit (MPU) is proposed. It includes a power control circuit activated by the newly supported power-off instruction for the deep-sleep mode. These means enable the power-off procedure for the MPU to be executed appropriately. A test chip was designed and fabricated using 90nm CMOS and an additional 100nm MTJ process; it was successfully operated. The guideline of the energy reduction effects for this MPU was presented, using the estimation based on the measurement results of the test chip. The result shows that a large operation energy reduction of 1/28 can be achieved when the operation duty is 10%, under the condition of a sufficient number of idle clock cycles. (C) 2015 The Japan Society of Applied Physics

    DOI

    Scopus

    8
    被引用数
    (Scopus)
  • A 500ps/8.5ns Array Read/Write Latency 1Mb Twin 1T1MTJ STT-MRAM designed in 90nm CMOS/40nm MTJ Process with Novel Positive Feedback S/A Circuit

    T. Ohsawa, S. Miura, H. Honjo, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh

    International Conference on Solid State Dvices and Materails (SSDM)   A-8-3  2014年09月  [査読有り]

  • 磁気ランダムアクセスメモリ(MRAM)の最新技術動向

    小池洋紀, 大澤隆, 池田正二, 羽生貴弘, 大野英男, 遠藤哲郎

    電子情報通信学会2014年ソサイエティ大会 エレクトロニクス講演論文集2   CT-1-3   SS-6-9  2014年09月  [招待有り]

  • Trend of tunnel magnetoresistance and variation in threshold voltage for keeping data load robustness of metal-oxide-semiconductor/magnetic tunnel junction hybrid latches

    T. Ohsawa, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh

    JOURNAL OF APPLIED PHYSICS   115 ( 17 )  2014年05月

     概要を見る

    The robustness of data load of metal-oxide-semiconductor/magnetic tunnel junction (MOS/MTJ) hybrid latches at power-on is examined by using Monte Carlo simulation with the variations in magnetoresistances for MTJs and in threshold voltages for MOSFETs involved in 90 nm technology node. Three differential pair type spin-transfer-torque-magnetic random access memory cells (4T2MTJ, 6T2MTJ, and 8T2MTJ) are compared for their successful data load at power-on. It is found that the 4T2MTJ cell has the largest pass area in the shmoo plot in TMR ratio (tunnel magnetoresistance ratio) and V-dd in which a whole 256 kb cell array can be powered-on successfully. The minimum TMR ratio for the 4T2MTJ in 0.9V < V-dd < 1.9V is 140%, while the 6T2MTJ and the 8T2MTJ cells require TMR ratio larger than 170%. (C) 2014 AIP Publishing LLC.

    DOI

    Scopus

    12
    被引用数
    (Scopus)
  • Studies on read-stability and write-ability of fast access STT-MRAMs

    T. Ohsawa, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh

    2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)     1 - 2  2014年04月  [査読有り]

    DOI

    Scopus

    2
    被引用数
    (Scopus)
  • 1.5ns/2.1nsのランダム読出/書込サイクル時間を達成した不揮発性混載メモリ用1Mb STT-MRAM -6T2MTJセルにバックグラウンド書き込み(BGW)方式を適用

    大澤隆, 小池洋紀, 三浦貞彦, 木下啓藏, 本庄弘明, 池田正二, 羽生貴弘, 大野英男, 遠藤哲郎

    信学技報   114 ( 13 ) 33 - 38  2014年04月  [査読有り]  [招待有り]

  • MTJベース不揮発フリップフロップを用いた3μsec-Entry/Exit 遅延時間のマイクロプロセッサ

    小池洋紀, 崎村昇, 根橋竜介, 辻幸秀, 森岡あゆ香, 三浦貞彦, 本庄弘明, 杉林直彦, 大澤隆, 池田正二, 羽生貴弘, 大野英男, 遠藤哲郎

    信学技報   114 ( 13 ) 85 - 90  2014年04月  [査読有り]  [招待有り]

  • Wide operational margin capability of 1 kbit spin-transfer-torque memory array chip with 1-PMOS and 1-bottom-pin-magnetic-tunnel-junction type cell

    Hiroki Koike, Takashi Ohsawa, Sadahiko Miura, Hiroaki Honjo, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

    JAPANESE JOURNAL OF APPLIED PHYSICS   53 ( 4 )  2014年04月

     概要を見る

    This paper discusses the optimal combination of 1 transistor (T) and 1 magnetic tunnel junction (MTJ) type cell for spin transfer torque memory. Taking into consideration of current magnitude for both the T and the MTJ, either PMOS-bottom pin structure or NMOS-top pin structure can be a promising choice. Focusing on the PMOS-bottom pin structure from the viewpoint of avoiding process difficulty, we clarified the condition that the structure would be effective. In order to verify the structure's effectiveness, a stand-alone MTJ test element group and a 1 kbit memory array chip were designed and fabricated with 90nm CMOS/100nm MTJ process. With the pass bit percentage measurement of the memory chip, we successfully demonstrated that 1-PMOS and 1-bottom-pin-MTJ has the wide operation margin of 100% pass at near 1.6V. It will be an effective solution for 1T-1MTJ memories. (C) 2014 The Japan Society of Applied Physics

    DOI

    Scopus

    10
    被引用数
    (Scopus)
  • Power reduction by power gating in differential pair type spin-transfer-torque magnetic random access memories for low-power nonvolatile cache memories

    Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

    JAPANESE JOURNAL OF APPLIED PHYSICS   53 ( 4 )  2014年04月

     概要を見る

    Array operation currents in spin-transfer-torque magnetic random access memories (STT-MRAMs) that use four differential pair type magnetic tunnel junction (MTJ)-based memory cells (4T2MTJ, two 6T2MTJs and 8T2MTJ) are simulated and compared with that in SRAM. With L3 cache applications in mind, it is assumed that the memories are composed of 32 Mbyte capacity to be accessed in 64 byte in parallel. All the STT-MRAMs except for the 8T2MTJ one are designed with 32 bit fine-grained power gating scheme applied to eliminate static currents in the memory cells that are not accessed. The 8T2MTJ STT-MRAM, the cell's design concept being not suitable for the fine-grained power gating, loads and saves 32 Mbyte data in 64 Mbyte unit per 1 Mbit sub-array in 2 x 10(3) cycles. It is shown that the array operation current of the 4T2MTJ STT-MRAM is 70mA averaged in 15 ns write cycles at V-dd = 0.9V. This is the smallest among the STT-MRAMs, about the half of the low standby power (LSTP) SRAM whose array operation current is totally dominated by the cells' subthreshold leakage. (C) 2014 The Japan Society of Applied Physics

    DOI

    Scopus

    6
    被引用数
    (Scopus)
  • A two-transistor bootstrap type selective device for spin-transfer-torque magnetic tunnel junctions

    Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

    JAPANESE JOURNAL OF APPLIED PHYSICS   53 ( 4 )  2014年04月

     概要を見る

    Two-transistor bootstrap type selective device for spin-transfer-torque magnetic tunnel junctions (STT-MTJs) is proposed that is smaller than the conventional ones with equivalent performance. The power supply voltage dependence of the area for the two-NFET bootstrap type selective device that can switch MTJs within 10 ns is compared with those of the conventional single-NFET, single-PFET, and CMOS type selective devices with the same performance in 90nm technology node. It is found that the two-NFET bootstrap type selective device can be smaller than the conventional ones especially for the power supply voltage equal to or lower than 0.9V. The two-NFET bootstrap type selective device is shown to maintain scalability to 32nm node just like the CMOS one, while the conventional single-NFET and single-PFET selective devices fail to be scaled properly. This selective device can be applied to every high-performance MOS/MTJ hybrid circuit for increasing the integration density. (C) 2014 The Japan Society of Applied Physics

    DOI

    Scopus

    3
    被引用数
    (Scopus)
  • A Power-Gated MPU with 3-microsecond Entry/Exit Delay using MTJ-Based Nonvolatile Flip-Flop

    Hiroki Koike, Takashi Ohsawa, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Katsuya Miura, Hiroaki Honjo, Tadahiko Sugibayashi, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

    IEEE Asian Solid-State Circuits Conference (ASSCC2013)     317 - 320  2013年11月  [査読有り]

    DOI

    Scopus

    22
    被引用数
    (Scopus)
  • Trend of TMR and Variation in Vth for Keeping Data Load Robustness of MOS/MTJ Hybrid Latches

    Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

    The 58th Annual Magnetism and Magnetic Materials Conference (MMM2013)   GT-10   693 - 693  2013年11月  [査読有り]

  • MTJ resistance distribution and its bit error rate of 1-kbit 1T-1MTJ STT-MRAM cell arrays fabricated on a 300-mm wafer

    H. Koike, T. Ohsawa, S. Miura, H. Honjo, S. Ikeda, T. Hanyu, H. Ohno

    58th Annual Conference on Magnetism & Magnetic Materials Abstract    2013年11月  [査読有り]

  • Strategy of STT-MRAM Cell Design and Its Power Gating Technique for Low-Voltage and Low-Power Cache Memories

    Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetuso Endoh

    2013 International Conference on Solid State Devices and Materials (SSDM)   M-7-1   1090 - 1091  2013年09月  [査読有り]

  • Studies on Selective Devices for Spin-Transfer-Torque Magnetic Tunnel Junctions

    Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetuso Endoh

    2013 International Conference on Solid State Devices and Materials (SSDM)   M-8-4   1104 - 1105  2013年09月  [査読有り]

  • A 4x4 Nonvolatile Multiplier Using Novel MTJ-CMOS Hybrid Latch and Flip-Flop

    Takashi Ohsawa, Sadahiro Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetuso Endoh

    2013 International Conference on Solid State Devices and Materials (SSDM)   M-6-3   1086 - 1087  2013年09月  [査読有り]

  • Wide Operational Margin Capability of 1kbit STT-MRAM Array Chip with 1-PMOS and 1-Bottom-Pin-MTJ Type Cell

    Hiroki Koike, Takashi Ohsawa, Sadahiro Miura, Hiroaki Honjo, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetuso Endoh

    2013 International Conference on Solid State Devices and Materials (SSDM)   M-7-3   1094 - 1095  2013年09月  [査読有り]

  • IEEE Journal of Solid-State Circuits

    T. Ohsawa, H. Koike, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh

    A 1 Mb nonvolatile embedded memory using 4T2MTJ cell with 32 b fine-grained power gating scheme   48 ( 6 ) 1511 - 1520  2013年06月  [査読有り]

  • A 1.5nsec/2.1nsec random read/write cycle 1Mb STT-RAM using 6T2MTJ cell with background write for nonvolatile e-memories

    Takashi Ohsawa, Sadahiro Miura, Keizo Kinoshita, Hiroaki Honjo, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetuso Endoh

    2013 Symposium on VLSI Technology (VLSIT) & 2013 Symposium on VLSI Cricuit (VLSIC) Digest of Technical Papers     C110 - C111  2013年06月  [査読有り]

  • Verification of Simulation Time Improvement for SPICE Simulator Using Built-in MTJ Model

    Hiroki Koike, Takashi Ohsawa, Tetsuo Endoh

    16th International Workshop on Computational Electronics (IWCE)     246 - 247  2013年06月  [査読有り]

  • A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme

    Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   48 ( 6 ) 1511 - 1520  2013年06月

     概要を見る

    A 1 Mb nonvolatile embedded memory using a four transistor and two spin-transfer-torque (STT) magnetic tunnel junction (MTJ) cell is designed and fabricated to demonstrate its zero standby power and high performance. The power supply voltages of 32 cells along a word line (WL) are controlled simultaneously by a power line (PL) driver to eliminate the standby power without impact on the access time. This fine-grained power gating scheme also optimizes the trade-off between macro size and operation power. The butterfly curve for the cell is measured to be asymmetric as predicted, enhancing the cell's static noise margin (SNM) for data retention. The scaling of 1 Mb macro size is compared with that of the 6T SRAM counterpart, indicating that the former will become smaller than the latter at 45 nm technology node and beyond by moderately thinning its tunnel dielectrics (MgO) in accordance with the shrink of the MTJ's cross sectional area. The operation current of the macro is also shown to be almost unchanged over generations, while that of the 6T SRAM increases exponentially due to the degradation of MOSFET off-current as the device scales.

    DOI

    Scopus

    66
    被引用数
    (Scopus)
  • A 1Mb STT-MRAM with Zero Array Standby Power and 1.5ns Quick Wake-up by 8b Fine-Grained Power Gating

    Takashi Ohsawa, Hiroki Koike, Takahiro Hanyu, Hideo Ohno, Tetuso Endoh

    5th IEEE International Memory Workshop (IMW)     80 - 83  2013年05月  [査読有り]

    DOI

    Scopus

    5
    被引用数
    (Scopus)
  • 不揮発性STT-MRAMの開発と今後の展望

    遠藤哲郎, 大澤隆, 伊賀文崇, 池田正二, 羽生貴弘, 大野英男

    応用物理学会・特別シンポジウム    2013年03月  [招待有り]

  • Two-step writing method for STT-MTJ to improve switching probability and write-speed

    Fumitaka Iga, Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

    The 3nd CSIS International Symposium on Spintronics-based VLSIs    2013年01月  [査読有り]

  • A fine-grained power gating architecture for MTJ-based embedded memories

    Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keiichi Tokutome, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

    The 3nd CSIS International Symposium on Spintronics-based VLSIs    2013年01月  [査読有り]

  • A New Sensing Scheme with High Signal Margin Suitable for Spin-Transfer Torque RAM

    Hiroki Koike, Takashi Ohsawa, Tetsuo Endoh

    The 3nd CSIS International Symposium on Spintronics-based VLSIs    2013年01月  [査読有り]

  • 600MHz Nonvolatile Latch Based on a New MTJ/CMOS Hybrid Circuit Concept

    Tetsuo Endoh, Shuta Togashi, Fumitaka Iga, Yasuhiro Yoshida, Takashi Ohsawa, Hiroki Koike, Shunsuke Fukami, Shoji Ikeda, Naoki Kasai, Noboru Sakimura, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

    The 3nd CSIS International Symposium on Spintronics-based VLSIs    2013年01月  [査読有り]

  • 省エネシステムのためのSTT-MRAMと、そのロジック応用

    遠藤哲郎, 小池洋紀, 大澤隆, 羽生貴弘, 笠井直記, 大野英男

    ゲートスタック研究会    2013年01月  [招待有り]

  • MTJ based Non Volatile Logic for Ultimate Power Management

    Tetsuo Endoh, Takashi Ohsawa, Takahiro Hanyu, Hideo Ohno

    the 19th International Conference on Magnetism with Strongly Correlated Electron Systems (ICM2012 with SCES)   Session BI02   5 - 7  2012年06月  [査読有り]  [招待有り]

  • Restructuring of Memory Hierarchy in Computing System with Spintronics-Based Technologies

    Tetsuo Endoh, Takashi Ohsawa, Hiroki Koike, Takahiro Hanyu, Hideo Ohno

    2012 Symposia on VLSI Technology and Circuits   T1003   89 - 90  2012年06月  [査読有り]  [招待有り]

    DOI

    Scopus

    32
    被引用数
    (Scopus)
  • 1Mb 4T-2MTJ Nonvolatile STT-RAM for Embedded Memories Using 32b Fine-Grained Power Gating Technique with 1.0ns/200ps Wake-up/Power-off Times

    T. Ohsawa, H. Koike, S. Miura, H. Honjo, K. Tokutome, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh

    2012 Symposium on VLSI Circuits, Digest of Technical Papers   J-C6.3   46 - 47  2012年06月  [査読有り]

    DOI

    Scopus

    58
    被引用数
    (Scopus)
  • MTJ based non volatile SRAM and low power non volatile logic-in-memory architecture

    Tetsuo Endoh, Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Naoki Kasai, Hideo Ohno

    IEEE International Magnetics Conference (INTERMAG2012)     HB-06 - HB-06  2012年05月  [査読有り]  [招待有り]

  • Low Power Nonvolatile Counter Unit with Fine-Grained Power Gating

    Shuta Togashi, Takashi Ohsawa, Tetsuo Endoh

    IEICE TRANSACTIONS ON ELECTRONICS   E95C ( 5 ) 854 - 859  2012年05月

     概要を見る

    In this paper, we propose a new low power nonvolatile counter unit based on Magnetic Tunnel Junction (MTJ) with fine-grained power gating. The proposed counter unit consists of only a single latch with two MTJs. We verify the basic operation and estimate the power consumption of the proposed counter unit. The operating power consumption of the proposed nonvolatile counter unit is smaller than the conventional one below 140 kHz. The power of the proposed unit is 74.6% smaller than the conventional one at low frequency.

    DOI

    Scopus

  • Proposal of New MTJ-Based Nonvolatile Memories

    T. Ohsawa, H. Koike, T. Hanyu, S. Ikeda, H. Ohno, T. Endoh

    The 2nd CSIS International Symposium on Spintronics-based VLSIs   F6   23 - 23  2012年02月  [査読有り]  [招待有り]

  • Nonvolatile Low Power 16-bit/32-bit Binary Counter with MTJ and its Scalability

    Shuta Togashi, Takashi Ohsawa, Tetsuo Endoh

    The 2nd CSIS International Symposium on Spintronics-based VLSIs   P20   46 - 46  2012年02月  [査読有り]

  • A Study for Adopting PMOS Memory Cell for 1T1R STT-RAM with Asymmetric Switching Current MTJ

    H. Koike, T. Ohsawa, T. Endoh

    The 2nd CSIS International Symposium on Spintronics-based VLSIs   P21   47 - 47  2012年02月  [査読有り]

  • Nonvolatile Low Power 16-bit/32-bit Magnetic Tunnel Junction Based Binary Counter and Its Scaling

    Shuta Togashi, Takashi Ohsawa, Tetsuo Endoh

    JAPANESE JOURNAL OF APPLIED PHYSICS   51 ( 2 )  2012年02月

     概要を見る

    We propose a nonvolatile 16-bit/32-bit magnetic tunnel junction (MTJ) based binary counter with fine-grained power gating scheme suitable for MTJ. We estimate the power consumption of the proposed counter by using simulation program with integrated circuit emphasis (SPICE) simulation. The power of the proposed 16-bit/32-bit counter is 59.1 and 72.5% smaller in case of 45 and 16 nm node, respectively, than that of the conventional complementary metal oxide semiconductor (CMOS) counter at low frequency (100 Hz). The proposed nonvolatile 32-bit counter achieves lower power at operating frequencies up to 49 kHz and 4 MHz in the case of 45 and 16 nm node, respectively, in comparison with the conventional CMOS counter. Moreover, we propose a hybrid 32-bit counter that is constructed with CMOS counter units for the beginning stages and nonvolatile MTJ based counter units for the latter stages. It achieves a lower power at operating frequencies up to 1 GHz than the conventional CMOS counter for 16 nm node. As a result, clear scalability of the proposed MTJ based multi-bit counter is obtained from the viewpoint of suppressing power. (C) 2012 The Japan Society of Applied Physics

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  • High-Density and Low-Power Nonvolatile Static Random Access Memory Using Spin-Transfer-Torque Magnetic Tunnel Junction

    Takashi Ohsawa, Fumitaka Iga, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

    JAPANESE JOURNAL OF APPLIED PHYSICS   51 ( 2 )  2012年02月

     概要を見る

    A novel nonvolatile static random access memory cell is proposed that consists of four transistors and two spin-transfer-torque magnetic tunnel junctions (STT-MTJs). In the case of the NFET driver cell, the free layers of the magnetic tunnel junctions are connected to the transistors' sources and drains to make the cell read-disturb free. The static power is totally eliminated as the power line is shut down during data hold. The static noise margin of the cell is calculated based on the experimental data on MTJ switching that is enhanced from the resistive load SRAM cell due to the MTJ's switching operation. The cell size is estimated to become smaller than the 6-transistor SRAM cell when it is designed at 45nm node and beyond owing to the MTJ's area shrink as well as the thinning of its tunnel dielectrics (MgO). (C) 2012 The Japan Society of Applied Physics

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  • High-Speed Simulator including Accurate MTJ Models for Spintronics Integrated Circuit Design

    Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

    2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012)     1971 - 1974  2012年  [査読有り]

     概要を見る

    An extremely practical simulation program with integrated circuits emphasis (SPICE) incorporating model parameters of magnetic tunnel junction (MTJ) was developed. The simulator provides reliable simulation results in spintronics circuit design because it can accurately calculate various MTJ characteristics that actual devices have, that considerably influence the operation margin and power dissipation. It can also accelerate the simulation speed, which makes it possible to simulate three times or more large-scale circuits than when a conventional macro-model is used.

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    被引用数
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  • A 600MHz MTJ-Based Nonvolatile Latch Making Use of Incubation Time in MTJ Switching

    T. Endoh, S. Togashi, F. Iga, Y. Yoshida, T. Ohsawa, H. Koike, S. Fukami, S. Ikeda, N. Kasai, N. Sakimura, T. Hanyu, H. Ohno

    International Electron Devices Meeting (IEDM2011)   Session No. 4.3  2011年12月  [査読有り]

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    11
    被引用数
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  • Nonvolatile Low Power 16-bit/32-bit MTJ Based Binary Counter and its Scaling

    Shuta Togashi, Takashi Ohsawa, Tetsuo Endoh

    2011 International Conference on Solid State Devices and Materials (SSDM2011)     166 - 167  2011年09月  [査読有り]

  • Studies on Static Noise Margin and Scalability for Low-Power and High-Density Nonvolatile SRAM using Spin -Transfer -Torque (STT) MTJs

    Takashi Ohsawa, Fumitaka Iga, Shoji Ikeda, Takahiro, Hanyu, Hideo Ohno, Testuo Endoh

    2011 International Conference on Solid State Devices and Materials (SSDM2011)     959 - 960  2011年09月  [査読有り]

  • Novel 2step Writing Method for STT-RAM to Improve Switching Probability and Write Speed

    Fumitaka. Iga, Yasuhiko Suzuki, Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

    2011 International Conference on Solid State Devices and Materials (SSDM2011)     963 - 964  2011年09月  [査読有り]

  • Generation of Accurate Reference Current for Data Sensing in High-Density Memories by Averaging Multiple Pairs of Dummy Cells

    Takashi Ohsawa, Kosuke Hatsuda, Katsuyuki Fujita, Fumiyoshi Matsuoka, Tomoki Higashi

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   46 ( 9 ) 2148 - 2157  2011年09月

     概要を見る

    Methods to generate an accurate reference current by averaging multi-pair dummy cells' currents for distinguishing the data in sense amplifiers (S/As) of a large scale memory with resistance change cell is presented and analyzed. The predicted characteristics are confirmed by comparing them with measurement results of the functionalities and the retention time distributions in a floating body random access memory (FBRAM). The methods are found to be especially effective in situations where signals are seriously degraded such as in sensing the signals of tail bit cells in retention time distributions, making the retention time performance of the FBRAM improved drastically. The sense amplifiers which can accommodate the dummy cell averaging methods are identified to find a necessary condition for a S/A to afford the methods.

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    8
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  • Low Power Nonvolatile Counter Circuit with Fine-Grained Power Gating

    Shuta Togashi, Takashi Ohsawa, Tetsuo Endoh

    2011 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD 2011)   3B.10   267 - 270  2011年06月  [査読有り]

  • Reduction of Bipolar Disturb of Floating-Body Cell (FBC) by Silicide and Thin Silicon Film Formed at Source and Drain Regions

    Takeshi Hamamoto, Yoshiaki Fukuzumi, Tomoki Higashi, Hiroomi Nakajima, Yoshihiro Minami, Tomoaki Shino, Takashi Ohsawa, Akihiro Nitayama

    IEEE TRANSACTIONS ON ELECTRON DEVICES   57 ( 8 ) 1781 - 1788  2010年08月

     概要を見る

    The cell-to-cell leakage caused by bipolar disturb of the floating-body cell (FBC) has been investigated. In the case of FBC without silicide at the source and drain regions, the change of data "0" to data "1" has been observed in the writing operation to the adjacent cell. However, this leakage can be reduced when the silicide is formed on the thin silicon film at the source and drain regions. It has been clarified that the diffusion of holes inside the n(+) region is restricted by the capture of holes at the silicide/silicon interface when silicon thickness reduces. Based on these experimental results, 6F(2) layout of FBC can be realized with the conventional logic device process platform.

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  • Autonomous Refresh of Floating-Body Cell due to Current Anomaly of Impact Ionization

    Takashi Ohsawa, Ryo Fukuda, Tomoki Higashi, Katsuyuki Fujita, Fumiyoshi Matsuoka, Tomoaki Shino, Hironobu Furuhashi, Yoshihiro Minami, Hiroomi Nakajima, Takeshi Hamamoto, Yohji Watanabe, Akihiro Nitayama, Tohru Furuyama

    IEEE TRANSACTIONS ON ELECTRON DEVICES   56 ( 10 ) 2302 - 2311  2009年10月

     概要を見る

    Physics of autonomous refresh is presented, which explains the mechanism of a spontaneous recovery of degraded binary states of the floating-body cell (FBC). Input current to the floating body and output current from the body balance to generate an unstable stationary state that is accompanied by two stable stationary ones. The current anomaly of impact ionization is essential for the instability that brings about the bistability and is realized by positive feedback where impact ionization current input increases as the body voltage increases. Experiments with charge pumping current as output show that the autonomous refresh is possible on a single-cell basis. Necessary conditions for a high-density memory to be autonomously refreshed are derived and assessed for state-of-the-art FBCs. FBC is shown in simulation to become an SRAM cell when the autonomous refresh is applied, which uses gate direct tunneling current as output. This is an SRAM cell that is theoretically expected to have the simplest structure ever reported.

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    3
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  • Overview and future challenges of floating body RAM (FBRAM) technology for 32 nm technology node and beyond

    Takeshi Hamamoto, Takashi Ohsawa

    SOLID-STATE ELECTRONICS   53 ( 7 ) 676 - 683  2009年07月

     概要を見る

    Floating body cell (FBC) is a one-transistor memory cell on SOI substrate aimed at high-density embedded memory on SOC. In order to verify this memory cell technology, a 128 Mb floating body RAM (FBRAM) with FBC has been designed and successfully developed. The memory cell design and the experimental results, including single-cell operation, are reviewed. Based on the experimental results, the scalability of FBC down to 32 nm technology node is also discussed. (C) 2009 Elsevier Ltd. All rights reserved.

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    19
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  • Array Architecture of Floating Body Cell (FBC) with Quasi-Shielded Open Bit Line Scheme for sub-40nm Node

    Katsuyuki Fujita, Takashi Ohsawa, Ryo Fukuda, Fumiyoshi Matsuoka, Tomoki Higashi, Tomoaki Shino, Yohji Watanabe

    2008 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS     31 - +  2008年  [査読有り]

     概要を見る

    Cell array architecture for floating body RAM of 35nm bit line half pitch is described. The quasi-non-destructive-read-out feature of floating body cell contributes to eliminating inter-bit fine coupling noise in open bit line architecture without degrading the cycle time of the RAM.

  • Scaling Scenario of Floating Body Cell (FBC) Suppressing V-th Variation Due to Random Dopant Fluctuation

    Hironobu Furuhashi, Tomoaki Shino, Takashi Ohsawa, Fumiyoshi Matsuoka, Tomoki Higashi, Yoshihiro Minami, Hiroomi Nakajima, Katsuyuki Fujita, Ryo Fukuda, Takeshi Hamamoto, Akihiro Nitayama

    2008 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS     33 - +  2008年  [査読有り]

     概要を見る

    A scaling scenario of fully-depleted floating body cell (FBC) is demonstrated in view of signal margin for stable array functionality. Measurement and numerical simulation reveal that the V-th variation of cell array transistors is mainly attributed to the random dopant fluctuation In channel region. By setting the channel impurity concentration in the order of 10(16) cm(-3) or lower, Gbit array functionality is guaranteed for the 32nm node and further scaled generations.

  • Overview and Future Challenges of Floating Body RAM (FBRAM) Technology for 32nm Technology Node and Beyond

    Takeshi Hamamoto, Takashi Ohsawa

    ESSDERC 2008: PROCEEDINGS OF THE 38TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE     25 - 29  2008年  [査読有り]

     概要を見る

    Floating Body Cell (FBC) is a one-transistor memory cell on SOI substrate, which aims high density embedded memory on SOC. In order to verify this memory cell technology, a 128Mb Floating Body RAM (FBRAM) with FBC has been designed and successfully developed. The memory cell design and the experimental results, including single cell (1Cell/Bit) operation, are reviewed. Based on the experimental results, the scalability of FBC is also discussed.

  • Autonomous Refresh of Floating Body Cell (FBC)

    Takashi Ohsawa, Ryo Fukuda, Tomoki Higashi, Katsuyuki Fujita, Fumiyoshi Matsuoka, Tomoaki Shino, Hironobu Furuhashi, Yoshihiro Minami, Hiroomi Nakajima, Takeshi Hamamoto, Yohji Watanabe, Akihiro Nitayama, Tohru Furuyama

    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2008, TECHNICAL DIGEST     801 - +  2008年  [査読有り]

     概要を見る

    Physics of autonomous refresh of FBC is presented. Current input to the floating body by impact ionization and output by charge pumping can balance to make FBC refresh by itself without sense amplifier operation. Thanks to this feature, multiple cells on a 131, can be refreshed simultaneously, leading to a drastic reduction of BL charging current compared to the conventional refresh. 600 mu A refresh current for IG-bit memory is achieved in 32nm technology node with 4ms retention time. If gate direct tunneling current is used as output, FBC can realize static RAM without periodical refresh when retaining data.

  • A floating-body cell fully compatible with 90-nm CMOS technology node for a 128-Mb SOI DRAM and its scalability

    Takeshi Hamamoto, Yoshihiro Minami, Tomoaki Shino, Naoki Kusunoki, Hiroomi Nakajima, Mutsuo Morikado, Takashi Yamada, Kazumi Inoh, Atsushi Sakamoto, Tomoki Higashi, Katsuyuki Fujita, Kosuke Hatsuda, Takashi Ohsawa, Akihiro Nitayama

    IEEE TRANSACTIONS ON ELECTRON DEVICES   54 ( 3 ) 563 - 571  2007年03月

     概要を見る

    A 128-Mb silicon-on-insulator dynamic random access memory with floating-body cell (FBC) has been successfully developed for the first time. Two technologies have been newly implemented, namely: 1) the optimized well structure and 2) Cu wiring. The well design has been optimized both for the array device and the peripheral circuit in order to realize full functionality and good retention characteristics. Cu wiring has been used for the bit line and the source line, which increases the signal of the worst bit in the array and also realizes full compatibility with the standard CMOS process. Scalability of FBC down to 45-nm CMOS technology node has been investigated by a device simulation. The signal and the maximum electric field can be maintained constant with the reduction of the device dimensions and the operation voltage.

    DOI

  • FBC's potential of 6F(2) single cell operation in multi-Gbit memories confirmed by a newly developed method for measuring signal sense margin

    Fumiyoshi Matsuoka, Takashi Ohsawa, Tomoki Higashi, Hironobu Furuhashi, Kosuke Hatsuda, Katsuyuki Fujita, Ryo Fukuda, Nobuyuki Ikumi, Tomoaki Shino, Yoshihiro Minami, Hiroomi. Nakajima, Takeshi Hamamoto, Akihiro Nitayama, Yohji Watanabe

    2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2     39 - +  2007年  [査読有り]

     概要を見る

    A 6F(2) single cell (one-cell-per-bit) operation of the floating body RAM (FBRAM) is successfully demonstrated for the first time with more than 60% yield of 16Mbit area in a wafer The signal sense margin (SSM) at actual read conditions is found to well back up the functional results. The parasitic resistance in the source and drain formed under the FBC's spacers can be optimized for making the SSM as large as 8 mu A at +/-4.5 sigma without sacrificing the retention time.

  • Design of a 128-Mb SOI DRAM using the floating body cell (FBC)

    T Ohsawa, K Fujita, K Hatsuda, T Higashi, T Shino, Y Minami, H Nakajima, M Morikado, K Inoh, T Hamamoto, S Watanabe, S Fujii, T Furuyama

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   41 ( 1 ) 135 - 145  2006年01月

     概要を見る

    A 128-Mb SOI DRAM has been developed featuring the floating body cell (FBC). To keep the cell data state from being degraded by the word-line (WL) disturb due to the charge pumping and to reduce the refresh busy rate, a sense amplifier (S/A) is arranged for every bit-line (BL) and replenishes data "1" cells' bodies with holes which are lost by the disturb in every read and write cycle. The power is reduced by operating the S/As asymmetrically between the selected and the unselected thanks to that the number of holes to be replenished in the unselected S/As for charge pumping is two order of magnitude smaller than that required for writing the data "1". The multi-pair averaging of dummy cells generates a very accurate reference current for distinguishing the data "1" and "0" and a Monte Carlo simulation shows that it achieves a sensing scheme robust enough to realize all good parts of the DRAM with a reasonable amount of redundancy. The cell's feature of quasi-nondestructive read-out is also advantageous for making an SRAM interface of the DRAM or hiding refresh from uses without sacrificing the access time.

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  • Floating body RAM technology and its scalability to 32nm node and beyond

    Tomoaki Shino, Naoki Kusunoki, Tomoki Higashi, Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda, Nobuyuki Ikumi, Fumiyoshi Matsuoka, Yasuyuki Kajitani, Ryo Fukuda, Yoji Watanabe, Yoshihiro Minami, Atsushi Sakamoto, Jun Nishimura, Hiroomi Nakajima, Mutsuo Morikado, Kazumi Inoh, Takeshi Hamamoto, Akihiro Nitayama

    2006 INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2     314 - +  2006年  [査読有り]

     概要を見る

    Technologies and improved performance of the Floating Body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb chip yield of 68% has been obtained. Device simulation proves that the Floating Body Cell is scalable to the 32nm node keeping signal margin (threshold voltage difference) and data retention time constant.

  • A Floating Body Cell (FBC) fully compatible with 90nm CMOS Technology Node for Embedded Applications

    Takeshi Hamamoto, Yoshihiro Minami, Tomoaki Shino, Atsushi Sakamoto, Tomoki Higashi, Naoki Kusunoki, Katsuyuki Fujita, Kosuke Hatsuda, Takashi Ohsawa, Nobutoshi Aoki, Hiroyoshi Tanimoto, Mutsuo Morikado, Hiroomi Nakajima, Kazumi Inoh, Akihiro Nitayama

    2006 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS     30 - +  2006年  [査読有り]

     概要を見る

    Floating Body Cell (FBC) is a one-transistor memory cell on SOI substrate, which aims high density embedded memory on SOC. In order to verify this memory cell technology, a 128Mb SOI DRAM with FBC has been designed and successfully developed. The memory cell design, and the experimental results, such as the signal and the retention characteristics, are reviewed. The results of the fabricated SOI DRAM and the prospect as embedded memory are also discussed.

  • Overview and future challenge of Floating Body Cell (FBC) technology for embedded applications

    Akihiro Nitayama, Takashi Ohsawa, Takeshi Hamamoto

    2006 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS     94 - +  2006年  [査読有り]

     概要を見る

    A one-transistor memory cell on silicon-on-insulator, called Floating Body Cell (FBC), has been developed for high density embedded DRAM applications. The functionality of a 128Mb FBC DRAM using fully compatible 90mn CMOS technology has been successfully demonstrated. The memory cell design, such as fully-depleted (FD) operation with substrate-bias, and the process integration, such as well and Cu wiring, are reviewed. The scalability and future challenge of FBC technology are discussed as well.

  • Operation voltage dependence of memory cell characteristics in fully depleted floating-body cell

    T Shino, T Ohsawa, T Higashi, K Fujita, N Kusunoki, Y Minami, M Morikado, H Nakajima, K Inoh, T Hamamoto, A Nitayama

    IEEE TRANSACTIONS ON ELECTRON DEVICES   52 ( 10 ) 2220 - 2226  2005年10月

     概要を見る

    A one-transistor memory cell on silicon-on-insulator, called floating-body cell (FBC), has been developed and demonstrated. Threshold voltage difference between the "0"-state and the "1"-state, which is a key parameter for realizing a larger scale memory by FBCs, is measured and analyzed using a 96 kb array diagnostic monitor (ADM). A function test of the ADM yielded a fail-bit probability of 0.002%. A new metric relating to the fail-bit probability, that is, the ratio of the threshold voltage difference over the total threshold voltage variation, is introduced and applied to the measurement results. Read current distributions are also evaluated for various operation voltages. This paper also investigates substrate bias dependence of the threshold voltage unique to fully-depleted devices. Channel impurity and substrate impurity concentration dependence of the threshold voltage are analyzed based on experimental data and device simulation.

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  • A 333MHz random cycle DRAM using the floating body cell

    Kosuke Hatsuda, Katsuyuki Fujita, Takashi Ohsawa

    Proceedings of the Custom Integrated Circuits Conference   2005   256 - 259  2005年  [査読有り]

     概要を見る

    A Monte Carlo simulation shows that a DRAM using the floating body cell (FBC) realizes a 333MHz high-speed random cycle with an introduction of a symmetrical sense amplifier circuit and optimization of its current mirror ratio. Since the FBC DRAM having a superior affinity with logic LSI process is also shown to have its macro size smaller than the conventional 1T-1C DRAM, the FBC is a promising candidate for next generation embedded DRAM cells. © 2005 IEEE.

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  • A Floating Body Cell (FBC) fully compatible with 90nm CMOS Technology(CMOS IV) for 128Mb SOI DRAM

    Y Minami, T Shino, A Sakamoto, T Higashi, N Kusunoki, K Fujita, K Hatsuda, T Ohsawa, N Aoki, H Tanimoto, M Morikado, H Nakajima, K Inoh, T Hamamoto, A Nitayama

    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST     317 - 320  2005年  [査読有り]

     概要を見る

    A 128Mb SOI DRAM with FBC (Floating Body Cell) has been successfully developed for the first time. Two technologies have been newly implemented. (i)In order to realize full functionality and good retention characteristics, the well design has been optimized both for the array device and the peripheral circuit. (ii)Cu wiring has been used for Bit Line(BL) and Source Line(SL), which leads to increasing the signal of the worst bit in the array and also realizes the full compatibility with 90nm CMOS Technology.

  • Fully-depleted FBC (Floating Body Cell) with enlarged signal window and excellent logic process compatibility

    T Shino, T Higashi, N Kusunoki, K Fujita, T Ohsawa, N Aoki, H Tanimoto, Y Minami, T Yamada, M Morikado, H Nakajima, K Inoh, T Hamamoto, A Nitayama

    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST     281 - 284  2004年  [査読有り]

     概要を見る

    Fully-depleted (FD) Floating Body Cell on 55nm SOI featuring excellent logic process compatibility has been successfully developed. For the first time FD operation is reported through significant signal enlargement by negative substrate bias. Using standard salicide process and FD operation, high-density embedded memory on SOI is achievable.

  • A memory using one-transistor gain cell on SOI(FBC) with performance suitable for embedded DRAM's

    T Ohsawa, T Higashi, K Fujita, T Ikehashi, T Kajiyama, Y Fukuzumi, T Shino, H Yamada, H Nakajima, Y Minami, T Yamada, K Inoh, T Hamamoto

    2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS     93 - 96  2003年  [査読有り]

     概要を見る

    A 288Kbit memory chip featuring a one-transistor gain cell on SOI of the size 0.21 mu m(2) (7F(2) with F=0.175 mu m) which we named the floating body transistor cell(FBC) is presented and basic characteristics of the cell and the memory chip performance are disclosed. The threshold voltages of a cell transistor in the chip for the data "1" and for the data "0" are measured by using a direct access test circuit and a fail bit map for the 96Kbit array is obtained. A sensing scheme which was designed to eliminate the effect of cell characteristics variation due to process and temperature fluctuation as common mode noise is verified to be working and the random access time is measured to be less than 100ns. The characteristics of data hold demonstrate that the FBC can satisfy retention time specifications for some embedded memories. The access time and the data retention time show that the FBC has a potential to be used as a future embedded DRAM memory cell.

  • Memory design using a one-transistor gain cell on SOI

    T Ohsawa, K Fujita, T Higashi, Y Iwata, T Kajiyama, Y Asao, K Sunouchi

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   37 ( 11 ) 1510 - 1522  2002年11月

     概要を見る

    A 512-kb memory has been developed featuring a one-transistor gain cell of size 7F(2) (F = 0. 18 mum) on SOI. The cell named the floating body transistor cell (FBC) has the ability to achieve a 4F(2) cell using self-aligned contact technologies and is proved to be scalable with respect to a cell signal. A basic operation was verified by device simulation and hardware measurement. An array driving method is disclosed which makes selective write possible. A cell signal sensing system consisting of a pair of reference cells written opposite data and comparing the combined current with the doubled cell current is shown to be robust against cell parameter variations in process and temperature. A random access time of 40 ns was simulated. Nondestructive readout and C-b/C-s free signal development drastically improve cell efficiency.

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  • A 250 mV bit-line swing scheme for 1-V operating gigabit scale DRAMs

    T Inaba, D Takashima, Y Oowaki, T Ozaki, S Watanabe, T Ohsawa, K Ohuchi, H Tango

    IEICE TRANSACTIONS ON ELECTRONICS   E79C ( 12 ) 1699 - 1706  1996年12月

     概要を見る

    This paper proposes a small 1/4 Vcc bit-line swing scheme and a related sense amplifier scheme for low power 1 V operating DRAM. Using the proposed small bit-line swing scheme, the stress bias of memory cell transistor and capacitor is reduced to half that of the conventional DRAM, resulting in improvement of device reliability. The proposed sense amplifier scheme achieves high speed and stable sensing/restoring operation at 250mV bit-line swing, which is much smaller than threshold voltage. The proposed scheme reduces the total power dissipation of bit-line sensing/restoring operation to 40% of the conventional one. This paper also proposes a small 4F(2) size memory cell and a new twisted bit-line scheme. The array noise is reduced to 8.6% of the conventional DRAM.

  • A 12-MHZ DATA CYCLE 4-MB DRAM WITH PIPELINE OPERATION

    N KUSHIYAMA, Y WATANABE, T OHSAWA, K MURAOKA, Y NAGAHAMA, T FURUYAMA

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   26 ( 4 ) 479 - 483  1991年04月

     概要を見る

    A 12-MHz data-cycle 4-Mb DRAM with pipeline operation has been designed and fabricated using 0.8-mu-m twin-tub CMOS technology. The pipeline DRAM outputs data corresponding to addresses that were accepted in the previous RAS cycle. The latter half of the previous read operation and the first half of the next read operation take place simultaneously, so the RAS cycle time is reduced. This pipeline DRAM technology needs no additional chip area and no process modification. A 95-ns RAS cycle time was obtained under worst conditions while this value is 125 ns for conventional DRAM's.

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  • A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM’s

    Yohji Watanabe, Takashi Ohsawa, Kiyofumi Sakurai, Tohru Furuyama

    IEEE Journal of Solid-State Circuits   24 ( 4 ) 905 - 910  1989年

     概要を見る

    A novel capacitance-resistance (CR-) delay circuit technology for high-density DRAM’s has been developed as a method to assure full asynchronicity between memory cell array and peripheral circuits over a wide range of both operating and process conditions, and thus, to realize a fast access time. A unique noise compensation scheme is introduced to the CR-delay circuit to generate a constant delay even under the power supply line noise. This CR-delay circuit was applied to the 4-Mbit DRAM peripheral circuit. As a result, a timing loss as well as a malfunction could be successfully avoided, and 7 ns faster access time and 39 ns shorter cycle time have been achieved, compared with a conventional design using normal inverter chains. © 1989 IEEE

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  • An Experimental 2-bit/Cell Storage DRAM for Macroce11 or Memory-on-Logic Application

    Tohru Furuyama, Takashi Ohsawa, Yohji Watanabe, Kazuyoshi Muraoka, Kenji Natori, Yousei Nagahama, Tohru Kimura, Hiroto Tanaka

    IEEE Journal of Solid-State Circuits   24 ( 2 ) 388 - 393  1989年

     概要を見る

    A novel 2-bit (four-level)/cell storage technique is described. This technique saves the RAM area, in particular the cell array area which is highly defect sensitive provides fairly fast access time. An experimental 1-Mbit DRAM has been fabricated and has successfully demon-strated the feasibility of this technique for embedded memory applications. ©1989 IEEE

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  • A New On-Chip Voltage Converter for Submicrometer High-Density DRAM's

    Tohru Furuyama, Yorji Watanabe, Takashi Ohsawa, Shigeyoshi Watanabe

    IEEE Journal of Solid-State Circuits   22 ( 3 ) 437 - 441  1987年

     概要を見る

    A new on-chip voltage converter has been developed and its characteristics have been examined. The converter is a feedback-type voltage regulator, and it supplies a reduced voltage to an entire RAM circuit. A novel timing activation method was introduced to save power. The converter has been implemented on an experimental 4-Mbit dynamic RAM. It was found that an even faster access time and higher reliability compared to a conventional design could be achieved by using an on-chip voltage converter and shorter channel transistors. This voltage converter is suitable for high-density, high-speed, and high-reliability DRAM's with submicrometer transistors. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.

    DOI

    Scopus

    25
    被引用数
    (Scopus)
  • A 60-ns 4-Mbit CMOS DRAM with Built-In Self-Test Function

    Takashi Ohsawa, Tohru Furuyama, Yohji Watanabe, Hiroto Tanaka, Kenji Natori, Satoshi Shinozaki, Takeshi Tanaka, Satoshi Yamano, Yohsei Nagahama, Natsuki Kushiyama, Kenji Tsuchida

    IEEE Journal of Solid-State Circuits   22 ( 5 ) 663 - 668  1987年

     概要を見る

    A 4-Mbit CMOS DRAM measuring 6.9×16.11 mm2 has been fabricated using a 0.9-µm twin-tub CMOS, triple-poly, single-metal process technology. N-channel depletion-type trench cells, 2.5 × 5.5 µm2 each, are incorporated in a p-well. A novel built-in self-test (BIST) function which enables a simultaneous and automatic test of all the memory devices on a board is introduced to reduce the RAM testing time in a system. This function is effective for system maintenance and a daily start-up test even in a relatively small system. A high-speed low-power 4-Mbit CMOS DRAM with 60-ns access time, 50-mA active current, and 200-µA standby current is realized by widening the DQ line bus which connects the sense amplifiers with the DQ buffers, thereby reducing the parasitic capacitance of the DQ lines. Copyright © 1987 by The Institute of Electrical and Electronics, Inc.

    DOI

    Scopus

    16
    被引用数
    (Scopus)
  • An Experimental 4-Mbit CMOS DRAM

    Tohru Furuyama, Takashi Ohsawa, Yohji Watanabe, Hidemi Ishiuchi, Toshiharu Watanabe, Takeshi Tanaka, Kenji Natori, Osamu Ozawa

    IEEE Journal of Solid-State Circuits   21 ( 5 ) 605 - 611  1986年

     概要を見る

    A 4-Mbit dynamic RAM has been designed and fabricated using 1.0-μm twin-tub CMOS technology. The memory array consists of trenched n-channel depletion-type capacitor cells in a p-well. Very high α-particle immunity was achieved with this structure. One cell measures 3.0×5.8 µm2 yielding a chip size of 7.84 x 17.48 mm2. An on-chip voltage converter circuit was implemented as a mask option to investigate a possible solution to the MOSFET reliability problem caused by hot carriers. An 8-bit parallel test mode was introduced to reduce the RAM test time. Metal mask options provide static column mode and fast page mode operation. The chip is usable as ×1 or ×4 with a bonding option. Using an external 5-V power supply, the RAS access time is 80 ns at room temperature. Typical active current is 60 mA at a 220-ns cycle time with a standby current of 0.5 mA. Copyright © 1986 by the Institute of Electrical and Electronics Engineers, Inc.

    DOI

    Scopus

    25
    被引用数
    (Scopus)
  • THERMODYNAMIC THEORY OF LIGHT-ION BEAM PROPAGATION IN A PLASMA

    T KATO, T OHSAWA

    JOURNAL OF THE PHYSICAL SOCIETY OF JAPAN   52 ( 8 ) 2720 - 2726  1983年

     概要を見る

    Propagation of a light ion beam in a plasma is investigated theoretically. The basic principle determining the steady state of the beam transport in a plasma is ascertained from the view points of the theory of the irreversible processes. As a preliminary work to discuss the collisional plasma, we consider a state in which the entropy production vanishes and obtain an extended result of Chen and Davidson to include the current due to the drift of the plasma electrons. Two extreme cases are considered: (i) No rotation of the beam around the axis of symmetry or complete neutralization of azimuthal beam current by the plasma electron. (ii) Complete balancing of the electrostatic repulsive force on a beam ion and the magnetically pinching force due to the axial beam current. It is shown that the distribution of ions in a rotational ion beam is given by the Bennett type, provided the current is over-neutralized azimuthally. © 1983, THE PHYSICAL SOCIETY OF JAPAN. All rights reserved.

    DOI

    Scopus

    1
    被引用数
    (Scopus)
  • AZIMUTHAL CURRENT-NEUTRALIZATION OF A ROTATIONAL LIGHT-ION BEAM BY A PLASMA

    T OHSAWA, T KATO

    JOURNAL OF THE PHYSICAL SOCIETY OF JAPAN   52 ( 8 ) 2727 - 2735  1983年

     概要を見る

    The rotational motion of a light ion beam and a plasma immersed in a uniform magnetic field is investigated within the framework of the macroscopic fluid equations including force terms due to radial pressure variations. Drift motion caused by the radial electric and magnetic forces rotates the beam fluid element and the plasma electron fluid element in the same azimuthal direction. The motion leads to the over-neutralization of the azimuthal beam current by the plasma electron current. It is found that the ion beam is compact and never hollowed out in over-neutralized states. The radial density profiles of the beam are obtained and the condition for radially confined equilibria in those over-neutralized states is examined. © 1983, THE PHYSICAL SOCIETY OF JAPAN. All rights reserved.

    DOI

    Scopus

  • SYNCHRONOUS QUENCHING DUE TO NON-LINEAR MODE-COUPLING IN BEAM-PLASMA SYSTEM

    T OHSAWA

    JOURNAL OF THE PHYSICAL SOCIETY OF JAPAN   49 ( 6 ) 2340 - 2348  1980年

     概要を見る

    A nonlinear theory is presented which shows mode-locking of a naturally excited instability by an externally launched wave whose frequency is around that of the instability. A procedure to remove secular solutions leads to a couple of nonlinear equations which describe slow-time evolutions of amplitudes. A stably stationary solution of these equations is investigated to show qualitative agreement with published experiments; the external field strength at which the instability vanishes increases as the frequency discrepancy between the instability and the external wave |Ω-ω0| increases, and a relation Aa2+Bb2=1 is obtained between the amplitude of the instability a and that of the externally excited wave b where the ratio B/A depends on the frequency discrepancy in the form (Ω-ω0)−2. © 1980, THE PHYSICAL SOCIETY OF JAPAN. All rights reserved.

    DOI

    Scopus

    2
    被引用数
    (Scopus)
  • Theory of the Parametric Oscillation in an Electron Beam-Plasma System

    Tomokazu Kato, Takashi Okazaki, Takashi Ohsawa

    Journal of the Physical Society of Japan   46   277 - 284  1979年01月

     概要を見る

    The density oscillations in a system composed of a one-dimensional cold electron plasma and a cold electron beam are considered where the beam is assumed to be modulated sinusoidally and also to be bounded by a repeller in the plasma. A nonlinear differential equation which describes the density oscillations in the beam-plasma system is derived from the Vlasov and Poisson equations. The equation does not take the so-called van der Pol-type, but is, as one of the linear approximations, reduced to a Mathieu-type equation with an inhomogeneous term: d2ρ⁄dt2+ωe2[1−σ cos (ωt)]ρ=σ(ω2−ωe2) cos (ωt). This inhomogeneous Mathieu equation is analyzed by the method of Bogoliubov and Mitropolsky. The spectrum of the characteristic frequency obtained from the analysis is compared with the experimental results. © 1979, THE PHYSICAL SOCIETY OF JAPAN. All rights reserved.

    DOI

    Scopus

    1
    被引用数
    (Scopus)

▼全件表示

書籍等出版物

  • Floating Body Cell ---- A Novel Capacitorless DRAM Cell ----

    大澤 隆( 担当: 共著,  担当範囲: pp. 1-111, pp. 113-116, pp. 127-254 (total 254 pages))

    Pan Stanford Publishing Pte. Ltd.  2012年

Misc

  • 招待講演 3次元構造とスピントロニクスによる半導体メモリの新展開

    遠藤 哲郎, 大澤 隆, 小池 洋紀

    半導体・集積回路技術シンポジウム講演論文集 = Proceedings of Symposium on Semiconductors and Integrated Circuits Technology   77   35 - 40  2013年07月

    CiNii

  • 依頼講演 32ビット細粒度パワーゲーティングを使った不揮発性混載用1Mb 4T2MTJ STT-RAM : 1.0ns/200psのWake-up/Power-off時間を達成 (集積回路)

    遠藤 哲郎, 大澤 隆, 小池 洋紀, 三浦 貞彦, 本庄 弘明, 徳留 圭一, 池田 正二, 羽生 貴弘, 大野 英男

    電子情報通信学会技術研究報告 : 信学技報   113 ( 1 ) 27 - 32  2013年04月

     概要を見る

    不揮発性でありながら書き込み耐性の良いスピン注入型の磁気トンネル接合素子(STT-MTJ)を用いた4T2MTJのメモリセルによる1Mbの高速な混載用メモリを設計・試作した。スタンドバイ電流をなくし、動作電流を極力下げ、かつ高速なアクセス時間とサイクル時間を達成するために32bからなる細粒度パワーゲーティングを適用した。このセルは4個のNFETでその大きささが決まるために、従来のSRAMよりもセルサイズが小さくなるポテンシャルを持ち、実際スケーリングに基づきSTTMTJのスイッチング電流が小さくなることによって、NFETのチャンネル幅をスケーリングできるために25nm-45nm世代以降においてSRAMよりも小さいマクロを実現できる可能性を示した。

    CiNii

  • シリコン不揮発性メモリ技術の限界を突破するスピントルク注入型磁気メモリの最新動向

    遠藤哲郎, 大澤隆, 小池洋紀, 羽生貴弘, 笠井直記, 大野英男

    電子情報通信学会誌   ( 平成24年11月号 )  2012年11月

    記事・総説・解説・論説等(その他)  

  • STT-MRAM for future high performance Nonvolatile memory

    遠藤哲郎, 大澤隆, 小池洋紀, 羽生貴弘, 笠井直記, 大野英男

    電子情報通信学会誌   ( 平成24年11月号 )  2012年11月

    記事・総説・解説・論説等(その他)  

  • 単一FETセルを用いたSOI DRAM

    大澤 隆

    應用物理   75 ( 9 ) 1131 - 1135  2006年09月

    CiNii

  • バイエルンにおける農民レーテ運動とその前提

    大澤 隆

    新潟史学   33   43 - 66  1994年10月

    CiNii

  • 社会福祉制度改革と福祉実践 : 地方自治体からみる課題(<特集>社会福祉制度改革と福祉実践)

    大澤 隆

    社会福祉学   31 ( 1 ) 81 - 97  1990年06月

    CiNii

▼全件表示

受賞

  • SSDM Paper Award

    2012年09月   International Conference on Solid State Devices and Materials (SSDM)  

    受賞者: 大澤 隆

  • The Takuo Sugano Award

    2003年02月   IEEE International Solid-State Circuits Confenetce  

    受賞者: 大澤 隆

講演・口頭発表等

  • Co-design of DNN Model Optimization for Binary ReRAM Array In-memory Processing

    Yue Guan, Takashi Ohsawa

    Proceedings of Technical Program - IEEE 2019 11th International Memory Workshop, Monterey, USA  

    発表年月: 2019年05月

  • User-Friendly Compact Model of Magnetic Tunnel Junctions for Circuit SImulation Based on Switching Probability

    Haoyan Liu, Takashi Ohsawa

    Proceedings of Technical Program - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019  

    発表年月: 2019年04月

  • Accurate Meassurement of Sneak Current in ReRAM Crossbar Array with Data Storage Pattern Dependencies

    Yaqi Shang, Takashi Ohsawa

    Proceedings of Technical Program - 2019 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2019  

    発表年月: 2019年04月

  • Cell Array Design with Row-Driven Source Line in Block Shunt Architecture Applicable to Future 6F2 1T1MTJ Memory

    Tongshuang Huang, Takashi Ohsawa

    Proceedings of Technical Program - 2019 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2019  

    発表年月: 2019年04月

  • Studies on read-stability and write-ability of fast access STT-MRAMs

    Takashi Ohsawa, Takashi Ohsawa, Shoji Ikeda, Shoji Ikeda, Takahiro Hanyu, Takahiro Hanyu, Takahiro Hanyu, Hideo Ohno, Hideo Ohno, Hideo Ohno, Tetsuo Endoh, Tetsuo Endoh, Tetsuo Endoh

    Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014  

    発表年月: 2014年01月

  • A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop

    H. Koike, T. Ohsawa, S. Ikeda, S. Ikeda, T. Hanyu, T. Hanyu, H. Ohno, H. Ohno, T. Endoh, T. Endoh, N. Sakimura, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, S. Miura, H. Honjo, T. Sugibayashi

    Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013  

    発表年月: 2013年12月

     概要を見る

    We propose a novel power-gated microprocessor unit (MPU) using a nonvolatile flip-flop (NV-F/F) with magnetic tunnel junction (MTJ). By using the NV-F/F to store the MPU's internal state, this MPU realizes power-gating operation with a small 3-microsecond entry/exit delay penalty in power-on/power-off, which is one order of magnitude faster than a conventional MPU's deep power down mode. To achieve this short entry/exit delay, an appropriate NV-F/F circuit, which can perform stable high speed store/recall operations, has been developed. The MPU will help in the realization of low power systems because of its easy controllability for the power gating mode. © 2013 IEEE.

  • A 1.5nsec/2.1nsec random read/write cycle 1Mb STT-RAM using 6T2MTJ cell with background write for nonvolatile e-memories

    T. Ohsawa, S. Miura, K. Kinoshita, H. Honjo, S. Ikeda, S. Ikeda, T. Hanyu, T. Hanyu, H. Ohno, H. Ohno, T. Endoh, T. Endoh, T. Endoh

    IEEE Symposium on VLSI Circuits, Digest of Technical Papers  

    発表年月: 2013年09月

     概要を見る

    A 1Mb STT-RAM with a 6T2MTJ cell is designed and fabricated using 90nm CMOS/MTJ process that can operate in 1.5nsec/2.1nsec random read/write cycle by adopting a background write scheme. It works around the problem of high error rate of MTJ switching in a short period of time at moderate drive current. The RAM is fast enough to be applicable to embedded memories such as L3 cache. © 2013 JSAP.

  • A 1-Mb STT-MRAM with zero-array standby power and 1.5-ns quick wake-up by 8-b fine-grained power gating

    Takashi Ohsawa, Shoji Ikeda, Shoji Ikeda, Takahiro Hanyu, Takahiro Hanyu, Hideo Ohno, Hideo Ohno, Tetsuo Endoh, Tetsuo Endoh, Tetsuo Endoh

    2013 5th IEEE International Memory Workshop, IMW 2013  

    発表年月: 2013年09月

     概要を見る

    The power gating is one of the key technologies that reduce the operation power of STT-RAMs for enjoying their non-volatility. Especially, the number of memory cells whose supply voltages are simultaneously controlled in the power gating (grain size) is required to be as small as the bit-width in read and write for minimizing the operation power. For this ultra-fine-grained power gating scheme, we proposed a small power line (PL) driver that utilizes an NFET bootstrap circuit. It is found that the size of the macro using this PL driver is almost independent of the grain size with its write and read performance kept constant. Therefore, this PL driver combined with a small grain is shown to realize a nonvolatile embedded memory macro of fast read/write cycles, ultra-low operation power and zero array standby power with no leak path in the PL drivers. © 2013 IEEE.

  • A 1.5nsec/2.1nsec random read/write cycle 1Mb STT-RAM using 6T2MTJ cell with background write for nonvolatile e-memories

    T. Ohsawa, S. Miura, K. Kinoshita, H. Honjo, S. Ikeda, S. Ikeda, T. Hanyu, T. Hanyu, H. Ohno, H. Ohno, T. Endoh, T. Endoh, T. Endoh

    Digest of Technical Papers - Symposium on VLSI Technology  

    発表年月: 2013年09月

     概要を見る

    A 1Mb STT-RAM with a 6T2MTJ cell is designed and fabricated using 90nm CMOS/MTJ process that can operate in 1.5nsec/2.1nsec random read/write cycle by adopting a background write scheme. It works around the problem of high error rate of MTJ switching in a short period of time at moderate drive current. The RAM is fast enough to be applicable to embedded memories such as L3 cache. © 2013 JSAP.

  • High-speed simulator including accurate MTJ models for spintronics integrated circuit design

    Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

    ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems  

    発表年月: 2012年09月

     概要を見る

    An extremely practical simulation program with integrated circuits emphasis (SPICE) incorporating model parameters of magnetic tunnel junction (MTJ) was developed. The simulator provides reliable simulation results in spintronics circuit design because it can accurately calculate various MTJ characteristics that actual devices have, that considerably influence the operation margin and power dissipation. It can also accelerate the simulation speed, which makes it possible to simulate three times or more large-scale circuits than when a conventional macro-model is used. © 2012 IEEE.

  • 1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times

    T. Ohsawa, H. Koike, S. Miura, H. Honjo, K. Tokutome, S. Ikeda, S. Ikeda, T. Hanyu, T. Hanyu, H. Ohno, H. Ohno, T. Endoh, T. Endoh, T. Endoh

    IEEE Symposium on VLSI Circuits, Digest of Technical Papers  

    発表年月: 2012年09月

     概要を見る

    A 1Mb nonvolatile STT-RAM using the 4T-2MTJ cell is designed and fabricated using 90nm CMOS and MTJ processes. 32 cells along a word line (WL) are simultaneously power-gated with quick wake-up/power-off times of 1.0ns/200ps, respectively, to reduce operation power and to eliminate standby power of the chip. The cell is experimentally shown to retain data with static noise margin (SNM) 0.32V under V dd=1V. The 1Mb chip with 2.19μm 2 cell is successfully operated with array access time of 8ns and read power of 10.7mW under 10ns cycle. The macro size of 1Mb STT-RAM is predicted to become smaller than the 1Mb 6T-SRAM in 45nm and beyond. © 2012 IEEE.

  • Restructuring of memory hierarchy in computing system with spintronics-based technologies

    Tetsuo Endoh, Tetsuo Endoh, Tetsuo Endoh, Takashi Ohsawa, Hiroki Koike, Takahiro Hanyu, Takahiro Hanyu, Hideo Ohno, Hideo Ohno

    Digest of Technical Papers - Symposium on VLSI Technology  

    発表年月: 2012年09月

     概要を見る

    The restructuring of today's computer memory hierarchies that are caught in a dilemma between performance gain and power reduction is one of the most promising ways to making the computers much more efficient with much less power. To this end, several possibilities of using NV memories and NV logic with spin-transfer-torque magnetic tunnel junction (STT-MTJ) as levels in new hierarchies are discussed. A new NV-SRAM cell consisting of four transistors and two MTJs (4T-2MTJ) is shown to be a promising candidate for future NV-cache memories. For NV-main memories, we propose a PFET-based 1T-1MTJ cell combined with a new sense amplifier (S/A). A new NV-latch that can be constructed in flip-flops of synchronous core circuits is proposed and the world's fastest 600MHz operation is experimentally demonstrated. © 2012 IEEE.

  • A 600MHz MTJ-based nonvolatile latch making use of incubation time in MTJ switching

    T. Endoh, T. Endoh, T. Endoh, S. Togashi, S. Togashi, F. Iga, F. Iga, Y. Yoshida, Y. Yoshida, T. Ohsawa, H. Koike, S. Fukami, S. Ikeda, S. Ikeda, N. Kasai, N. Sakimura, T. Hanyu, T. Hanyu, H. Ohno, H. Ohno

    Technical Digest - International Electron Devices Meeting, IEDM  

    発表年月: 2011年12月

     概要を見る

    The incubation (transit) time of the perpendicular magnetic tunnel junction (MTJ) is found shorter (longer) than the in-plane MTJ. By making use of the incubation time, a new concept is proposed for MTJ/CMOS hybrid circuits that operate as fast as CMOS circuits without operation power overhead and with negligible MTJ switching error. A nonvolatile latch based on the concept is fabricated in 90nm technology to demonstrate 600MHz stable operation. © 2011 IEEE.

  • Array architecture of floating body cell (FBC) with quasi-shielded open bit line scheme for sub-40nm node

    Katsuyuki Fujita, Takashi Ohsawa, Ryo Fukuda, Fumiyoshi Matsuoka, Tomoki Higashi, Tomoaki Shino, Yohji Watanabe

    Proceedings - IEEE International SOI Conference  

    発表年月: 2008年12月

     概要を見る

    Cell array architecture for floating body RAM of 35nm bit line half pitch is described. The quasi-non-destructive-read-out feature of floating body cell contributes to eliminating inter-bit line coupling noise in open bit line architecture without degrading the cycle time of the RAM. ©2008 IEEE.

  • Scaling scenario of floating body cell (FBC) suppressing V<inf>th</inf> variation due to random dopant fluctuation

    Hironobu Furuhashi, Tomoaki Shino, Takashi Ohsawa, Fumiyoshi Matsuoka, Tomoki Higashi, Yoshihiro Minami, Hiroomi Nakajima, Katsuyuki Fujita, Ryo Fukuda, Takeshi Hamamoto, Akihiro Nitayama

    Proceedings - IEEE International SOI Conference  

    発表年月: 2008年12月

     概要を見る

    A scaling scenario of fully-depleted floating body cell (FBC) is demonstrated in view of signal margin for stable array functionality. Measurement and numerical simulation reveal that the Vth variation of cell array transistors is mainly attributed to the random dopant fluctuation in channel region. By setting the channel impurity concentration in the order of 1016cm-3 or lower, Gbit array functionality is guaranteed for the 32nm node and further scaled generations. ©2008 IEEE.

  • Autonomous refresh of floating body cell (FBC)

    Takashi Ohsawa, Ryo Fukuda, Tomoki Higashi, Katsuyuki Fujita, Fumiyoshi Matsuoka, Tomoaki Shino, Hironobu Furuhashi, Yoshihiro Minami, Hiroomi Nakajima, Takeshi Hamamoto, Yohji Watanabe, Akihiro Nitayama, Tohru Furuyama

    Technical Digest - International Electron Devices Meeting, IEDM  

    発表年月: 2008年12月

     概要を見る

    Physics of autonomous refresh of FBC is presented. Current input to the floating body by impact ionization and output by charge pumping can balance to make FBC refresh by itself without sense amplifier operation. Thanks to this feature, multiple cells on a BL can be refreshed simultaneously, leading to a drastic reduction of BL charging current compared to the conventional refresh. 600μA refresh current for 1G-bit memory is achieved in 32nm technology node with 4ms retention time. If gate direct tunneling current is used as output, FBC can realize static RAM without periodical refresh when retaining data.

  • Overview and future challenges of floating Body RAM (FBRAM) technology for 32nm technology node and beyond

    Takeshi Hamamoto, Takashi Ohsawa

    ESSDERC 2008 - Proceedings of the 38th European Solid-State Device Research Conference  

    発表年月: 2008年01月

     概要を見る

    Floating Body Cell (FBC) is a one-transistor memory cell on SOI substrate, which aims high density embedded memory on SOC. In order to verify this memory cell technology, a 128Mb Floating Body RAM (FBRAM) with FBC has been designed and successfully developed. The memory cell design and the experimental results, including single cell (1 Cell/Bit) operation, are reviewed. Based on the experimental results, the scalability of FBC is also discussed. © 2008 IEEE.

  • FBC's potential of 6F2single cell operation in multi-gbit memories confirmed by a newly developed method for measuring signal sense margin

    Fumiyoshi Matsuoka, Takashi Ohsawa, Tomoki Higashi, Hironobu Furuhashi, Kosuke Hatsuda, Katsuyuki Fujita, Ryo Fukuda, Nobuyuki Ikumi, Tomoaki Shino, Yoshihiro Minami, Hiroomi Nakajima, Takeshi Hamamoto, Akihiro Nitayama, Yohji Watanabe

    Technical Digest - International Electron Devices Meeting, IEDM  

    発表年月: 2007年12月

     概要を見る

    A 6F2single cell (one-cell-per-bit) operation of the floating body RAM (FBRAM) is successfully demonstrated for the first time with more than 60% yield of 16Mbit area in a wafer. The signal sense margin (SSM) at actual read conditions is found to well back up the functional results. The parasitic resistance in the source and drain formed under the FBC's spacers can be optimized for making the SSM as large as 8μA at ±4.5σ without sacrificing the retention time. © 2007 IEEE.

  • Floating body RAM technology and its scalability to 32nm node and beyond

    Tomoaki Shino, Naoki Kusunoki, Tomoki Higashi, Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda, Nobuyuki Ikumi, Fumiyoshi Matsuoka, Yasuyuki Kajitani, Ryo Fukuda, Yoji Watanabe, Yoshihiro Minami, Atsushi Sakamoto, Jun Nishimura, Hiroomi Nakajima, Mutsuo Morikado, Kazumi Inoh, Takeshi Hamamoto, Akihiro Nitayama

    Technical Digest - International Electron Devices Meeting, IEDM  

    発表年月: 2006年12月

     概要を見る

    Technologies and improved performance of the Floating Body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb chip yield of 68% has been obtained. Device simulation proves that the Floating Body Cell is scalable to the 32nm node keeping signal margin (threshold voltage difference) and data retention time constant.

  • A 128Mb floating body RAM(FBRAM) on SOI with multi-averaging scheme of dummy cell

    Takashi Ohsawa, Tomoki Higashi, Katsuyuki Fujita, Kosuke Hatsuda, Nobuyuki Ikumi, Tomoaki Shino, Hiroomi Nakajima, Yoshihiro Minami, Naoki Kusunoki, Atsushi Sakamoto, Jun Nishimura, Takeshi Hamamoto, Shuso Fujii

    IEEE Symposium on VLSI Circuits, Digest of Technical Papers  

    発表年月: 2006年12月

     概要を見る

    A 128Mbit FBRAM using the floating body cell(FBC) the size of 0.17μm2(6.24F2with F-0.165μm) was successfully fabricated and a high bit yield(∼99.999%) was obtained. © 2006 IEEE.

  • Overview and future challenge of Floating Body Cell (FBC) technology for embedded applications

    Akihiro Nitayama, Takashi Ohsawa, Takeshi Hamamoto

    International Symposium on VLSI Technology, Systems, and Applications, Proceedings  

    発表年月: 2006年12月

     概要を見る

    A one-transistor memory cell on silicon-on-insulator, called Floating Body Cell (FBC), has been developed for high density embedded DRAM applications. The functionality of a 128Mb FBC DRAM using fully compatible 90nm CMOS technology has been successfully demonstrated. The memory cell design, such as fully-depleted (FD) operation with substrate-bias, and the process integration, such as well and Cu wiring, are reviewed. The scalability and future challenge of FBC technology are discussed as well. © 2006 IEEE.

  • A Floating Body Cell (FBC) fully compatible with 90nm CMOS technology node for embedded applications

    Takeshi Hamamoto, Yoshihiro Minami, Tomoaki Shino, Atsushi Sakamoto, Tomoki Higashi, Naoki Kusunoki, Katsuyuki Fujita, Kosuke Hatsuda, Takashi Ohsawa, Nobutoshi Aoki, Hiroyoshi Tanimoto, Mutsuo Morikado, Hiroomi Nakajima, Kazumi Inoh, Akihiro Nitayama

    2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06  

    発表年月: 2006年12月

     概要を見る

    Floating Body Cell (FBC) is a one-transistor memory cell on SOI substrate, which aims high density embedded memory on SOC. In order to verify this memory cell technology, a 128Mb SOI DRAM with FBC has been designed and successfully developed. The memory cell design, and the experimental results, such as the signal and the retention characteristics, are reviewed. The results of the fabricated SOI DRAM and the prospect as embedded memory are also discussed. © 2006 IEEE.

  • An 18.5ns 128Mb SOI DRAM with a floating body cell

    Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda, Tomoki Higashi, Mutsuo Morikado, Yoshihiro Minami, Tomoaki Shino, Hiroomi Nakajima, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe

    Digest of Technical Papers - IEEE International Solid-State Circuits Conference  

    発表年月: 2005年12月

     概要を見る

    A dynamic latch sense amplifier/bit line replenishes "1" cells with holes lost during word line cycles and reduces the refresh busy rate. A multi-averaging method of dummy cells over 128 pairs of "1s" and "0s" enhances the sense margin and contributes to the 18.5ns access time. The 25.7ns virtually static RAM (VSRAM) mode is realized by taking advantage of the cell's quasi non-destructive read-out. © 2005 IEEE.

  • An 18.5ns 128Mb SOI DRAM with a floating body cell

    Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda, Tomoki Higashi, Mutsuo Morikado, Yoshihiro Minami, Tomoaki Shino, Hiroomi Nakajima, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe

    Digest of Technical Papers - IEEE International Solid-State Circuits Conference  

    発表年月: 2005年12月

  • A Floating Body Cell (FBC) fully compatible with 90nm CMOS technology(CMOS IV) for 128Mb SOI DRAM

    Yoshihiro Minami, Tomoaki Shino, Atsushi Sakamoto, Tomoki Higashi, Naoki Kusunoki, Katsuyuki Fujita, Kosuke Hatsuda, Takashi Ohsawa, Nobutoshi Aoki, Hiroyoshi Tanimoto, Mutsuo Morikado, Hiroomi Nakajima, Kazumi Inoh, Takeshi Hamamoto, Akihiro Nitayama

    Technical Digest - International Electron Devices Meeting, IEDM  

    発表年月: 2005年12月

     概要を見る

    A 128Mb SOI DRAM with FBC (Floating Body Cell) has been successfully developed for the first time. Two technologies have been newly implemented. (i)In order to realize full functionality and good retention characteristics, the well design has been optimized both for the array device and the peripheral circuit. (ii)Cu wiring has been used for Bit Line(BL) and Source Line(SL), which leads to increasing the signal of the worst bit in the array and also realizes the full compatibility with 90nm CMOS Technology. © 2005 IEEE.

  • A 333MHz random cycle DRAM using the floating body cell

    Kosuke Hatsuda, Katsuyuki Fujita, Takashi Ohsawa

    Proceedings of the Custom Integrated Circuits Conference  

    発表年月: 2005年12月

     概要を見る

    A Monte Carlo simulation shows that a DRAM using the floating body cell (FBC) realizes a 333MHz high-speed random cycle with an introduction of a symmetrical sense amplifier circuit and optimization of its current mirror ratio. Since the FBC DRAM having a superior affinity with logic LSI process is also shown to have its macro size smaller than the conventional 1T-1C DRAM, the FBC is a promising candidate for next generation embedded DRAM cells. © 2005 IEEE.

  • Fully-depleted FBC (Floating Body Cell) with enlarged signal window and excellent logic process compatibility

    Tomoaki Shino, Tomoki Higashi, Naoki Kusunoki, Katsuyuki Fujita, Takashi Ohsawa, Nobutoshi Aoki, Hiroyoshi Tanimoto, Yoshihiro Minami, Takashi Yamada, Mutsuo Morikado, Hiroomi Nakajima, Kazumi Inoh, Takeshi Hamamoto, Akihiro Nitayama

    Technical Digest - International Electron Devices Meeting, IEDM  

    発表年月: 2004年12月

     概要を見る

    Fully-depleted (FD) Floating Body Cell on 55nm SOI featuring excellent logic process compatibility has been successfully developed. For the first time FD operation is reported through significant signal enlargement by negative substrate bias. Using standard salicide process and FD operation, high-density embedded memory on SOI is achievable. © 2004 IEEE.

  • Highly scalable FBC (floating body cell) with 25nm BOX structure for embedded DRAM applications

    Tomoaki Shino, Tomoki Higashi, Katsuyuki Fujita, Takashi Ohsawa, Yoshihiro Minami, Takashi Yamada, Mutsuo Morikado, Hiroomi Nakajima, Kazumi Inoh, Takeshi Hamamoto, Akihiro Nitayama

    Digest of Technical Papers - Symposium on VLSI Technology  

    発表年月: 2004年10月

     概要を見る

    A novel FBC with 25nm-thick BOX (buried oxide) structure has been developed. A feature of new FBC is scalability in the case of thinner SOI, which promises embedded DRAM on SOI in future generations. Using 96Kbit array, the pause time distribution of FBC is demonstrated for the first time. Due to simplified structure, pause time variation of new FBC is significantly suppressed compared with conventional FBC.

  • FBC (Floating Body Cell) for Embedded DRAM on SOI

    Kazumi Inoh, Tomoaki Shino, Hiroaki Yamada, Hiroomi Nakajima, Yoshihiro Minami, Takashi Yamada, Takashi Ohsawa, Tomoki Higashi, Katsuyuki Fujita, Tamio Ikehashi, Takeshi Kajiyama, Yoshiaki Fukuzumi, Takeshi Hamamoto, Hidemi Ishiuchi

    Digest of Technical Papers - Symposium on VLSI Technology  

    発表年月: 2003年10月

     概要を見る

    The memory cell characteristics of the FBC (Floating Body Cell) have been experimentally verified by 0.17μm cell array for the first time. The FBC is a one-transistor gain cell, which is a suitable structure for the future embedded DRAM on SOI wafer. The memory cell layout and the process integration have been designed from the viewpoint of the logic process compatibility without sacrificing the data retention characteristics. The salicide process with the poly-Si plug is implemented into the process integration. The most important device characteristics for realizing the FBC is the threshold voltage difference (Δ Vth) of the cell transistor between "1" state and "0" state. The key device parameters in order to enlarge the Δ Vth are experimentally clarified. A Δ Vth of 0.4V has been obtained, which leads to 99.77% function bit yield of 96Kbit ADM (Array Diagnostic Monitor). The retention time of 5sec has been realized at the room temperature.

  • A Memory Using One-transistor Gain Cell on SOI(FBC) with Performance Suitable for Embedded DRAM's

    Takashi Ohsawa, Tomoki Higashi, Katsuyuki Fujita, Tamio Ikehashi, Takeshi Kajiyama, Yoshiaki Fukuzumi, Tomoaki Shino, Hiroaki Yamada, Hiroomi Nakajima, Yoshihiro Minami, Takashi Yamada, Kazumi Inoh, Takeshi Hamamoto

    IEEE Symposium on VLSI Circuits, Digest of Technical Papers  

    発表年月: 2003年10月

     概要を見る

    A 288Kbit memory chip featuring a one-transistor gain cell on SOI of the size 0.21 μ m2(7F2with F=0.175 μ m) which we named the floating body transistor cell(FBC) is presented and basic characteristics of the cell and the memory chip performance are disclosed. The threshold voltages of a cell transistor in the chip for the data "1" and for the data "0" are measured by using a direct access test circuit and a fail bit map for the 96Kbit array is obtained. A sensing scheme which was designed to eliminate the effect of cell characteristics variation due to process and temperature fluctuation as common mode noise is verified to be working and the random access time is measured to be less than 100ns. The characteristics of data hold demonstrate that the FBC can satisfy retention time specifications for some embedded memories. The access time and the data retention time show that the FBC has a potential to be used as a future embedded DRAM memory cell.

  • Memory design using one-transistor gain cell on SOI

    Takashi Ohsawa, Katsuyuki Fujita, Tomoki Higashi, Yoshihisa Iwata, Takeshi Kajiyama, Yoshiaki Asao, Kazumasa Sunouchi

    Digest of Technical Papers - IEEE International Solid-State Circuits Conference  

    発表年月: 2002年01月

     概要を見る

    A 512 kb DRAM has a 7F2one-transistor gain cell (F=0.18 μm) on SOI. The array driving method makes selective write possible. Basic operation is verified by device simulation and hardware measurement. Simulations show 40 ns access time. Non-destructive readout and Cb/Cs-free signal development improve cell efficiency.

  • Memory design using one-transistor gain cell on SOI

    Takashi Ohsawa, Katsuyuki Fujita, Tomoki Higashi, Yoshihisa Iwata, Takeshi Kajiyama, Yoshiaki Asao, Kazumasa Sunouchi

    Digest of Technical Papers - IEEE International Solid-State Circuits Conference  

    発表年月: 2002年01月

     概要を見る

    Memory design was carried out using one-transistor gain cell on SOI. This memory design is based on a one-transistor gain cell which is smaller, less complex to make and more scalable to sub-0.1μm generations than the existing dynamic random access memory (DRAM) cells, without resorting to new materials and device structure. Transient analysis of a device simulation was also discussed to verify operation of the floating body transistor cell (FBC).

  • A high random-access-data-rate 4MbDRAM with pipeline operation

    Tohru Furuyama, Natsuki Kushiyama, Yohji Watanabe, Takashi Ohsawa, Kazuyoshi Muraoka, Yousei Nagahama

    1990 Symposium on VLSI Circuits; Honolulu, HI, USA; ; 7 June 1990 through 9 June 1990  

    発表年月: 1990年12月

     概要を見る

    A novel circuit technology which introduces a pipeline scheme in a read operation and improves the random-access data rate by roughly 30% is described. This technology has been applied to a 4M DRAM, and the RAM showed a short cycle time of less than 100 ns, i.e., a more than 10-MHz data rate, under the worst operating condition. In addition, a very fast virtual RAS access time of 20 ns has been obtained. Since the pipeline DRAM does not require any new process and/or assembly technologies, it can be added to the standard DRAM family.

  • Experimental 2-bit/cell storage DRAM for macro cell or memory-on-logic application.

    Tohru Furuyama, Takashi Ohsawa, Yousei Nagahama, Hiroto Tanaka, Yohji Watanabe, Tohru Kimura, Kazuyoshi Muraoka, Kenji Natori

    Proceedings of the Custom Integrated Circuits Conference  

    発表年月: 1988年12月

     概要を見る

    A novel multiple-level storage DRAM (dynamic random-access memory) technique which obtains fairly fast access time is presented. The RAM area, especially the cell-array area, which is highly defect-sensitive, is reduced with this technique. Reasonable yield can thus be achieved. An experimental 1-Mb DRAM has been fabricated, and the 2-bit/cell storage technique has been verified to be suitable for macro-cell or memory-on-logic application.

  • New CR-delay circuit technology for high-density and high-speed DRAMs

    Yohji Watanabe, Takashi Ohsawa, Kiyofumi Sakurai, Tohru Furuyama

    1988 Symposium on VLSI Circuits - Digest of Technical Papers; Tokyo, Japan; ; 22 August 1988 through 24 August 1988  

    発表年月: 1988年12月

     概要を見る

    A CR-delay circuit technology for the realization of high-speed operation with a wide operational margin and minimized timing loss is discussed. It was applied to a 4-Mb CMOS DRAM, and the experimental results are described. A significant reduction in access time and cycle time was achieved.

  • A 60ns 4Mb DRAM with built-in self-test

    大澤 隆

    International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, pp. 286-287  

    発表年月: 1987年02月

  • ON-CHIP SUPPLY VOLTAGE CONVERSION SYSTEM AND ITS APPLICATION TO A 4Mb DRAM.

    Yohji Watanabe, Shigeyoshi Watanabe, Takashi Ohsawa, Tohru Furuyama, Kazunori Ohuchi

    Conference on Solid State Devices and Materials  

    発表年月: 1986年12月

     概要を見る

    An on-chip supply voltage conversion system for VLSI DRAMs, which realizes supply voltage reduction in whole RAM circuits, is proposed and applied to a 4Mb DRAM. Implementing the system on a DRAM, short channel MOSFETs could be utilized, thus achieving faster access time than a DRAM using conventional long channel MOSFETs. The system has been successfully demonstrated to be effective for high density and high speed DRAMs.

  • NEW ON-CHIP VOLTAGE CONVERTER FOR SUBMICRON HIGH-DENSITY DRAMs.

    Tohru Furuyama, Yohji Watanabe, Takashi Ohsawa, Shigeyoshi Watanabe

    ESSCIRC '86: Twelfth European Solid-State Circuits Conference.; Delft, Neth  

    発表年月: 1986年12月

     概要を見る

    A new on-chip voltage converter has been developed, and its characteristics have been examined. Being implemented in an experimental 4Mb dynamic RAM, this voltage converter has successfully demonstrated to be of importance for high-density, high-speed, and high-reliability DRAMs with submicron transistors.

  • An experimental 4Mb CMOS DRAM

    大澤 隆

    International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, pp. 272-273  

    発表年月: 1986年02月

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学内研究費(特定課題)

  • 統計的ばらつき耐性を向上させるニューラルネットワーク推論エンジンの学習法の研究

    2019年  

     概要を見る

    ReRAMはアナログ抵抗値を記憶できるデバイスで、人工ニューラルネットワーク(ANN)を小型・低消費電力化するのに最適の不揮発性メモリデバイスである。抵抗値をANNの重みとみなす場合、負の重みを実現するためには従来、正のクロスバ・アレー(CBA)と負のCBAのダブルCBA(DCBA)構造を用いていた。正のCBAから流れ出る電流から負のCBAから流れ出る電流を引き算回路で差し引くことによって対応するReRAM抵抗対の大小関係によって正と負の重みを実現していた。我々は、このような構造に比べてほぼ半分のサイズ、消費電流になるシングルCBA(SCBA)方式を提案し、推論の精度が同等であることを示すことができた、この方式をReRAMデバイスとCMOS回路で設計した。

  • ニューラルネットワーク推論アクセラレータを高精度化する学習法に関する研究

    2019年  

     概要を見る

    昨年度、トランジスタ1個とキャパシタ1個からなるDRAMセルをベースとしたANNを設計し、その性能をシミュレーションにより検証した。入力と重み共にディジタル信号を用いた。今年度は、推論精度の向上、アレー面積の小型化、低消費電力を目指し、入力をアナログ信号にしたANNを設計して、その性能をシミュレーションにて検証した。また、ReRAMを用いたクロスバー・アレー(CBA)からなるANNをオンチップにて学習する方法を研究した。我々は、標準的な誤差逆伝搬法(BP)を使った学習をアナログ積算回路を用いてCBA内に組み込んだ。また、シナプス回路のメモリを削減するために、BPを改良したアルゴリズムを使った新たな学習法を考案し、それがBPと同等の推論精度を与えることを示すことができた。

  • アナログ・ディジタル混成型ニューラルネットワーク構築のための基礎研究

    2018年  

     概要を見る

    単一トランジスタ(1T)と単一容量(1C)からなる複数の1T1C型DRAMセルに電荷を蓄積させてそれを人工シナプスと見做し、各シナプスに蓄積された電荷を再配分することによりアナログ的な積・和演算をローパワーで実行するアナログ・ディジタル混成型ニューラルネットワークを考案した。回路シミュレーションにより、演算の線形性と等値性を確認した[1]。 他方、ReRAMを2値の抵抗値記憶素子として2個のトランジスタと2個のReRAMからなるシナプスを考案し、これを用いたニューラルネットワークを提案した[2]。ハードウェアのランダムバラツキ情報を考慮した学習法を採用することにより、バラツキに対する推論精度が大幅に改善できることがシミュレーションによって判明した[3]。

  • シングルエンドデータ・セルアレーへの電流モード型センスアンプ組み込み法

    2017年  

     概要を見る

    ”1”と”0”のセル特性ばらつきに非対称性がある場合でもメモリ歩留まりを最大化できる新しい基準電位(電流)発生方式を考案し、それが大容量MRAMのメモリセルを構成する磁気トンネル・ジャンクション素子(MTJ)に要求されるスペックを緩和できる効果があることを具体的に示した。本方式は、複数の”1”と”0”セルを平均化する機構の枠内において、従来同じだった”1”セルの数と”0”セルの数を同数からずらすことで、基準レベルの位置を”1”と”0”のばらつきの標準偏差の小さい方へシフトさせ、セルアレー内のデータパターンに依存しない歩留まりを確保しその値を最大化するものである。これを128MbのMRAMに適用することで、従来130%必要だったMTJのTMR比が90%でよくなることが判明し、MTJデバイス開発の負担を大きく緩和できることを示すことができた。

 

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