OHSAWA, Takashi

写真a

Affiliation

Faculty of Science and Engineering, Graduate School of Information, Production, and Systems

Job title

Professor(without tenure)

Homepage URL

https://www.waseda.jp/fsci/gips/other/2017/03/31/7685/

Concurrent Post 【 display / non-display

  • Faculty of Science and Engineering   School of Fundamental Science and Engineering

Research Institute 【 display / non-display

  • 2020
    -
    2022

    理工学術院総合研究所   兼任研究員

Degree 【 display / non-display

  • University of Tsukuba   Ph.D.

 

Research Areas 【 display / non-display

  • Computer system

Papers 【 display / non-display

  • Co-Design of Binary Processing in Memory ReRAM Array and DNN Model Optimization Algorithm

    Yue Guan, Takashi Ohsawa

    IEICE TRANSACTIONS ON ELECTRONICS   E103C ( 11 ) 685 - 692  2020.11

     View Summary

    In recent years, deep neural network (DNN) has achieved considerable results on many artificial intelligence tasks, e.g. natural language processing. However, the computation complexity of DNN is extremely high. Furthermore, the performance of traditional von Neumann computing architecture has been slowing down due to the memory wall problem. Processing in memory (PIM), which places computation within memory and reduces the data movement, breaks the memory wall. ReRAM PIM is thought to be a available architecture for DNN accelerators. In this work, a novel design of ReRAM neuromorphic system is proposed to process DNN fully in array efficiently. The binary ReRAM array is composed of 2T2R storage cells and current minor sense amplifiers. A dummy BL reference scheme is proposed for reference voltage generation. A binary DNN (BDNN) model is then constructed and optimized on MNIST dataset. The model reaches a validation accuracy of 96.33% and is deployed to the ReRAM PIM system. Co-design model optimization method between hardware device and software algorithm is proposed with the idea of utilizing hardware variance information as uncertainness in optimization procedure. This method is analyzed to achieve feasible hardware design and generalizable model. Deployed with such co-design model, ReRAM array processes DNN with high robustness against fabrication fluctuation.

    DOI

  • Array Design of High-Density Emerging Memories Making Clamped Bit-Line Sense Amplifier Compatible with Dummy Cell Average Read Scheme

    Ziyue Zhang, Takashi Ohsawa

    IEICE TRANSACTIONS ON ELECTRONICS   E103C ( 8 ) 372 - 380  2020.08

     View Summary

    Reference current used in sense amplifiers is a crucial factor in a single-end read manner for emerging memories. Dummy cell average read scheme uses multiple pairs of dummy cells inside the array to generate an accurate reference current for data sensing. The previous research adopts current minor sense amplifier (CMSA) which is compatible with the dummy cell average read scheme. However, clamped bit-line sense amplifier (CBLSA) has higher sensing speed and lower power consumption compared with CMSA. Therefore, applying CBLSA to dummy cell average read scheme is expected to enhance the performance. This paper reveals that direct combination of CBLSA and dummy cell average read scheme leads to sense margin degradation. In order to solve this problem, a new array design is proposed to make CBLSA compatible with dummy cell average read scheme. Current minor structure is employed to prevent CBLSA from being short-circuited directly. The simulation result shows that the minimum sensible tunnel magnetoresistance ratio (TMRR) can be extended from 14.3% down to 1%. The access speed of the proposed sensing scheme is less than 2 ns when TMRR is 70% or larger, which is about twice higher than the previous research. And this circuit design just consumes half of the energy in one read cycle compared with the previous research. In the proposed array architecture, all the dummy cells can be always short-circuited in totally isolated area by low-resistance metal wiring instead of using controlling transistors. This structure is able to contribute to increasing the dummy cell averaging effect. Besides, the array-level simulation validates that the array design is accessible to every data cell. This design is generally applicable to any kinds of resistance-variable emerging memories including STT-MRAM.

    DOI

  • Cell Array Design with Row-Driven Source Line in Block Shunt Architecture Applicable to Future 6F(2) 1T1MTJ Memory

    Tongshuang Huang, Takashi Ohsawa

    2019 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA)    2019

     View Summary

    In this paper, we propose a new 1T1MTJ cell array architecture with SL parallel to WL to achieve a small cell size, in which page mode write can be realized without performance degradation. We propose a row-driven source line (RSL) 1T1MTJ memory cell array architecture for minimizing the cell size and a corresponding operational waveform. A block shunt architecture (BSA) that shunts lower source line (LSL) and upper source line (USL) is proposed to make page mode write possible. Size of 1T1MTJ cell can be shrunk to 6F(2) when the state-of-the-art design rules are applied.

  • User-Friendly Compact Model of Magnetic Tunnel Junctions for Circuit Simulation Based on Switching Probability

    Haoyan Liu, Takashi Ohsawa

    2019 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)    2019

     View Summary

    We propose a new compact MTJ model for circuit simulation which is implemented by Verilog-A and can be easily built in de-facto standard SPICE. The model is based on switching probability of an MTJ with time-varying input current. The transition between the adiabatic precessional model and the thermal activation model is made smooth by using an interpolation function with a technique to predict a switching time from an input current. Simulation results validate that the model is consistent with physical model and effective for MTJ/CMOS hybrid circuit simulation.

  • A new read scheme for high-density emerging memories

    Takashi Ohsawa

    IEICE Transactions on Electronics   E101C ( 6 ) 423 - 429  2018.06

     View Summary

    Several new memories are being studied as candidates of future DRAM that seems difficult to be scaled. However, the read signal in these new memories needs to be amplified in a single-end manner with reference signal supplied if they are aimed for being applied to the high-density main memory. This scheme, which is fortunately not necessary in DRAM's 1/2Vdd pre-charge sense amp, can become a serious bottleneck in the new memory development, because the device electrical parameters in these new memory cells are prone to large cell-to-cell variations without exception. Furthermore, the extent to which the parameter fluctuates in data “1” is generally not the same as in data “0”. In these situations, a new sensing scheme is proposed that can minimize the sensing error rate for high-density single-end emerging memories like STT-MRAM, ReRAM and PCRAM. The scheme is based on averaging multiple dummy cell pairs that are written “1” and “0” in a weighted manner according to the fluctuation unbalance between “1” and “0”. A detailed analysis shows that this scheme is effective in designing 128Mb 1T1MTJ STT-MRAM with the results that the required TMR ratio of an MTJ can be relaxed from 130% to 90% for the fluctuation of 6% sigma-to-average ratio of MTJ resistance in a 16 pair-dummy cell averaging case by using this technology when compared with the arithmetic averaging method.

    DOI

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Books and Other Publications 【 display / non-display

  • Floating Body Cell ---- A Novel Capacitorless DRAM Cell ----

    Takashi Ohsawa, Takeshi Hamamoto( Part: Joint author, pp. 1-111, pp. 113-116, pp. 127-254 (total 254 pages))

    Pan Stanford Publishing Pte. Ltd.  2012

Misc 【 display / non-display

  • 1Mb 4T-2MTJ Nonvolatile STT-RAM for Embedded Memories Using 32b Fine-Gained Power Gating Technique : Achieves 1.0ns/200ps Wake-Up/Power-Off Times

    ENDOH Tetsuo, OHSAWA Takashi, KOIKE Hiroki, MIURA Sadahiko, HONJO Hiroaki, TOKUTOME Keiichi, IKEDA Shoji, HANYU Takahiro, OHNO Hideo

    Technical report of IEICE. ICD   113 ( 1 ) 27 - 32  2013.04

     View Summary

    A 1Mb embedded memory was designed and fabricated using a cell consisting of four NFETs and two spin-transfer torque magnetic tunnel junctions (STT-MTJs) which is a nonvolatile memory device with excellent write endurance. A 32b fine-grained power gating technique is applied to achieve a fast access/cycle times along with a low standby and operation powers. Since the 4T2MTJ cell size is defined by its four NFETs with the two MTJs put on them, the cell has a potential to become smaller than the SRAM cell. It was shown that the 4T2MTJ STT-RAM macro can be smaller than the SRAM counterpart by scaling the technology to 25nm-45nm and beyond, depending on its scaling scenarios, due to the MTJ switching current reduction by the scaling.

    CiNii

  • シリコン不揮発性メモリ技術の限界を突破するスピントルク注入型磁気メモリの最新動向

    遠藤哲郎, 大澤隆, 小池洋紀, 羽生貴弘, 笠井直記, 大野英男

    電子情報通信学会誌   ( 平成24年11月号 )  2012.11

    Article, review, commentary, editorial, etc. (other)  

  • STT-MRAM for future high performance Nonvolatile memory

    遠藤哲郎, 大澤隆, 小池洋紀, 羽生貴弘, 笠井直記, 大野英男

    電子情報通信学会誌   ( 平成24年11月号 )  2012.11

    Article, review, commentary, editorial, etc. (other)  

Awards 【 display / non-display

  • SSDM Paper Award

    2012.09   International Conference on Solid State Devices and Materials  

    Winner: Takashi Ohsawa

  • The Takuo Sugano Award

    2003.02   IEEE International Solid-State Circuits Confenetce  

    Winner: Takashi Ohsawa

Presentations 【 display / non-display

  • Co-design of DNN Model Optimization for Binary ReRAM Array In-memory Processing

    Yue Guan, Takashi Ohsawa

    Proceedings of Technical Program - IEEE 2019 11th International Memory Workshop, Monterey, USA 

    Presentation date: 2019.05

  • User-Friendly Compact Model of Magnetic Tunnel Junctions for Circuit SImulation Based on Switching Probability

    Haoyan Liu, Takashi Ohsawa

    Proceedings of Technical Program - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 

    Presentation date: 2019.04

  • Accurate Meassurement of Sneak Current in ReRAM Crossbar Array with Data Storage Pattern Dependencies

    Yaqi Shang, Takashi Ohsawa

    Proceedings of Technical Program - 2019 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2019 

    Presentation date: 2019.04

  • Cell Array Design with Row-Driven Source Line in Block Shunt Architecture Applicable to Future 6F2 1T1MTJ Memory

    Tongshuang Huang, Takashi Ohsawa

    Proceedings of Technical Program - 2019 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2019 

    Presentation date: 2019.04

  • Studies on read-stability and write-ability of fast access STT-MRAMs

    Takashi Ohsawa, Takashi Ohsawa, Shoji Ikeda, Shoji Ikeda, Takahiro Hanyu, Takahiro Hanyu, Takahiro Hanyu, Hideo Ohno, Hideo Ohno, Hideo Ohno, Tetsuo Endoh, Tetsuo Endoh, Tetsuo Endoh

    Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2014 

    Presentation date: 2014.01

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Specific Research 【 display / non-display

  • 統計的ばらつき耐性を向上させるニューラルネットワーク推論エンジンの学習法の研究

    2019  

     View Summary

    ReRAMはアナログ抵抗値を記憶できるデバイスで、人工ニューラルネットワーク(ANN)を小型・低消費電力化するのに最適の不揮発性メモリデバイスである。抵抗値をANNの重みとみなす場合、負の重みを実現するためには従来、正のクロスバ・アレー(CBA)と負のCBAのダブルCBA(DCBA)構造を用いていた。正のCBAから流れ出る電流から負のCBAから流れ出る電流を引き算回路で差し引くことによって対応するReRAM抵抗対の大小関係によって正と負の重みを実現していた。我々は、このような構造に比べてほぼ半分のサイズ、消費電流になるシングルCBA(SCBA)方式を提案し、推論の精度が同等であることを示すことができた、この方式をReRAMデバイスとCMOS回路で設計した。

  • ニューラルネットワーク推論アクセラレータを高精度化する学習法に関する研究

    2019  

     View Summary

    昨年度、トランジスタ1個とキャパシタ1個からなるDRAMセルをベースとしたANNを設計し、その性能をシミュレーションにより検証した。入力と重み共にディジタル信号を用いた。今年度は、推論精度の向上、アレー面積の小型化、低消費電力を目指し、入力をアナログ信号にしたANNを設計して、その性能をシミュレーションにて検証した。また、ReRAMを用いたクロスバー・アレー(CBA)からなるANNをオンチップにて学習する方法を研究した。我々は、標準的な誤差逆伝搬法(BP)を使った学習をアナログ積算回路を用いてCBA内に組み込んだ。また、シナプス回路のメモリを削減するために、BPを改良したアルゴリズムを使った新たな学習法を考案し、それがBPと同等の推論精度を与えることを示すことができた。

  • アナログ・ディジタル混成型ニューラルネットワーク構築のための基礎研究

    2018  

     View Summary

    単一トランジスタ(1T)と単一容量(1C)からなる複数の1T1C型DRAMセルに電荷を蓄積させてそれを人工シナプスと見做し、各シナプスに蓄積された電荷を再配分することによりアナログ的な積・和演算をローパワーで実行するアナログ・ディジタル混成型ニューラルネットワークを考案した。回路シミュレーションにより、演算の線形性と等値性を確認した[1]。 他方、ReRAMを2値の抵抗値記憶素子として2個のトランジスタと2個のReRAMからなるシナプスを考案し、これを用いたニューラルネットワークを提案した[2]。ハードウェアのランダムバラツキ情報を考慮した学習法を採用することにより、バラツキに対する推論精度が大幅に改善できることがシミュレーションによって判明した[3]。

  • シングルエンドデータ・セルアレーへの電流モード型センスアンプ組み込み法

    2017  

     View Summary

    ”1”と”0”のセル特性ばらつきに非対称性がある場合でもメモリ歩留まりを最大化できる新しい基準電位(電流)発生方式を考案し、それが大容量MRAMのメモリセルを構成する磁気トンネル・ジャンクション素子(MTJ)に要求されるスペックを緩和できる効果があることを具体的に示した。本方式は、複数の”1”と”0”セルを平均化する機構の枠内において、従来同じだった”1”セルの数と”0”セルの数を同数からずらすことで、基準レベルの位置を”1”と”0”のばらつきの標準偏差の小さい方へシフトさせ、セルアレー内のデータパターンに依存しない歩留まりを確保しその値を最大化するものである。これを128MbのMRAMに適用することで、従来130%必要だったMTJのTMR比が90%でよくなることが判明し、MTJデバイス開発の負担を大きく緩和できることを示すことができた。

 

Syllabus 【 display / non-display

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