INUISHI, Masahide

写真a

Affiliation

Faculty of Science and Engineering, Graduate School of Information, Production, and Systems

Job title

Professor(without tenure)

Concurrent Post 【 display / non-display

  • Faculty of Science and Engineering   School of Fundamental Science and Engineering

Research Institute 【 display / non-display

  • 2020
    -
    2022

    理工学術院総合研究所   兼任研究員

Degree 【 display / non-display

  • Northwestern Univ.   Ph.D

Research Experience 【 display / non-display

  • 2003.04
    -
    2016.02

    ルネサスエレクトロニクス   生産本部技術統括部   技師長/統括部長/部長

 

Papers 【 display / non-display

  • On the scaling limit of the Si-IGBTs with very narrow mesa structure

    Eikyu Katsumi, Sakai Atsushi, Matsuura Hitoshi, Nakazawa Yoshito, Akiyama Yutaka, Yamaguchi Yasuo, Inuishi Masahide

    IEEE Conference Proceedings   2016 ( ISPSD ) 211‐214  2016

    DOI J-GLOBAL

  • A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits

    Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinobara

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   42 ( 4 ) 820 - 829  2007.04

     View Summary

    In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-mu m(2) SRAM cell with a beta ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology.

    DOI J-GLOBAL

  • Suppression of boron penetration from source/drain-extension to improve gate leakage characteristics and gate-oxide reliability for 65-nm node CMOS and beyond

    T Hayashi, T Yamashita, K Shiga, K Hayashi, H Oda, T Eimori, M Inuishi, Y Ohji

    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS   44 ( 4B ) 2157 - 2160  2005.04

     View Summary

    Boron penetration from the poly-silicon gate to the silicon substrate through gate dielectrics is a crucial problem in the dual gate complementary rnetal-oxide semiconductor (CMOS) process. Therefore, the plasma nitridation technique has been studied well, and it has succeeded to suppress boron penetration. However, boron penetration occurs not only front the doped poly-silicon gate but also from the substrate, and resulting in several degradations of gate-oxide characteristics. On the other hand, the boron concentration of source/drain (S/D) extension has been increasing with gate shrinkage. We found that boron penetration from the S/D extension becomes a crucial problem in gate leakage and gate-oxide integrity, particularly for nanoscale positive-channel MOS (pMOS). In this study, we examined several treatments in detail to suppress boron penetration from the S/D extension, and demonstrated that the plasma nitridation treatment after gate etching is the best solution for 65-nm node CMOS and beyond.

    DOI J-GLOBAL

  • Novel shallow trench isolation process from viewpoint of total strain process design for 45 nm node devices and beyond

    M Ishibashi, K Horita, M Sawada, M Kitazawa, M Igarashi, T Kuroi, T Eimori, K Kobayashi, M Inuishi, Y Ohji

    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS   44 ( 4B ) 2152 - 2156  2005.04

     View Summary

    In this paper, a novel shallow trench isolation (STI) process is proposed for 45 nm node technologies and beyond. The major features of this process are the use of a fluorine-doped (F-doped) SiO(2) film for gap filling and high-temperature rapid thermal oxidation (HT-RTO) for gate oxidation. Voidless filling of a narrow trench can be realized by F-doped high-density plasma chemical vapor deposition (F-doped HDP-CVD). Moreover, electron mobility degradation caused by STI stress and junction leakage currents can be minimized using F-doped HDP-CVD with HT-RTO. It was also confirmed that compressive stress in the F-doped HDP-CVD sample is smaller in every measurement point around STI than that in the conventional HDP-CVD sample by convergent-beam electron diffraction (CBED). The Si-F bonds in the oxide film play a very important role in stress reduction, By utilizing HT-RTO, Si-F bonds remain and make the SiO(2) film in the trench coarse. This technique is a very promising 45 nm node STI scheme with high performance and high reliability.

    DOI J-GLOBAL

  • W-polymetal gate with low W/poly-Si interface resistance for high-speed/high-density embedded memory

    T Yamashita, Y Nishida, K Hayashi, T Eimori, M Inuishi, Y Ohji

    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS   43 ( 4B ) 1799 - 1803  2004.04

     View Summary

    A new W-polymetal gate electrode with the structure of W/WN/WSi/poly-Si is proposed. The W-polymetal gate is suitable for high-density memories since it has low resistance and is compatible with the self-aligned contact process. In our study, however, it is found that the interface of W and poly-Si has non-ohmic and quite high resistance in the case wherein only WN is used as a barrier film. This resistance increases the delay in complementary metal-oxide-semiconductor (CMOS) logic circuits and prevents high-speed operation. Our new process includes the deposition of thin WSi on poly-Si, followed by rapid thermal annealing, which results in ohmic and sufficiently low contact resistance between W and poly-Si. It is also demonstrated that selective gate reoxidation is successfully applied for this new structure, and the insertion of thin WSi does not cause any adverse effect on the electrical characteristics of metal-oxide-semiconductor field-effect transistor (MOSFET). This process is promising for high-speed and high-density embedded memory.

    DOI J-GLOBAL

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Misc 【 display / non-display

  • IoTにおける低電力LSIデバイス(SOTB)の最新技術

    山口泰男, 新川田裕樹, 蒲原史朗, 犬石昌秀

    応用物理学会春季学術講演会講演予稿集(CD-ROM)   63rd   ROMBUNNO.19P-W631-4  2016.03

    J-GLOBAL

  • A 65nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits

    YABUUCHI Makoto, OHBAYASHI Shigeki, NII Koji, TSUKAMOTO Yasumasa, IMAOKA Susumu, IGARASHI Motoshige, TAKEUCHI Masahiko, KAWASHIMA Hiroshi, MAKINO Hiroshi, YAMAGUCHI Yasuo, TSUKAMOTO Kazuhiro, INUISHI Masahide, ISHIBASHI Koichiro, SHINOHARA Hirofumi

    IEICE technical report   106 ( 206 ) 149 - 153  2006.08

     View Summary

    We propose a new design scheme to improve the SRAM read and write operation margins in the presence of a large Vth variability. By applying this scheme to a 0.494μm^2 SRAM cell with a β ratio of 1, which is an aggressively small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth value using a 65nm LSTP CMOS technology.

    CiNii

  • スタック型フラッシュメモリーセルのカップリング比直接評価

    岡垣健, 谷沢元昭, 藤永正人, 国清辰也, 結城秀昭, 石川清志, 西川毅一, 栄森貴尚, 犬石昌秀

    応用物理学関係連合講演会講演予稿集   52nd ( 0 ) 16  2005.03

    J-GLOBAL

  • A Novel Shallow Trench Isolation Process from the View Point of Total Strain Process Design for 45nm Node Devices and Beyond

    石橋真人, 堀田勝之, 沢田真人, 北沢雅志, 五十嵐元繁, 黒井隆, 栄森貴尚, 小林清輝, 犬石昌秀

    半導体・集積回路技術シンポジウム講演論文集   67th   68 - 71  2004.12

    J-GLOBAL

  • Low-Voltage SOI CMOS Device Technology using Vth Controlling

    前川繁登, 一法師隆志, 犬石昌秀, 大路譲

    電子情報通信学会技術研究報告   104 ( 251(ICD2004 82-96) ) 19 - 23  2004.08

    J-GLOBAL

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Industrial Property Rights 【 display / non-display

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Presentations 【 display / non-display

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Specific Research 【 display / non-display

  • パワー半導体デバイスの研究

    2019  

     View Summary

    ダイオードとIGBTを同一チップに内蔵して、順方向と逆方向に電流を流せるReverse conducting IGBT は ①snap backによる電流の不連続、不均一な変化の抑制、②内蔵ダイオードの逆回復特性の改良、③IGBTのturn off 特性の改善による消費電力ロスの抑制、などの課題が有り、課題解決には裏面構造、裏面の高濃度N型領域とP型領域のレイアウト、表面側ダイオードの構造、レイアウトと動作への影響を明確に解析することが重要である。このため、プロセス・デバイスシミュレーションと回路シミュレーションを組み合わせたmixed mode の数値解析により、内部動作機構を解析し、構造設計の方法を明らかにした。

 

Syllabus 【 display / non-display

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