2022/12/08 更新

写真a

シノハラ ヒロフミ
篠原 尋史
Scopus 論文情報  
論文数: 0  Citation: 0  h-index: 11

Citation Countは当該年に発表した論文の被引用数

所属
理工学術院 大学院情報生産システム研究科
職名
特任教授

他学部・他研究科等兼任情報

  • 理工学術院   基幹理工学部

学内研究所・附属機関兼任歴

  • 2020年
    -
    2022年

    理工学術院総合研究所   兼任研究員

学歴

  • 2005年04月
    -
    2008年03月

    京都大学   大学院情報学研究科   通信情報システム専攻  

  • 1976年04月
    -
    1978年03月

    京都大学   大学院工学研究科   電子工学専攻  

  • 1972年04月
    -
    1976年03月

    京都大学   工学部   電子工学科  

学位

  • 博士

経歴

  • 2015年03月
    -
    継続中

    早稲田大学   大学院情報生産システム研究科 (IPS)   教授

  • 2014年08月
    -
    2015年03月

    株式会社半導体理工学研究センター(STARC)   執行役員

  • 2010年04月
    -
    2014年07月

    ルネサスエレクトロニクス株式会社

  • 2009年07月
    -
    2014年07月

    株式会社半導体理工学研究センター(STARC) 出向   執行役員

  • 2003年04月
    -
    2010年03月

    株式会社ルネサステクノロジ

  • 1978年04月
    -
    2003年03月

    三菱電機株式会社

▼全件表示

所属学協会

  •  
     
     

    IEEE

  •  
     
     

    電子情報通信学会

 

研究分野

  • 電子デバイス、電子機器   集積回路

  • 情報学基礎論

研究キーワード

  • ハードウェアセキュリティ

  • 低エネルギー回路

  • SRAM

  • 真乱数発生器

  • PUF

論文

  • A 0.186-pJ per Bit Latch-Based True Random Number Generator Featuring Mismatch Compensation and Random Noise Enhancement

    Ruilin Zhang, Xingyu Wang, Kunyang Liu, Hirofumi Shinohara

    IEEE JOURNAL OF SOLID-STATE CIRCUITS    2022年03月

     概要を見る

    This article proposes a mismatch self-compensation latch-based true random number generator (TRNG) that harvests a metastable region's enhanced random noise. The proposed TRNG exhibits high randomness across a wide voltage (0.3-1.0 V) and temperature (-20 degrees C-100 degrees C) range by employing XOR of only four entropy sources (ESs). To achieve a full entropy output, an 8-bit von Neumann post-processing with waiting (VN8W) is used. The randomness of the TRNG's output is verified by NIST SP 800-22 and NIST SP 800-90B tests. The proposed TRNG, fabricated in 130-nm CMOS, achieves state-of-the-art energy of 0.186 pJ/bit at 0.3 V with a core (four ESs + XOR circuits) area of 661 mu m(2) and a total area of 5561 mu m(2), including VN8W. The robustness against power noise injection attacks is also demonstrated. An accelerating aging test revealed that the TRNG achieves a stable operation after 19 h of aging, which is equivalent to the 11-year life reliability. The mismatch-to-noise ratio analysis revealed that the XOR-OUT of TRNG core has more than 6 sigma robustness against random mismatch variations.

    DOI

    Scopus

    1
    被引用数
    (Scopus)
  • A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement

    Xingyu Wang, Ruilin Zhang, Yuxin Wang, Kunyang Liu, Xuanzhen Wang, Hirofumi Shinohara

    2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings    2022年

     概要を見る

    This paper presents a latch-based TRNG that achieves high raw entropy generation (>0.9) across wide voltage and temperature (0.31.0 V, -40110 °C) in a single latch-based entropy source by static inverter selection and noise enhancement techniques. In a 130 nm CMOS technology, the TRNG occupies 5343 μm2 and consumes 0.116pJ/bit at 0.3 V including an on-chip Von Neumann post-processing circuit. The crypto-graphically-secure randomness of TRNG's output is verified by NIST SP 800-22 and 800-90B tests. An equivalent 20-year life at 0.3 V, 25°C is confirmed by an accelerated aging test.

    DOI

    Scopus

  • A 0.5-V Hybrid SRAM Physically Unclonable Function Using Hot Carrier Injection Burn-In for Stability Reinforcement

    Kunyang Liu, Xinpeng Chen, Hongliang Pu, Hirofumi Shinohara

    IEEE Journal of Solid-State Circuits   56 ( 7 ) 2193 - 2204  2021年07月  [査読有り]

    担当区分:最終著者

    DOI

  • Energy-Efficient Post-Processing Technique Having High Extraction Efficiency for True Random Number Generators

    Ruilin Zhang, Xingyu Wang, Hirofumi Shinohara

    IEICE TRANSACTIONS ON ELECTRONICS   E104C ( 7 ) 300 - 308  2021年07月

     概要を見る

    In this paper, we describe a post-processing technique having high extraction efficiency (ExE) for de-biasing and de-correlating a random bitstream generated by true random number generators (TRNGs). This research is based on the N-bit von Neumann (VN_N) post-processing method. It improves the ExE of the original von Neumann method close to the Shannon entropy bound by a large N value. However, as the N value increases, the mapping table complexity increases exponentially (2(N)), which makes VN_N unsuitable for low-power TRNGs. To overcome this problem, at the algorithm level, we propose a waiting strategy to achieve high ExE with a small N value. At the architectural level, a Hamming weight mapping-based hierarchical structure is used to reconstruct the large mapping table using smaller tables. The hierarchical structure also decreases the correlation factor in the raw bitstream. To develop a technique with high ExE and low cost, we designed and fabricated an 8-bit von Neumann with waiting strategy (VN_8W) in a 130-nm CMOS. The maximum ExE of VN_8W is 62.21%, which is 2.49 times larger than the ExE of the original von Neumann. NIST SP 800-22 randomness test results proved the debiasing and de-correlation abilities of VN_8W. As compared with the state-of-the-art optimized 7-element iterated von Neumann, VN_8W achieved more than 20% energy reduction with higher ExE. At 0.45V and 1 MHz, VN_8W achieved the minimum energy of 0.18 pJ/bit, which was suitable for sub-pJ low energy TRNGs.

    DOI

    Scopus

    2
    被引用数
    (Scopus)
  • A 0.186-pJ per Bit Latch-Based True Random Number Generator with Mismatch Compensation and Random Noise Enhancement

    Ruilin Zhang, Xingyu Wang, Luying Wang, Xinpeng Chen, Fan Yang, Kunyang Liu, Hirofumi Shinohara

    2021 Symposium on VLSI Circuits    2021年06月

    DOI

  • 36.3 A Modeling Attack Resilient Strong PUF with Feedback-SPN Structure Having <0.73% Bit Error Rate through In-Cell Hot-Carrier Injection Burn-In

    Kunyang Liu, Zihan Fu, Gen Li, Hongliang Pu, Zhibo Guan, Xingyu Wang, Xinpeng Chen, Hirofumi Shinohara

    Digest of Technical Papers - IEEE International Solid-State Circuits Conference   64   502 - 504  2021年02月

     概要を見る

    Strong physically unclonable functions (Strong PUFs) are expected to meet the low-energy and low-latency authentication requirements of IoT applications, owing to their exponential number of challenge-response pairs (CRPs). However, Strong PUFs suffer from vulnerability to modeling attacks and a high bit-error rate (BER). The first Strong PUF, known as the arbiter PUF, has little tolerance against modeling attacks because of the linear summation of path-delay times in its response [1]. Several studies have been conducted to improve immunity by introducing non-linearity in the response-generation procedure [2] -[6]. Out of these, only look-up-table (LUT)-based solutions [2], [6] achieved a high machine-learning (ML) robustness against more than 0.1M training CRPs. However, the design in [2] requires 112K bits of entropy, and that in [6] uses many AES S-boxes, as well as entropy sources. The complex response procedures cause high native BER in Strong PUFs, although zero error is not essential because cryptography is not needed in the authentication procedure. CRP filtering [3], [5], [6], a popular countermeasure, not only reduces usable CRPs, but it also requires the server to perform additional tasks in both enrollment and authentication. Taking advantage of a LUT, one can apply SRAM-PUF stabilization techniques. Hot-carrier-injection (HCI) burn-in [7] does not reduce the number of usable bitcells. However, conventionally, it requires the inverse data to be written back before HCI burn-in. Although this could be done on-chip, it provides a potential attack point to an adversary.

    DOI

    Scopus

    3
    被引用数
    (Scopus)
  • An Inverter-Based True Random Number Generator with 4-bit Von-Neumann Post-Processing Circuit

    Xingyu Wang, Hongjie Liu, Ruilin Zhang, Kunyang Liu, Hirofumi Shinohara

    Midwest Symposium on Circuits and Systems   2020-August   285 - 288  2020年08月

     概要を見る

    This paper proposes a small-area low-power inverter-based true random number generator (I-TRNG) which harvests entropy from thermal noise. A single CMOS inverter is used for noise amplification. Clock-feedthrough (CLFT) compensation and body-bias technique provide robustness across a wide range of supply voltage 0.7~1.0 V and temperature -40~100 °C. An on-chip 4-bit Von-Neumann post-processing circuit is implemented for maximum entropy harvesting. I-TRNG is fabricated in 130-nm CMOS technology. It occupies 1495 µm2 (0.08846 MF2) and consumes 0.6585 pJ/bit with a throughput of 0.4456 Mbps (0.1308 Mbits/µW). The random bits generated by I- TRNG pass all FIPS 140-2 and NIST 800-22 tests.

    DOI

    Scopus

    2
    被引用数
    (Scopus)
  • A 373-F-2 0.21%-Native-BER EE SRAM Physically Unclonable Function With 2-D Power-Gated Bit Cells and V-SS Bias-Based Dark-Bit Detection

    Kunyang Liu, Yue Min, Xuan Yang, Hanfeng Sun, Hirofumi Shinohara

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   55 ( 6 ) 1719 - 1732  2020年06月

     概要を見る

    This article presents a highly stable SRAM-based physically unclonable function (PUF) using enhancement-enhancement (EE)-structure bit cells for native stability improvement. The PUF bit cells are power-gated 2-D and are normally in the OFF state, which largely reduces power and is beneficial to attack tolerance. In addition, a dark-bit detection technique based on a lightweight integrated V-SS-bias generator is implemented in order to screen out potentially unstable bit cells (dark bits) induced by supply voltage/temperature (VT) variations and other factors. Measured native bit error rate (BER) of prototype chips fabricated in 130-nm standard CMOS is 0.21% at 0.8 V and 23 degrees C, which is 14x better compared with the conventional SRAM-based PUF. After masking the detected dark bits, no bit error (3339 bits x 500 evaluations) appeared at the worst VT corner across 0.8 to 1.4 V and -40 degrees C to 120 degrees C. This technique also eliminated all unstable bits in the accelerated aging test. Both the data before and after dark-bit masking have passed all applicable NIST SP 800-22 randomness tests. The measured operational energy at 0.8 V is 128 fJ/bit and the standby power is 0.44 pW/bit, thanks to the 2-D power-gating scheme. The nMOS-only bit cell is highly compact, with a normalized bit cell area of 373 F-2.

    DOI

    Scopus

    26
    被引用数
    (Scopus)
  • A 0.5-V 2.07-fJ/b 497-F2 EE/CMOS Hybrid SRAM Physically Unclonable Function with < 1E-7 Bit Error Rate Achieved through Hot Carrier Injection Burn-in

    Kunyang Liu, Hongliang Pu, Hirofumi Shinohara

    Proceedings of the Custom Integrated Circuits Conference   2020-March  2020年03月

     概要を見る

    This paper presents a bit-error free SRAM-based physically unclonable function (PUF) in 130-nm standard CMOS. The PUF has a compact bitcell, with a bitcell area of 497 F2. It switches from EE SRAM to CMOS SRAM mode during evaluation, achieving high native stability, low-voltage evaluation, and low-power operation. Its stability is reinforced to 100% through hot carrier injection (HCI) burn-in on the alternate-direction nMOS load, which causes no visible oxide damage and does not require additional fabrication processes or extra transistors in the bitcell. Experimental results show that the prototype chips achieved actual zero bit error across 0.5-0.7 V and -40°C to 120 °C, as well as zero error (<1E-7 BER) at the worst VT corner after accelerated aging test equivalent to 21 years of operation. The PUF functions stably down to 0.5 V, with an energy of 2.07 fJ/b, which includes both the evaluation and read-out power. The secure, compact, low-power and 100% stable features of the PUF make it an excellent candidate for the resource-constrained Internet of Things security.

    DOI

    Scopus

    7
    被引用数
    (Scopus)
  • A 0.5-V Hybrid SRAM Physically Unclonable Function Using Hot Carrier Injection Burn-In for Stability Reinforcement

    Kunyang Liu, Xinpeng Chen, Hongliang Pu, Hirofumi Shinohara

    IEEE Journal of Solid-State Circuits   56 ( 7 ) 2193 - 2204  2020年

     概要を見る

    This article introduces an SRAM-based physically unclonable function (PUF) that employs hybrid-mode operations in the enhancement-enhancement (EE) SRAM mode and CMOS SRAM mode to achieve both high native stability and low power. A data latching scheme based on the hybrid structure enables operations under low supply voltage (VDD). Furthermore, the proposed hybrid SRAM PUF is compatible with hot carrier injection (HCI) burn-in stabilization, which can reinforce PUF stability to ~100&#x0025; without the requirements of bitcell redundancy, visible oxide damages, additional fabrication processes, helper data storage, or error-correcting code (ECC) circuits. The proposed PUF is fabricated in 130-nm standard CMOS, and the experimental results show that it achieves 0.29&#x0025; native bit error rate (BER) at the nominal condition of 0.6 V/25 &#x00B0;C. The operating VDD scales down to 0.5 V, with a core energy efficiency of 2.07 fJ/b. After HCI burn-in, no bit errors are found across all VDD/temperature (VT) corners from 0.5 to 0.7 V and from -40 &#x00B0;C to 120 &#x00B0;C (5120 bits x 500 evaluations tested at each condition). Long-term reliability is verified by using an accelerated aging test equivalent to approximately 21 years of operation, where the reinforced PUF shows no bit errors even at the worst VT corner of 0.5 V/120 &#x00B0;C during the test. The introduced hybrid SRAM PUF also passes all applicable NIST SP 800-22 randomness tests. It has a compact bitcell with an area of 497 F&#x00B2;.

    DOI

    Scopus

    12
    被引用数
    (Scopus)
  • A 0.5-V 2.07-0/b 497-F-2 EE/CMOS Hybrid SRAM Physically Unclonable Function with < 1E-7 Bit Error Rate Achieved through Hot Carrier Injection Burn-in

    Kunyang Liu, Hongliang Pu, Hirofumi Shinohara

    2020 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC)    2020年

     概要を見る

    This paper presents a bit-error free SRAM-based physically unclonable function (PUF) in 130-nm standard CMOS. The PUF has a compact bitcell, with a bitcell area of 497 F-2. It switches from EE SRAM to CMOS SRAM mode during evaluation, achieving high native stability, low-voltage evaluation, and low-power operation. Its stability is reinforced to 100% through hot carrier injection (HCI) burn-in on the alternate-direction nMOS load, which causes no visible oxide damage and does not require additional fabrication processes or extra transistors in the bitcell. Experimental results show that the prototype chips achieved actual zero bit error across 0.5-0.7 V and -40 degrees C to 120 degrees C, as well as zero error (<1E-7 BER) at the worst VT corner after accelerated aging test equivalent to 21 years of operation. The PUF functions stably down to 0.5 V, with an energy of 2.07 fJ/b, which includes both the evaluation and read-out power. The secure, compact, low-power and 100% stable features of the PUF make it an excellent candidate for the resource-constrained Internet of Things security.

  • A CMOS 0.85-V 15.8-nW current and voltage reference without resistors

    Jing Wang, Hirofumi Shinohara

    2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019    2019年04月

     概要を見る

    © 2019 IEEE. In this paper, a CMOS sub-1-V nanopower reference is proposed, which is realized without resistors and with only standard CMOS transistors. The proposed circuit affords reference current and reference voltage simultaneously. It is verified with CMOS 180 nm process with silicon measurement results. The temperature coefficients for output voltage Vref and output current Iref are 28 ppm/°C and 138 ppm/°C, respectively. The minimum supply voltage is 0.85 V and the minimum power consumption is achieved about 15.8 nW. Also, the line regulations of the Vref and Iref are 0.74%/V and 4.15%/V, respectively.

    DOI

    Scopus

    3
    被引用数
    (Scopus)
  • A 373 F 2 2D Power-Gated EE SRAM Physically Unclonable Function with Dark-Bit Detection Technique

    Kunyang Liu, Yue Min, Xuan Yang, Hanfeng Sun, Hirofumi Shinohara

    2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings     161 - 164  2018年12月

     概要を見る

    © 2018 IEEE. This paper presents an Enhancement-Enhancement (EE) SRAM physically unclonable function (PUF) with a dark-bit detection technique based on an integrated Vss-bias generator. The EE SRAM PUF cell improves native stability to 0.21% bit-error rate (BER). Bit cells that are potentially unstable due to environmental variations or aging are detected via the lightweight bias generator to ensure stability, and the effectiveness is verified with experimental results of dark-bit detection performed at room temperature. Measurement results of 10 chips in 130-nm CMOS show that after masking the detected dark bits, 1.3×10 -6 BER is achieved across 0.8-1.4 V/-40-120 °C VT corners. The nMOS-only bit cell is also highly compact (i.e., 373 F 2 ). Moreover, a 2D power-gating scheme is implemented for low operation energy, low standby power, and high attack tolerance.

    DOI

    Scopus

    11
    被引用数
    (Scopus)
  • High-throughput von Neumann post-processing for random number generator

    Ruilin Zhang, Sijia Chen, Chao Wan, Hirofumi Shinohara

    2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018     1 - 4  2018年06月

     概要を見る

    © 2018 IEEE. This paper presents the improvement and implementation of N bits Von Neumann (VN-N) post-processing technique, which is used to produce unbiased random bits sequence from biased one. Algorithm to realize general N bits VN-N and circuit level implementation of 4 bits VN-4 are shown. VN-4 achieved 40.6% output rate. A waiting strategy is further proposed to improve the output rate. VN-4+waiting and VN-8+waiting reached to 46.9% and 62.5% output rate, respectively. They are 1.88× and 2.50× improvements compared with original Von Neumann (VN-2) with 25.0%, respectively.

    DOI

    Scopus

    9
    被引用数
    (Scopus)
  • Measurement of Static Random Access Memory Power-Up State Using an Addressable Cell Array Test Structure

    Kiyoshi Takeuchi, Tomoko Mizutani, Hirofumi Shinohara, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto

    IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING   30 ( 3 ) 209 - 215  2017年08月

     概要を見る

    The data stored in a static random access memory (SRAM) immediately after power-up is of practical interest for some applications, such as SRAM physical unclonable functions. In this paper, measurements of SRAM cell power-up state (i.e., whether the cell is storing 0 or 1 after the power supply is turned on) using an addressable cell array test structure are reported. The test structure provides direct access to individual transistor characteristics of many SRAM cells, which would facilitate the characterization of SRAM power-up behavior. Methods and considerations necessary for reliable and stable power- up state characterization using the test structure will be discussed and demonstrated.

    DOI

    Scopus

    1
    被引用数
    (Scopus)
  • Accurate Nanopower Supply-Insensitive CMOS Unit V-th Extractor and alpha V-th Extractor with Continuous Variety

    Jing Wang, Li Ding, Qiang Li, Hirofumi Shinohara, Yasuaki Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E100A ( 5 ) 1145 - 1155  2017年05月  [査読有り]

     概要を見る

    In this paper, a nanopower supply-insensitive complementary metal-oxide-semiconductor (CMOS) unit threshold voltage (Vth) extractor circuit is proposed. It meets the contemporary industry demand for portable devices that operate with very low power consumption and small output sensitivity. An alpha times Vth (alpha Vth) extractor is also described, in which alpha varies continuously. Both incremental and decremental alpha Vth voltages are obtained. A post-layout simulation results using HSPICE with CMOS 0.18 um process show that the proposed unit Vth extractor consumes 265nW of power given a 1.6V power supply. Sensitivity to temperature is 0.022%/degrees C ranging from 0 degrees C to 100 degrees C. Sensitivity to supply voltage is 0.027%/V.

    DOI

    Scopus

  • Accurate nanopower supply-insensitive CMOS unit Vth extractor and α V<inf>th</inf> extractor with continuous variety

    Jing Wang, Li Ding, Qiang Li, Hirofumi Shinohara, Yasuaki Inoue

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E100A ( 5 ) 1145 - 1155  2017年05月

     概要を見る

    © 2017 The Institute of Electronics, Information and Communication Engineers. In this paper, a nanopower supply-insensitive complementary metal-oxide-semiconductor (CMOS) unit threshold voltage (Vth) extractor circuit is proposed. It meets the contemporary industry demand for portable devices that operate with very low power consumption and small output sensitivity. An α times Vth (α Vth) extractor is also described, in which α varies continuously. Both incremental and decremental α Vth voltages are obtained. A post-layout simulation results using HSPICE with CMOS 0.18 um process show that the proposed unit α Vth extractor consumes 265nW of power given a 1.6 V power supply. Sensitivity to temperature is 0.022%/°C ranging from 0°C to 100°C. Sensitivity to supply voltage is 0.027%/V.

    DOI

    Scopus

  • Correlation between static random access memory power-up state and transistor variation

    Takeuchi, Kiyoshi, Mizutani, Tomoko, Saraya, Takuya, Shinohara, Hirofumi, Kobayashi, Masaharu, Hiramoto, Toshiro

    JAPANESE JOURNAL OF APPLIED PHYSICS   56 ( 4 )  2017年04月

     概要を見る

    The correlation between the static random access memory (SRAM) power-up state (i.e., state 0 or 1 immediately after the power supply is turned on) and cell transistor variation is systematically studied by circuit simulations and mismatch space partitioning. It is revealed that, while both the mismatches of pFETs (pull-up) and nFETs (pull-down and access) contribute, their relative importance changes depending on the voltage ramping speed. The static retention noise margin well correlates with the power-up state only if the ramping speed is sufficiently low. Otherwise, pull-up transistor mismatch dominates the power-up state determination owing to the interference of capacitive current and asymmetrical capacitive coupling of the storage nodes to the ground and power supply. (c) 2017 The Japan Society of Applied Physics

    DOI

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    7
    被引用数
    (Scopus)
  • Parallel programmable nonvolatile memory using ordinary static random access memory cells

    Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Hirofumi Shinohara, Masaharu Kobayashi, Toshiro Hiramoto

    JAPANESE JOURNAL OF APPLIED PHYSICS   56 ( 4 )  2017年04月

     概要を見る

    A technique of using an ordinary static random access memory (SRAM) array for a programmable nonvolatile (NV) memory is proposed. The parallel NV writing of the entire array is achieved by simply applying high-voltage stress to the power supply terminal, after storing inverted desired data in the static random access memory (SRAM) array. Successful 2 kbit NV writing is demonstrated using a device-matrix-array (DMA) test element group (TEG) fabricated by 0.18 mu m technology. (C) 2017 The Japan Society of Applied Physics

    DOI

    Scopus

    2
    被引用数
    (Scopus)
  • Analysis and Reduction of SRAM PUF Bit Error Rate

    Hirofumi Shinohara, Baikun Zheng, Yanhao Piao, Bo Liu, Shiyu Liu

    2017 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)    2017年

     概要を見る

    Reducing BER (Bit Error Rate) is a crucial problem for a PUF (Physical Unclonable Function) in the security application. In this paper, BER is analyzed focusing on two major factors: mismatch factor and noise. By comparing five SRAM PUFs with different transistor sizes, weight factor of load pMOS and driver nMOS that determines the mismatch is extracted. And it is shown that BER can be reduced by unbalancing the pMOS/nMOS transistor size ratio.

    DOI

    Scopus

    9
    被引用数
    (Scopus)
  • Measurement of Mismatch Factor and Noise of SRAM PUF Using Small Bias Voltage

    Ziyang Cui, Baikun Zheng, Yanhao Piao, Shiyu Liu, Ronghao Xie, Hirofumi Shinohara

    2017 INTERNATIONAL CONFERENCE OF MICROELECTRONIC TEST STRUCTURES (ICMTS)    2017年

     概要を見る

    Mismatch factor of SRAM bit cell and noise factor that affects its power up state are measured using 256 bit SRAM PUF test structure with bias voltage inputs. Probability of power up state is used to extract a mismatch factor normalized by sigma n ( sigma noise voltage). By combining shifted bias voltages and repeat evaluation, whole 256 bit mismatch factors from real SRAM with small modification are obtained. According to the measurement data, it is confirmed that both noise factor and mismatch factor follow Gaussian distribution within a range of +/- 3.5 sigma and +/- 2.9 sigma respectively.

    DOI

    Scopus

    7
    被引用数
    (Scopus)
  • Parallel Programmable Non-volatile Memory Using Normal SRAM Cells

    Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Hirofumi Shinohara, Masaharu Kobayashi, Toshiro Hiramoto

    International Conference on Solid State Devices and Materials (SSDM), Tsukuba International Congress Center, Ibaraki     57 - 58  2016年09月  [査読有り]

  • A Study on the Correlation between SRAM Power-up State and Transistor Variation

    Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Hirofumi Shinohara, Masaharu Kobayashi, Toshiro Hiramoto

    International Conference on Solid State Devices and Materials (SSDM), Tsukuba International Congress Center, Ibaraki     55 - 56  2016年09月  [査読有り]

  • A 3.5 ppm /degrees C 0.85V Bandgap Reference Circuit without Resistors

    Jing Wang, Qiang Li, Li Ding, Hirofumi Shinohara, Yasuaki Inoue

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E99A ( 7 )  2016年07月  [査読有り]

     概要を見る

    A CMOS bandgap reference circuit without resistors, which can successfully operate under 1V supply voltage is proposed. The improvement is realized by the technique of the voltage divider and a new current source. The most attractive merit is that the proposed circuit breaks the bottleneck of low supply voltage design caused by the constant bandgap voltage value (1.25 V). Moreover, the temperature coefficient of the reference voltage V-ref is improved by compensating the temperature dependence caused by the current source. The simulation results using a standard CMOS 0.18 um process show that the value of V-ref can be achieved around 0.5 V with a minimum supply voltage of 0.85 V. Meanwhile, the temperature coefficient of the output voltage is only 3.5 ppm/degrees C from 0 degrees C to 70 degrees C.

    DOI

    Scopus

    2
    被引用数
    (Scopus)
  • A 3.5 ppm/°C 0.85V bandgap reference circuit without resistors

    Jing Wang, Qiang Li, Li Ding, Hirofumi Shinohara, Yasuaki Inoue

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E99A ( 7 ) 1430 - 1437  2016年07月

     概要を見る

    © 2016 The Institute of Electronics, Information and Communication Engineers. A CMOS bandgap reference circuit without resistors, which can successfully operate under 1V supply voltage is proposed. The improvement is realized by the technique of the voltage divider and a new current source. The most attractive merit is that the proposed circuit breaks the bottleneck of low supply voltage design caused by the constant bandgap voltage value (1.25 V). Moreover, the temperature coefficient of the reference voltage Vref is improved by compensating the temperature dependence caused by the current source. The simulation results using a standard CMOS 0.18 um process show that the value of Vref can be achieved around 0.5 V with a minimum supply voltage of 0.85 V. Meanwhile, the temperature coefficient of the output voltage is only 3.5 ppm/°C from 0 °C to 70 °C.

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  • Design of a low-order sensorless controller by robust H∞ control for boost converters

    Xutao Li, Minjie Chen, Hirofumi Shinohara, Tsutomu Yoshihara

    Journal of Power Electronics   16 ( 3 ) 1025 - 1035  2016年05月

     概要を見る

    © 2016 KIPE. Luenberger observer (LO)-based sensorless multi-loop control of a converter requires an iterative trial-and-error design process, considering that many parameters should be determined, and loop gains are indirectly related to the closed-loop characteristics. Robust H∞ control adopts a compact sensorless controller. The algebraic Riccati equation (ARE)-based and linear matrix inequality (LMI)-based H∞ approaches need an exhaustive procedure, particularly for a low-order controller. Therefore, in this study, a novel robust H∞ synthesis approach is proposed to design a low-order sensorless controller for boost converters, which need not solve any ARE or LMI, and to parameterize the controller by an adjustable parameter behaving like a “knob” on the closed-loop characteristics. Simulation results show the straightforward closed-loop characteristics evaluation and better dynamic performance by the proposed H∞ approach, compared with the LO-based sensorless multi-loop control. Practical experiments on a digital processor confirmed the simulation results.

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  • 39% access time improvement, 11% energy reduction, 32 kbit 1-read/1-write 2-port static random-access memory using two-stage read boost and write-boost after read sensing scheme

    Yasue Yamamoto, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara

    JAPANESE JOURNAL OF APPLIED PHYSICS   55 ( 4 )  2016年04月

     概要を見る

    We propose novel circuit techniques for 1 clock (1CLK) 1 read/1 write (1R/1W) 2-port static random-access memories (SRAMs) to improve read access time (tAC) and write margins at low voltages. Two-stage read boost (TSR-BST) and write word line boost (WWL-BST) after the read sensing schemes have been proposed. TSR-BST reduces the worst read bit line (RBL) delay by 61% and RBL amplitude by 10% at V-DD = 0.5 V, which improves tAC by 39% and reduces energy dissipation by 11% at V-DD = 0.55 V. WWL-BST after read sensing scheme improves minimum operating voltage (V-min) by 140 mV. A 32 kbit 1CLK 1R/1W 2-port SRAM with TSR-BST and WWL-BST has been developed using a 40 nm CMOS. (C) 2016 The Japan Society of Applied Physics

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  • Design of a sensorless controller synthesized by robust H∞ control for boost converters

    Xutao Li, Minjie Chen, Hirofumi Shinohara, Tsutomu Yoshihara

    IEICE Transactions on Communications   E99B ( 2 ) 356 - 363  2016年02月

     概要を見る

    Copyright © 2016 The Institute of Electronics, Information and Communication Engineers. Small loop gain and low crossover frequency result in poor dynamic performance of a single-loop output voltage controlled boost converter in continuous conduction mode. Multi-loop current control can improve the dynamic performance, however, the cost, size and weight of the circuit will also be increased. Sensorless multi-loop control solves the problems, however, the difficulty of the closed-loop characteristics evaluation will be severely aggravated, because there are more parameters in the loops, meanwhile, different from the single-loop, the relationships between the loop gains and closed-loop characteristics including audio susceptibility and output impedance are generally indirect for the multi-loop. Therefore, in this paper, a novel robust H ∞synthesis approach in the time-domain is proposed to design a sensorless controller for boost converters, which need not solve any algebraic Riccati equation or linear matrix inequalities, and most importantly, provides an approach to parameterizing the controller by an adjustable parameter. The adjustable parameter behaves like a &#039;knob&#039; on the dynamic performance, consequently, which makes the closed-loop characteristics evaluation straightforward. A boost converter is used to verify the proposed synthesis approach. Simulations show the great convenience of the closed-loop characteristics evaluation. Practical experiments confirm the simulations.

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  • Measurement of SRAM Power-Up State for PUF Applications using an Addressable SRAM Cell Array Test Structure

    Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto, Hirofumi Shinohara

    2016 INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES (ICMTS)   2016-May   130 - 134  2016年

     概要を見る

    SRAM data just after power-up were measured using an addressable SRAM cell array test structure. It was found that the results are strongly affected by the address switching noise and "memory effect". An addressing sequence combined with word line reset pulse application is proposed for reliable power-up data stability evaluation.

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  • Design of a Luenberger Observer Based Sensorless Multi-loop Control for Boost Converters

    Xutao Li, Minjie Chen, Shinohara Hirofumi, Yoshihara Tsutomu

    2016 INTERNATIONAL CONFERENCE ON ELECTRONICS, INFORMATION, AND COMMUNICATIONS (ICEIC)    2016年

     概要を見る

    The conventional multi-loop control of a boost converter needs a current sampling circuit to detect the inductor current. Sensorless multi-loop control reduces the cost, size and weight of the power conversion system. The Luenberger observer (LO) is widely used to estimate the inductor current for the sensorless control of a switching converter. However, the design of the LO based sensorless multi-loop control has not been well presented by far. In this paper, a closed-loop characteristics evaluation method is proposed to design a LO based sensorless multi-loop control for boost converters. Simulations show the closed-loop characteristics evaluations. Practical experiments on a digital processor confirm the simulations.

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  • An Output Capacitor-less Low Dropout Regulator with Quick-Responding Circuits

    Chunxu Zhang, Jie Mei, Hirofumi Shinohara, Tsutomu Yoshihara

    2015 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC)     51 - 52  2015年

     概要を見る

    An output capacitor-less low dropout regulator with three quick-responding (QR) loops is implemented in 0.18 mu m CMOS technology, featuring low sensitivity with changes in input voltage and load current. The proposed capacitor-less LDO has high stability for a current load from 0 to 100 mA and a capacitor load of 100 pF while the dropout voltage is 200 mV. A buffer is used to improve loop gain. The line regulation is 0.95 mV/V and the load regulation is 20 mu V/mA. The quick-responding loops can effectively reduce the overshoot and undershoot. When the load current switch between 0 and 100 mA with 1 mu s edge time, the maximum overshoot and undershoot are 36.13 mV and 36.81 mV under a 1.2 V supply voltage. And setting time is about 1.8 mu s.

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  • AC Direct Multiple-string LED Driver with Low THD and Minimum Components

    Yutsung Yeh, Minjie Chen, Xutao Li, Hirofumi Shinohara, Tsutomu Yoshihara

    2015 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC)     117 - 118  2015年

     概要を見る

    A multiple-string LED driver with low total harmonic distortion (THD) by sinusoid-like reference and minimum components is presented in this paper. The proposed commutating method is able to control the source-coupled-pair by simplest circuitry and without passive components. The reference voltage is divided from rectifier in order to minimize the THD. The simulated 4-strings LED driver is able to achieve high power factor 99.95% and very low THD 3.16% under a 10W/100V AC condition. And the proposed circuit is implemented by differential pair and diodes to replace op-amp and bias voltage.

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    5
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  • Comparison and distribution of minimum operation voltage in fully depleted silicon-on-thin-buried-oxide and bulk static random access memory cells

    Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Hirofumi Shinohara, Toshiaki Iwamatsu, Hidekazu Oda, Nobuyuki Sugii, Toshiro Hiramoto

    JAPANESE JOURNAL OF APPLIED PHYSICS   53 ( 4 )  2014年04月

     概要を見る

    The minimum operation voltage (V-min) of intrinsic channel fully depleted (FD) silicon-on-thin-buried-oxide (SOTB) static random access memory (SRAM) cells are measured and compared with those of conventional bulk SRAM cells in order to directly compare the worst cells. It is confirmed that the worst V-min of 1 kbit SOTB SRAM cells is half that of 1 kbit bulk cells. The distribution of V-min of 48 kbit SOTB and bulk SRAM cells are also measured and compared. The results show a great advantage of SOTB SRAM cells for lower power and lower voltage operation upon introducing SOTB, because of reduced V-TH variability. (C) 2014 The Japan Society of Applied Physics

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    10
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  • Extremely low power digital and analog circuits

    Hirofumi Shinohara

    IEICE Transactions on Electronics   E97-C ( 6 ) 469 - 475  2014年

     概要を見る

    Extremely low voltage operation near or below threshold voltage is a key circuit technology to improve the energy efficiency of information systems and to realize ultra-low power sensor nodes. However, it is difficult to operate conventional analog circuits based on amplifier at low voltage. Furthermore, PVT (Process, Voltage and Temperature) variation and random Vth variation degrade the minimum operation voltage and the energy efficiency in both digital and analog circuits. In this paper, extremely low power analog circuits based on comparator and switched capacitor as well as extremely low power digital circuits are presented. Many kinds of circuit technologies are applied to cope with the variation problem. Finally, image processing SoC that integrates digital and analog circuits is presented, where improvement of total performance by a cooperation of analog circuits and digital circuits is demonstrated. Copyright © 2014 The Institute of Electronics, Information and Communication Engineers.

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  • 0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS

    M. Nomura, A. Muramatsu, H. Takeno, S. Hattori, D. Ogawa, M. Nasu, K. Hirairi, S. Kumashiro, S. Moriwaki, Y. Yamamoto, S. Miyano, Y. Hiraku, I. Hayashi, K. Yoshioka, A. Shikata, H. Ishikuro, M. Ahn, Y. Okuma, X. Zhang, Y. Ryu, K. Ishida, M. Takamiya, T. Kuroda, H. Shinohara, T. Sakurai

    IEEE Symposium on VLSI Circuits, Digest of Technical Papers    2013年09月

     概要を見る

    A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%. © 2013 JSAP.

  • 0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS

    M. Nomura, A. Muramatsu, H. Takeno, S. Hattori, D. Ogawa, M. Nasu, K. Hirairi, S. Kumashiro, S. Moriwaki, Y. Yamamoto, S. Miyano, Y. Hiraku, I. Hayashi, K. Yoshioka, A. Shikata, H. Ishikuro, M. Ahn, Y. Okuma, X. Zhang, Y. Ryu, K. Ishida, M. Takamiya, T. Kuroda, H. Shinohara, T. Sakurai

    Digest of Technical Papers - Symposium on VLSI Technology    2013年09月

     概要を見る

    A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%. © 2013 JSAP.

  • Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits

    Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   48 ( 8 ) 1986 - 1994  2013年08月  [査読有り]

     概要を見る

    An abnormal increase in crosstalk noise in subthreshold logic circuits is observed for the first time. When the threshold voltages (V-TH) of nMOS and pMOS are imbalanced and the on-resistance of the aggressor driver is much lower than that of the victim driver, large crosstalk noise is observed, because the on-resistance has an exponential dependence on V-TH in the subthreshold region being different from normal voltage operations. A simple crosstalk noise model is also proposed and verified with SPICE simulations. In a crosstalk noise test chip with a 1.5-mm interconnect in 40-nm CMOS at a power supply voltage (V-DD) of 0.3 V, the measured noise amplitude increases from 32% of V-DD to 71% of V-DD, when V-TH imbalance is realized by tuning body bias in pMOS. This body bias tuning can be used to mitigate the crosstalk problem in chip designs. For noise induced by a rising edge, the noise becomes largest under the slow-nMOS/fast-pMOS corner condition, while for noise induced by a falling edge, the noise becomes largest under the fast-nMOS/slow-pMOS corner condition, which is explained by the proposed model.

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  • Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: V-DDmin-Aware Dual Supply Voltage Technique

    Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS   21 ( 6 ) 1175 - 1179  2013年06月

     概要を見る

    To achieve the most energy-efficient operation, this brief presents a circuit design technique for separating the power supply voltage (V-DD) of flip-flops (FFs) from that of combinational circuits, called the higher voltage FF (HVFF). Although V-DD scaling can reduce the energy, the minimum operating voltage (V-DDmin) of FFs prevents the operation at the optimum supply voltage that minimizes the energy, because the V-DDmin of FFs is higher than the optimum supply voltage. In HVFF, the V-DD of combinational logic gates is reduced below the V-DDmin of FFs while keeping the V-DD of FFs at their V-DDmin. This makes it possible to minimize the energy without power and delay penalties at the nominal supply voltage (1.2 V) as well as without FF topological difications. A 16-bit integer unit with HVFF is fabricated in a 65-nm CMOS process, and measurement results show that HVFF reduces the minimum energy by 13% compared with the conventional operation, which is 1/10 times smaller than the energy at the nominal supply voltage.

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    3
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  • Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges

    Shinji Miyano, Shinichi Moriwaki, Yasue Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Hirofumi Shinohara

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   48 ( 4 ) 924 - 931  2013年04月

     概要を見る

    Low voltage SRAM at a near-threshold voltage has two major sources of power waste: excess bit line swing due to the random variation of transistors and dynamic power consumption of the bit line swing of non-selected columns. In order to overcome these waste power consumption issues and achieve the highest energy-efficient operation of low voltage SRAM, the new CSHBL technique and CCC techniques, which is the improved version of the CSHBL, have been proposed. An SRAM fabricated using 65 nm technology adopting the CSHBL achieved an energy consumption of 26.4 pJ/Access/Mbit, and that of 13.8 pJ/Acess/Mbit is achieved by the SRAM macro that adopted CCC with 40 nm technology. This energy consumption is lower than values in previous works.

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  • Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation

    H. Makiyama, Y. Yamamoto, H. Shinohara, T. Iwamatsu, H. Oda, N. Sugii, K. Ishibashi, T. Mizutani, T. Hiramoto, Y. Yamaguchi

    Technical Digest - International Electron Devices Meeting, IEDM     33.2.4  2013年  [査読有り]

     概要を見る

    Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation voltage (Vdd). In the ultralow-Vdd regime, however, the upsurging delay (τpd) variability is the most important challenge. This paper proposes the balanced n/p drivability control method for reducing the die-to-die delay variation by back bias applicable for various circuits. Excellent variability reduction by this balanced control is demonstrated at Vdd = 0.4 V. © 2013 IEEE.

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  • Variation-aware subthreshold logic circuit design

    Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

    Proceedings of International Conference on ASIC    2013年

     概要を見る

    Subthreshold logic circuits are one of promising solutions to achieve ultra-low power operation. However, subthreshold circuits are significantly sensitive to manufacturing and environmental variability. In this paper, we will discuss design challenges in subthreshold logic circuits, such as rise in a minimum operating voltage, signal integrity degradation, and large delay variations. © 2013 IEEE.

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  • A 40-nm 8T SRAM with Selective Source Line Control of Read Bitlines and Address Preset Structure

    S. Yoshimoto, S. Miyano, M. Takamiya, H. Shinohara, H. Kawaguchi, M. Yoshimoto

    2013 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC)    2013年

     概要を見る

    This paper presents a 40-nm 8T SRAM in which bitlines are partially discharged by a selective source line control (SSLC) for low-power operation. The proposed SSLC scheme reduces a read bitline voltage swing in an unselected column with a floating source line (SL) of dedicated read ports. The SL is controlled by an additional NMOS switch that is turned on in a selected column, but the switch is kept off in the remaining unselected columns. The proposed scheme is effective for power reduction in successive address readouts through a single column. Furthermore, this paper introduces an address preset structure. The preset address enables the SRAM to be read out with no access time penalty for preferred use of the SSLC scheme. We fabricated a 16-Kb 8T SRAM test chip in a 40-nm CMOS process and observed that the proposed SSLC scheme with the address preset structure saves 38.1% of the readout power on average.

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    2
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  • Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature

    Ryo Takahashi, Hidehiro Takata, Tadashi Yasufuku, Hiroshi Fuketa, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS   59 ( 12 ) 918 - 921  2012年12月

     概要を見る

    Temperature dependence of 256 within-die random gate delay variations in sub-threshold logic circuits is measured in 40-nm CMOS test chips. When the temperature is reduced from 25 degrees C to -40 degrees C, the sigma/average (sigma/mu) of the gate delay at 0.3 V increases by 1.4 times. A newly developed model shows that sigma/mu of the gate delay is proportional to 1/T for the first time, where T is the absolute temperature.

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    9
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  • 13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with Parity-based Error Prediction and Detection (PEPD) and fully integrated digital LDO

    Koji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

    Digest of Technical Papers - IEEE International Solid-State Circuits Conference   55   486 - 487  2012年

     概要を見る

    Scaling power supply voltages (V DD's) of logic circuits down to the sub/near-threshold region is a promising approach to achieve significant power reductions. Circuit delays in the ultra-low voltage region, however, are extremely sensitive to process, voltage, and temperature (PVT) variations, and hence, large timing margins are required for worst-case design. Since such large timing margins reduce the energy efficiency benefits of lower V DD, adaptive V DD control to cope with PVT variations is indispensable for ultra-low voltage circuits. In this paper, an adaptive V DD control system with parity-based error prediction and detection (PEPD) and 0.5-V input fully-integrated digital LDO (DLDO) is proposed. © 2012 IEEE.

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  • 24% Power Reduction by Post-Fabrication Dual Supply Voltage Control of 64 Voltage Domains in V-DDmin Limited Ultra Low Voltage Logic Circuits

    Tadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai

    2012 13TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED)     586 - 591  2012年

     概要を見る

    A post-fabrication dual supply voltage (V-DD) control (PDVC) of multiple voltage domains is proposed for a minimum operating voltage (V-DDmin)-limited ultra low voltage logic circuits. PDVC effectively reduces an average V-DD below V-DDmin, thereby reducing the power consumption of logic circuits. PDVC is applied to a DES CODEC's circuit fabricated in 65nm CMOS. The layout of DES CODEC's is divided into 64 VDD domains and each domain size is 54 mu m x 63.2 mu m. High V-DD (V-DDH) or low V-DD (V-DDL) is applied to each domain and the selection of V-DD's is performed based on multiple built-in self tests. V-DDH is selected in V-DDmin-critical domains, while V-DDL is selected in V-DDmin-non-critical domains. A maximum 24% power reduction was measured with the proposed PDVC at 300kHz, V-DDH=437mV, and V-DDL=397mV.

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    9
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  • A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges

    S. Moriwaki, Y. Yamamoto, A. Kawasumi, T. Suzuki, S. Miyano, T. Sakurai, H. Shinohara

    IEEE Symposium on VLSI Circuits, Digest of Technical Papers     60 - 61  2012年

     概要を見る

    1Mb SRAM with charge collector circuits for effective use of non-selected bit line charges has been fabricated in 40nm technology. These circuits reduce two major wasted power sources of the low voltage SRAM: excess bit line swing due to random variation and bit line swing of non-selected columns. The lowest power consumption of 13.8pJ/Access/Mbit in the previous works has been achieved. © 2012 IEEE.

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    10
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  • Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage between NMOS and PMOS in Sub-Threshold Logic Circuits

    Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

    2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC)    2012年

     概要を見る

    Abnormal increase of the crosstalk noise in the subthreshold logic circuits is found for the first time. When the threshold voltages (V-TH) of nMOS and pMOS are imbalanced and the on-resistance of the aggressor driver is much lower than that of the victim driver, the large crosstalk noise is observed, because the on-resistance has an exponential dependence on V-TH in the sub-threshold circuits. In this paper, the large crosstalk noise due to the imbalanced V-TH is measured. A new crosstalk noise model is also proposed and verified with SPICE simulations. In a crosstalk noise test chip with 1.5-mm wire in a 40-nm CMOS at the power supply voltage (V-DD) of 0.3V, the measured noise amplitude increases from 32% of V-DD to 71% of V-DD, when the imbalanced V-TH is realized by tuning a body bias in pMOS. In the worst case fast-nMOS/slow-pMOS corner simulations, the noise amplitude increases from 47% of V-DD to 68% of V-DD, when V-DD is reduced from 1.1V to 0.3V, which is explained by the proposed model.

    DOI

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    1
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  • 60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations

    Yasue Yamamoto, Atsushi Kawasumi, Shinichi Moriwaki, Toshikazu Suzuki, Shinji Miyano, Hirofumi Shinohara

    European Solid-State Circuits Conference     317 - 320  2012年

     概要を見る

    An auto selective boost (ASB) scheme for slow SRAM memory cells in random variations has been proposed. ASB shortens the cycle time and decreases the average BL amplitude, which reduces both dynamic and leakage energy dissipation. The cycle time of SRAM is reduced by 60% at 0.5V using the proposed ASB scheme. By combining the ASB with a BL amplitude limiter (BAL), the energy dissipation is reduced by 55%. A 32Kbit SRAM with the ASB and BAL schemes has been fabricated by 40nm CMOS technology. © 2012 IEEE.

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    2
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  • Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage between NMOS and PMOS in Sub-Threshold Logic Circuits

    Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

    2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC)   48   1986 - 1994  2012年

     概要を見る

    Abnormal increase of the crosstalk noise in the subthreshold logic circuits is found for the first time. When the threshold voltages (V-TH) of nMOS and pMOS are imbalanced and the on-resistance of the aggressor driver is much lower than that of the victim driver, the large crosstalk noise is observed, because the on-resistance has an exponential dependence on V-TH in the sub-threshold circuits. In this paper, the large crosstalk noise due to the imbalanced V-TH is measured. A new crosstalk noise model is also proposed and verified with SPICE simulations. In a crosstalk noise test chip with 1.5-mm wire in a 40-nm CMOS at the power supply voltage (V-DD) of 0.3V, the measured noise amplitude increases from 32% of V-DD to 71% of V-DD, when the imbalanced V-TH is realized by tuning a body bias in pMOS. In the worst case fast-nMOS/slow-pMOS corner simulations, the noise amplitude increases from 47% of V-DD to 68% of V-DD, when V-DD is reduced from 1.1V to 0.3V, which is explained by the proposed model.

    DOI

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    6
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  • Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits

    Yu Pu, Xin Zhang, Katsuyuki Ikeuchi, Atsushi Muramatsu, Atsushi Kawasumi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS   58 ( 5 ) 294 - 298  2011年05月

     概要を見る

    Clock skew is a major cause of severe timing yield degradation for sub-/near-threshold digital circuits. We report for the first time on employing hot-carrier injection (HCI) for post-silicon clock-deskew trimming. An HCI trimmed clock buffer, which can be individually selected and stressed to adjust the clock edge, is proposed. In addition, it can be used in conjunction with on-chip skew monitoring circuits to achieve auto-stressing. Our approach is proven to be effective through a representative 1.1-mm x 0.8-mm clock tree in a 40-nm high-k complimentary metal-oxide-semiconductor process. On average, it reduces the clock skew by eight times at 0.4 V V(dd). No significant recovery is noticed two weeks after trimming.

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  • A Closed- form Expression for Estimating Minimum Operating Voltage (V-DDmin) of CMOS Logic Gates

    Hiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

    PROCEEDINGS OF THE 48TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC)     984 - 989  2011年

     概要を見る

    In this paper, a closed-form expression for estimating a minimum operating voltage (V-DDmin) of CMOS logic gates is proposed. V-DDmin is defined as the minimum supply voltage at which circuits can operate correctly. V-DDmin of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that V-DDmin of inverter chains can be estimated within 11% error. The expression is also verified with silicon measurements in a 65nm CMOS process.

  • 12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2V to 310mV enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics

    Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

    Proceedings of the International Symposium on Low Power Electronics and Design     163 - 168  2011年

     概要を見る

    Contention-less flip-flops (CLFF's) and separated power supply voltages (VDD) between flip-flops (FF's) and combinational logics are proposed to achieve a maximum energy efficiency operation. The proposed technologies were applied to a 16-bit integer unit (IU) for media processing in a 65-nm CMOS process. Measurement results of fabricated chips show that the proposed CLFF reduces the minimum operating voltage of IU's by 64mV on average. By scaling VDD from 1.2V to 310mV with the proposed CLFF, the maximum energy efficiency of 1835GOPS/W and the highest energy efficiency increase of 12.7 times are achieved. © 2011 IEEE.

    DOI

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    12
    被引用数
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  • Device-Circuit Interactions in Extremely Low Voltage CMOS Designs (Invited)

    Hiroshi Fuketa, Tadashi Yasufuku, Satoshi Iida, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

    2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)    2011年

     概要を見る

    In this paper, energy and minimum operating voltage (V-DDmin) are investigated for extremely-low-voltage CMOS logic designs. The dependences of energy and V-DDmin on device parameters, such as threshold voltage, subthreshold swing parameter, and DIBL coefficient, are examined based on simulations and measurements.

    DOI

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    11
    被引用数
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  • 12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains

    Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomura, Makoto Takamiya, Hirofumi Shinohara, Takayasu Sakurai

    European Solid-State Circuits Conference     191 - 194  2011年

     概要を見る

    Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations within a functional block are compensated by the fine-grained supply voltage (VDD) control to minimize power at fixed clock frequency. In the 40-nm test chips, the layout of a data encryption core is divided into 6x7 voltage domains. Both high VDD (VDDH) and low VDD (VDDL) are supplied to each power domain and either VDDH or VDDL is adaptively selected according to the setup error warning signals generated by canary flip-flops. Compared with the conventional single VDD operation, the proposed FADVC reduced the power by 12% at 1-MHz clock in the measurement. © 2011 IEEE.

    DOI

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    4
    被引用数
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  • Phase-Adjustable Error Detection Flip-Flops with 2-Stage Hold-Driven Optimization, Slack-Based Grouping Scheme and Slack Distribution Control for Dynamic Voltage Scaling

    Masanori Kurimoto, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara

    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS   15 ( 2 )  2010年02月

     概要を見る

    For Dynamic Voltage Scaling (DVS), we propose a novel design methodology. This methodology is composed of an error detection circuit and three technologies to reduce the area and power penalties which are the large issues for the conventional DVS with error detection. The proposed circuit, Phase-Adjustable Error Detection Flip-Flip (PEDFF), adjusts the clock phase of an additional FF for the timing error detection, based on the timing slack. 2-Stage Hold-Driven Optimization (2-SHDO) technology splits the hold-driven optimization in two stages. Slack-Based Grouping Scheme (SBGS) technology divides each timing path into appropriate groups based on the timing slack. Slack Distribution Control (SDC) technology improves the sharp distribution of the path delay at which the logic synthesis tool has relaxed the delay. We evaluate the methodology by simulating a 32-bit microprocessor in 90 nm CMOS technology. The proposed methodology reduces the energy consumption by 19.8% compared to non-DVS. The OR-tree&apos;s latency is shortened to 16.3% compared to the conventional DVS. The area and power penalties for delay buffers on short paths are reduced to 35.0% and 40.6% compared to the conventional DVS, respectively. The proposed methodology with SDC reduces the energy consumption by 17.0% on another example with the sharp slack distribution by the logic synthesis compared to non-DVS.

    DOI

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    5
    被引用数
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  • 0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme

    Toshikazu Suzuki, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara

    ESSCIRC 2010 - 36th European Solid State Circuits Conference     354 - 357  2010年

     概要を見る

    A low-voltage high-speed bulk-CMOS SRAM that operates over 100MHz at 0.5V, for the first time, is proposed. A novel 8-transistor (8T) memory cell with a complementary read port (C-RP) improves the read speed by enabling differential bit-line sensing, while the conventional 8T SRAM drives the bit line with a single read port (S-RP). The cell layout of the C-RP SRAM has point symmetry and a small area overhead (1.4x) compared with the conventional 6T SRAM cell, without any additional layers. The read delay and the delay variation at 0.5V were reduced by 52% and 54%, respectively, compared with the conventional S-RP 8T cell. A suspended bit-line read (SBLR) scheme is also applied to the read circuit in order to eliminate the leakage current from the unselected cells, which is an inevitable issue for a C-RP 8T cell with a conventional voltage sense amplifier (VSA). The simulated results of 1 Kbit SRAM in a 65-nm standard bulk-CMOS technology demonstrated 150-MHz operating frequency at 0.5-V single Vdd without any assist techniques. The power-delay product was reduced by 64% compared with the conventional S-RP 8T. This SRAM was implemented in test chips using 65-nm and 40-nm bulk-CMOS technologies. ©2010 IEEE.

    DOI

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    14
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  • Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access

    Koji Nii, Yasumasa Tsukamoto, Makoto Yabuuchi, Yasuhiro Masuda, Susumu Imaoka, Keiichi Usui, Shigeki Ohbayashi, Hiroshi Makino, Hirofumi Shinohara

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   44 ( 3 ) 977 - 986  2009年03月

     概要を見る

    We propose an access scheme for a synchronous dual-port (DP) SRAM that minimizes the 8T-DP-cell area and maintains cell stability. A priority row decoder circuit and shifted bit-line access scheme eliminates access conflict issues. Using 65 nm CMOS technology (hp90) with the proposed scheme, we fabricated 32 kB DP-SRAM macros. We obtained a 0.71 mu m(2) 8T-DP-cell for which the cell size is only 1.44 x larger than a 6T-single-port (SP)cell. The bit-density of the fabricated 32 kB DP-RAM macro is 667 kbit/mm(2), which is 25 % larger than a conventional 8T SRAM. The standby leakage is 27 % less because of the small drive-NMOS transistor of the proposed 8T-DP-cell.

    DOI

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    42
    被引用数
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  • A 45nm 0.6V Cross-Point 8T SRAM with Negative Biased Read/Write Assist

    M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Ohbayashi, Y. Nakase, H. Shinohara

    2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS     158 - 159  2009年

     概要を見る

    We propose a new design solution for embedded SRAM macros with cross point 8T-SRAM for low operating voltage and power. A negative bias technique for VSS and bitline (BL) enables us to achieve not only low power and high access speed, but also the large cell stability and write ability. Using 45-nm CMOS technology, we fabricated the SRAM macro based on our proposal and confirmed that the 1 Mbit-SRAM successfully operated at 0.6V. The active power is reduced by 66%, compared to the conventional 6T-SRAM.

  • Analysis Technique for Systematic Variation over Whole Shot and Wafer at 45 nm Process Node

    Jingo Nakanishi, Hiromi Notani, Yasunobu Nakase, Hirofumi Shinohara

    2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS     585 - 588  2009年

     概要を見る

    We propose a test structure for systematic variation measurement over the whole shot and wafer area at a 45 nm process node. With this structure, we found that the systematic variation had two kinds of site dependence, one is a wafer scale and the other is a shot scale component. Additionally, the Die-to-Die and Within-Die variations for any chip size are calculated. Then, the systematic variation component has the correlation length more than 16mm. This shows that it is necessary to take into consideration the Within-Die variation according to the Die size.

    DOI

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  • Analytical model of static noise margin in CMOS SRAM for variation consideration

    Hirofumi Shinohara, Koji Nii, Hidetoshi Onodera

    IEICE TRANSACTIONS ON ELECTRONICS   E91C ( 9 ) 1488 - 1500  2008年09月

     概要を見る

    An analytical model of the static noise margin (SNM) for a 6T CMOS SRAM suitable for use in investigating the effect of random V-th variation is derived. A three-step approach using characteristic points of the half cell inverter's transfer curve is developed. Parameters of each transistor are handled individually so that their sensitivities are calculable. A new MOSFET model in the moderate inversion is proposed to maintain accuracy, even in the low V-DD condition. Correlation between the proposed model calculations and circuit simulations was verified using a 90 nm CMOS LSTP device. Closely correlated dependency on parameters such as V-th, the W ratio, and V-DD were obtained. Maximum error measured in the VDD range of 0.6-1.6 V was 16 mV (7% of typical SNM). Finally, guidelines to obtain large SNM are discussed in this paper.

    DOI

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    1
    被引用数
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  • A large-scale, flip-flop RAM imitating a logic LSI for fast development of process technology

    Masako Fujii, Koji Nii, Hiroshi Makino, Shigeki Ohbayashi, Motoshige Igarashi, Takeshi Kawamura, Miho Yokota, Nobuhiro Tsuda, Tomoaki Yoshizawa, Toshikazu Tsutsui, Naohiko Takeshita, Naofumi Murata, Tomohiro Tanaka, Takanari Fujiwara, Kyoko Asahina, Masakazu Okada, Kazuo Tomita, Masahiko Takeuchi, Shigehisa Yamamoto, Hiromitsu Sugimoto, Hirofumi Shinohara

    IEICE TRANSACTIONS ON ELECTRONICS   E91C ( 8 ) 1338 - 1347  2008年08月

     概要を見る

    We propose a new large-scale logic test element group (TEG). called a flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and to imitate a logic LSI. We implemented a 10 Mgates FF-RAM using our 65-nm CMOS process. The FF-RAM enables us to make fail-bit maps (FBM) of logic cells because of its cell array structure as an SRAM. An FF-RAM has an additional structure to detect the open and short failure of upper metal layers. The test results show that it can detect failure locations and layers effortlessly using FBMs. We measured and analyzed it for both the cell arrays and the upper metal layers. Their results provided many important clues to improve our processes. We also measured the neutron-induced soft error rate (SER) of FF-RAM, which is becoming a serious problem as transistors become smaller. We compared the results of the neutron-induced soft error rate to those of previous generations: 180 nm, 130 nm. and 90 nm. Because of this TEG, we can considerably shorten the development period for advanced CMOS technology.

    DOI

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    2
    被引用数
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  • A 45 nm 2-port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues

    Satoshi Ishikura, Marefusa Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi, Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara, Hironori Akamatsu

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   43 ( 4 ) 938 - 945  2008年04月

     概要を見る

    We propose a new 2-port SRAM with a single read bit line (SRBL) eight transistors (8T) memory cell for a 45 nm system-on-a-chip (SoC). Access time tends to be slower as a fabrication is scaled down because of threshold voltage (V-t) random variations. A Divided read Bit line scheme with Shared local Amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous Read and-Write (R/W) access at the same row by using DBSA with the SRBL-8T cell. A rise of the storage node causes misreading. A Read End detecting Replica circuit (RER) and a Local read bit line Dummy Capacitance (LDC) are introduced to solve this issue. A 128 bit lines-512 word lines 64 kb 2-port SRAM macro using these schemes was fabricated by a 45 nm bulk CMOS low-standby-power (LSTP) CMOS process technology [1]. The memory cell size is 0.597 mu m(2). This 2-port SRAM macro achieves 7 times faster access time without misreading.

    DOI

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    30
    被引用数
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  • On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect

    M. Fujii, H. Suzuki, H. Notani, H. Makino, H. Shinohara

    ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference     258 - 261  2008年  [査読有り]

     概要を見る

    This paper proposes on-chip leakage monitor circuit to scan optimal reversed body-biasing voltage (VBB) at which leakage current becomes minimal under gate induced drain leakage (GIDL) effect. The proposed circuit determines optimal VBB from the differential measurement of two replica circuit without absolute leakage current measurement. We fabricated this leakage monitor circuit in a 45nm-CMOS process. Measurement results shows 0.1 V resolution of VBB optimization. © 2008 IEEE.

    DOI

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    3
    被引用数
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  • A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

    K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, Y. Oda, K. Usui, T. Kawamura, N. Tsuboi, T. Iwasaki, K. Hashimoto, H. Makino, H. Shinohara

    2008 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS     212 - +  2008年  [査読有り]

     概要を見る

    We propose an enhanced design solution for embedded SRAM macros under dynamic voltage and frequency scaling (DVFS) environment. The improved wordline Suppression technique using replica cell transistors and passive resistances compensates the read stability against process variation, facilitating the Fab. portability. The negative bitline technique expands the write margin for not only 6T single-port (SP) cell but also 8T dual-port (DP) cell even at the 0.7 V lower supply voltage. Using 45-nm CMOS technology, we fabricated both SP and DP SRAMs with the proposed circuitry. We achieve robust operations from 0.7 V to 1.3 V wide Supply voltage.

  • A 45-nm bulk CMOS embedded SRAM with improved immunity against process and temperature variations

    Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshmobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   43 ( 1 ) 180 - 191  2008年01月

     概要を見る

    The variation tolerant assist circuits of an SRAM against process and temperature are proposed. Passive resistances are introduced to the read assist circuit with replica memory transistors to lower the wordline voltage accurately reflecting the process and temperature variations. For the sake of not only enlarging the write margin but also reducing power consumption and speed overhead, the divided dynamic power-line scheme based on a charge sharing is adopted. Test chips of 512-Kb SRAM macros and isolated memory cell TEGs are fabricated using 45-nm bulk CMOS technology. Two types of 6-T SRAM cells, whose sizes were 0.245 mu m(2) and 0.327 mu m(2) were designed and evaluated. From the measurement results, we achieved over 100-mV improvement for static noise margin, and 35 mV for write margin for both SRAM cells at 1.0-V worst condition by using assist circuitry. It enables the wordline level to keep higher voltage at the slowest condition than the typical process condition, which results in 83% improvement of the cell current compared with the conventional assist circuit. Furthermore, the minimum operating voltage in the worst case condition Was improved by 170 mV, confirming a high immunity against process and temperature variations with less than 10% area overhead.

    DOI

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    51
    被引用数
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  • A 65 nm embedded SRAM with wafer level burn-in mode, leak-bit redundancy and Cu E-trim fuse for known good die

    Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   43 ( 1 ) 96 - 108  2008年01月

     概要を見る

    We propose a wafer level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair for an embedded 6T-SRAM to achieve a known good die (KGD) SoC. We fabricated a 16 Mb SRAM with these techniques using 65 nm LSTP technology, and confirmed the efficient operations of these techniques. The WLBI mode enables simultaneous write operation for 6T-SRAM, and has no area penalty and a speed penalty of only 50 ps. The leak-bit redundancy for 6T-SRAM can reduce the infant mortality of the bare die, and improves the standby current distribution. The area penalty is less than 2%. The Cu E-trim fuse can be used beyond the 45 nm advanced process technology. The fuse requires no additional wafer process steps. Using only 1.2 V core transistors will allow CMOS technology scaling to enable fuse circuit size reduction. The trimming transistor is placed under the fuse due to there being no cracking around the trimmed position. We achieve the small fuse circuit size of 6 x 36 mu m(2) using 65 nm technology.

    DOI

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    11
    被引用数
    (Scopus)
  • Phase-adjustable Error Detection Flip-Flops with 2-Stage Hold Driven Optimization and Slack Based Grouping Scheme for Dynamic Voltage Scaling

    Masanori Kurimoto, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara

    2008 45TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2     884 - +  2008年

     概要を見る

    Error Detection FFs for Dynamic Voltage Scaling (DVS) has been proposed. This technique controls the clock phase based on the timing slack, and reduces the energy consumption by 19.8% compared to non-DVS. The error signal latency is shortened to 6.3%, the area and power penalties for delay buffers on short paths become 35.0% and 40.6% lower compared to the conventional DVS.

    DOI

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    9
    被引用数
    (Scopus)
  • A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

    K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, Y. Oda, K. Usui, T. Kawamura, N. Tsuboi, T. Iwasaki, K. Hashimoto, H. Makino, H. Shinohara

    2008 IEEE SYMPOSIUM ON VLSI CIRCUITS     167 - +  2008年

     概要を見る

    We propose an enhanced design solution for embedded SRAM macros under dynamic voltage and frequency scaling (DVFS) environment. The improved wordline suppression technique using replica cell transistors and passive resistances compensates the read stability against process variation, facilitating the Fab. portability. The negative bitline technique expands the write margin for not only 6T single-port (SP) cell but also 8T dual-port (DP) cell even at the 0.7 V lower supply voltage. Using 45-nm CMOS technology, we fabricated both SP and DP SRAMs with the proposed circuitry. We achieve robust operations from 0.7 V to 1.3 V wide supply voltage.

    DOI

    Scopus

    95
    被引用数
    (Scopus)
  • On-chip Digital I-dn and I-dp Measurement by 65 nm CMOS Speed Monitor Circuit

    H. Notani, M. Fujii, H. Suzuki, H. Makino, H. Shinohara

    2008 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE     401 - +  2008年

     概要を見る

    An on-chip digital I-ds measurement method is proposed in this report. In the proposed method, I-ds is digitally derived from the two values measured by three ring oscillators with PN balanced, N-rich, and P-rich inverters. The first value is the frequency of the PN balanced inverter ring. The second value is the frequency difference between the N-rich and the P-rich inverter rings. The post-digital processing derives NMOS I-ds (I-dn) and PMOS I-ds (I-dp) separately. The monitor circuit was implemented by 65 nm CMOS technology. The mismatch error between the first I-ds calculated from measured frequencies, and the second I-ds directly measured for reference, was analyzed. The standard deviations of the mismatch error in I-dn and I-dp are 1.64% and 1.09%, respectively. The margin of 3 sigma is within 5% which is our target tolerance for a practical application.

    DOI

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    11
    被引用数
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  • Post-Silicon Programmed Body-Biasing Platform suppressing device variability in 45 nm CMOS technology

    Hiroaki Suzuki, Masanori Kurimoto, Tadao Yamanaka, Hidehiro Takata, Hiroshi Makino, Hirofumi Shinohara

    Proceedings of the International Symposium on Low Power Electronics and Design     15 - 20  2008年

     概要を見る

    The Post-Silicon Programmed Body-Biasing Platform is proposed to suppress device variability in the 45-nm CMOS technology era. The proposed platform measures device speed during post-fabrication testing. Then the fast die is marked so that the body-bias circuit turns on and reduces leakage current of the die that is selected and marked in a user application. Because the slow die around the speed specifications of a product is not body-biased, the product runs as fast as a normal non-body-biasing product. Although the leakage power of a fast die is reduced, the speed specification does not change. The proposed platform improves the worst corner specification comprising the two worst cases of speed and leakage power. The test chip, fabricated using 45-nm technology, improves the worst corner of stand-by leakage power vs. speed by 70%. Copyright 2008 ACM.

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  • A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits

    Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   42 ( 4 ) 820 - 829  2007年04月

     概要を見る

    In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-mu m(2) SRAM cell with a beta ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology.

    DOI

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    100
    被引用数
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  • A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die

    Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Qkada, Atsushi Ishii, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

    Digest of Technical Papers - IEEE International Solid-State Circuits Conference     485 - 617  2007年

     概要を見る

    A wafer-level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable electrically trimmable (e-trim) fuse repair scheme for an embedded 6T-SRAM is used to achieve a known-good-die SoC. A 16Mb SRAM is fabricated with these techniques using a 65nm low-standby-power technology, and its operation is verified. The WLBI mode has a speed penalty of 50ps. The leak-bit redundancy area penalty is less than 2%. © 2007 IEEE.

    DOI

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    4
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  • A Large Scale, flip-flop RAM imitating a logic LSI for fast development of process technology

    M. Fujii, K. Nii, H. Makino, S. Ohbayashi, M. Igarashi, T. Kawamura, M. Yokota, N. Tsuda, T. Yoshizawa, T. Tsutsui, N. Takeshita, N. Murata, T. Tanaka, T. Fujiwara, K. Asahina, M. Okada, K. Tomita, M. Takeuchi, H. Shinohara

    2007 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, PROCEEDINGS     131 - +  2007年

     概要を見る

    We propose a new, large-scale, logic TEG which is called flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and imitates a logic LSI. We implemented a 10-Mgate FF-RAM using our 65 nm CMOS process. The test results show that it is effortless to detect failure locations and layers by using fail bit maps. Owing to this TEG we can significantly shorten the development period for advanced CMOS technology.

    DOI

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    9
    被引用数
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  • A 45nm low-standby-power embedded SRAM with improved immunity against process and temperature variations

    Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara

    Digest of Technical Papers - IEEE International Solid-State Circuits Conference     321 - 606  2007年

     概要を見る

    A 512kb SRAM module is implemented in a 45nm low-standby-power CMOS with variation-tolerant assist circuits against process and temperature. A passive resistance is introduced to the read assist circuit and a divided VDD line is adopted in the memory array to assist the write. Two SRAM cells with areas of 0.245μm2 and 0.327μm2 are fabricated. Measurements show that the SNM exceeds 120mV and the write margin improves by 15% in the worst PVT condition. © 2007 IEEE.

    DOI

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    50
    被引用数
    (Scopus)
  • A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues

    S. Ishikura, M. Kurumada, T. Terano, Y. Yamagami, N. Kotani, K. Satomi, K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, T. Oashi, H. Makino, H. Shinohara, H. Akamatsu

    2007 Symposium on VLSI Circuits, Digest of Technical Papers     254 - 255  2007年

     概要を見る

    We propose a new 2port (2P) SRAM with an 8T single-bit-line (SBL) memory cell for 45nm SOCs. Access time tends to be slower as the device size is scaled down because of the random threshold-voltage variations. The Divided read Bit line scheme with Shared local Amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous Read and Write (R/W) access at the same row by using DBSA with the 8T-SBL memory cell. A rise of the storage node voltage causes the misreading. The Read End detecting Replica circuit (RER) and the Local read bit line with Dummy Capacitance (LDC) are introduced to solve this issue. A 128BLx512WL 64Kb 2P-SRAM macro which cell size is 0.597 mu m(2) using these schemes was fabricated by 45nm LSTP CMOS process [1].

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  • A 65 nm SoC embedded 6T-SRAM design for manufacturing with read and write cell stabilizing circuits

    S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, M. Igarashi, M. Takeuchi, H. Kawashima, H. Makino, Y. Yamaguchi, K. Tsukamoto, M. Inuishi, K. Ishibashi, H. Shinohara

    IEEE Symposium on VLSI Circuits, Digest of Technical Papers     17 - 18  2006年12月

     概要を見る

    We propose a new design scheme to improve the SRAM read and write operation margins in the presence of a large Vth variability. By applying this scheme to a 0.494 μm2 SRAM cell with a β ratio of 1, which is an aggressively small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth value using a 65 nm LSTP CMOS technology. © 2006 IEEE.

  • A 65 nm ultra-high-density dual-port SRAM with 0.71um2 8T-cell for SoC

    K. Nii, Y. Masuda, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, S. Imaoka, M. Igarashi, K. Tomita, N. Tsuboi, H. Makino, K. Ishibashi, H. Shinohara

    IEEE Symposium on VLSI Circuits, Digest of Technical Papers     130 - 131  2006年12月

     概要を見る

    We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stability. A priority row decoder circuit and shifted bit-line access scheme eliminates access conflict problem. Using 65nm CMOS technology (hp90), we fabricated 32KB DP-SRAM macros with the proposed scheme. We obtain 0.71um2 8T-DP-cell, which cell size is 1.44x larger than 6T-single-port (SP)-cell. © 2006 IEEE.

  • Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability

    Y Tsukamoto, K Nii, S Imaoka, Y Oda, S Ohbayashi, T Yoshizawa, H Makino, K Ishibashi, H Shinohara

    ICCAD-2005: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS     398 - 405  2005年  [査読有り]

     概要を見る

    6T-SRAM cells in the sub-100 nm CMOS generation are now being exposed to a fatal risk that originates from large local Vth variability (sigma v_(Local)) To achieve high-yield SRAM arrays in presence of random sigma v-(Local) component, we propose worst-case analysis that determines the boundary of the stable Vth region for the SRAM read/write DC margin (Vth curve). Applying this to our original 65 nm SPICE model, we demonstrate typical behavior of the Vth curve and show new criteria for discussing SRAM array stability with Vth variability.

  • A wide lock-in range PLL using self-calibrating technique for processors

    Jingo Nakanishi, Hiromi Notani, Hiroshi Makino, Hirofumi Shinohara

    2005 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS     285 - 288  2005年

     概要を見る

    A wide lock-in range PLL using a self-calibrating technique is proposed. This technique realizes a wide lock-in range and good jitter characteristics by performing the digital calibration at the start of the operation. However, self-calibration with a large number of digital control steps increases the test costs and circuit scale. In this paper, by estimating the margin for self-calibrating operation, the minimum number of digital control steps was determined. A PLL with a low test cost, a wide lock-in range and low jitter was designed and implemented using a 0.15 mu m 1.5 V CMOS process. The measured PLL lock-in range is 80 MHz - 630 MHz with four digital calibration steps. The peak-to-peak jitter at 380 MHz is 100 ps.

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  • Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability

    Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

    IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD   2005   398 - 405  2005年

     概要を見る

    6T-SRAM cells in the sub-100 nm CMOS generation are now being exposed to a fatal risk that originates from large local Vth variability (σ V_Local). To achieve high-yield SRAM arrays in presence of random σV_Local component, we propose worst-case analysis that determines the boundary of the stable Vth region for the SRAM read/write DC margin (Vth curve). Applying this to our original 65 nm SPICE model, we demonstrate typical behavior of the Vth curve and show new criteria for discussing SRAM array stability with Vth variability. © 2005 IEEE.

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  • A 64-bit carry look ahead adder using pass transistor BiCMOS gates

    K Ueda, H Suzuki, K Suda, H Shinohara, K Mashiko

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   31 ( 6 ) 810 - 818  1996年06月

     概要を見る

    This paper describes a 64-bit two-stage carry look ahead adder utilizing pass transistor BiCMOS gate. The new pass transistor BiCMOS gate has a smaller intrinsic delay time than conventional BiCMOS gates. Furthermore, this: gate has a rail-to-rail output voltage, Therefore the next gate does not have a large degradation of its driving capability, The exclusive OR and NOR gate using the pass transistor BiCMOS gate shows a speed advantage over CMOS gates under a wide variance in load capacitance, The pass transistor BiCMOS gates were applied to full adders, carry path circuits, and carry select circuits, In consequence, a 64-bit two-stage carry look ahead adder was fabricated using a 0.5 mu m BiCMOS process with single-polysilicon and double-metal interconnections. A critical path delay time of 3.5 ns was observed at a supply voltage of 3.3 V. This is 25% better than the result of the adder circuit using CMOS technology, Even at the supply voltage of 2.0 V, this adder is faster than the CMOS adder.

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    10
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  • An 8.8-ns 54 × 54-bit multiplier with high speed redundant binary architecture

    Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko

    IEEE Journal of Solid-State Circuits   31 ( 6 ) 773 - 783  1996年06月

     概要を見る

    A high speed redundant binary (RB) architecture, which is optimized for the fast CMOS parallel multiplier, is developed. This architecture enables one to convert a pair of partial products in normal binary (NB) form to one RB number with no additional circuit. We improved the RB adder (RBA) circuit so that it can make a fast addition of the RB partial products. We also simplified the converter circuit that converts the final RB number into the corresponding NB number. The carry propagation path of the converter circuit is carried out with only multiplexer circuits. A 54 × 54-bit multiplier is designed with this architecture. It is fabricated by 0.5 μm CMOS with triple level metal technology. The active area size is 3.05 × 3.08 mm2and the number of transistors is 78,800. This is the smallest number for all 54 × 54-bit multipliers ever reported. Under the condition of 3.3 V supply voltage, the chip achieves 8.8 ns multiplication time. The power dissipation of 540 mW is estimated for the operating frequency of 100 MHz. These are, so far, the fastest speed and the lowest power for 54 × 54-bit multipliers with 0.5-μm CMOS.

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    108
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  • A 1.2GFLOPS NEURAL-NETWORK CHIP EXHIBITING FAST CONVERGENCE

    Y KONDO, Y KOSHIBA, Y ARIMA, M MURASAKI, T YAMADA, H AMISHIRO, H SHINOHARA, H MORI

    1994 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - DIGEST OF TECHNICAL PAPERS   37   218 - 219  1994年

     概要を見る

    This paper describes a digital neural network chip for use as core in neural network accelerators employs a single-instruction multi-data-stream (SIMD architecture and includes twelve 24b floating-point processing units (PUs), a nonlinear function unit (NFU), and a control unit (CU). Each PU includes 24b×1.28kw local memory and communicates with its neighbor through a shift register ring. This configuration permits both feed-forward and error back propagation (BP) processes to be executed efficiently. The CU, which includes a three stage pipelined sequencer, a 24b×1kw instruction code memory (ICM) and a 144b×256w microcode memory (MCM), broadcasts network parameters (e.g., learning coefficients or temperature parameters) or addresses for local memories through a data and an address bus. Two external memory ports and a ring expansion-port permit large networks to be constructed. The external memory can be expanded by up to 768kW using the two ports.

  • A VOLTAGE COMPENSATED SERIES-GATE BIPOLAR CIRCUIT OPERATING AT SUB-2V

    H SATO, K UEDA, N SASAKI, K NIWANO, H SHINOHARA

    PROCEEDINGS OF THE 1993 BIPOLAR/BICOMS CIRCUITS AND TECHNOLOGY MEETING     232 - 235  1993年

     概要を見る

    A low-voltage series-gate (LSG) bipolar circuit is proposed. A lower-input transistor of the series-gate circuit also acts as a current source transistor. A switching current is compensated for a supply voltage. A 4-bit counter using this circuit operates at 500 MHz with the supply voltage of -1.6 V.

  • 8.8-ns 54×54-bit multiplier using new redundant binary architecture

    Hiroshi Makino, Yasunobu Nakase, Hirofumi Shinohara

    Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors     202 - 205  1993年

     概要を見る

    A new redundant binary (RB) architecture for the high speed multiplier is presented. In this architecture, a pair of partial products is converted to one RB number by inverting one of the pair without additional circuit and latency. Generated RB partial products are added by the Wallace tree of improved RB adders (RBAs) which have a latency of 0.9 ns, and converted to a normal binary (NB) number by a simply structured RB-to-NB converter in which the carry propagation circuit is constructed only with simple selector circuits. A 54×54-bit multiplier is designed using 0.5-μm CMOS technology. The multiplication time of 8.8 ns is obtained by SPICE2 simulation for the supply voltage of 3.3 V which is the fastest that has been reported for 54×54-bit multipliers.

  • A 20 TERA-CPS ANALOG NEURAL-NETWORK BOARD

    M MURASAKI, Y ARIMA, H SHINOHARA

    IJCNN '93-NAGOYA : PROCEEDINGS OF 1993 INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS, VOLS 1-3   3   3027 - 3030  1993年

     概要を見る

    We demonstrate an analog neural network board which integrates 18 interconnected neural network chips. The board realizes a fully feedback connection network consisting of 1,008 neurons and 1,016,064 synapses. The speed performance of the neural network is 20×1012 connections per second (CPS) and 500×109 connections update per second (CUPS).

  • A refreshable analog VLSI neural network chip with 400 neurons and 40k synapses

    Yutaka Arima, Mitsuhiro Murasaki, Tsuyoshi Yamada, Atushi Maeda, Hirofumi Shinohara

    Digest of Technical Papers - IEEE International Solid-State Circuits Conference   1992-February   132 - 133  1992年01月

     概要を見る

    © 1992 IEEE. Describes a self-learning neural network chip with refresh on-chip analog synaptic weight storage. The chip integrates 400 neurons and 40000 synapses with 0.8μm double poly-Si double metal CMOS technology. Refresh time is less than 300 mu s. The chip retains learned information by repeating refresh at 100 ms intervals. The proposed refresh method is based on the decision made by a subnetwork. The subnetwork learns if the settling states of the main network should be memorized, retains the weights until they are relearned, and stores a 4-b representation of subnetwork weights in a counter. The main network is refreshed according to the output of the subnetwork.

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  • A Refreshable Analog VLSI Neural Network Chip with 400 Neurons and 40K Synapses

    Yutaka Arima, Mitsuhiro Murasaki, Tsuyoshi Yamada, Atsushi Maeda, Hirofumi Shinohara

    IEEE Journal of Solid-State Circuits   27 ( 12 ) 1854 - 1861  1992年

     概要を見る

    This paper describes an on-chip learning neural network LSI circuit that can refresh the analog storage synaptic weights located on the chip. The chip integrates 400 neurons and 40 000 synapses with a 0.8-μm double-poly double-metal CMOS technology. This device stores learned information by repeating the refresh process at 200-ms intervals. © 1992 IEEE

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  • A high density data path generator with stretchable cells

    Y. Tsujihashi, H. Matsumoto, S. Kato, H. Nakao, O. Kitada, K. Okazaki, H. Shinohara

    Proceedings of the Custom Integrated Circuits Conference     11.3.4  1992年

     概要を見る

    This paper describes a newly developed module generator for data-path. Function blocks are designed in 0.8μm double metal CMOS technology. Adopting new cell structure for over the cell routing, called "stretchable cell with access free terminals (SCAT)", high density of more than 7K trs./mm 2 and high performance data-path has been obtained. © 1992 IEEE.

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    5
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  • A Flexible Multiport RAM Compiler for Data Path

    Hirofumi Shinohara, Kumiko Fujimori, Yoshiki Tsujihashi, Shuichi Kato, Yasutaka Horiba, Noriaki Matsumoto, Hiroomi Nakao, Akiharu Tada

    IEEE Journal of Solid-State Circuits   26 ( 3 ) 343 - 349  1991年

     概要を見る

    A multiport RAM compiler with flexible layout and port organization has been developed using 1.0-μm CMOS technology. A new memory cell with an additional column-enable gate yielded a controllability over the aspect ratio of the memory cell array. Wide bit-word organization range including 2048 words × 16 b and 512 words × 72 b was also obtained. This compiler generates up to 32K three-port RAM and 16K six-port RAM. In addition to read and write ports, read/write ports are also available. The operations of the ports are fully static and asynchronous to each other. The RAM requires no dc power consumption. The address access times of the generated three-port RAM's are, for example, 5.0 ns for 1K and 11.0 ns for 32K. © 1991 IEEE

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  • A 24-b 50-ns Digital Image Signal Processor

    Shin-Ichi Nakagawa, Tetsuya Matsumura, Hiroshi Segawa, Masahiko Yoshimoto, Hirofumi Shinohara, Shu-Ichi Kato, Masahiro Hatanaka, Yasutaka Horiba

    IEEE Journal of Solid-State Circuits   25 ( 6 ) 1484 - 1493  1990年

     概要を見る

    This paper will report a 50-ns digital image signal processor (DISP), excellently suited for picture coding. The chip integrates 538K transistors and dissipates 1.4 W at 40-MHz clock. It is based on a 24-b fixed-point architecture with a five-stage pipeline. The instruction cycle time is 35 ns typically and 50 ns at worst. The DISP features a real-time processing capability realized by an enhanced parallel architecture, video-oriented data processing functions, and a 50-ns instruction cycle time at worst. Its 50-ns cycle time allows it to execute more than 60-million operations per second (MOPS). High-density 1.0-μm CMOS technology allows numerous on-chip features, which include specified resources optimized for the image processing. This enables a flexible hardware implementation of various algorithms for the picture coding. Several circuit design techniques to attain the fast instruction cycle include a distributed instruction decoding and a hierarchical clocking circuit. The LSI has been designed by the extensive use of a cell-based design method. The processor incorporates a sophisticated testing function compatible with the cell-based design environment. This paper will also discuss system performance advantages in the image/ video processing including the picture coding. © 1990 IEEE

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    12
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  • A FLEXIBLE MULTIPORT RAM COMPILER FOR DATAPATH

    H SHINOHARA, N MATSUMOTO, K FUJIMORI, S KATO

    PROCEEDINGS OF THE IEEE 1990 CUSTOM INTEGRATED CIRCUITS CONFERENCE     400 - 403  1990年

     概要を見る

    A multiport RAM compiler with flexible layout and port-organization has been developed in an 1.0-μm CMOS technology. A novel memory cell scheme with an additional column enable gate yielded a controllability over the aspect ratio of the layout. This compiler generates up to 32K three-port RAM and 16K six-port RAM. Each port operates statically and asynchronously with each other port. The address access times of the generated three-port RAMs are 5.0 ns (1 kb) and 10.0 ns (32 kb), for example.

  • 50 ns video signal processor

    Shin ichi Nakagawa, Hideyuki Terane, Tetsuya Matsumura, Hiroshi Segawa, Masahiko Yoshimoto, Hirofumi Shinohara, Shu ichi Kato, Atsushi Maeda, Yasutaka Horiba, Hideo Ohira, Yoshi aki Katoh, Mamoru Iwatsuki, Kin ya Tabuchi

    Digest of Technical Papers - IEEE International Solid-State Circuits Conference   32  1989年12月

     概要を見る

    A 50-ns CMOS DSP (digital signal processor) with enhanced parallel architecture suited for video signal processing is reported. It has significant performance advantages, especially for video codecs in ISDN (integrated services digital network) video communication, is based on a 24-b fixed-point architecture, and operates in a five-stage pipeline (instruction-fetch, instruction-decode, source-data-transfer, execution, and destination-data-transfer). It contains 538k transistors and typically consumes 1.4 W at an instruction cycle rate of 50 ns. The DSP was fabricated in a 1.0-μm double-metal CMOS technology. Computation speed for the several coding procedures is approximately 3 to 10 times faster than that of traditional DSPs. A 64-kb/s video codec can be implemented with four or five DSPs for full common-source-interface-formats (CSIF) mode and one or two DSPs for 1/4 CSIF mode.

  • A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon

    Tomohisa Wada, Toshihiko Hirose, Hirofumi Shinohara, Yuji Kawai, Kojiro Yuzuriha, Yoshio Kohno, Shimpei Kayano

    IEEE Journal of Solid-State Circuits   22 ( 5 ) 727 - 732  1987年

     概要を見る

    This paper will describe a 128-kbit word × 8-bit CMOS SRAM with an access time of 34 ns and a standby current of 2 µA. This RAM has been fabricated using triple-polysilicon and single-aluminum CMOS technology with 0.8-µm minimum design features. A high-resistive third polysilicon load has been developed to realize a low standby current. In order to obtain a faster access time, a 16-block architecture and a data-output presetting technique combined with address transistion detection (ATD) are used. This RAM has a “flash-clear” function in which logical zero's are written into all memory cells in less than 1 μs. Copyright © 1987 by The Institute of Electrical and Electronics, Inc.

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  • Submicrometer-Gate MOSFET's by the Use of Focused-Ion-Beam Exposure and a Dry Development Technique

    Hiroaki Morimoto, Katsuhiro Tsukamoto, Hirofumi Shinohara, Masahide Inuishi, Tadao Kato

    IEEE Transactions on Electron Devices   34 ( 2 ) 230 - 234  1987年

     概要を見る

    Resist patterns as small as 0.1 μm, were fabricated by the irradiation of a gallium focused ion beam followed by an oxygen plasma development. The measured width of the patterns fabricated by this technique was in good agreement with the designed linewidth in the sub-half-micrometer region, n-channel Si MOSFET's with 0.3-0.8-(μm, gates were fabricated by the use of this technique. These results, accompanied by the fabricated and demonstrated performance of a ring oscillator, showed the feasibility of focused-ion-beam lithography. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.

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  • 25-ns 256K ×1/64K × 4 CMOS SRAM's

    Shinpei Kayano, Katsuki Ichinose, Yoshio Kohno, Hirofumi Shinohara, Kenji Anami, Shuji Murakami, Tomohisa Wada, Yuji Kawai, Yoichi Akasaka

    IEEE Journal of Solid-State Circuits   21 ( 5 ) 686 - 691  1986年

     概要を見る

    This paper describes 25-ns 256K CMOS static RAM&#039;s (SRAM‘s). Through a metal option, either 256K word × 1-bit or 64K word×4-bit organization is obtained. A fast access time has been achieved with a short bit-line structure and a data-bus precharging technique which minimize the bit-line and data-bus delay. A feedback-controlled address transition detector (ATD) circuit has been adopted to assure the fast access time in the presence of address skew. A 1.0-µm double-polysilicon and single-metal process technology with polycide gate offers a memory cell size of 90 µm2 and a chip size of 47.4 mm2. Copyright © 1986 by the Institute of Electrical and Electronics Engineers, Inc.

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  • SUBMICRON LITHOGRAPHY USING FOCUSED-ION-BEAM EXPOSURE FOLLOWED BY A DRY DEVELOPMENT.

    T. Kato, H. Morimoto, K. Tsukamoto, H. Shinohara, M. Inuishi

    Digest of Technical Papers - Symposium on VLSI Technology     72 - 73  1985年12月

     概要を見る

    Ultrafine lithography for dimensions less than 0. 5 mu m is one of the most promising applications of focused ion beams (FIB) because ion beams hardly suffer from a proximity effect. Submicron patterns are delineated in the resist by irradiation of gallium FIB followed by a dry development. The patterning characteristics and their application to N-MOS FETs with 0. 3-0. 8 mu m gates are discussed.

  • A 45-NS 256K CMOS STATIC RAM WITH A TRI-LEVEL WORD LINE

    H SHINOHARA, K ANAMI, K ICHINOSE, T WADA, Y KOHNO, Y KAWAI, Y AKASAKA, S KAYANO

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   20 ( 5 ) 929 - 934  1985年

     概要を見る

    This paper describes a 32K words by 8-bit static RAM fabricated with a CMOS technology. The key feature of the RAM is a tri-level word line, in which an automatic power down by a pulsed word line in the read cycle and a power saving by a middle-level word line in the WRITE cycle are combined. This circuit technique minimizes bit-line swing, shortens the precharging time, and depresses the transient current. An improved address transition detection circuit reduces the chip select access time. The sense amplifier uses internally synchronized signals for improved operation. The RAM has a typical access time of 45 ns with an active power dissipation of 7 mW. The peak transient current is less than 40 mA. A double-level polysilicon technology with a 13- μm design rule enabled layout of the NMOS memory cell in an area of 116.0 μm2 and the die in 49.6 mm2. © 1985 IEEE

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  • A FAST 8K X 8 MIXED CMOS STATIC RAM

    H SHINOHARA, K ANAMI, T YOSHIHARA, Y KIHARA, Y KOHNO, Y AKASAKA, S KAYANO

    IEEE TRANSACTIONS ON ELECTRON DEVICES   32 ( 9 ) 1792 - 1796  1985年

     概要を見る

    This paper describes a fast 8K x 8 static RAM fabricated with a mixed CMOS technology. To realize a fast access time and yet a low active power, a block-oriented die architecture with four submodules and a new sense amplifier are applied. An address access time of 34 ns and a chip select access time of 38 ns have been achieved at an active power of 90 mW. In addition to redundant memory cells, the RAM incorporates a spare element disable (SED) function to make it easy to obtain the information of the replaced memory cell. Another feature is a high latchup immunity of the CMOS peripheral circuits. This is obtained from an optimized well structure and guard baids around the wells. A 2-μm design rule combined with the double level polysilicon layer allowed for layout of the NMOS memory cell in 266.5 μm&lt;sup&gt;2&lt;/sup&gt;and design of the die in 34.3 mm&lt;sup&gt;2&lt;/sup&gt;. Copyright © 1985 by The Institute of Electrical and Electronics Engineers, Inc.

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    2
    被引用数
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  • A 45-NS 256K CMOS STATIC RAM WITH A TRI-LEVEL WORD LINE

    H SHINOHARA, K ANAMI, K ICHINOSE, T WADA, Y KOHNO, Y KAWAI, Y AKASAKA, S KAYANO

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   20 ( 5 ) 929 - 934  1985年

     概要を見る

    A 32K words by 8-bit static RAM fabricated with a CMOS technology. is described. The key feature of the RAM is a tri-level word-line, in which an automatic power down by a pulsed word-line in the READ cycle and a power saving by a middle-level word-line in the WRITE cycle are combined. This circuit technique minimizes bitline swing, shortens the precharging time, and depresses the transient current. An improved address transition detection circuit reduces the chip select access time. The sense amplifier uses internally synchronized signals for improved operation. The RAM has a typical access time of 45 ns with an active power dissipation of 7 mW. The peak transient current is less than 40 mA. A double-level polysilicon technology with a 1. 3- mu m design rule allowed layout of the NMOS memory cell in an area of 116. 0 mu m**2 and the die in 49. 6 mm**2.

  • A 4.5NS 256K CMOS SRAM WITH TRI-LEVEL WORD LINE

    H SHINOHARA, K ANAMI, K ICHINOSE, T WADA, Y KOHNO, Y KAWAI, Y AKASAKA, S KAYANO

    ISSCC DIGEST OF TECHNICAL PAPERS   28   62 - 63  1985年

     概要を見る

    Summary form only given. The 32K multiplied by 8-b static RAM includes an address-transition-activated circuit combined with a tri-level word line, which affords an active power of 7 mW at 1 MHz and a peak current of 40 mA. An address access time of 45 ns has been obtained. The RAM was fabricated with double-polysilicon single-aluminum CMOS technology. The gate lengths of the MOS transistors are scaled to 1. 3 mu (N channel) and 1. 8 mu (P channel) for fast access time. The use of 1. 3- mu m design rules permits layout of a NMOS memory cell with high resistance loads in area 8. 0 mu multiplied by 14. 5 mu area.

  • A 64KB FULL CMOS RAM WITH DIVIDED WORD LINE STRUCTURE

    M YOSHIMOTO, K ANAMI, H SHINOHARA, T YOSHIHARA, H TAKAGI, S NAGAO, S KAYANO, T NAKANO

    ISSCC DIGEST OF TECHNICAL PAPERS   26   58 - &  1983年  [査読有り]

  • Analysis of parasitic resistance effects in MOS LSI

    Kenji Anami, Masahiko Yoshimoto, Hirofumi Shinohara, Osamu Tomisawa, Takao Nakano

    Electronics and Communications in Japan (Part I: Communications)   66 ( 10 ) 106 - 113  1983年

     概要を見る

    This paper describes simplified analysis of the effects of transistor source and drain parasitic resistances and interconnect resistance in MOS LSI's, and their application to the circuit designs for MOS LSI circuits and mask patterns. Heretofore the analysis of parasitic resistance effects has been complex and could only be calculated numerically with circuit analysis programs. However, in this paper, a simple expression is given for the effect of the source and drain parasitic resistances by using a linear approximation to the MOS transistor drain i‐v characteristics. Furthermore, the delays caused by interconnection resistance are analyzed under assumptions that are actually obtained in practical LSI's. the rules for optimum design of the crossunders used frequently in LSI's are obtained using the result. Finally, experimental results from MOS transistors which agreed well with the source and drain parasitic resistance effect analysis. A ring oscillator experiment which also resulted in good agreement with the interconnect resistance delay analysis shows the applicability of both analysis methods. Copyright © 1983 Wiley Periodicals, Inc., A Wiley Company

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  • A DIVIDED WORD-LINE STRUCTURE IN THE STATIC RAM AND ITS APPLICATION TO A 64K FULL CMOS RAM

    M YOSHIMOTO, K ANAMI, H SHINOHARA, T YOSHIHARA, H TAKAGI, S NAGAO, S KAYANO, T NAKANO

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   18 ( 5 ) 479 - 485  1983年

     概要を見る

    This paper will describe a divided word-line (DWL) structure which solves inherent problems encountered in VLSI static RAM&#039;s. The key feature is to divide the word-line and to select it hierarchically with little area penalty using conventional process technology. In the application of the DWL structure, an 8K × 8 full CMOS RAM has been developed with 2 μ m double polysilicon technology. The RAM has a typical access time of 60 ns. An operating current of 20 mA was obtained with a simple static design. The six transistor cell configuration achieved a low standby current of less than 10 nA. For further improvement in the speed performance, second poly-Si layer was replaced with a polycide (poly-Si + MoSi2) layer, thus offering a 50 ns address access time. Copyright © 1983 by the Institute of Electrical and Electronics Engineers, Inc.

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    141
    被引用数
    (Scopus)
  • DESIGN CONSIDERATION OF A STATIC MEMORY CELL

    K ANAMI, M YOSHIMOTO, H SHINOHARA, Y HIRATA, T NAKANO

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   18 ( 4 ) 414 - 417  1983年

     概要を見る

    This paper describes design criteria for high-density low-power static RAM cells with a four-transistor two-resistor configuration. The states of the cell latch are expressed by a dc stability factor introduced from transfer curves of the inverters in the cell. The criteria feature using only static conditions for read/write/retain operations. The designed cell considering mask-misalignment measured 22.8 × 27.6 µm with 2.5 µm layout rules. From the evaluation of dynamic characteristics, it was shown that the 16K RAM using the cell had a sufficient operating margin. Copyright © 1983 by The Institute of Electrical and Electronics Engineers, Inc.

    DOI

    Scopus

    32
    被引用数
    (Scopus)
  • SOFT ERROR ANALYSIS OF FULLY STATIC MOS RAM.

    Masahiko Yoshimoto, Kenji Anami, Hirofumi Shinohara, Yoshihiro Hirata, Tsutomu Yoshihara, Takao Nakano

    Proceedings of the Conference on Solid State Devices   22   69 - 73  1983年01月

    CiNii

  • PARASITIC RESISTANCE EFFECTS ON STATIC MOS RAM.

    H. Shinohara, K. Anami, M. Yoshimoto, Y. Hirata, T. Nakano

    Digest of Technical Papers - Symposium on VLSI Technology     106 - 107  1982年12月

    CiNii

  • A 35NS 16K NMOS STATIC RAM

    K ANAMI, M YOSHIMOTO, H SHINOHARA, Y HIRATA, H HARADA, T NAKANO

    ISSCC DIGEST OF TECHNICAL PAPERS   25   250 - &  1982年  [査読有り]

  • A 35 NS 16K NMOS STATIC RAM

    K ANAMI, M YOSHIMOTO, H SHINOHARA, Y HIRATA, H HARADA, T NAKANO

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   17 ( 5 ) 815 - 820  1982年

     概要を見る

    An NMOS 16K × 1 bit fully static MOS RAM with 35 ns access time has been successfully developed. High speed access time was achieved by the combination of an NMOS process with the 2.2 μm gate length transistor, high speed sense amplifier, and reduction of delay time at the crossunder. The improvements of row and column decoder circuits result in the low active and standby power dissipation of 275 mW and 22.5 mW, respectively. The soft error rate of poly load cell was minimized by reducing the collection efficiency of alpha-particle induced electrons. Copyright © 1982 by the Institute of Electrical and Electronics Engineers, Inc.

    DOI

    Scopus

    1
    被引用数
    (Scopus)

▼全件表示

書籍等出版物

  • メモリデバイス イメージセンサ

    篠原 尋史( 担当: 共著,  担当範囲: 2.2 SRAM)

    丸善株式会社  2009年12月

Misc

  • 不揮発情報一括書き込み・読み出し可能な初期値確定SRAM (集積回路)

    水谷 朋子, 竹内 潔, 更屋 拓哉, 篠原 尋史, 小林 正治, 平本 俊郎

    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   117 ( 167 ) 49 - 54  2017年07月

    CiNii

  • 不揮発情報一括書き込み・読み出し可能な初期値確定SRAM (情報センシング)

    水谷 朋子, 竹内 潔, 更屋 拓哉, 篠原 尋史, 小林 正治, 平本 俊郎

    映像情報メディア学会技術報告 = ITE technical report   41 ( 25 ) 49 - 54  2017年07月

    CiNii

  • 0.5V動作低エネルギー回路と応用

    篠原 尋史

    電子情報通信学会技術研究報告. ICD, 集積回路   112 ( 170 ) 23 - 28  2012年07月

     概要を見る

    電源電圧を0.5Vあるいはそれ以下の極低電圧で動作させることが、根本的なLSI消費エネルギー低減策として期待が集まっているが、素子ばらつきへの対応など課題も多い。ロジック、メモリ、電源、無線の様々な要素回路とその統合において、0.5V級の低電圧動作で低消費エネルギーを実現する最近の研究事例を紹介する。

    CiNii

  • ビット線振幅量を抑えるチャージシェア階層ビット線方式を用いた0.4V動作SRAM

    森脇 真一, 川澄 篤, 鈴木 利一, 山本 安衛, 宮野 信治, 篠原 尋史, 桜井 貴康

    電子情報通信学会技術研究報告. ICD, 集積回路   112 ( 15 ) 67 - 71  2012年04月

     概要を見る

    本論文では、チャージシェア階層ビット線を用いた65nmプロセス128kb SRAMを開発した。ビット線をローカルビット線とグローバルビット線に分け、その間でチャージシェアを発生させることによって、低電圧動作時での、無駄な電力消費となるビット線振幅を抑制した。本提案技術を用いて0.4V動作3.3μW/MHzを達成した。

    CiNii

  • 低電圧動作可能なコンテンションレス・フリップフロップと2種の電源電圧による整数演算回路のエネルギー効率向上の実証(低電圧/低消費電力技術,新デバイス・回路とその応用)

    更田 裕司, 平入 孝二, 安福 正, 高宮 真, 野村 昌弘, 篠原 尋史, 桜井 貴康

    電子情報通信学会技術研究報告. ICD, 集積回路   111 ( 188 ) 127 - 132  2011年08月

     概要を見る

    本稿では,エネルギー効率向上を実現する為に,低電圧動作可能なコンテンションレス・フリップフロップと2種の電源電圧を用いた回路の提案を行う.メディア処理向け整数演算回路に提案技術を適用し,65nmプロセスで回路試作を行った.電源電圧を1.2Vから310mvまで低下させる事でエネルギー効率を12.7倍高めることができ,1835GOPS/Wの最大エネルギー効率を達成した.

    CiNii

  • プロセスばらつきや温度耐性を向上した45nm SoC向け混載SRAM

    薮内 誠, 新居 浩二, 塚本 康正, 大林 茂樹, 今岡 進, 山上 由展, 石倉 聡, 寺野 登志夫, 里見 勝治, 赤松 寛範, 篠原 尋史

    電子情報通信学会技術研究報告. SDM, シリコン材料・デバイス   108 ( 139 ) 17 - 21  2008年07月

     概要を見る

    微細化によるランダムばらつき増大によって、SRAMの動作マージンが減少している。これを改善するために、抵抗型リードアシスト回路と階層化ライトアシスト回路を開発した。45nmLSTPテクノロジでセルサイズ0.245μm^2と0.327μm^2の二種類についてこの技術を搭載したSRAM512Kbを試作し、SNMが120mV、Writeマージンが15%改善したことを確認した。

    CiNii

  • 招待講演 A 65nm embedded SRAM with wafer level burn-in mode, leak-bit redundancy and E-trim fuse for known good die (集積回路)

    Ohbayashi Shigeki, Yabuuchi Makoto, Kono Kazushi, ODA Yuji, IMAOKA Susumu, USUI Keiichi, YONEZU Toshiaki, IWAMOTO Takeshi, NII Koji, TSUKAMOTO Yasumasa, ARAKAWA Masashi, UCHIDA Takahiro, MAKINO Hiroshi, ISHIBASHI Koichiro, SHINOHARA Hirofumi

    電子情報通信学会技術研究報告. ICD, 集積回路   107 ( 1 ) 59 - 64  2007年04月

     概要を見る

    We propose a wafer level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair scheme for an embedded 6T-SRAM to achieve a KGD-SoC. We febricated a 16M-SRAM with these techniques using 65 nm LSTP technology, and confirmed its efficient operation. The WLBI mode has almost no area penalyy and a speed penalty of only 50 ps. The leak-bit redundancy area penalty is less than 2%.

    CiNii

  • 局所的な閾値電圧ばらつきに対するSRAM安定動作解析手法

    塚本 康正, 新居 浩二, 今岡 進, 小田 祐士, 大林 茂樹, 薮内 誠, 牧野 博之, 石橋 孝一郎, 篠原 尋史

    電子情報通信学会技術研究報告. ICD, 集積回路   106 ( 2 ) 95 - 100  2006年04月

     概要を見る

    サブ100nm世代のCMOSプロセスでは、ドーパント揺らぎ等に起因した局所的な閾値電圧のばらつき(σ_<V_Local>)を無視できない。特にSoCに搭載されるSRAMは微細なMOSFETを用いるためσ_<V_Local>は大きく、スケーリングに伴うσ_<V_Local>増加により性能劣化や歩留低下が懸念されている。したがって、局所ばらつきを考慮して歩留向上を目指すSRAMセル設計は必須である。本講演では、SRAMにおけるσ_<V_Local>を数学的にモデル化して、SRAMの読み出し、書き込み安定動作解析方法について論じる。

    CiNii

▼全件表示

共同研究・競争的資金等の研究課題

  • 初期状態設定によるセキュリティー用自然由来データの高品質化の研究

    研究期間:

    2017年04月
    -
    2020年03月
     

     概要を見る

    PUFでは目標以上の性能を、TRNGでは目標性能をそれぞれ達成した。PUFでは、新規な8TハイブリッドSRAM PUFを開発し、これにホットエレクトロン注入によるミスマッチ強化を行った。12分のホットエレクトロン注入の結果、電源電圧0.5V~0.7Vかつ周囲温度-40℃~120℃の広い動作範囲でエラーゼロを達成した。更に、21年相当の加速エージング試験でもエラーが観測されず、信頼性も確認された。次測定で1bitエラー発生したと仮定した悲観的ビットエラー率は1E-7。また消費エネルギーは2.08fF/bitで、世界最小クラスである。なお、エラーゼロなので、当初予定の軽量ECCは不要となった。TRNGでは、ラッチベースTRNGの16セルから0.8V~1.5Vの広い電源電圧範囲で0.30bit以上の平均エントロピーを得た。TRNG出力から高品質乱数を抽出する軽量混ぜ合わせ論理では、改良8bitフォンノイマン+Waitingアルゴリズム(VN_8W)の論理簡略化と低エネルギー設計を行った。出力効率は62.2%で、130nm CMOSでゲートカウント381GE、エネルギー3.12pJ/bitとなり、先行研究よりも出力効率が高くエネルギーも小さい結果が得られた、 ラッチベースTRNGの成果と組み合わせると、生TRNG出力6bitから生成される高品質乱数は1.12bitとなり、目標の1bitを達成した

講演・口頭発表等

  • [特別講演] A 373 F2 2D Power-Gated EE SRAM Physically Unclonable Function (PUF) with Dark-Bit Detection Technique

    Kunyang LIU, Yue MIN, Xuan YANG, Hanfeng SUN, Hirofumi SHINOHARA

    信学技報 ICD  

    発表年月: 2019年04月

  • Compensation of Temperature Induced Flipping-Bits in CMOS SRAM PUF by NMOS Body-Bias

    Xuanhao ZHANG, Xiang CHEN, Hanfeng SUN, Hirofumi SHINOHARA

    信学技報 HWS  

    発表年月: 2018年08月

  • [招待講演] 情報セキュリティのためのランダム回路

    篠原 尋史  [招待有り]

    信学技報 ICD  

    発表年月: 2018年04月

学内研究費(特定課題)

  • セキュリティ用ストロングPUFの攻撃耐性強化・無エラー化と真乱数発生器の攻撃耐性強化の研究

    2020年  

     概要を見る

     IoTセキュリティの信頼度向上のため、ハードウェア実装の重要構成要素である(a)PUF (Physical Unclonable Function)と(b)真乱数発生器 (True Random Number generator)の攻撃耐性強化に関する研究を行った。 (a) では、ストロングPUFと呼ばれる実質無尽蔵の入出力空間を持つクラスのPUFにおいて、SRAM PUFに対称鍵暗号に用いられるSPN (Substitution Permutation Network)構造を組み合わせたアーキテクチャを開発した。これにより、2千万CRP (Challenge Response Pair)学習でもモデリングに成功しない、これまで最高の攻撃耐性を得ることに成功した。 更にホットキャリア注入によるSRAM PUFの安定化を行い、ビットエラー率をストロングPUFとして実使用可能な0.73%未満にまで削減した。 以上の成果は、最重要国際会議であるIEEE ISSCC 2021で発表した。 (b) では、当研究室独自の低消費エネルギー真乱数発生器に電源ノイズ注入攻撃を試みた。電源電圧近い振幅の正弦波ノイズ注入でも、スループットは低下するものの、後処理後の乱数性はNIST SP800-22試験に合格し、攻撃耐性を実証した。 この成果は、主要国際会議で発表する予定である。

  • 素子ばらつきを用いたセキュリティーチップの低エネルギー化と動作安定化の研究

    2016年  

     概要を見る

    Secure LSI is akey technology to protect growing IoT from hacking. In this research, its primebuilding block PUF (Physical Unclonable Function) is focused. Test chip hasbeen designed and fabricated in 180nm CMOS using VDEC shuttle service. Testcircuits and measurement results are as follows. (1) nMOS and pMOStransistors array: It has 5 types of nMOS FETs and 3 types of pMOS transistors eachof them is repeated 16 times. Drain current of each transistor can be measured independently.&nbsp;Vth random variation of each type of MOS FETis evaluated by measuring 5 chips. And&nbsp;Perglom’sconstant Avt are derived for nMOS FET and for pMOS FET. (2) SRAM PUFs:Eight SRAM PUFs with different bit cell FET sizes are integrated on the chip. Bit error rate (BER) of the PUFs aremeasured by evaluating the output data 500 times each. Measured BERs arecompared and discussed, and effects of device mismatch and noise on BER hasbeen made clear. NBTI (Negative BiasTemperature Instability) electric stress is imposed to one of the&nbsp; PUF, and BER was reduced from 3.23% to 0%.&nbsp;

  • 素子ばらつきを用いたセキュリティーチップにおける組み込み自動テストの研究

    2016年  

     概要を見る

    Build-in self test(BIST) of PUF (Physical Unclonable Function) is researched. Generally outputdata is compared with the expected data in test. However, there is no expecteddata&nbsp;for PUF. Furthermore, don’t read the PUF output data to outside thechip is preferred for higher security. Thus BIST is very important for PUF.&nbsp;In PUF BIST, following three items must betested: a) Randomness (randomness of each output data), b) Reproducibility(output data is always same), c) Uniqueness (output data differs each other).In this year we focused to a) and b). a) Randomness test: Our SRAM PUFs aretested by NIST SP800-22 randomness test and autocorrelation Rxx(j)is also evaluated. The PUFs passed all 13 NIST test items except for 2 items wheredata length was not long enough. Distribution of Rxx(j) was also withinreasonable range.b) Reproducibility test: In order toaccelerate the degradation of reproducibility by temperature change or longtime use, our strategy is to add disturb during data evaluation. As a firststep, SRAM PUF with pair VSS terminals are designed. By adding small bias tothe terminals, it has been confirmed that this structure work well forthe acceleration.

  • IoTセキュリティーのための集積回路研究

    2015年  

     概要を見る

    Secure LSI is a key technology to protect growing IoT from hacking. In this research, its prime building blocks PUF (Physical Unclonable Function) and TRNG (True Random Number Generator) are focused. Device variation and noise plays important rolls in both circuits. To obtain fundamental data on them and to evaluate SRAM based PUF, a test chip has been designed in 180nm CMOS. The design data has been taped out to VDEC and is now under fabrication. The test chip consists of following circuits.(1) nMOS and pMOS transistors array: Statistic data of devise variations and noises are obtained from this test circuit.(2) SRAM based PUFs: Seven types of SRAM based PUFs are integrated on the chip. By comparing characteristics of them, effects of device variation and noise on operation stability will be made clear. This data can also be utilized to predict the randomness of TRNG.&nbsp; Furthermore, a new PUF circuit and a new TRNG circuit for stable operation and low power are thought-up, and their basic operations are verified by circuit simulations using SPICE.

 

現在担当している科目

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委員歴

  • 2016年10月
    -
    継続中

    IEEE VLSI-DAT  Technical Program Committee

  • 2017年03月
    -
    2021年02月

    IEEE ISSCC  International Technical Program Committee