SHINOHARA, Hirofumi

写真a

Affiliation

Faculty of Science and Engineering, Graduate School of Information, Production, and Systems

Job title

Professor

Concurrent Post 【 display / non-display

  • Faculty of Science and Engineering   School of Fundamental Science and Engineering

Research Institute 【 display / non-display

  • 2020
    -
    2022

    理工学術院総合研究所   兼任研究員

Education 【 display / non-display

  • 2005.04
    -
    2008.03

    Kyoto University   Graduate School of Informatics   Department of Communication and Computer Engineering  

  • 1976.04
    -
    1978.03

    Kyoto University   Graduate School of Engineering   Electronic Science and Engineering  

  • 1972.04
    -
    1976.03

    Kyoto University   Faculty of Engineering   Electronic Engineering  

Degree 【 display / non-display

  • 博士

Research Experience 【 display / non-display

  • 2015.03
    -
    Now

    Waseda University   Graduate School of information, Production and Systems (IPS)   Professor

  • 2014.08
    -
    2015.03

    Semiconductor Technology Academic Research Center (STARC)   Vice President

  • 2010.04
    -
    2014.07

    Renesas Electronics Co.

  • 2009.07
    -
    2014.07

    Semiconductor Technology Academic Research Center (STARC)   Vice President

  • 2003.04
    -
    2010.03

    Renesas Technology Co.

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Professional Memberships 【 display / non-display

  •  
     
     

    IEEE

  •  
     
     

    THE INSTITUTE OF ELECTRONICS

 

Research Areas 【 display / non-display

  • Electron device and electronic equipment   Solid-State Circuits

  • Theory of informatics

Research Interests 【 display / non-display

  • Hardware Security

  • Low Energy Circuits

  • SRAM

  • TRNG

  • PUF

Papers 【 display / non-display

  • A CMOS 0.85-V 15.8-nW current and voltage reference without resistors

    Jing Wang, Hirofumi Shinohara

    2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019    2019.04

     View Summary

    © 2019 IEEE. In this paper, a CMOS sub-1-V nanopower reference is proposed, which is realized without resistors and with only standard CMOS transistors. The proposed circuit affords reference current and reference voltage simultaneously. It is verified with CMOS 180 nm process with silicon measurement results. The temperature coefficients for output voltage Vref and output current Iref are 28 ppm/°C and 138 ppm/°C, respectively. The minimum supply voltage is 0.85 V and the minimum power consumption is achieved about 15.8 nW. Also, the line regulations of the Vref and Iref are 0.74%/V and 4.15%/V, respectively.

    DOI

  • A 373 F 2 2D Power-Gated EE SRAM Physically Unclonable Function with Dark-Bit Detection Technique

    Kunyang Liu, Yue Min, Xuan Yang, Hanfeng Sun, Hirofumi Shinohara

    2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings     161 - 164  2018.12

     View Summary

    © 2018 IEEE. This paper presents an Enhancement-Enhancement (EE) SRAM physically unclonable function (PUF) with a dark-bit detection technique based on an integrated Vss-bias generator. The EE SRAM PUF cell improves native stability to 0.21% bit-error rate (BER). Bit cells that are potentially unstable due to environmental variations or aging are detected via the lightweight bias generator to ensure stability, and the effectiveness is verified with experimental results of dark-bit detection performed at room temperature. Measurement results of 10 chips in 130-nm CMOS show that after masking the detected dark bits, 1.3×10 -6 BER is achieved across 0.8-1.4 V/-40-120 °C VT corners. The nMOS-only bit cell is also highly compact (i.e., 373 F 2 ). Moreover, a 2D power-gating scheme is implemented for low operation energy, low standby power, and high attack tolerance.

    DOI

  • High-throughput von Neumann post-processing for random number generator

    Ruilin Zhang, Sijia Chen, Chao Wan, Hirofumi Shinohara

    2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018     1 - 4  2018.06

     View Summary

    © 2018 IEEE. This paper presents the improvement and implementation of N bits Von Neumann (VN-N) post-processing technique, which is used to produce unbiased random bits sequence from biased one. Algorithm to realize general N bits VN-N and circuit level implementation of 4 bits VN-4 are shown. VN-4 achieved 40.6% output rate. A waiting strategy is further proposed to improve the output rate. VN-4+waiting and VN-8+waiting reached to 46.9% and 62.5% output rate, respectively. They are 1.88× and 2.50× improvements compared with original Von Neumann (VN-2) with 25.0%, respectively.

    DOI

  • Measurement of Static Random Access Memory Power-Up State Using an Addressable Cell Array Test Structure

    Kiyoshi Takeuchi, Tomoko Mizutani, Hirofumi Shinohara, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto

    IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING   30 ( 3 ) 209 - 215  2017.08

     View Summary

    The data stored in a static random access memory (SRAM) immediately after power-up is of practical interest for some applications, such as SRAM physical unclonable functions. In this paper, measurements of SRAM cell power-up state (i.e., whether the cell is storing 0 or 1 after the power supply is turned on) using an addressable cell array test structure are reported. The test structure provides direct access to individual transistor characteristics of many SRAM cells, which would facilitate the characterization of SRAM power-up behavior. Methods and considerations necessary for reliable and stable power- up state characterization using the test structure will be discussed and demonstrated.

    DOI

  • Measurement of mismatch factor and noise of SRAM PUF using small bias voltage

    Ziyang Cui, Baikun Zheng, Yanhao Piao, Shiyu Liu, Ronghao Xie, Hirofumi Shinohara

    IEEE International Conference on Microelectronic Test Structures    2017.06

     View Summary

    © 2017 IEEE. Mismatch factor of SRAM bit cell and noise factor that affects its power up state are measured using 256 bit SRAM PUF test structure with bias voltage inputs. Probability of power up state is used to extract a mismatch factor normalized by σn (sigma noise voltage). By combining shifted bias voltages and repeat evaluation, whole 256 bit mismatch factors from real SRAM with small modification are obtained. According to the measurement data, it is confirmed that both noise factor and mismatch factor follow Gaussian distribution within a range of ±3.5σ and ± 2.9σ, respectively.

    DOI

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Books and Other Publications 【 display / non-display

  • メモリデバイス イメージセンサ

    篠原 尋史( Part: Joint author)

    丸善株式会社  2009.12

Research Projects 【 display / non-display

  • Quality Improvement of Natural Data for Security by Controling Initial State

    Project Year :

    2017.04
    -
    2020.03
     

     View Summary

    PUFでは目標以上の性能を、TRNGでは目標性能をそれぞれ達成した。PUFでは、新規な8TハイブリッドSRAM PUFを開発し、これにホットエレクトロン注入によるミスマッチ強化を行った。12分のホットエレクトロン注入の結果、電源電圧0.5V~0.7Vかつ周囲温度-40℃~120℃の広い動作範囲でエラーゼロを達成した。更に、21年相当の加速エージング試験でもエラーが観測されず、信頼性も確認された。次測定で1bitエラー発生したと仮定した悲観的ビットエラー率は1E-7。また消費エネルギーは2.08fF/bitで、世界最小クラスである。なお、エラーゼロなので、当初予定の軽量ECCは不要となった。TRNGでは、ラッチベースTRNGの16セルから0.8V~1.5Vの広い電源電圧範囲で0.30bit以上の平均エントロピーを得た。TRNG出力から高品質乱数を抽出する軽量混ぜ合わせ論理では、改良8bitフォンノイマン+Waitingアルゴリズム(VN_8W)の論理簡略化と低エネルギー設計を行った。出力効率は62.2%で、130nm CMOSでゲートカウント381GE、エネルギー3.12pJ/bitとなり、先行研究よりも出力効率が高くエネルギーも小さい結果が得られた、 ラッチベースTRNGの成果と組み合わせると、生TRNG出力6bitから生成される高品質乱数は1.12bitとなり、目標の1bitを達成した

Presentations 【 display / non-display

  • A 373 F2 2D Power-Gated EE SRAM Physically Unclonable Function (PUF) with Dark-Bit Detection Technique

    Kunyang LIU, Yue MIN, Xuan YANG, Hanfeng SUN, Hirofumi SHINOHARA

    IEICE Technical Report ICD 

    Presentation date: 2019.04

  • Compensation of Temperature Induced Flipping-Bits in CMOS SRAM PUF by NMOS Body-Bias

    Xuanhao ZHANG, Xiang CHEN, Hanfeng SUN, Hirofumi SHINOHARA

    IEICE Technical Report-HWS 

    Presentation date: 2018.08

  • [Invited Paper] Randon Circuits for Information security

    SHINOHARA, Hirofumi  [Invited]

    IEICE Technical Report ICD 

    Presentation date: 2018.04

Specific Research 【 display / non-display

  • セキュリティ用ストロングPUFの攻撃耐性強化・無エラー化と真乱数発生器の攻撃耐性強化の研究

    2020  

     View Summary

     IoTセキュリティの信頼度向上のため、ハードウェア実装の重要構成要素である(a)PUF (Physical Unclonable Function)と(b)真乱数発生器 (True Random Number generator)の攻撃耐性強化に関する研究を行った。 (a) では、ストロングPUFと呼ばれる実質無尽蔵の入出力空間を持つクラスのPUFにおいて、SRAM PUFに対称鍵暗号に用いられるSPN (Substitution Permutation Network)構造を組み合わせたアーキテクチャを開発した。これにより、2千万CRP (Challenge Response Pair)学習でもモデリングに成功しない、これまで最高の攻撃耐性を得ることに成功した。 更にホットキャリア注入によるSRAM PUFの安定化を行い、ビットエラー率をストロングPUFとして実使用可能な0.73%未満にまで削減した。 以上の成果は、最重要国際会議であるIEEE ISSCC 2021で発表した。 (b) では、当研究室独自の低消費エネルギー真乱数発生器に電源ノイズ注入攻撃を試みた。電源電圧近い振幅の正弦波ノイズ注入でも、スループットは低下するものの、後処理後の乱数性はNIST SP800-22試験に合格し、攻撃耐性を実証した。 この成果は、主要国際会議で発表する予定である。

  • 素子ばらつきを用いたセキュリティーチップの低エネルギー化と動作安定化の研究

    2016  

     View Summary

    Secure LSI is akey technology to protect growing IoT from hacking. In this research, its primebuilding block PUF (Physical Unclonable Function) is focused. Test chip hasbeen designed and fabricated in 180nm CMOS using VDEC shuttle service. Testcircuits and measurement results are as follows. (1) nMOS and pMOStransistors array: It has 5 types of nMOS FETs and 3 types of pMOS transistors eachof them is repeated 16 times. Drain current of each transistor can be measured independently. Vth random variation of each type of MOS FETis evaluated by measuring 5 chips. And Perglom’sconstant Avt are derived for nMOS FET and for pMOS FET. (2) SRAM PUFs:Eight SRAM PUFs with different bit cell FET sizes are integrated on the chip. Bit error rate (BER) of the PUFs aremeasured by evaluating the output data 500 times each. Measured BERs arecompared and discussed, and effects of device mismatch and noise on BER hasbeen made clear. NBTI (Negative BiasTemperature Instability) electric stress is imposed to one of the  PUF, and BER was reduced from 3.23% to 0%. 

  • 素子ばらつきを用いたセキュリティーチップにおける組み込み自動テストの研究

    2016  

     View Summary

    Build-in self test(BIST) of PUF (Physical Unclonable Function) is researched. Generally outputdata is compared with the expected data in test. However, there is no expecteddata for PUF. Furthermore, don’t read the PUF output data to outside thechip is preferred for higher security. Thus BIST is very important for PUF. In PUF BIST, following three items must betested: a) Randomness (randomness of each output data), b) Reproducibility(output data is always same), c) Uniqueness (output data differs each other).In this year we focused to a) and b). a) Randomness test: Our SRAM PUFs aretested by NIST SP800-22 randomness test and autocorrelation Rxx(j)is also evaluated. The PUFs passed all 13 NIST test items except for 2 items wheredata length was not long enough. Distribution of Rxx(j) was also withinreasonable range.b) Reproducibility test: In order toaccelerate the degradation of reproducibility by temperature change or longtime use, our strategy is to add disturb during data evaluation. As a firststep, SRAM PUF with pair VSS terminals are designed. By adding small bias tothe terminals, it has been confirmed that this structure work well forthe acceleration.

  • IoTセキュリティーのための集積回路研究

    2015  

     View Summary

    Secure LSI is a key technology to protect growing IoT from hacking. In this research, its prime building blocks PUF (Physical Unclonable Function) and TRNG (True Random Number Generator) are focused. Device variation and noise plays important rolls in both circuits. To obtain fundamental data on them and to evaluate SRAM based PUF, a test chip has been designed in 180nm CMOS. The design data has been taped out to VDEC and is now under fabrication. The test chip consists of following circuits.(1) nMOS and pMOS transistors array: Statistic data of devise variations and noises are obtained from this test circuit.(2) SRAM based PUFs: Seven types of SRAM based PUFs are integrated on the chip. By comparing characteristics of them, effects of device variation and noise on operation stability will be made clear. This data can also be utilized to predict the randomness of TRNG.  Furthermore, a new PUF circuit and a new TRNG circuit for stable operation and low power are thought-up, and their basic operations are verified by circuit simulations using SPICE.

 

Syllabus 【 display / non-display

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Committee Memberships 【 display / non-display

  • 2017.03
    -
    Now

    IEEE ISSCC  国際論文委員

  • 2017.03
    -
    Now

    IEEE ISSCC  International Technical Program Committee

  • 2016.10
    -
    Now

    IEEE VLSI-DAT  Technical Program Committee

  • 2016.10
    -
    Now

    IEEE VLSI-DAT  論文委員