Concurrent Post

Faculty of Science and Engineering School of Fundamental Science and Engineering
Details of a Researcher
Updated on 2022/10/01
Faculty of Science and Engineering School of Fundamental Science and Engineering
理工学術院総合研究所 兼任研究員
Kyoto University Graduate School of Informatics Department of Communication and Computer Engineering
Kyoto University Graduate School of Engineering Electronic Science and Engineering
Kyoto University Faculty of Engineering Electronic Engineering
博士
Waseda University Graduate School of information, Production and Systems (IPS) Professor
Semiconductor Technology Academic Research Center (STARC) Vice President
Renesas Electronics Co.
Semiconductor Technology Academic Research Center (STARC) Vice President
Renesas Technology Co.
Mitsubishi Electric Co.
IEEE
THE INSTITUTE OF ELECTRONICS
Electron device and electronic equipment SolidState Circuits
Theory of informatics
Hardware Security
Low Energy Circuits
SRAM
TRNG
PUF
A 0.186pJ per Bit LatchBased True Random Number Generator Featuring Mismatch Compensation and Random Noise Enhancement
Ruilin Zhang, Xingyu Wang, Kunyang Liu, Hirofumi Shinohara
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 2022.03
A 0.116pJ/bit LatchBased True Random Number Generator with Static Inverter Selection and Noise Enhancement
Xingyu Wang, Ruilin Zhang, Yuxin Wang, Kunyang Liu, Xuanzhen Wang, Hirofumi Shinohara
2022 International Symposium on VLSI Design, Automation and Test, VLSIDAT 2022  Proceedings 2022
Kunyang Liu, Xinpeng Chen, Hongliang Pu, Hirofumi Shinohara
IEEE Journal of SolidState Circuits 56 ( 7 ) 2193  2204 2021.07 [Refereed]
Authorship：Last author
EnergyEfficient PostProcessing Technique Having High Extraction Efficiency for True Random Number Generators
Ruilin Zhang, Xingyu Wang, Hirofumi Shinohara
IEICE TRANSACTIONS ON ELECTRONICS E104C ( 7 ) 300  308 2021.07
Ruilin Zhang, Xingyu Wang, Luying Wang, Xinpeng Chen, Fan Yang, Kunyang Liu, Hirofumi Shinohara
2021 Symposium on VLSI Circuits 2021.06
36.3 A Modeling Attack Resilient Strong PUF with FeedbackSPN Structure Having <0.73% Bit Error Rate through InCell HotCarrier Injection BurnIn
Kunyang Liu, Zihan Fu, Gen Li, Hongliang Pu, Zhibo Guan, Xingyu Wang, Xinpeng Chen, Hirofumi Shinohara
Digest of Technical Papers  IEEE International SolidState Circuits Conference 64 502  504 2021.02
An InverterBased True Random Number Generator with 4bit VonNeumann PostProcessing Circuit
Xingyu Wang, Hongjie Liu, Ruilin Zhang, Kunyang Liu, Hirofumi Shinohara
Midwest Symposium on Circuits and Systems 2020August 285  288 2020.08
A 373F2 0.21%NativeBER EE SRAM Physically Unclonable Function With 2D PowerGated Bit Cells and VSS BiasBased DarkBit Detection
Kunyang Liu, Yue Min, Xuan Yang, Hanfeng Sun, Hirofumi Shinohara
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 55 ( 6 ) 1719  1732 2020.06
A 0.5V 2.07fJ/b 497F^{2} EE/CMOS Hybrid SRAM Physically Unclonable Function with < 1E7 Bit Error Rate Achieved through Hot Carrier Injection Burnin
Kunyang Liu, Hongliang Pu, Hirofumi Shinohara
Proceedings of the Custom Integrated Circuits Conference 2020March 2020.03
A 0.5V Hybrid SRAM Physically Unclonable Function Using Hot Carrier Injection BurnIn for Stability Reinforcement
Kunyang Liu, Xinpeng Chen, Hongliang Pu, Hirofumi Shinohara
IEEE Journal of SolidState Circuits 56 ( 7 ) 2193  2204 2020
A 0.5V 2.070/b 497F2 EE/CMOS Hybrid SRAM Physically Unclonable Function with < 1E7 Bit Error Rate Achieved through Hot Carrier Injection Burnin
Kunyang Liu, Hongliang Pu, Hirofumi Shinohara
2020 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) 2020
A CMOS 0.85V 15.8nW current and voltage reference without resistors
Jing Wang, Hirofumi Shinohara
2019 International Symposium on VLSI Design, Automation and Test, VLSIDAT 2019 2019.04
A 373 F ^{2} 2D PowerGated EE SRAM Physically Unclonable Function with DarkBit Detection Technique
Kunyang Liu, Yue Min, Xuan Yang, Hanfeng Sun, Hirofumi Shinohara
2018 IEEE Asian SolidState Circuits Conference, ASSCC 2018  Proceedings 161  164 2018.12
Highthroughput von Neumann postprocessing for random number generator
Ruilin Zhang, Sijia Chen, Chao Wan, Hirofumi Shinohara
2018 International Symposium on VLSI Design, Automation and Test, VLSIDAT 2018 1  4 2018.06
Kiyoshi Takeuchi, Tomoko Mizutani, Hirofumi Shinohara, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 30 ( 3 ) 209  215 2017.08
Accurate Nanopower SupplyInsensitive CMOS Unit Vth Extractor and alpha Vth Extractor with Continuous Variety
Jing Wang, Li Ding, Qiang Li, Hirofumi Shinohara, Yasuaki Inoue
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E100A ( 5 ) 1145  1155 2017.05 [Refereed]
Jing Wang, Li Ding, Qiang Li, Hirofumi Shinohara, Yasuaki Inoue
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E100A ( 5 ) 1145  1155 2017.05
Correlation between static random access memory powerup state and transistor variation
Takeuchi, Kiyoshi, Mizutani, Tomoko, Saraya, Takuya, Shinohara, Hirofumi, Kobayashi, Masaharu, Hiramoto, Toshiro
JAPANESE JOURNAL OF APPLIED PHYSICS 56 ( 4 ) 2017.04
Parallel programmable nonvolatile memory using ordinary static random access memory cells
Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Hirofumi Shinohara, Masaharu Kobayashi, Toshiro Hiramoto
JAPANESE JOURNAL OF APPLIED PHYSICS 56 ( 4 ) 2017.04
Analysis and Reduction of SRAM PUF Bit Error Rate
Hirofumi Shinohara, Baikun Zheng, Yanhao Piao, Bo Liu, Shiyu Liu
2017 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSIDAT) 2017
Measurement of Mismatch Factor and Noise of SRAM PUF Using Small Bias Voltage
Ziyang Cui, Baikun Zheng, Yanhao Piao, Shiyu Liu, Ronghao Xie, Hirofumi Shinohara
2017 INTERNATIONAL CONFERENCE OF MICROELECTRONIC TEST STRUCTURES (ICMTS) 2017
Parallel Programmable Nonvolatile Memory Using Normal SRAM Cells
Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Hirofumi Shinohara, Masaharu Kobayashi, Toshiro Hiramoto
International Conference on Solid State Devices and Materials (SSDM), Tsukuba International Congress Center, Ibaraki 57  58 2016.09 [Refereed]
A Study on the Correlation between SRAM Powerup State and Transistor Variation
Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Hirofumi Shinohara, Masaharu Kobayashi, Toshiro Hiramoto
International Conference on Solid State Devices and Materials (SSDM), Tsukuba International Congress Center, Ibaraki 55  56 2016.09 [Refereed]
A 3.5 ppm /degrees C 0.85V Bandgap Reference Circuit without Resistors
Jing Wang, Qiang Li, Li Ding, Hirofumi Shinohara, Yasuaki Inoue
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E99A ( 7 ) 2016.07 [Refereed]
A 3.5 ppm/°C 0.85V bandgap reference circuit without resistors
Jing Wang, Qiang Li, Li Ding, Hirofumi Shinohara, Yasuaki Inoue
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E99A ( 7 ) 1430  1437 2016.07
Design of a LowOrder Sensorless Controller by Robust H infinity Control for Boost Converters
Xutao Li, Minjie Chen, Hirofumi Shinohara, Tsutomu Yoshihara
JOURNAL OF POWER ELECTRONICS 16 ( 3 ) 1025  1035 2016.05
Yasue Yamamoto, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara
JAPANESE JOURNAL OF APPLIED PHYSICS 55 ( 4 ) 2016.04
Design of a Sensorless Controller Synthesized by Robust H infinity Control for Boost Converters
Xutao Li, Minjie Chen, Hirofumi Shinohara, Tsutomu Yoshihara
IEICE TRANSACTIONS ON COMMUNICATIONS E99B ( 2 ) 356  363 2016.02
Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto, Hirofumi Shinohara
2016 INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES (ICMTS) 2016May 130  134 2016
Design of a Luenberger Observer Based Sensorless Multiloop Control for Boost Converters
Xutao Li, Minjie Chen, Shinohara Hirofumi, Yoshihara Tsutomu
2016 INTERNATIONAL CONFERENCE ON ELECTRONICS, INFORMATION, AND COMMUNICATIONS (ICEIC) 2016
An Output Capacitorless Low Dropout Regulator with QuickResponding Circuits
Chunxu Zhang, Jie Mei, Hirofumi Shinohara, Tsutomu Yoshihara
2015 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) 51  52 2015
AC Direct Multiplestring LED Driver with Low THD and Minimum Components
Yutsung Yeh, Minjie Chen, Xutao Li, Hirofumi Shinohara, Tsutomu Yoshihara
2015 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) 117  118 2015
Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Hirofumi Shinohara, Toshiaki Iwamatsu, Hidekazu Oda, Nobuyuki Sugii, Toshiro Hiramoto
JAPANESE JOURNAL OF APPLIED PHYSICS 53 ( 4 ) 2014.04
Extremely low power digital and analog circuits
Hirofumi Shinohara
IEICE Transactions on Electronics E97C ( 6 ) 469  475 2014
M. Nomura, A. Muramatsu, H. Takeno, S. Hattori, D. Ogawa, M. Nasu, K. Hirairi, S. Kumashiro, S. Moriwaki, Y. Yamamoto, S. Miyano, Y. Hiraku, I. Hayashi, K. Yoshioka, A. Shikata, H. Ishikuro, M. Ahn, Y. Okuma, X. Zhang, Y. Ryu, K. Ishida, M. Takamiya, T. Kuroda, H. Shinohara, T. Sakurai
IEEE Symposium on VLSI Circuits, Digest of Technical Papers 2013.09
M. Nomura, A. Muramatsu, H. Takeno, S. Hattori, D. Ogawa, M. Nasu, K. Hirairi, S. Kumashiro, S. Moriwaki, Y. Yamamoto, S. Miyano, Y. Hiraku, I. Hayashi, K. Yoshioka, A. Shikata, H. Ishikuro, M. Ahn, Y. Okuma, X. Zhang, Y. Ryu, K. Ishida, M. Takamiya, T. Kuroda, H. Shinohara, T. Sakurai
Digest of Technical Papers  Symposium on VLSI Technology 2013.09
Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits
Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 48 ( 8 ) 1986  1994 2013.08 [Refereed]
Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 21 ( 6 ) 1175  1179 2013.06
Shinji Miyano, Shinichi Moriwaki, Yasue Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Hirofumi Shinohara
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 48 ( 4 ) 924  931 2013.04
Suppression of dietodie delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with backbias for ultralowvoltage (0.4 V) operation
H. Makiyama, Y. Yamamoto, H. Shinohara, T. Iwamatsu, H. Oda, N. Sugii, K. Ishibashi, T. Mizutani, T. Hiramoto, Y. Yamaguchi
Technical Digest  International Electron Devices Meeting, IEDM 33.2.4 2013 [Refereed]
Variationaware subthreshold logic circuit design
Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
Proceedings of International Conference on ASIC 2013
A 40nm 8T SRAM with Selective Source Line Control of Read Bitlines and Address Preset Structure
S. Yoshimoto, S. Miyano, M. Takamiya, H. Shinohara, H. Kawaguchi, M. Yoshimoto
2013 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) 2013
Large WithinDie Gate Delay Variations in SubThreshold Logic Circuits at Low Temperature
Ryo Takahashi, Hidehiro Takata, Tadashi Yasufuku, Hiroshi Fuketa, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS IIEXPRESS BRIEFS 59 ( 12 ) 918  921 2012.12
Koji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
Digest of Technical Papers  IEEE International SolidState Circuits Conference 55 486  487 2012
Tadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai
2012 13TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED) 586  591 2012
S. Moriwaki, Y. Yamamoto, A. Kawasumi, T. Suzuki, S. Miyano, T. Sakurai, H. Shinohara
IEEE Symposium on VLSI Circuits, Digest of Technical Papers 60  61 2012
Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) 2012
Yasue Yamamoto, Atsushi Kawasumi, Shinichi Moriwaki, Toshikazu Suzuki, Shinji Miyano, Hirofumi Shinohara
European SolidState Circuits Conference 317  320 2012
Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) 48 1986  1994 2012
Yu Pu, Xin Zhang, Katsuyuki Ikeuchi, Atsushi Muramatsu, Atsushi Kawasumi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS IIEXPRESS BRIEFS 58 ( 5 ) 294  298 2011.05
A Closed form Expression for Estimating Minimum Operating Voltage (VDDmin) of CMOS Logic Gates
Hiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
PROCEEDINGS OF THE 48TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC) 984  989 2011
Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
Proceedings of the International Symposium on Low Power Electronics and Design 163  168 2011
DeviceCircuit Interactions in Extremely Low Voltage CMOS Designs (Invited)
Hiroshi Fuketa, Tadashi Yasufuku, Satoshi Iida, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) 2011
Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomura, Makoto Takamiya, Hirofumi Shinohara, Takayasu Sakurai
European SolidState Circuits Conference 191  194 2011
Masanori Kurimoto, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 15 ( 2 ) 2010.02
0.5V, 150MHz, bulkCMOS SRAM with suspended bitline read scheme
Toshikazu Suzuki, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara
ESSCIRC 2010  36th European Solid State Circuits Conference 354  357 2010
Koji Nii, Yasumasa Tsukamoto, Makoto Yabuuchi, Yasuhiro Masuda, Susumu Imaoka, Keiichi Usui, Shigeki Ohbayashi, Hiroshi Makino, Hirofumi Shinohara
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 44 ( 3 ) 977  986 2009.03
A 45nm 0.6V CrossPoint 8T SRAM with Negative Biased Read/Write Assist
M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Ohbayashi, Y. Nakase, H. Shinohara
2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS 158  159 2009
Analysis Technique for Systematic Variation over Whole Shot and Wafer at 45 nm Process Node
Jingo Nakanishi, Hiromi Notani, Yasunobu Nakase, Hirofumi Shinohara
2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS 585  588 2009
Analytical model of static noise margin in CMOS SRAM for variation consideration
Hirofumi Shinohara, Koji Nii, Hidetoshi Onodera
IEICE TRANSACTIONS ON ELECTRONICS E91C ( 9 ) 1488  1500 2008.09
A largescale, flipflop RAM imitating a logic LSI for fast development of process technology
Masako Fujii, Koji Nii, Hiroshi Makino, Shigeki Ohbayashi, Motoshige Igarashi, Takeshi Kawamura, Miho Yokota, Nobuhiro Tsuda, Tomoaki Yoshizawa, Toshikazu Tsutsui, Naohiko Takeshita, Naofumi Murata, Tomohiro Tanaka, Takanari Fujiwara, Kyoko Asahina, Masakazu Okada, Kazuo Tomita, Masahiko Takeuchi, Shigehisa Yamamoto, Hiromitsu Sugimoto, Hirofumi Shinohara
IEICE TRANSACTIONS ON ELECTRONICS E91C ( 8 ) 1338  1347 2008.08
Satoshi Ishikura, Marefusa Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi, Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara, Hironori Akamatsu
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 43 ( 4 ) 938  945 2008.04
Onchip leakage monitor circuit to scan optimal reverse bias voltage for adaptive bodybias circuit under gate induced drain leakage effect
M. Fujii, H. Suzuki, H. Notani, H. Makino, H. Shinohara
ESSCIRC 2008  Proceedings of the 34th European SolidState Circuits Conference 258  261 2008 [Refereed]
A 45nm singleport and dualport SRAM family with robust read/write stabilizing circuitry under DVFS environment
K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, Y. Oda, K. Usui, T. Kawamura, N. Tsuboi, T. Iwasaki, K. Hashimoto, H. Makino, H. Shinohara
2008 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS 212  + 2008 [Refereed]
A 45nm bulk CMOS embedded SRAM with improved immunity against process and temperature variations
Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshmobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 43 ( 1 ) 180  191 2008.01
Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 43 ( 1 ) 96  108 2008.01
Masanori Kurimoto, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara
2008 45TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 884  + 2008
K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, Y. Oda, K. Usui, T. Kawamura, N. Tsuboi, T. Iwasaki, K. Hashimoto, H. Makino, H. Shinohara
2008 IEEE SYMPOSIUM ON VLSI CIRCUITS 167  + 2008
Onchip Digital Idn and Idp Measurement by 65 nm CMOS Speed Monitor Circuit
H. Notani, M. Fujii, H. Suzuki, H. Makino, H. Shinohara
2008 IEEE ASIAN SOLIDSTATE CIRCUITS CONFERENCE 401  + 2008
Hiroaki Suzuki, Masanori Kurimoto, Tadao Yamanaka, Hidehiro Takata, Hiroshi Makino, Hirofumi Shinohara
Proceedings of the International Symposium on Low Power Electronics and Design 15  20 2008
Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 42 ( 4 ) 820  829 2007.04
Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Qkada, Atsushi Ishii, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
Digest of Technical Papers  IEEE International SolidState Circuits Conference 485  617 2007
A Large Scale, flipflop RAM imitating a logic LSI for fast development of process technology
M. Fujii, K. Nii, H. Makino, S. Ohbayashi, M. Igarashi, T. Kawamura, M. Yokota, N. Tsuda, T. Yoshizawa, T. Tsutsui, N. Takeshita, N. Murata, T. Tanaka, T. Fujiwara, K. Asahina, M. Okada, K. Tomita, M. Takeuchi, H. Shinohara
2007 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, PROCEEDINGS 131  + 2007
Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara
Digest of Technical Papers  IEEE International SolidState Circuits Conference 321  606 2007
S. Ishikura, M. Kurumada, T. Terano, Y. Yamagami, N. Kotani, K. Satomi, K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, T. Oashi, H. Makino, H. Shinohara, H. Akamatsu
2007 Symposium on VLSI Circuits, Digest of Technical Papers 254  255 2007
A 65 nm SoC embedded 6TSRAM design for manufacturing with read and write cell stabilizing circuits
S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, M. Igarashi, M. Takeuchi, H. Kawashima, H. Makino, Y. Yamaguchi, K. Tsukamoto, M. Inuishi, K. Ishibashi, H. Shinohara
IEEE Symposium on VLSI Circuits, Digest of Technical Papers 17  18 2006.12
A 65 nm ultrahighdensity dualport SRAM with 0.71um^{2} 8Tcell for SoC
K. Nii, Y. Masuda, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, S. Imaoka, M. Igarashi, K. Tomita, N. Tsuboi, H. Makino, K. Ishibashi, H. Shinohara
IEEE Symposium on VLSI Circuits, Digest of Technical Papers 130  131 2006.12
Worstcase analysis to obtain stable read/write DC margin of high density 6TSRAMarray with local Vth variability
Y Tsukamoto, K Nii, S Imaoka, Y Oda, S Ohbayashi, T Yoshizawa, H Makino, K Ishibashi, H Shinohara
ICCAD2005: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS 398  405 2005 [Refereed]
A wide lockin range PLL using selfcalibrating technique for processors
Jingo Nakanishi, Hiromi Notani, Hiroshi Makino, Hirofumi Shinohara
2005 IEEE ASIAN SOLIDSTATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS 285  288 2005
Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
IEEE/ACM International Conference on ComputerAided Design, Digest of Technical Papers, ICCAD 2005 398  405 2005
A 64bit carry look ahead adder using pass transistor BiCMOS gates
K Ueda, H Suzuki, K Suda, H Shinohara, K Mashiko
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 31 ( 6 ) 810  818 1996.06
An 8.8ns 54x54bit multiplier with high speed redundant binary architecture
H Makino, Y Nakase, H Suzuki, H Morinaka, H Shinohara, K Mashiko
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 31 ( 6 ) 773  783 1996.06
A 1.2GFLOPS NEURALNETWORK CHIP EXHIBITING FAST CONVERGENCE
Y KONDO, Y KOSHIBA, Y ARIMA, M MURASAKI, T YAMADA, H AMISHIRO, H SHINOHARA, H MORI
1994 IEEE INTERNATIONAL SOLIDSTATE CIRCUITS CONFERENCE  DIGEST OF TECHNICAL PAPERS 37 218  219 1994
A VOLTAGE COMPENSATED SERIESGATE BIPOLAR CIRCUIT OPERATING AT SUB2V
H SATO, K UEDA, N SASAKI, K NIWANO, H SHINOHARA
PROCEEDINGS OF THE 1993 BIPOLAR/BICOMS CIRCUITS AND TECHNOLOGY MEETING 232  235 1993
A 8.8NS 54 X 54BIT MULTIPLIER USING NEW REDUNDANT BINARY ARCHITECTURE
H MAKINO, Y NAKASE, H SHINOHARA
1993 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN : VLSI IN COMPUTERS & PROCESSORS  PROCEEDINGS 202  205 1993
A 20 TERACPS ANALOG NEURALNETWORK BOARD
M MURASAKI, Y ARIMA, H SHINOHARA
IJCNN '93NAGOYA : PROCEEDINGS OF 1993 INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS, VOLS 13 3 3027  3030 1993
A refreshable analog VLSI neural network chip with 400 neurons and 40k synapses
Yutaka Arima, Mitsuhiro Murasaki, Tsuyoshi Yamada, Atushi Maeda, Hirofumi Shinohara
Digest of Technical Papers  IEEE International SolidState Circuits Conference 1992February 132  133 1992.01
A Refreshable Analog VLSI Neural Network Chip with 400 Neurons and 40K Synapses
Yutaka Arima, Mitsuhiro Murasaki, Tsuyoshi Yamada, Atsushi Maeda, Hirofumi Shinohara
IEEE Journal of SolidState Circuits 27 ( 12 ) 1854  1861 1992
A high density data path generator with stretchable cells
Y. Tsujihashi, H. Matsumoto, S. Kato, H. Nakao, O. Kitada, K. Okazaki, H. Shinohara
Proceedings of the Custom Integrated Circuits Conference 11.3.4 1992
A Flexible Multiport RAM Compiler for Data Path
Hirofumi Shinohara, Kumiko Fujimori, Yoshiki Tsujihashi, Shuichi Kato, Yasutaka Horiba, Noriaki Matsumoto, Hiroomi Nakao, Akiharu Tada
IEEE Journal of SolidState Circuits 26 ( 3 ) 343  349 1991
A 24b 50ns Digital Image Signal Processor
ShinIchi Nakagawa, Tetsuya Matsumura, Hiroshi Segawa, Masahiko Yoshimoto, Hirofumi Shinohara, ShuIchi Kato, Masahiro Hatanaka, Yasutaka Horiba
IEEE Journal of SolidState Circuits 25 ( 6 ) 1484  1493 1990
A FLEXIBLE MULTIPORT RAM COMPILER FOR DATAPATH
H SHINOHARA, N MATSUMOTO, K FUJIMORI, S KATO
PROCEEDINGS OF THE IEEE 1990 CUSTOM INTEGRATED CIRCUITS CONFERENCE 400  403 1990
Shin ichi Nakagawa, Hideyuki Terane, Tetsuya Matsumura, Hiroshi Segawa, Masahiko Yoshimoto, Hirofumi Shinohara, Shu ichi Kato, Atsushi Maeda, Yasutaka Horiba, Hideo Ohira, Yoshi aki Katoh, Mamoru Iwatsuki, Kin ya Tabuchi
Digest of Technical Papers  IEEE International SolidState Circuits Conference 32 1989.12
A 34ns 1Mbit CMOS SRAM Using Triple Polysilicon
Tomohisa Wada, Toshihiko Hirose, Hirofumi Shinohara, Yuji Kawai, Kojiro Yuzuriha, Yoshio Kohno, Shimpei Kayano
IEEE Journal of SolidState Circuits 22 ( 5 ) 727  732 1987
SubmicrometerGate MOSFET's by the Use of FocusedIonBeam Exposure and a Dry Development Technique
Hiroaki Morimoto, Katsuhiro Tsukamoto, Hirofumi Shinohara, Masahide Inuishi, Tadao Kato
IEEE Transactions on Electron Devices 34 ( 2 ) 230  234 1987
25ns 256K ×1/64K × 4 CMOS SRAM's
Shinpei Kayano, Katsuki Ichinose, Yoshio Kohno, Hirofumi Shinohara, Kenji Anami, Shuji Murakami, Tomohisa Wada, Yuji Kawai, Yoichi Akasaka
IEEE Journal of SolidState Circuits 21 ( 5 ) 686  691 1986
SUBMICRON LITHOGRAPHY USING FOCUSEDIONBEAM EXPOSURE FOLLOWED BY A DRY DEVELOPMENT.
T. Kato, H. Morimoto, K. Tsukamoto, H. Shinohara, M. Inuishi
Digest of Technical Papers  Symposium on VLSI Technology 72  73 1985.12
A 45NS 256K CMOS STATIC RAM WITH A TRILEVEL WORD LINE
H SHINOHARA, K ANAMI, K ICHINOSE, T WADA, Y KOHNO, Y KAWAI, Y AKASAKA, S KAYANO
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 20 ( 5 ) 929  934 1985
A FAST 8K X 8 MIXED CMOS STATIC RAM
H SHINOHARA, K ANAMI, T YOSHIHARA, Y KIHARA, Y KOHNO, Y AKASAKA, S KAYANO
IEEE TRANSACTIONS ON ELECTRON DEVICES 32 ( 9 ) 1792  1796 1985
A 45NS 256K CMOS STATIC RAM WITH A TRILEVEL WORD LINE
H SHINOHARA, K ANAMI, K ICHINOSE, T WADA, Y KOHNO, Y KAWAI, Y AKASAKA, S KAYANO
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 20 ( 5 ) 929  934 1985
A 4.5NS 256K CMOS SRAM WITH TRILEVEL WORD LINE
H SHINOHARA, K ANAMI, K ICHINOSE, T WADA, Y KOHNO, Y KAWAI, Y AKASAKA, S KAYANO
ISSCC DIGEST OF TECHNICAL PAPERS 28 62  63 1985
A 64KB FULL CMOS RAM WITH DIVIDED WORD LINE STRUCTURE
M YOSHIMOTO, K ANAMI, H SHINOHARA, T YOSHIHARA, H TAKAGI, S NAGAO, S KAYANO, T NAKANO
ISSCC DIGEST OF TECHNICAL PAPERS 26 58  & 1983 [Refereed]
Analysis of parasitic resistance effects in MOS LSI
Kenji Anami, Masahiko Yoshimoto, Hirofumi Shinohara, Osamu Tomisawa, Takao Nakano
Electronics and Communications in Japan (Part I: Communications) 66 ( 10 ) 106  113 1983
A DIVIDED WORDLINE STRUCTURE IN THE STATIC RAM AND ITS APPLICATION TO A 64K FULL CMOS RAM
M YOSHIMOTO, K ANAMI, H SHINOHARA, T YOSHIHARA, H TAKAGI, S NAGAO, S KAYANO, T NAKANO
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 18 ( 5 ) 479  485 1983
DESIGN CONSIDERATION OF A STATIC MEMORY CELL
K ANAMI, M YOSHIMOTO, H SHINOHARA, Y HIRATA, T NAKANO
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 18 ( 4 ) 414  417 1983
SOFT ERROR ANALYSIS OF FULLY STATIC MOS RAM.
Masahiko Yoshimoto, Kenji Anami, Hirofumi Shinohara, Yoshihiro Hirata, Tsutomu Yoshihara, Takao Nakano
Proceedings of the Conference on Solid State Devices 22 69  73 1983.01
PARASITIC RESISTANCE EFFECTS ON STATIC MOS RAM.
H. Shinohara, K. Anami, M. Yoshimoto, Y. Hirata, T. Nakano
Digest of Technical Papers  Symposium on VLSI Technology 106  107 1982.12
A 35NS 16K NMOS STATIC RAM
K ANAMI, M YOSHIMOTO, H SHINOHARA, Y HIRATA, H HARADA, T NAKANO
ISSCC DIGEST OF TECHNICAL PAPERS 25 250  & 1982 [Refereed]
K ANAMI, M YOSHIMOTO, H SHINOHARA, Y HIRATA, H HARADA, T NAKANO
IEEE JOURNAL OF SOLIDSTATE CIRCUITS 17 ( 5 ) 815  820 1982
メモリデバイス イメージセンサ
篠原 尋史( Part： Joint author, 2.2 SRAM)
丸善株式会社 2009.12
Low Energy Dissipation Circuits with 0.5V Operation Voltage and Applications
SHINOHARA Hirofumi
Technical report of IEICE. ICD 112 ( 170 ) 23  28 2012.07
0.4V SRAM with Bit Line Swing Suppression Charge Share Hierarchical Bit Line Scheme
MORIWAKI Shinichi, KAWASUMI Atsushi, SUZUKI Toshikazu, YAMAMOTO Yasue, MIYANO Shinji, SHINOHARA Hirofumi, SAKURAI Takayasu
Technical report of IEICE. ICD 112 ( 15 ) 67  71 2012.04
Energy Efficiency Increase of Integer Unit Enabled by Contentionless FlipFlops (CLFF) and Separated Supply Voltage Between FlipFlops and Combinational Logics
FUKETA Hiroshi, HIRAIRI Koji, YASUFUKU Tadashi, Takamiya Makoto, NOMURA Masahiro, SHINOHARA Hirofumi, SAKURAI Takayasu
Technical report of IEICE. ICD 111 ( 188 ) 127  132 2011.08
YABUUCHI Makoto, NII Koji, TSUKAMOTO Yasumasa, OHBAYASHI Shigeki, IMAOKA Susumu, YAMAGAMI Yoshinobu, ISHIKURA Satoshi, TERANO Toshio, SATOMI Katsuji, AKAMATSU Hironori, SHINOHARA Hirofumi
IEICE technical report 108 ( 139 ) 17  21 2008.07
OHBAYASHI Shigeki, YABUUCHI Makoto, KONO Kazushi, ODA Yuji, IMAOKA Susumu, USUI Keiichi, YONEZU Toshiaki, IWAMOTO Takeshi, NII Koji, TSUKAMOTO Yasumasa, ARAKAWA Masashi, UCHIDA Takahiro, MAKINO Hiroshi, ISHIBASHI Koichiro, SHINOHARA Hirofumi
IEICE technical report 107 ( 1 ) 59  64 2007.04
TSUKAMOTO Yasumasa, NII Koji, IMAOKA Susumu, ODA Yuji, OHBAYASHI Shigeki, YABUUCHI Makoto, MAKINO Hiroshi, ISHIBASHI Koichiro, SHINOHARA Hirofumi
IEICE technical report 106 ( 2 ) 95  100 2006.04
Quality Improvement of Natural Data for Security by Controling Initial State
Project Year :
A 373 F2 2D PowerGated EE SRAM Physically Unclonable Function (PUF) with DarkBit Detection Technique
Kunyang LIU, Yue MIN, Xuan YANG, Hanfeng SUN, Hirofumi SHINOHARA
IEICE Technical Report ICD
Presentation date： 2019.04
Compensation of Temperature Induced FlippingBits in CMOS SRAM PUF by NMOS BodyBias
Xuanhao ZHANG, Xiang CHEN, Hanfeng SUN, Hirofumi SHINOHARA
IEICE Technical ReportHWS
Presentation date： 2018.08
[Invited Paper] Randon Circuits for Information security
SHINOHARA, Hirofumi [Invited]
IEICE Technical Report ICD
Presentation date： 2018.04
Graduate School of Information, Production and Systems
2022 fall semester
Dependable Information Systems Research (Doctor's Thesis)
Graduate School of Information, Production and Systems
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Dependable Information Systems Research (Fall)
Graduate School of Information, Production and Systems
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Graduate School of Information, Production and Systems
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Dependable Information Systems C
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Dependable Information Systems B
Graduate School of Information, Production and Systems
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Dependable Information Systems D
Graduate School of Information, Production and Systems
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Dependable Information Systems A
Graduate School of Information, Production and Systems
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Graduate School of Information, Production and Systems
2022 spring semester
Dependable Information Systems Research (Master's Thesis)
Graduate School of Information, Production and Systems
2022 full year
Dependable Information Systems
Graduate School of Information, Production and Systems
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Dependable Information Systems Research (Fall)
Graduate School of Information, Production and Systems
2022 fall semester
Dependable Information Systems Research (Spring)
Graduate School of Information, Production and Systems
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Topics in Fundamental Science and Engineering C
School of Fundamental Science and Engineering
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Topics in Fundamental Science and Engineering C
School of Fundamental Science and Engineering
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Topics in Fundamental Science and Engineering C
School of Fundamental Science and Engineering
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Topics in Fundamental Science and Engineering C
School of Fundamental Science and Engineering
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School of Fundamental Science and Engineering
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IEEE VLSIDAT Technical Program Committee
IEEE ISSCC International Technical Program Committee