© 2017 IEEE. Reducing BER (Bit Error Rate) is a crucial problem for a PUF (Physical Unclonable Function) in the security application. In this paper, BER is analyzed focusing on two major factors: mismatch factor and noise. By comparing five SRAM PUFs with different transistor sizes, weight factor of load pMOS and driver nMOS that determines the mismatch is extracted. And it is shown that BER can be reduced by unbalancing the pMOS/nMOS transistor size ratio.

In this paper, a nanopower supply-insensitive complementary metal-oxide-semiconductor (CMOS) unit threshold voltage (Vth) extractor circuit is proposed. It meets the contemporary industry demand for portable devices that operate with very low power consumption and small output sensitivity. An α times Vth (α Vth) extractor is also described, in which α varies continuously. Both incremental and decremental α Vth voltages are obtained. A post-layout simulation results using HSPICE with CMOS 0.18 um process show that the proposed unit α Vth extractor consumes 265nW of power given a 1.6 V power supply. Sensitivity to temperature is 0.022%/°C ranging from 0°C to 100°C. Sensitivity to supply voltage is 0.027%/V.

The correlation between the static random access memory (SRAM) power-up state (i.e., state 0 or 1 immediately after the power supply is turned on) and cell transistor variation is systematically studied by circuit simulations and mismatch space partitioning. It is revealed that, while both the mismatches of pFETs (pull-up) and nFETs (pull-down and access) contribute, their relative importance changes depending on the voltage ramping speed. The static retention noise margin well correlates with the power-up state only if the ramping speed is sufficiently low. Otherwise, pull-up transistor mismatch dominates the power-up state determination owing to the interference of capacitive current and asymmetrical capacitive coupling of the storage nodes to the ground and power supply. (c) 2017 The Japan Society of Applied Physics

A technique of using an ordinary static random access memory (SRAM) array for a programmable nonvolatile (NV) memory is proposed. The parallel NV writing of the entire array is achieved by simply applying high-voltage stress to the power supply terminal, after storing inverted desired data in the static random access memory (SRAM) array. Successful 2 kbit NV writing is demonstrated using a device-matrix-array (DMA) test element group (TEG) fabricated by 0.18 mu m technology. (C) 2017 The Japan Society of Applied Physics

© 2016 IEEE. The conventional multi-loop control of a boost converter needs a current sampling circuit to detect the inductor current. Sensorless multi-loop control reduces the cost, size and weight of the power conversion system. The Luenberger observer (LO) is widely used to estimate the inductor current for the sensorless control of a switching converter. However, the design of the LO based sensorless multi-loop control has not been well presented by far. In this paper, a closed-loop characteristics evaluation method is proposed to design a LO based sensorless multi-loop control for boost converters. Simulations show the closed-loop characteristics evaluations. Practical experiments on a digital processor confirm the simulations.

A CMOS bandgap reference circuit without resistors, which can successfully operate under 1V supply voltage is proposed. The improvement is realized by the technique of the voltage divider and a new current source. The most attractive merit is that the proposed circuit breaks the bottleneck of low supply voltage design caused by the constant bandgap voltage value (1.25 V). Moreover, the temperature coefficient of the reference voltage Vref is improved by compensating the temperature dependence caused by the current source. The simulation results using a standard CMOS 0.18 um process show that the value of Vref can be achieved around 0.5 V with a minimum supply voltage of 0.85 V. Meanwhile, the temperature coefficient of the output voltage is only 3.5 ppm/°C from 0 °C to 70 °C.

Luenberger observer (LO)-based sensorless multi-loop control of a converter requires an iterative trial-and-error design process, considering that many parameters should be determined, and loop gains are indirectly related to the closed-loop characteristics. Robust H infinity control adopts a compact sensorless controller. The algebraic Riccati equation (ARE) -based and linear matrix inequality (LMI)-based H infinity approaches need an exhaustive procedure, particularly for a low-order controller. Therefore, in this study, a novel robust H infinity synthesis approach is proposed to design a low-order sensorless controller for boost converters, which need not solve any ARE or LMI, and to parameterize the controller by an adjustable parameter behaving like a "knob" on the closed-loop characteristics. Simulation results show the straightforward closed-loop characteristics evaluation and better dynamic performance by the proposed H infinity approach, compared with the LO-based sensorless multi-loop control. Practical experiments on a digital processor confirmed the simulation results.

We propose novel circuit techniques for 1 clock (1CLK) 1 read/1 write (1R/1W) 2-port static random-access memories (SRAMs) to improve read access time (tAC) and write margins at low voltages. Two-stage read boost (TSR-BST) and write word line boost (WWL-BST) after the read sensing schemes have been proposed. TSR-BST reduces the worst read bit line (RBL) delay by 61% and RBL amplitude by 10% at V-DD = 0.5 V, which improves tAC by 39% and reduces energy dissipation by 11% at V-DD = 0.55 V. WWL-BST after read sensing scheme improves minimum operating voltage (V-min) by 140 mV. A 32 kbit 1CLK 1R/1W 2-port SRAM with TSR-BST and WWL-BST has been developed using a 40 nm CMOS. (C) 2016 The Japan Society of Applied Physics

Small loop gain and low crossover frequency result in poor dynamic performance of a single-loop output voltage controlled boost converter in continuous conduction mode. Multi-loop current control can improve the dynamic performance, however, the cost, size and weight of the circuit will also be increased. Sensorless multi-loop control solves the problems, however, the difficulty of the closed-loop characteristics evaluation will be severely aggravated, because there are more parameters in the loops, meanwhile, different from the single-loop, the relationships between the loop gains and closed-loop characteristics including audio susceptibility and output impedance are generally indirect for the multi-loop. Therefore, in this paper, a novel robust H infinity synthesis approach in the time-domain is proposed to design a sensorless controller for boost converters, which need not solve any algebraic Riccati equation or linear matrix inequalities, and most importantly, provides an approach to parameterizing the controller by an adjustable parameter. The adjustable parameter behaves like a 'knob' on the dynamic performance, consequently, which makes the closed-loop characteristics evaluation straightforward. A boost converter is used to verify the proposed synthesis approach. Simulations show the great convenience of the closed-loop characteristics evaluation. Practical experiments confirm the simulations.

SRAM data just after power-up were measured using an addressable SRAM cell array test structure. It was found that the results are strongly affected by the address switching noise and "memory effect". An addressing sequence combined with word line reset pulse application is proposed for reliable power-up data stability evaluation.

An output capacitor-less low dropout regulator with three quick-responding (QR) loops is implemented in 0.18 mu m CMOS technology, featuring low sensitivity with changes in input voltage and load current. The proposed capacitor-less LDO has high stability for a current load from 0 to 100 mA and a capacitor load of 100 pF while the dropout voltage is 200 mV. A buffer is used to improve loop gain. The line regulation is 0.95 mV/V and the load regulation is 20 mu V/mA. The quick-responding loops can effectively reduce the overshoot and undershoot. When the load current switch between 0 and 100 mA with 1 mu s edge time, the maximum overshoot and undershoot are 36.13 mV and 36.81 mV under a 1.2 V supply voltage. And setting time is about 1.8 mu s.

A multiple-string LED driver with low total harmonic distortion (THD) by sinusoid-like reference and minimum components is presented in this paper. The proposed commutating method is able to control the source-coupled-pair by simplest circuitry and without passive components. The reference voltage is divided from rectifier in order to minimize the THD. The simulated 4-strings LED driver is able to achieve high power factor 99.95% and very low THD 3.16% under a 10W/100V AC condition. And the proposed circuit is implemented by differential pair and diodes to replace op-amp and bias voltage.

The minimum operation voltage (V-min) of intrinsic channel fully depleted (FD) silicon-on-thin-buried-oxide (SOTB) static random access memory (SRAM) cells are measured and compared with those of conventional bulk SRAM cells in order to directly compare the worst cells. It is confirmed that the worst V-min of 1 kbit SOTB SRAM cells is half that of 1 kbit bulk cells. The distribution of V-min of 48 kbit SOTB and bulk SRAM cells are also measured and compared. The results show a great advantage of SOTB SRAM cells for lower power and lower voltage operation upon introducing SOTB, because of reduced V-TH variability. (C) 2014 The Japan Society of Applied Physics

Extremely low voltage operation near or below threshold voltage is a key circuit technology to improve the energy efficiency of information systems and to realize ultra-low power sensor nodes. However, it is difficult to operate conventional analog circuits based on amplifier at low voltage. Furthermore, PVT (Process, Voltage and Temperature) variation and random Vth variation degrade the minimum operation voltage and the energy efficiency in both digital and analog circuits. In this paper, extremely low power analog circuits based on comparator and switched capacitor as well as extremely low power digital circuits are presented. Many kinds of circuit technologies are applied to cope with the variation problem. Finally, image processing SoC that integrates digital and analog circuits is presented, where improvement of total performance by a cooperation of analog circuits and digital circuits is demonstrated. Copyright © 2014 The Institute of Electronics, Information and Communication Engineers.

This paper presents a 40-nm 8T SRAM in which bitlines are partially discharged by a selective source line control (SSLC) for low-power operation. The proposed SSLC scheme reduces a read bitline voltage swing in an unselected column with a floating source line (SL) of dedicated read ports. The SL is controlled by an additional NMOS switch that is turned on in a selected column, but the switch is kept off in the remaining unselected columns. The proposed scheme is effective for power reduction in successive address readouts through a single column. Furthermore, this paper introduces an address preset structure. The preset address enables the SRAM to be read out with no access time penalty for preferred use of the SSLC scheme. We fabricated a 16-Kb 8T SRAM test chip in a 40-nm CMOS process and observed that the proposed SSLC scheme with the address preset structure saves 38.1% of the readout power on average. © 2013 IEEE.

A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%. © 2013 JSAP.

A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%. © 2013 JSAP.

To achieve the most energy-efficient operation, this brief presents a circuit design technique for separating the power supply voltage (V-DD) of flip-flops (FFs) from that of combinational circuits, called the higher voltage FF (HVFF). Although V-DD scaling can reduce the energy, the minimum operating voltage (V-DDmin) of FFs prevents the operation at the optimum supply voltage that minimizes the energy, because the V-DDmin of FFs is higher than the optimum supply voltage. In HVFF, the V-DD of combinational logic gates is reduced below the V-DDmin of FFs while keeping the V-DD of FFs at their V-DDmin. This makes it possible to minimize the energy without power and delay penalties at the nominal supply voltage (1.2 V) as well as without FF topological difications. A 16-bit integer unit with HVFF is fabricated in a 65-nm CMOS process, and measurement results show that HVFF reduces the minimum energy by 13% compared with the conventional operation, which is 1/10 times smaller than the energy at the nominal supply voltage.

An abnormal increase in crosstalk noise in subthreshold logic circuits is observed for the first time. When the threshold voltages (VTH) of nMOS and pMOS are imbalanced and the on-resistance of the aggressor driver is much lower than that of the victim driver, large crosstalk noise is observed, because the on-resistance has an exponential dependence on VTH in the subthreshold region being different from normal voltage operations. A simple crosstalk noise model is also proposed and verified with SPICE simulations. In a crosstalk noise test chip with a 1.5-mm interconnect in 40-nm CMOS at a power supply voltage (V DD) of 0.3 V, the measured noise amplitude increases from 32% of V DD to 71% of V DD, when V TH imbalance is realized by tuning body bias in pMOS. This body bias tuning can be used to mitigate the crosstalk problem in chip designs. For noise induced by a rising edge, the noise becomes largest under the slow-nMOS/fast-pMOS corner condition, while for noise induced by a falling edge, the noise becomes largest under the fast-nMOS/slow-pMOS corner condition, which is explained by the proposed model. © 1966-2012 IEEE.

Low voltage SRAM at a near-threshold voltage has two major sources of power waste: excess bit line swing due to the random variation of transistors and dynamic power consumption of the bit line swing of non-selected columns. In order to overcome these waste power consumption issues and achieve the highest energy-efficient operation of low voltage SRAM, the new CSHBL technique and CCC techniques, which is the improved version of the CSHBL, have been proposed. An SRAM fabricated using 65 nm technology adopting the CSHBL achieved an energy consumption of 26.4 pJ/Access/Mbit, and that of 13.8 pJ/Acess/Mbit is achieved by the SRAM macro that adopted CCC with 40 nm technology. This energy consumption is lower than values in previous works.

Subthreshold logic circuits are one of promising solutions to achieve ultra-low power operation. However, subthreshold circuits are significantly sensitive to manufacturing and environmental variability. In this paper, we will discuss design challenges in subthreshold logic circuits, such as rise in a minimum operating voltage, signal integrity degradation, and large delay variations. © 2013 IEEE.

Temperature dependence of 256 within-die random gate delay variations in sub-threshold logic circuits is measured in 40-nm CMOS test chips. When the temperature is reduced from 25 degrees C to -40 degrees C, the sigma/average (sigma/mu) of the gate delay at 0.3 V increases by 1.4 times. A newly developed model shows that sigma/mu of the gate delay is proportional to 1/T for the first time, where T is the absolute temperature.

Abnormal increase of the crosstalk noise in the sub-threshold logic circuits is found for the first time. When the threshold voltages (V TH) of nMOS and pMOS are imbalanced and the on-resistance of the aggressor driver is much lower than that of the victim driver, the large crosstalk noise is observed, because the on-resistance has an exponential dependence on VTH in the sub-threshold circuits. In this paper, the large crosstalk noise due to the imbalanced VTH is measured. A new crosstalk noise model is also proposed and verified with SPICE simulations. In a crosstalk noise test chip with 1.5-mm wire in a 40-nm CMOS at the power supply voltage (VDD) of 0.3V, the measured noise amplitude increases from 32% of VDD to 71% of VDD, when the imbalanced V TH is realized by tuning a body bias in pMOS. In the worst case fast-nMOS/slow-pMOS corner simulations, the noise amplitude increases from 47% of VDD to 68% of VDD, when VDD is reduced from 1.1V to 0.3V, which is explained by the proposed model. © 2012 IEEE.

Scaling power supply voltages (V DD's) of logic circuits down to the sub/near-threshold region is a promising approach to achieve significant power reductions. Circuit delays in the ultra-low voltage region, however, are extremely sensitive to process, voltage, and temperature (PVT) variations, and hence, large timing margins are required for worst-case design. Since such large timing margins reduce the energy efficiency benefits of lower V DD, adaptive V DD control to cope with PVT variations is indispensable for ultra-low voltage circuits. In this paper, an adaptive V DD control system with parity-based error prediction and detection (PEPD) and 0.5-V input fully-integrated digital LDO (DLDO) is proposed. © 2012 IEEE.

A post-fabrication dual supply voltage (V-DD) control (PDVC) of multiple voltage domains is proposed for a minimum operating voltage (V-DDmin)-limited ultra low voltage logic circuits. PDVC effectively reduces an average V-DD below V-DDmin, thereby reducing the power consumption of logic circuits. PDVC is applied to a DES CODEC's circuit fabricated in 65nm CMOS. The layout of DES CODEC's is divided into 64 VDD domains and each domain size is 54 mu m x 63.2 mu m. High V-DD (V-DDH) or low V-DD (V-DDL) is applied to each domain and the selection of V-DD's is performed based on multiple built-in self tests. V-DDH is selected in V-DDmin-critical domains, while V-DDL is selected in V-DDmin-non-critical domains. A maximum 24% power reduction was measured with the proposed PDVC at 300kHz, V-DDH=437mV, and V-DDL=397mV.

1Mb SRAM with charge collector circuits for effective use of non-selected bit line charges has been fabricated in 40nm technology. These circuits reduce two major wasted power sources of the low voltage SRAM: excess bit line swing due to random variation and bit line swing of non-selected columns. The lowest power consumption of 13.8pJ/Access/Mbit in the previous works has been achieved. © 2012 IEEE.

An auto selective boost (ASB) scheme for slow SRAM memory cells in random variations has been proposed. ASB shortens the cycle time and decreases the average BL amplitude, which reduces both dynamic and leakage energy dissipation. The cycle time of SRAM is reduced by 60% at 0.5V using the proposed ASB scheme. By combining the ASB with a BL amplitude limiter (BAL), the energy dissipation is reduced by 55%. A 32Kbit SRAM with the ASB and BAL schemes has been fabricated by 40nm CMOS technology. © 2012 IEEE.

In this paper, energy and minimum operating voltage (V DDmin) are investigated for extremely-low-voltage CMOS logic designs. The dependences of energy and V DDmin on device parameters, such as threshold voltage, subthreshold swing parameter, and DIBL coefficient, are examined based on simulations and measurements. © 2011 IEEE.

Clock skew is a major cause of severe timing yield degradation for sub-/near-threshold digital circuits. We report for the first time on employing hot-carrier injection (HCI) for post-silicon clock-deskew trimming. An HCI trimmed clock buffer, which can be individually selected and stressed to adjust the clock edge, is proposed. In addition, it can be used in conjunction with on-chip skew monitoring circuits to achieve auto-stressing. Our approach is proven to be effective through a representative 1.1-mm x 0.8-mm clock tree in a 40-nm high-k complimentary metal-oxide-semiconductor process. On average, it reduces the clock skew by eight times at 0.4 V V(dd). No significant recovery is noticed two weeks after trimming.

In this paper, a closed-form expression for estimating a minimum operating voltage (V-DDmin) of CMOS logic gates is proposed. V-DDmin is defined as the minimum supply voltage at which circuits can operate correctly. V-DDmin of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that V-DDmin of inverter chains can be estimated within 11% error. The expression is also verified with silicon measurements in a 65nm CMOS process.

Contention-less flip-flops (CLFF's) and separated power supply voltages (VDD) between flip-flops (FF's) and combinational logics are proposed to achieve a maximum energy efficiency operation. The proposed technologies were applied to a 16-bit integer unit (IU) for media processing in a 65-nm CMOS process. Measurement results of fabricated chips show that the proposed CLFF reduces the minimum operating voltage of IU's by 64mV on average. By scaling VDD from 1.2V to 310mV with the proposed CLFF, the maximum energy efficiency of 1835GOPS/W and the highest energy efficiency increase of 12.7 times are achieved. © 2011 IEEE.

Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations within a functional block are compensated by the fine-grained supply voltage (VDD) control to minimize power at fixed clock frequency. In the 40-nm test chips, the layout of a data encryption core is divided into 6x7 voltage domains. Both high VDD (VDDH) and low VDD (VDDL) are supplied to each power domain and either VDDH or VDDL is adaptively selected according to the setup error warning signals generated by canary flip-flops. Compared with the conventional single VDD operation, the proposed FADVC reduced the power by 12% at 1-MHz clock in the measurement. © 2011 IEEE.

For Dynamic Voltage Scaling (DVS), we propose a novel design methodology. This methodology is composed of an error detection circuit and three technologies to reduce the area and power penalties which are the large issues for the conventional DVS with error detection. The proposed circuit, Phase-Adjustable Error Detection Flip-Flip (PEDFF), adjusts the clock phase of an additional FF for the timing error detection, based on the timing slack. 2-Stage Hold-Driven Optimization (2-SHDO) technology splits the hold-driven optimization in two stages. Slack-Based Grouping Scheme (SBGS) technology divides each timing path into appropriate groups based on the timing slack. Slack Distribution Control (SDC) technology improves the sharp distribution of the path delay at which the logic synthesis tool has relaxed the delay. We evaluate the methodology by simulating a 32-bit microprocessor in 90 nm CMOS technology. The proposed methodology reduces the energy consumption by 19.8% compared to non-DVS. The OR-tree's latency is shortened to 16.3% compared to the conventional DVS. The area and power penalties for delay buffers on short paths are reduced to 35.0% and 40.6% compared to the conventional DVS, respectively. The proposed methodology with SDC reduces the energy consumption by 17.0% on another example with the sharp slack distribution by the logic synthesis compared to non-DVS.

A low-voltage high-speed bulk-CMOS SRAM that operates over 100MHz at 0.5V, for the first time, is proposed. A novel 8-transistor (8T) memory cell with a complementary read port (C-RP) improves the read speed by enabling differential bit-line sensing, while the conventional 8T SRAM drives the bit line with a single read port (S-RP). The cell layout of the C-RP SRAM has point symmetry and a small area overhead (1.4x) compared with the conventional 6T SRAM cell, without any additional layers. The read delay and the delay variation at 0.5V were reduced by 52% and 54%, respectively, compared with the conventional S-RP 8T cell. A suspended bit-line read (SBLR) scheme is also applied to the read circuit in order to eliminate the leakage current from the unselected cells, which is an inevitable issue for a C-RP 8T cell with a conventional voltage sense amplifier (VSA). The simulated results of 1 Kbit SRAM in a 65-nm standard bulk-CMOS technology demonstrated 150-MHz operating frequency at 0.5-V single Vdd without any assist techniques. The power-delay product was reduced by 64% compared with the conventional S-RP 8T. This SRAM was implemented in test chips using 65-nm and 40-nm bulk-CMOS technologies. ©2010 IEEE.

We propose an access scheme for a synchronous dual-port (DP) SRAM that minimizes the 8T-DP-cell area and maintains cell stability. A priority row decoder circuit and shifted bit-line access scheme eliminates access conflict issues. Using 65 nm CMOS technology (hp90) with the proposed scheme, we fabricated 32 kB DP-SRAM macros. We obtained a 0.71 mu m(2) 8T-DP-cell for which the cell size is only 1.44 x larger than a 6T-single-port (SP)cell. The bit-density of the fabricated 32 kB DP-RAM macro is 667 kbit/mm(2), which is 25 % larger than a conventional 8T SRAM. The standby leakage is 27 % less because of the small drive-NMOS transistor of the proposed 8T-DP-cell.

We propose a new design solution for embedded SRAM macros with cross point 8T-SRAM for low operating voltage and power. A negative bias technique for VSS and bitline (BL) enables us to achieve not only low power and high access speed, but also the large cell stability and write ability. Using 45-nm CMOS technology, we fabricated the SRAM macro based on our proposal and confirmed that the 1 Mbit-SRAM successfully operated at 0.6V. The active power is reduced by 66%, compared to the conventional 6T-SRAM.

We propose a test structure for systematic variation measurement over the whole shot and wafer area at a 45 nm process node. With this structure, we found that the systematic variation had two kinds of site dependence, one is a wafer scale and the other is a shot scale component. Additionally, the Die-to-Die and Within-Die variations for any chip size are calculated. Then, the systematic variation component has the correlation length more than 16mm. This shows that it is necessary to take into consideration the Within-Die variation according to the Die size.

An on-chip digital Ids measurement method is proposed in this report. In the proposed method, Ids is digitally derived from the two values measured by three ring oscillators with PN balanced, N-rich, and P-rich inverters. The first value is the frequency of the PN balanced inverter ring. The second value is the frequency difference between the N-rich and the P-rich inverter rings. The post-digital processing derives NMOS Ids (I dn) and PMOS Ids (Idp) separately. The monitor circuit was implemented by 65 nm CMOS technology. The mismatch error between the first Ids calculated from measured frequencies, and the second Ids directly measured for reference, was analyzed. The standard deviations of the mismatch error in Idn and Idp are 1.64% and 1.09%, respectively. The margin of 3σ is within 5% which is our target tolerance for a practical application. © 2008 IEEE.

We propose an enhanced design solution for embedded SRAM macros under dynamic voltage and frequency scaling (DVFS) environment. The improved wordline suppression technique using replica cell transistors and passive resistances compensates the read stability against process variation, facilitating the Fab. portability. The negative bitline technique expands the write margin for not only 6T single-port (SP) cell but also 8T dual-port (DP) cell even at the 0.7 V lower supply voltage. Using 45-nm CMOS technology, we fabricated both SP and DP SRAMs with the proposed circuitry. We achieve robust operations from 0.7 V to 1.3 V wide supply voltage. © 2008 IEEE.

Error Detection FFs for Dynamic Voltage Scaling (DVS) has been proposed. This technique controls the clock phase based on the timing slack, and reduces the energy consumption by 19.8% compared to non-DVS. The error signal latency is shortened to 6.3%, the area and power penalties for delay buffers on short paths become 35.0% and 40.6% lower compared to the conventional DVS. © 2008 ACM.

An analytical model of the static noise margin (SNM) for a 6T CMOS SRAM suitable for use in investigating the effect of random V-th variation is derived. A three-step approach using characteristic points of the half cell inverter's transfer curve is developed. Parameters of each transistor are handled individually so that their sensitivities are calculable. A new MOSFET model in the moderate inversion is proposed to maintain accuracy, even in the low V-DD condition. Correlation between the proposed model calculations and circuit simulations was verified using a 90 nm CMOS LSTP device. Closely correlated dependency on parameters such as V-th, the W ratio, and V-DD were obtained. Maximum error measured in the VDD range of 0.6-1.6 V was 16 mV (7% of typical SNM). Finally, guidelines to obtain large SNM are discussed in this paper.

We propose a new large-scale logic test element group (TEG). called a flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and to imitate a logic LSI. We implemented a 10 Mgates FF-RAM using our 65-nm CMOS process. The FF-RAM enables us to make fail-bit maps (FBM) of logic cells because of its cell array structure as an SRAM. An FF-RAM has an additional structure to detect the open and short failure of upper metal layers. The test results show that it can detect failure locations and layers effortlessly using FBMs. We measured and analyzed it for both the cell arrays and the upper metal layers. Their results provided many important clues to improve our processes. We also measured the neutron-induced soft error rate (SER) of FF-RAM, which is becoming a serious problem as transistors become smaller. We compared the results of the neutron-induced soft error rate to those of previous generations: 180 nm, 130 nm. and 90 nm. Because of this TEG, we can considerably shorten the development period for advanced CMOS technology.

We propose a new 2-port SRAM with a single read bit line (SRBL) eight transistors (8T) memory cell for a 45 nm system-on-a-chip (SoC). Access time tends to be slower as a fabrication is scaled down because of threshold voltage (V-t) random variations. A Divided read Bit line scheme with Shared local Amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous Read and-Write (R/W) access at the same row by using DBSA with the SRBL-8T cell. A rise of the storage node causes misreading. A Read End detecting Replica circuit (RER) and a Local read bit line Dummy Capacitance (LDC) are introduced to solve this issue. A 128 bit lines-512 word lines 64 kb 2-port SRAM macro using these schemes was fabricated by a 45 nm bulk CMOS low-standby-power (LSTP) CMOS process technology [1]. The memory cell size is 0.597 mu m(2). This 2-port SRAM macro achieves 7 times faster access time without misreading.

The variation tolerant assist circuits of an SRAM against process and temperature are proposed. Passive resistances are introduced to the read assist circuit with replica memory transistors to lower the wordline voltage accurately reflecting the process and temperature variations. For the sake of not only enlarging the write margin but also reducing power consumption and speed overhead, the divided dynamic power-line scheme based on a charge sharing is adopted. Test chips of 512-Kb SRAM macros and isolated memory cell TEGs are fabricated using 45-nm bulk CMOS technology. Two types of 6-T SRAM cells, whose sizes were 0.245 mu m(2) and 0.327 mu m(2) were designed and evaluated. From the measurement results, we achieved over 100-mV improvement for static noise margin, and 35 mV for write margin for both SRAM cells at 1.0-V worst condition by using assist circuitry. It enables the wordline level to keep higher voltage at the slowest condition than the typical process condition, which results in 83% improvement of the cell current compared with the conventional assist circuit. Furthermore, the minimum operating voltage in the worst case condition Was improved by 170 mV, confirming a high immunity against process and temperature variations with less than 10% area overhead.

We propose a wafer level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair for an embedded 6T-SRAM to achieve a known good die (KGD) SoC. We fabricated a 16 Mb SRAM with these techniques using 65 nm LSTP technology, and confirmed the efficient operations of these techniques. The WLBI mode enables simultaneous write operation for 6T-SRAM, and has no area penalty and a speed penalty of only 50 ps. The leak-bit redundancy for 6T-SRAM can reduce the infant mortality of the bare die, and improves the standby current distribution. The area penalty is less than 2%. The Cu E-trim fuse can be used beyond the 45 nm advanced process technology. The fuse requires no additional wafer process steps. Using only 1.2 V core transistors will allow CMOS technology scaling to enable fuse circuit size reduction. The trimming transistor is placed under the fuse due to there being no cracking around the trimmed position. We achieve the small fuse circuit size of 6 x 36 mu m(2) using 65 nm technology.

The Post-Silicon Programmed Body-Biasing Platform is proposed to suppress device variability in the 45-nm CMOS technology era. The proposed platform measures device speed during post-fabrication testing. Then the fast die is marked so that the body-bias circuit turns on and reduces leakage current of the die that is selected and marked in a user application. Because the slow die around the speed specifications of a product is not body-biased, the product runs as fast as a normal non-body-biasing product. Although the leakage power of a fast die is reduced, the speed specification does not change. The proposed platform improves the worst corner specification comprising the two worst cases of speed and leakage power. The test chip, fabricated using 45-nm technology, improves the worst corner of stand-by leakage power vs. speed by 70%. Copyright 2008 ACM.

We propose a new, large-scale, logic TEG, which is called flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and imitates a logic LSI. We implemented a 10-Mgate FF-RAM using our 65 nm CMOS process. The test results show that it is effortless to detect failure locations and layers by using fail bit maps. Owing to this TEG, we can significantly shorten the development period for advanced CMOS technology. © 2007 IEEE.

In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-mu m(2) SRAM cell with a beta ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology.

A wafer-level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable electrically trimmable (e-trim) fuse repair scheme for an embedded 6T-SRAM is used to achieve a known-good-die SoC. A 16Mb SRAM is fabricated with these techniques using a 65nm low-standby-power technology, and its operation is verified. The WLBI mode has a speed penalty of 50ps. The leak-bit redundancy area penalty is less than 2%. © 2007 IEEE.

A 512kb SRAM module is implemented in a 45nm low-standby-power CMOS with variation-tolerant assist circuits against process and temperature. A passive resistance is introduced to the read assist circuit and a divided VDD line is adopted in the memory array to assist the write. Two SRAM cells with areas of 0.245μm2 and 0.327μm2 are fabricated. Measurements show that the SNM exceeds 120mV and the write margin improves by 15% in the worst PVT condition. © 2007 IEEE.

We propose a new 2port (2P) SRAM with an 8T single-bit-line (SBL) memory cell for 45nm SOCs. Access time tends to be slower as the device size is scaled down because of the random threshold-voltage variations. The Divided read Bit line scheme with Shared local Amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous Read and Write (R/W) access at the same row by using DBSA with the 8T-SBL memory cell. A rise of the storage node voltage causes the misreading. The Read End detecting Replica circuit (RER) and the Local read bit line with Dummy Capacitance (LDC) are introduced to solve this issue. A 128BLx512WL 64Kb 2P-SRAM macro which cell size is 0.597 mu m(2) using these schemes was fabricated by 45nm LSTP CMOS process [1].

We propose a new design scheme to improve the SRAM read and write operation margins in the presence of a large Vth variability. By applying this scheme to a 0.494 μm2 SRAM cell with a β ratio of 1, which is an aggressively small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth value using a 65 nm LSTP CMOS technology. © 2006 IEEE.

We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stability. A priority row decoder circuit and shifted bit-line access scheme eliminates access conflict problem. Using 65nm CMOS technology (hp90), we fabricated 32KB DP-SRAM macros with the proposed scheme. We obtain 0.71um2 8T-DP-cell, which cell size is 1.44x larger than 6T-single-port (SP)-cell. © 2006 IEEE.

A wide lock-in range PLL using a self-calibrating technique is proposed. This technique realizes a wide lock-in range and good jitter characteristics by performing the digital calibration at the start of the operation. However, self-calibration with a large number of digital control steps increases the test costs and circuit scale. In this paper, by estimating the margin for self-calibrating operation, the minimum number of digital control steps was determined. A PLL with a low test cost, a wide lock-in range and low jitter was designed and implemented using a 0.15 mu m 1.5 V CMOS process. The measured PLL lock-in range is 80 MHz - 630 MHz with four digital calibration steps. The peak-to-peak jitter at 380 MHz is 100 ps.

6T-SRAM cells in the sub-100 nm CMOS generation are now being exposed to a fatal risk that originates from large local Vth variability (σ V_Local). To achieve high-yield SRAM arrays in presence of random σV_Local component, we propose worst-case analysis that determines the boundary of the stable Vth region for the SRAM read/write DC margin (Vth curve). Applying this to our original 65 nm SPICE model, we demonstrate typical behavior of the Vth curve and show new criteria for discussing SRAM array stability with Vth variability. © 2005 IEEE.

This paper describes a 64-bit two-stage carry look ahead adder utilizing pass transistor BiCMOS gate. The new pass transistor BiCMOS gate has a smaller intrinsic delay time than conventional BiCMOS gates. Furthermore, this gate has a rail-to-rail output voltage. Therefore the next gate does not have a large degradation of its driving capability. The exclusive OR and NOR gate using the pass transistor BiCMOS gate shows a speed advantage over CMOS gates under a wide variance in load capacitance. The pass transistor BiCMOS gates were applied to full adders, carry path circuits, and carry select circuits. In consequence, a 64-bit two-stage carry look ahead adder was fabricated using a 0.5 μm BiCMOS process with single-polysilicon and double-metal interconnections. A critical path delay time of 3.5 ns was observed at a supply voltage of 3.3 V. This is 25% better than the result of the adder circuit using CMOS technology. Even at the supply voltage of 2.0 V, this adder is faster than the CMOS adder.

A high speed redundant binary (RB) architecture, which is optimized for the fast CMOS parallel multiplier, is developed. This architecture enables one to convert a pair of partial products in normal binary (NB) form to one RB number with no additional circuit. We improved the RB adder (RBA) circuit so that it can make a fast addition of the RB partial products. We also simplified the converter circuit that converts the final RB number into the corresponding NB number. The carry propagation path of the converter circuit is carried out with only multiplexer circuits. A 54 × 54-bit multiplier is designed with this architecture. It is fabricated by 0.5 μm CMOS with triple level metal technology. The active area size is 3.05 × 3.08 mm2and the number of transistors is 78,800. This is the smallest number for all 54 × 54-bit multipliers ever reported. Under the condition of 3.3 V supply voltage, the chip achieves 8.8 ns multiplication time. The power dissipation of 540 mW is estimated for the operating frequency of 100 MHz. These are, so far, the fastest speed and the lowest power for 54 × 54-bit multipliers with 0.5-μm CMOS.

This paper describes a digital neural network chip for use as core in neural network accelerators employs a single-instruction multi-data-stream (SIMD architecture and includes twelve 24b floating-point processing units (PUs), a nonlinear function unit (NFU), and a control unit (CU). Each PU includes 24b×1.28kw local memory and communicates with its neighbor through a shift register ring. This configuration permits both feed-forward and error back propagation (BP) processes to be executed efficiently. The CU, which includes a three stage pipelined sequencer, a 24b×1kw instruction code memory (ICM) and a 144b×256w microcode memory (MCM), broadcasts network parameters (e.g., learning coefficients or temperature parameters) or addresses for local memories through a data and an address bus. Two external memory ports and a ring expansion-port permit large networks to be constructed. The external memory can be expanded by up to 768kW using the two ports.

A low-voltage series-gate (LSG) bipolar circuit is proposed. A lower-input transistor of the series-gate circuit also acts as a current source transistor. A switching current is compensated for a supply voltage. A 4-bit counter using this circuit operates at 500 MHz with the supply voltage of -1.6 V.

A new redundant binary (RB) architecture for the high speed multiplier is presented. In this architecture, a pair of partial products is converted to one RB number by inverting one of the pair without additional circuit and latency. Generated RB partial products are added by the Wallace tree of improved RB adders (RBAs) which have a latency of 0.9 ns, and converted to a normal binary (NB) number by a simply structured RB-to-NB converter in which the carry propagation circuit is constructed only with simple selector circuits. A 54×54-bit multiplier is designed using 0.5-μm CMOS technology. The multiplication time of 8.8 ns is obtained by SPICE2 simulation for the supply voltage of 3.3 V which is the fastest that has been reported for 54×54-bit multipliers.

We demonstrate an analog neural network board which integrates 18 interconnected neural network chips. The board realizes a fully feedback connection network consisting of 1,008 neurons and 1,016,064 synapses. The speed performance of the neural network is 20×1012 connections per second (CPS) and 500×109 connections update per second (CUPS).

© 1992 IEEE. Describes a self-learning neural network chip with refresh on-chip analog synaptic weight storage. The chip integrates 400 neurons and 40000 synapses with 0.8μm double poly-Si double metal CMOS technology. Refresh time is less than 300 mu s. The chip retains learned information by repeating refresh at 100 ms intervals. The proposed refresh method is based on the decision made by a subnetwork. The subnetwork learns if the settling states of the main network should be memorized, retains the weights until they are relearned, and stores a 4-b representation of subnetwork weights in a counter. The main network is refreshed according to the output of the subnetwork.

This paper describes an on-chip learning neural network LSI circuit that can refresh the analog storage synaptic weights located on the chip. The chip integrates 400 neurons and 40 000 synapses with a 0.8-μm double-poly double-metal CMOS technology. This device stores learned information by repeating the refresh process at 200-ms intervals. © 1992 IEEE

This paper describes a newly developed module generator for data-path. Function blocks are designed in 0.8μm double metal CMOS technology. Adopting new cell structure for over the cell routing, called "stretchable cell with access free terminals (SCAT)", high density of more than 7K trs./mm 2 and high performance data-path has been obtained. © 1992 IEEE.

A multiport RAM compiler with flexible layout and port organization has been developed using 1.0-μm CMOS technology. A new memory cell with an additional column-enable gate yielded a controllability over the aspect ratio of the memory cell array. Wide bit-word organization range including 2048 words × 16 b and 512 words × 72 b was also obtained. This compiler generates up to 32K three-port RAM and 16K six-port RAM. In addition to read and write ports, read/write ports are also available. The operations of the ports are fully static and asynchronous to each other. The RAM requires no dc power consumption. The address access times of the generated three-port RAM's are, for example, 5.0 ns for 1K and 11.0 ns for 32K. © 1991 IEEE

A multiport RAM compiler with flexible layout and port-organization has been developed in an 1.0-μm CMOS technology. A novel memory cell scheme with an additional column enable gate yielded a controllability over the aspect ratio of the layout. This compiler generates up to 32K three-port RAM and 16K six-port RAM. Each port operates statically and asynchronously with each other port. The address access times of the generated three-port RAMs are 5.0 ns (1 kb) and 10.0 ns (32 kb), for example.

This paper will report a 50-ns digital image signal processor (DISP), excellently suited for picture coding. The chip integrates 538K transistors and dissipates 1.4 W at 40-MHz clock. It is based on a 24-b fixed-point architecture with a five-stage pipeline. The instruction cycle time is 35 ns typically and 50 ns at worst. The DISP features a real-time processing capability realized by an enhanced parallel architecture, video-oriented data processing functions, and a 50-ns instruction cycle time at worst. Its 50-ns cycle time allows it to execute more than 60-million operations per second (MOPS). High-density 1.0-μm CMOS technology allows numerous on-chip features, which include specified resources optimized for the image processing. This enables a flexible hardware implementation of various algorithms for the picture coding. Several circuit design techniques to attain the fast instruction cycle include a distributed instruction decoding and a hierarchical clocking circuit. The LSI has been designed by the extensive use of a cell-based design method. The processor incorporates a sophisticated testing function compatible with the cell-based design environment. This paper will also discuss system performance advantages in the image/ video processing including the picture coding. © 1990 IEEE

A 50-ns CMOS DSP (digital signal processor) with enhanced parallel architecture suited for video signal processing is reported. It has significant performance advantages, especially for video codecs in ISDN (integrated services digital network) video communication, is based on a 24-b fixed-point architecture, and operates in a five-stage pipeline (instruction-fetch, instruction-decode, source-data-transfer, execution, and destination-data-transfer). It contains 538k transistors and typically consumes 1.4 W at an instruction cycle rate of 50 ns. The DSP was fabricated in a 1.0-μm double-metal CMOS technology. Computation speed for the several coding procedures is approximately 3 to 10 times faster than that of traditional DSPs. A 64-kb/s video codec can be implemented with four or five DSPs for full common-source-interface-formats (CSIF) mode and one or two DSPs for 1/4 CSIF mode.

This paper will describe a 128-kbit word × 8-bit CMOS SRAM with an access time of 34 ns and a standby current of 2 µA. This RAM has been fabricated using triple-polysilicon and single-aluminum CMOS technology with 0.8-µm minimum design features. A high-resistive third polysilicon load has been developed to realize a low standby current. In order to obtain a faster access time, a 16-block architecture and a data-output presetting technique combined with address transistion detection (ATD) are used. This RAM has a “flash-clear” function in which logical zero's are written into all memory cells in less than 1 μs. Copyright © 1987 by The Institute of Electrical and Electronics, Inc.

Resist patterns as small as 0.1 μm, were fabricated by the irradiation of a gallium focused ion beam followed by an oxygen plasma development. The measured width of the patterns fabricated by this technique was in good agreement with the designed linewidth in the sub-half-micrometer region, n-channel Si MOSFET's with 0.3-0.8-(μm, gates were fabricated by the use of this technique. These results, accompanied by the fabricated and demonstrated performance of a ring oscillator, showed the feasibility of focused-ion-beam lithography. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.

This paper describes 25-ns 256K CMOS static RAM's (SRAM‘s). Through a metal option, either 256K word × 1-bit or 64K word×4-bit organization is obtained. A fast access time has been achieved with a short bit-line structure and a data-bus precharging technique which minimize the bit-line and data-bus delay. A feedback-controlled address transition detector (ATD) circuit has been adopted to assure the fast access time in the presence of address skew. A 1.0-µm double-polysilicon and single-metal process technology with polycide gate offers a memory cell size of 90 µm2 and a chip size of 47.4 mm2. Copyright © 1986 by the Institute of Electrical and Electronics Engineers, Inc.

Ultrafine lithography for dimensions less than 0. 5 mu m is one of the most promising applications of focused ion beams (FIB) because ion beams hardly suffer from a proximity effect. Submicron patterns are delineated in the resist by irradiation of gallium FIB followed by a dry development. The patterning characteristics and their application to N-MOS FETs with 0. 3-0. 8 mu m gates are discussed.

Summary form only given. The 32K multiplied by 8-b static RAM includes an address-transition-activated circuit combined with a tri-level word line, which affords an active power of 7 mW at 1 MHz and a peak current of 40 mA. An address access time of 45 ns has been obtained. The RAM was fabricated with double-polysilicon single-aluminum CMOS technology. The gate lengths of the MOS transistors are scaled to 1. 3 mu (N channel) and 1. 8 mu (P channel) for fast access time. The use of 1. 3- mu m design rules permits layout of a NMOS memory cell with high resistance loads in area 8. 0 mu multiplied by 14. 5 mu area.

A 32K words by 8-bit static RAM fabricated with a CMOS technology. is described. The key feature of the RAM is a tri-level word-line, in which an automatic power down by a pulsed word-line in the READ cycle and a power saving by a middle-level word-line in the WRITE cycle are combined. This circuit technique minimizes bitline swing, shortens the precharging time, and depresses the transient current. An improved address transition detection circuit reduces the chip select access time. The sense amplifier uses internally synchronized signals for improved operation. The RAM has a typical access time of 45 ns with an active power dissipation of 7 mW. The peak transient current is less than 40 mA. A double-level polysilicon technology with a 1. 3- mu m design rule allowed layout of the NMOS memory cell in an area of 116. 0 mu m**2 and the die in 49. 6 mm**2.

This paper describes a 32K words by 8-bit static RAM fabricated with a CMOS technology. The key feature of the RAM is a tri-level word line, in which an automatic power down by a pulsed word line in the read cycle and a power saving by a middle-level word line in the WRITE cycle are combined. This circuit technique minimizes bit-line swing, shortens the precharging time, and depresses the transient current. An improved address transition detection circuit reduces the chip select access time. The sense amplifier uses internally synchronized signals for improved operation. The RAM has a typical access time of 45 ns with an active power dissipation of 7 mW. The peak transient current is less than 40 mA. A double-level polysilicon technology with a 13- μm design rule enabled layout of the NMOS memory cell in an area of 116.0 μm2 and the die in 49.6 mm2. © 1985 IEEE

This paper describes a fast 8K x 8 static RAM fabricated with a mixed CMOS technology. To realize a fast access time and yet a low active power, a block-oriented die architecture with four submodules and a new sense amplifier are applied. An address access time of 34 ns and a chip select access time of 38 ns have been achieved at an active power of 90 mW. In addition to redundant memory cells, the RAM incorporates a spare element disable (SED) function to make it easy to obtain the information of the replaced memory cell. Another feature is a high latchup immunity of the CMOS peripheral circuits. This is obtained from an optimized well structure and guard baids around the wells. A 2-μm design rule combined with the double level polysilicon layer allowed for layout of the NMOS memory cell in 266.5 μm<sup>2</sup>and design of the die in 34.3 mm<sup>2</sup>. Copyright © 1985 by The Institute of Electrical and Electronics Engineers, Inc.

This paper describes simplified analysis of the effects of transistor source and drain parasitic resistances and interconnect resistance in MOS LSI's, and their application to the circuit designs for MOS LSI circuits and mask patterns. Heretofore the analysis of parasitic resistance effects has been complex and could only be calculated numerically with circuit analysis programs. However, in this paper, a simple expression is given for the effect of the source and drain parasitic resistances by using a linear approximation to the MOS transistor drain i‐v characteristics. Furthermore, the delays caused by interconnection resistance are analyzed under assumptions that are actually obtained in practical LSI's. the rules for optimum design of the crossunders used frequently in LSI's are obtained using the result. Finally, experimental results from MOS transistors which agreed well with the source and drain parasitic resistance effect analysis. A ring oscillator experiment which also resulted in good agreement with the interconnect resistance delay analysis shows the applicability of both analysis methods. Copyright © 1983 Wiley Periodicals, Inc., A Wiley Company

This paper will describe a divided word-line (DWL) structure which solves inherent problems encountered in VLSI static RAM's. The key feature is to divide the word-line and to select it hierarchically with little area penalty using conventional process technology. In the application of the DWL structure, an 8K × 8 full CMOS RAM has been developed with 2 μ m double polysilicon technology. The RAM has a typical access time of 60 ns. An operating current of 20 mA was obtained with a simple static design. The six transistor cell configuration achieved a low standby current of less than 10 nA. For further improvement in the speed performance, second poly-Si layer was replaced with a polycide (poly-Si + MoSi2) layer, thus offering a 50 ns address access time. Copyright © 1983 by the Institute of Electrical and Electronics Engineers, Inc.

This paper describes design criteria for high-density low-power static RAM cells with a four-transistor two-resistor configuration. The states of the cell latch are expressed by a dc stability factor introduced from transfer curves of the inverters in the cell. The criteria feature using only static conditions for read/write/retain operations. The designed cell considering mask-misalignment measured 22.8 × 27.6 µm with 2.5 µm layout rules. From the evaluation of dynamic characteristics, it was shown that the 16K RAM using the cell had a sufficient operating margin. Copyright © 1983 by The Institute of Electrical and Electronics Engineers, Inc.

An NMOS 16K × 1 bit fully static MOS RAM with 35 ns access time has been successfully developed. High speed access time was achieved by the combination of an NMOS process with the 2.2 μm gate length transistor, high speed sense amplifier, and reduction of delay time at the crossunder. The improvements of row and column decoder circuits result in the low active and standby power dissipation of 275 mW and 22.5 mW, respectively. The soft error rate of poly load cell was minimized by reducing the collection efficiency of alpha-particle induced electrons. Copyright © 1982 by the Institute of Electrical and Electronics Engineers, Inc.