Concurrent Post
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Faculty of Science and Engineering School of Fundamental Science and Engineering
Details of a Researcher
Updated on 2022/06/28
Faculty of Science and Engineering School of Fundamental Science and Engineering
理工学術院総合研究所 兼任研究員
Kyoto University Graduate School of Informatics Department of Communication and Computer Engineering
Kyoto University Graduate School of Engineering Electronic Science and Engineering
Kyoto University Faculty of Engineering Electronic Engineering
博士
Waseda University Graduate School of information, Production and Systems (IPS) Professor
Semiconductor Technology Academic Research Center (STARC) Vice President
Renesas Electronics Co.
Semiconductor Technology Academic Research Center (STARC) Vice President
Renesas Technology Co.
Mitsubishi Electric Co.
IEEE
THE INSTITUTE OF ELECTRONICS
Electron device and electronic equipment Solid-State Circuits
Theory of informatics
Hardware Security
Low Energy Circuits
SRAM
TRNG
PUF
A CMOS 0.85-V 15.8-nW current and voltage reference without resistors
Jing Wang, Hirofumi Shinohara
2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 2019.04
A 373 F 2 2D Power-Gated EE SRAM Physically Unclonable Function with Dark-Bit Detection Technique
Kunyang Liu, Yue Min, Xuan Yang, Hanfeng Sun, Hirofumi Shinohara
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings 161 - 164 2018.12
High-throughput von Neumann post-processing for random number generator
Ruilin Zhang, Sijia Chen, Chao Wan, Hirofumi Shinohara
2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 1 - 4 2018.06
Kiyoshi Takeuchi, Tomoko Mizutani, Hirofumi Shinohara, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 30 ( 3 ) 209 - 215 2017.08
Measurement of mismatch factor and noise of SRAM PUF using small bias voltage
Ziyang Cui, Baikun Zheng, Yanhao Piao, Shiyu Liu, Ronghao Xie, Hirofumi Shinohara
IEEE International Conference on Microelectronic Test Structures 2017.06
Analysis and reduction of SRAM PUF Bit Error Rate
Hirofumi Shinohara, Baikun Zheng, Yanhao Piao, Bo Liu, Shiyu Liu
2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 2017.06
Jing Wang, Li Ding, Qiang Li, Hirofumi Shinohara, Yasuaki Inoue
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E100A ( 5 ) 1145 - 1155 2017.05
Correlation between static random access memory power-up state and transistor variation
Takeuchi, Kiyoshi, Mizutani, Tomoko, Saraya, Takuya, Shinohara, Hirofumi, Kobayashi, Masaharu, Hiramoto, Toshiro
JAPANESE JOURNAL OF APPLIED PHYSICS 56 ( 4 ) 2017.04
Parallel programmable nonvolatile memory using ordinary static random access memory cells
Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Hirofumi Shinohara, Masaharu Kobayashi, Toshiro Hiramoto
JAPANESE JOURNAL OF APPLIED PHYSICS 56 ( 4 ) 2017.04
Design of a Luenberger observer based sensorless multi-loop control for boost converters
Xutao Li, Minjie Chen, Shinohara Hirofumi, Yoshihara Tsutomu
International Conference on Electronics, Information, and Communications, ICEIC 2016 2016.09
A 3.5 ppm/°C 0.85V bandgap reference circuit without resistors
Jing Wang, Qiang Li, Li Ding, Hirofumi Shinohara, Yasuaki Inoue
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E99A ( 7 ) 1430 - 1437 2016.07
Design of a Low-Order Sensorless Controller by Robust H infinity Control for Boost Converters
Xutao Li, Minjie Chen, Hirofumi Shinohara, Tsutomu Yoshihara
JOURNAL OF POWER ELECTRONICS 16 ( 3 ) 1025 - 1035 2016.05
Yasue Yamamoto, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara
JAPANESE JOURNAL OF APPLIED PHYSICS 55 ( 4 ) 2016.04
Design of a Sensorless Controller Synthesized by Robust H infinity Control for Boost Converters
Xutao Li, Minjie Chen, Hirofumi Shinohara, Tsutomu Yoshihara
IEICE TRANSACTIONS ON COMMUNICATIONS E99B ( 2 ) 356 - 363 2016.02
Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto, Hirofumi Shinohara
2016 INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES (ICMTS) 2016-May 130 - 134 2016
An Output Capacitor-less Low Dropout Regulator with Quick-Responding Circuits
Chunxu Zhang, Jie Mei, Hirofumi Shinohara, Tsutomu Yoshihara
2015 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) 51 - 52 2015
AC Direct Multiple-string LED Driver with Low THD and Minimum Components
Yutsung Yeh, Minjie Chen, Xutao Li, Hirofumi Shinohara, Tsutomu Yoshihara
2015 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) 117 - 118 2015
Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Hirofumi Shinohara, Toshiaki Iwamatsu, Hidekazu Oda, Nobuyuki Sugii, Toshiro Hiramoto
JAPANESE JOURNAL OF APPLIED PHYSICS 53 ( 4 ) 2014.04
Extremely low power digital and analog circuits
Hirofumi Shinohara
IEICE Transactions on Electronics E97-C ( 6 ) 469 - 475 2014
A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure
S. Yoshimoto, S. Miyano, M. Takamiya, H. Shinohara, H. Kawaguchi, M. Yoshimoto
Proceedings of the Custom Integrated Circuits Conference 2013.11
M. Nomura, A. Muramatsu, H. Takeno, S. Hattori, D. Ogawa, M. Nasu, K. Hirairi, S. Kumashiro, S. Moriwaki, Y. Yamamoto, S. Miyano, Y. Hiraku, I. Hayashi, K. Yoshioka, A. Shikata, H. Ishikuro, M. Ahn, Y. Okuma, X. Zhang, Y. Ryu, K. Ishida, M. Takamiya, T. Kuroda, H. Shinohara, T. Sakurai
IEEE Symposium on VLSI Circuits, Digest of Technical Papers 2013.09
M. Nomura, A. Muramatsu, H. Takeno, S. Hattori, D. Ogawa, M. Nasu, K. Hirairi, S. Kumashiro, S. Moriwaki, Y. Yamamoto, S. Miyano, Y. Hiraku, I. Hayashi, K. Yoshioka, A. Shikata, H. Ishikuro, M. Ahn, Y. Okuma, X. Zhang, Y. Ryu, K. Ishida, M. Takamiya, T. Kuroda, H. Shinohara, T. Sakurai
Digest of Technical Papers - Symposium on VLSI Technology 2013.09
Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 21 ( 6 ) 1175 - 1179 2013.06
Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
IEEE Journal of Solid-State Circuits 48 1986 - 1994 2013.05
Shinji Miyano, Shinichi Moriwaki, Yasue Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Hirofumi Shinohara
IEEE JOURNAL OF SOLID-STATE CIRCUITS 48 ( 4 ) 924 - 931 2013.04
Variation-aware subthreshold logic circuit design
Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
Proceedings of International Conference on ASIC 2013
Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature
Ryo Takahashi, Hidehiro Takata, Tadashi Yasufuku, Hiroshi Fuketa, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 59 ( 12 ) 918 - 921 2012.12
Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
Proceedings of the Custom Integrated Circuits Conference 2012.11
Koji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
Digest of Technical Papers - IEEE International Solid-State Circuits Conference 55 486 - 487 2012
Tadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai
2012 13TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED) 586 - 591 2012
S. Moriwaki, Y. Yamamoto, A. Kawasumi, T. Suzuki, S. Miyano, T. Sakurai, H. Shinohara
IEEE Symposium on VLSI Circuits, Digest of Technical Papers 60 - 61 2012
Yasue Yamamoto, Atsushi Kawasumi, Shinichi Moriwaki, Toshikazu Suzuki, Shinji Miyano, Hirofumi Shinohara
European Solid-State Circuits Conference 317 - 320 2012
Device-circuit interactions in extremely low voltage CMOS designs (invited)
Hiroshi Fuketa, Tadashi Yasufuku, Satoshi Iida, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
Technical Digest - International Electron Devices Meeting, IEDM 2011.12
Yu Pu, Xin Zhang, Katsuyuki Ikeuchi, Atsushi Muramatsu, Atsushi Kawasumi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 58 ( 5 ) 294 - 298 2011.05
A Closed- form Expression for Estimating Minimum Operating Voltage (V-DDmin) of CMOS Logic Gates
Hiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
PROCEEDINGS OF THE 48TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC) 984 - 989 2011
Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
Proceedings of the International Symposium on Low Power Electronics and Design 163 - 168 2011
Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomura, Makoto Takamiya, Hirofumi Shinohara, Takayasu Sakurai
European Solid-State Circuits Conference 191 - 194 2011
Masanori Kurimoto, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 15 ( 2 ) 2010.02
0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme
Toshikazu Suzuki, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara
ESSCIRC 2010 - 36th European Solid State Circuits Conference 354 - 357 2010
Koji Nii, Yasumasa Tsukamoto, Makoto Yabuuchi, Yasuhiro Masuda, Susumu Imaoka, Keiichi Usui, Shigeki Ohbayashi, Hiroshi Makino, Hirofumi Shinohara
IEEE JOURNAL OF SOLID-STATE CIRCUITS 44 ( 3 ) 977 - 986 2009.03
A 45nm 0.6V Cross-Point 8T SRAM with Negative Biased Read/Write Assist
M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Ohbayashi, Y. Nakase, H. Shinohara
2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS 158 - 159 2009
Analysis Technique for Systematic Variation over Whole Shot and Wafer at 45 nm Process Node
Jingo Nakanishi, Hiromi Notani, Yasunobu Nakase, Hirofumi Shinohara
2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS 585 - 588 2009
On-chip digital I<inf>dn</inf> and I<inf>dp</inf> measurement by 65 nm CMOS speed monitor circuit
H. Notani, M. Fujii, H. Suzuki, H. Makino, H. Shinohara
Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 405 - 408 2008.12
K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, Y. Oda, K. Usui, T. Kawamura, N. Tsuboi, T. Iwasaki, K. Hashimoto, H. Makino, H. Shinohara
IEEE Symposium on VLSI Circuits, Digest of Technical Papers 202 - 203 2008.09
Masanori Kurimoto, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara
Proceedings - Design Automation Conference 884 - 889 2008.09
Analytical model of static noise margin in CMOS SRAM for variation consideration
Hirofumi Shinohara, Koji Nii, Hidetoshi Onodera
IEICE TRANSACTIONS ON ELECTRONICS E91C ( 9 ) 1488 - 1500 2008.09
A large-scale, flip-flop RAM imitating a logic LSI for fast development of process technology
Masako Fujii, Koji Nii, Hiroshi Makino, Shigeki Ohbayashi, Motoshige Igarashi, Takeshi Kawamura, Miho Yokota, Nobuhiro Tsuda, Tomoaki Yoshizawa, Toshikazu Tsutsui, Naohiko Takeshita, Naofumi Murata, Tomohiro Tanaka, Takanari Fujiwara, Kyoko Asahina, Masakazu Okada, Kazuo Tomita, Masahiko Takeuchi, Shigehisa Yamamoto, Hiromitsu Sugimoto, Hirofumi Shinohara
IEICE TRANSACTIONS ON ELECTRONICS E91C ( 8 ) 1338 - 1347 2008.08
Satoshi Ishikura, Marefusa Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi, Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara, Hironori Akamatsu
IEEE JOURNAL OF SOLID-STATE CIRCUITS 43 ( 4 ) 938 - 945 2008.04
A 45-nm bulk CMOS embedded SRAM with improved immunity against process and temperature variations
Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshmobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara
IEEE JOURNAL OF SOLID-STATE CIRCUITS 43 ( 1 ) 180 - 191 2008.01
Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
IEEE JOURNAL OF SOLID-STATE CIRCUITS 43 ( 1 ) 96 - 108 2008.01
Hiroaki Suzuki, Masanori Kurimoto, Tadao Yamanaka, Hidehiro Takata, Hiroshi Makino, Hirofumi Shinohara
Proceedings of the International Symposium on Low Power Electronics and Design 15 - 20 2008
A large scale, flip-flop RAM imitating a logic LSI for fast development of process technology
M. Fujii, K. Nii, H. Makino, S. Ohbayashi, M. Igarashi, T. Kawamura, M. Yokota, N. Tsuda, T. Yoshizawa, T. Tsutsui, N. Takeshita, N. Murata, T. Tanaka, T. Fujiwara, K. Asahina, M. Okada, K. Tomita, M. Takeuchi, H. Shinohara
IEEE International Conference on Microelectronic Test Structures 131 - 134 2007.09
Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinobara
IEEE JOURNAL OF SOLID-STATE CIRCUITS 42 ( 4 ) 820 - 829 2007.04
Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Qkada, Atsushi Ishii, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
Digest of Technical Papers - IEEE International Solid-State Circuits Conference 485 - 617 2007
Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara
Digest of Technical Papers - IEEE International Solid-State Circuits Conference 321 - 606 2007
S. Ishikura, M. Kurumada, T. Terano, Y. Yamagami, N. Kotani, K. Satomi, K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, T. Oashi, H. Makino, H. Shinohara, H. Akamatsu
2007 Symposium on VLSI Circuits, Digest of Technical Papers 254 - 255 2007
A 65 nm SoC embedded 6T-SRAM design for manufacturing with read and write cell stabilizing circuits
S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, M. Igarashi, M. Takeuchi, H. Kawashima, H. Makino, Y. Yamaguchi, K. Tsukamoto, M. Inuishi, K. Ishibashi, H. Shinohara
IEEE Symposium on VLSI Circuits, Digest of Technical Papers 17 - 18 2006.12
A 65 nm ultra-high-density dual-port SRAM with 0.71um2 8T-cell for SoC
K. Nii, Y. Masuda, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, S. Imaoka, M. Igarashi, K. Tomita, N. Tsuboi, H. Makino, K. Ishibashi, H. Shinohara
IEEE Symposium on VLSI Circuits, Digest of Technical Papers 130 - 131 2006.12
A wide lock-in range PLL using self-calibrating technique for processors
Jingo Nakanishi, Hiromi Notani, Hiroshi Makino, Hirofumi Shinohara
2005 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS 285 - 288 2005
Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD 2005 398 - 405 2005
A 64-bit carry look ahead adder using pass transistor BiCMOS gates
Kimio Ueda, Hiroaki Suzuki, Kakutaro Suda, Hirofumi Shinohara, Koichiro Mashiko
IEEE Journal of Solid-State Circuits 31 810 - 817 1996.06
An 8.8-ns 54 × 54-bit multiplier with high speed redundant binary architecture
Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko
IEEE Journal of Solid-State Circuits 31 773 - 782 1996.06
A 1.2GFLOPS NEURAL-NETWORK CHIP EXHIBITING FAST CONVERGENCE
Y KONDO, Y KOSHIBA, Y ARIMA, M MURASAKI, T YAMADA, H AMISHIRO, H SHINOHARA, H MORI
1994 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - DIGEST OF TECHNICAL PAPERS 37 218 - 219 1994
A VOLTAGE COMPENSATED SERIES-GATE BIPOLAR CIRCUIT OPERATING AT SUB-2V
H SATO, K UEDA, N SASAKI, K NIWANO, H SHINOHARA
PROCEEDINGS OF THE 1993 BIPOLAR/BICOMS CIRCUITS AND TECHNOLOGY MEETING 232 - 235 1993
A 8.8-NS 54 X 54-BIT MULTIPLIER USING NEW REDUNDANT BINARY ARCHITECTURE
H MAKINO, Y NAKASE, H SHINOHARA
1993 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN : VLSI IN COMPUTERS & PROCESSORS - PROCEEDINGS 202 - 205 1993
A 20 TERA-CPS ANALOG NEURAL-NETWORK BOARD
M MURASAKI, Y ARIMA, H SHINOHARA
IJCNN '93-NAGOYA : PROCEEDINGS OF 1993 INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS, VOLS 1-3 3 3027 - 3030 1993
A refreshable analog VLSI neural network chip with 400 neurons and 40k synapses
Yutaka Arima, Mitsuhiro Murasaki, Tsuyoshi Yamada, Atushi Maeda, Hirofumi Shinohara
Digest of Technical Papers - IEEE International Solid-State Circuits Conference 1992-February 132 - 133 1992.01
A Refreshable Analog VLSI Neural Network Chip with 400 Neurons and 40K Synapses
Yutaka Arima, Mitsuhiro Murasaki, Tsuyoshi Yamada, Atsushi Maeda, Hirofumi Shinohara
IEEE Journal of Solid-State Circuits 27 ( 12 ) 1854 - 1861 1992
A high density data path generator with stretchable cells
Y. Tsujihashi, H. Matsumoto, S. Kato, H. Nakao, O. Kitada, K. Okazaki, H. Shinohara
Proceedings of the Custom Integrated Circuits Conference 11.3.4 1992
A Flexible Multiport RAM Compiler for Data Path
Hirofumi Shinohara, Kumiko Fujimori, Yoshiki Tsujihashi, Shuichi Kato, Yasutaka Horiba, Noriaki Matsumoto, Hiroomi Nakao, Akiharu Tada
IEEE Journal of Solid-State Circuits 26 ( 3 ) 343 - 349 1991
A flexible multi-port RAM compiler for datapath
Hirofumi Shinohara, Noriaki Matsumoto, Kumiko Fujimori, Shuichi Kato
Proceedings of the Custom Integrated Circuits Conference 1990.12
A 24-b 50-ns Digital Image Signal Processor
Shin-Ichi Nakagawa, Tetsuya Matsumura, Hiroshi Segawa, Masahiko Yoshimoto, Hirofumi Shinohara, Shu-Ichi Kato, Masahiro Hatanaka, Yasutaka Horiba
IEEE Journal of Solid-State Circuits 25 ( 6 ) 1484 - 1493 1990
Shin ichi Nakagawa, Hideyuki Terane, Tetsuya Matsumura, Hiroshi Segawa, Masahiko Yoshimoto, Hirofumi Shinohara, Shu ichi Kato, Atsushi Maeda, Yasutaka Horiba, Hideo Ohira, Yoshi aki Katoh, Mamoru Iwatsuki, Kin ya Tabuchi
Digest of Technical Papers - IEEE International Solid-State Circuits Conference 32 1989.12
A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon
Tomohisa Wada, Toshihiko Hirose, Hirofumi Shinohara, Yuji Kawai, Kojiro Yuzuriha, Yoshio Kohno, Shimpei Kayano
IEEE Journal of Solid-State Circuits 22 ( 5 ) 727 - 732 1987
Submicrometer-Gate MOSFET's by the Use of Focused-Ion-Beam Exposure and a Dry Development Technique
Hiroaki Morimoto, Katsuhiro Tsukamoto, Hirofumi Shinohara, Masahide Inuishi, Tadao Kato
IEEE Transactions on Electron Devices 34 ( 2 ) 230 - 234 1987
25-ns 256K ×1/64K × 4 CMOS SRAM's
Shinpei Kayano, Katsuki Ichinose, Yoshio Kohno, Hirofumi Shinohara, Kenji Anami, Shuji Murakami, Tomohisa Wada, Yuji Kawai, Yoichi Akasaka
IEEE Journal of Solid-State Circuits 21 ( 5 ) 686 - 691 1986
SUBMICRON LITHOGRAPHY USING FOCUSED-ION-BEAM EXPOSURE FOLLOWED BY A DRY DEVELOPMENT.
T. Kato, H. Morimoto, K. Tsukamoto, H. Shinohara, M. Inuishi
Digest of Technical Papers - Symposium on VLSI Technology 72 - 73 1985.12
4. 5NS 256K CMOS SRAM WITH TRI-LEVEL WORD LINE.
Hirofumi Shinohara, Kenji Anami, Katsuki Ichinose, Tomehisa Wada, Yoshio Kohno, Yuji Kawai, Yoichi Akasaka, Shinpei Kayano
Digest of Technical Papers - IEEE International Solid-State Circuits Conference 62 - 63 1985.12
45-NS 256K CMOS STATIC RAM WITH A TRI-LEVEL WORD LINE.
Hirofumi Shinohara, Kenji Anami, Katsuki Ichinose, Tomohisa Wada, Yoshio Kohno, Yuji Kawai, Yoichi Akasaka, Shinpei Kayano
IEEE Journal of Solid-State Circuits SC-20 1985.10
A 45-NS 256K CMOS STATIC RAM WITH A TRI-LEVEL WORD LINE
H SHINOHARA, K ANAMI, K ICHINOSE, T WADA, Y KOHNO, Y KAWAI, Y AKASAKA, S KAYANO
IEEE JOURNAL OF SOLID-STATE CIRCUITS 20 ( 5 ) 929 - 934 1985
A FAST 8K X 8 MIXED CMOS STATIC RAM
H SHINOHARA, K ANAMI, T YOSHIHARA, Y KIHARA, Y KOHNO, Y AKASAKA, S KAYANO
IEEE TRANSACTIONS ON ELECTRON DEVICES 32 ( 9 ) 1792 - 1796 1985
Analysis of parasitic resistance effects in MOS LSI
Kenji Anami, Masahiko Yoshimoto, Hirofumi Shinohara, Osamu Tomisawa, Takao Nakano
Electronics and Communications in Japan (Part I: Communications) 66 ( 10 ) 106 - 113 1983
A DIVIDED WORD-LINE STRUCTURE IN THE STATIC RAM AND ITS APPLICATION TO A 64K FULL CMOS RAM
M YOSHIMOTO, K ANAMI, H SHINOHARA, T YOSHIHARA, H TAKAGI, S NAGAO, S KAYANO, T NAKANO
IEEE JOURNAL OF SOLID-STATE CIRCUITS 18 ( 5 ) 479 - 485 1983
Design Consideration of a Static Memory Cell
Kenji Anami, Masahiko Yoshimoto, Hirofumi Shinohara, Yoshihiro Hirata, Takao Nakano
IEEE Journal of Solid-State Circuits 18 414 - 418 1983.01
SOFT ERROR ANALYSIS OF FULLY STATIC MOS RAM.
Masahiko Yoshimoto, Kenji Anami, Hirofumi Shinohara, Yoshihiro Hirata, Tsutomu Yoshihara, Takao Nakano
Proceedings of the Conference on Solid State Devices 69 - 73 1983.01
PARASITIC RESISTANCE EFFECTS ON STATIC MOS RAM.
H. Shinohara, K. Anami, M. Yoshimoto, Y. Hirata, T. Nakano
Digest of Technical Papers - Symposium on VLSI Technology 106 - 107 1982.12
K ANAMI, M YOSHIMOTO, H SHINOHARA, Y HIRATA, H HARADA, T NAKANO
IEEE JOURNAL OF SOLID-STATE CIRCUITS 17 ( 5 ) 815 - 820 1982
メモリデバイス イメージセンサ
篠原 尋史( Part: Joint author, 2.2 SRAM)
丸善株式会社 2009.12
Quality Improvement of Natural Data for Security by Controling Initial State
Project Year :
A 373 F2 2D Power-Gated EE SRAM Physically Unclonable Function (PUF) with Dark-Bit Detection Technique
Kunyang LIU, Yue MIN, Xuan YANG, Hanfeng SUN, Hirofumi SHINOHARA
IEICE Technical Report ICD
Presentation date: 2019.04
Compensation of Temperature Induced Flipping-Bits in CMOS SRAM PUF by NMOS Body-Bias
Xuanhao ZHANG, Xiang CHEN, Hanfeng SUN, Hirofumi SHINOHARA
IEICE Technical Report-HWS
Presentation date: 2018.08
[Invited Paper] Randon Circuits for Information security
SHINOHARA, Hirofumi [Invited]
IEICE Technical Report ICD
Presentation date: 2018.04
Topics in Fundamental Science and Engineering C
School of Fundamental Science and Engineering
2022 spring semester
Topics in Fundamental Science and Engineering C
School of Fundamental Science and Engineering
2022 spring semester
Topics in Fundamental Science and Engineering C
School of Fundamental Science and Engineering
2022 spring semester
Topics in Fundamental Science and Engineering C
School of Fundamental Science and Engineering
2022 spring semester
Topics in Fundamental Science and Engineering C
School of Fundamental Science and Engineering
2022 spring semester
Dependable Information Systems Research (Doctor's Thesis)
Graduate School of Information, Production and Systems
2022 full year
Dependable Information Systems Research (Fall)
Graduate School of Information, Production and Systems
2022 fall semester
Dependable Information Systems Research (Spring)
Graduate School of Information, Production and Systems
2022 spring semester
Dependable Information Systems C
Graduate School of Information, Production and Systems
2022 spring semester
Dependable Information Systems B
Graduate School of Information, Production and Systems
2022 spring semester
Dependable Information Systems D
Graduate School of Information, Production and Systems
2022 fall semester
Dependable Information Systems A
Graduate School of Information, Production and Systems
2022 fall semester
Graduate School of Information, Production and Systems
2022 spring semester
Dependable Information Systems Research (Master's Thesis)
Graduate School of Information, Production and Systems
2022 full year
Dependable Information Systems
Graduate School of Information, Production and Systems
2022 fall semester
Dependable Information Systems Research (Fall)
Graduate School of Information, Production and Systems
2022 fall semester
Dependable Information Systems Research (Spring)
Graduate School of Information, Production and Systems
2022 spring semester
Graduate School of Information, Production and Systems
2022 fall semester
IEEE ISSCC 国際論文委員
IEEE ISSCC International Technical Program Committee
IEEE VLSI-DAT Technical Program Committee
IEEE VLSI-DAT 論文委員