Copyright © 2020 The Institute of Electronics, Information and Communication Engineers. This paper presents two ultra-low voltage and high performance VCO ICs with two novel transformer-based harmonic tuned tanks. The first proposed harmonic tuned tank effectively shapes the pseudo-square drain-node voltage waveform for close-in phase noise reduction. To compensate the voltage drop caused by the transformer, an improved second tank is proposed. It not only has tuned harmonic impedance but also provides a voltage gain to enlarge the output voltage swing over supply voltage limitation. The VCO with second tank exhibits over 3 dB better phase noise performance in 1/f2 region among all tuning range. The two VCO ICs are designed, fabricated and measured on wafer in 45-nm SOI CMOS technology. With only 0.3 V supply voltage, the proposed two VCO ICs exhibit best phase noise of -123.3 and -127.2 dBc/Hz at 10 MHz offset and related FoMs of -191.7 and -192.2 dBc/Hz, respectively. The frequency tuning ranges of them are from 14.05 to 15.14 GHz and from 14.23 to 15.68 GHz, respectively.

© 1963-2012 IEEE. A wideband LC-VCO IC with an Inversion-MOS (IMOS)-based novel varactor is proposed in this article. The novel varactor that consists of an IMOS and a fixed metal-insulator-metal (MIM) capacitor is able to provide a continuous tuning range with a single analog control voltage. The proposed VCO IC is designed, fabricated, and fully evaluated on the wafer in 40-nm CMOS SOI. The proposed wideband VCO IC has exhibited a tuning range of 40.3% from 4.14 to 6.23 GHz and a measured FoMT of-197.3 dBc/Hz under a supply voltage of only 0.34 V.

© 2020 IEEE. Recently reported CMOS power amplifier ICs for microwave and millimeter-wave communication systems such as 5G are summarized and reviewed in this paper. Stacked-FETs are widely utilized to increase the output power and to conquer low breakdown voltage issues. In addition, adaptive bias and load circuits are fully described to improve the linearity and back-off efficiency of the power amplifier ICs in this paper.

Copyright © 2020 The Institute of Electronics, Information and Communication Engineers. This paper presents a 28-GHz-band highly linear stacked- FET power amplifier (PA) IC. A 4-stacked-FET structure is employed for high output power considering the low breakdown voltage of scaled MOSFET transistors. A novel adaptive bias circuit is proposed to dynamically control the gate-to-source bias voltage for amplification MOSFETs. The novel adaptive bias allows the PA to attain high linearity with high back-off efficiency. In addition, the third-order intermodulation distortion (IM3) is improved by a multi-cascode structure. The PA IC is designed, fabricated and fully tested in 56-nm SOI CMOS technology. At a supply voltage of 4 V, the PA IC has achieved an output power of 20.0 dBm with a PAE as high as 38.1% at the 1-dB gain compression point (P1dB). Moreover, PAEs at 3-dB and 6-dB back-off from P1dB are 36.2% and 28.7%, respectively. The PA IC exhibits an output third-order intercept point (OIP3) of 25.0 dBm.

© 2019 IEEE. This paper presents a wideband excellent FoMT LC-VCO IC with a novel varactor controlled by a single tuning voltage. The novel varactor includes an Inversion-MOS (IMOS) and an MIM capacitor to widen the capacitance variation. The proposed wideband VCO IC is designed, fabricated and fully evaluated on wafer in 40-nm SOI CMOS. The proposed VCO IC has a completely continuous frequency tuning range from 4.14 GHz to 6.23 GHz (40.3 %) and a-131.0-dBc/Hz measured phase noise at 10-MHz offset frequency from the oscillation frequency of 4.14 GHz. Moreover, the VCO IC has exhibited a measured FoMT of-197.3 dBc/Hz under a 0.34-V supply voltage.

© 2019 IEEE. This paper presents a 26 GHz band high efficiency power amplifier (PA) IC with adaptively controlled load and bias conditions. An adaptively controlled load matching circuit cooperating with an adaptive bias circuit is proposed to achieve a high efficiency PA IC in a broad range of input power. The chip of PA IC is fabricated using 40-nm silicon on insulator (SOI) CMOS process and evaluated on wafer. The fabricated PA IC has shown a peak PAE of 40.2% and a saturation output power (Psat) of 20.5 dBm with a 4.0 V applied voltage on Vdd at 26GHz. A PAE of over 35% at an input power between-2 dBm and 7 dBm has been realized.

© 2019 IEEE. This paper presents a high efficiency linear stacked FET power amplifier (PA) IC for 5G wireless communication systems. An adaptive bias circuit is used to enhance linearity and back-off efficiency. In addition, third-order trans-conductance component (gm3) is cancelled by multi-cascode structure. The PA IC is designed, fabricated and fully evaluated in 56-nm SOI CMOS. At a supply voltage of 4 V, the PA IC has exhibited an output power of 20.0 dBm and a PAE of 38.1% at 1-dB gain compression point (P1dB). The PAEs at 3 dB and 6 dB back-off from P1dB are 36.2 % and 28.7 %, respectively. The output IP3 of 25.0 dBm is obtained.

© 2019 IEEE. A low-supply-voltage 15-GHz-band LC-VCO IC is presented in this paper to improve the phase noise and FoM performance. The proposed VCO IC adopts a drain harmonic tuned filter and an LC bias circuit to realize high load impedance at the third harmonics and to amplify carrier signal for improving the phase noise performance. The LC-VCO IC is designed, fabricated and fully evaluated on wafer in 40-nm SOI CMOS. The fabricated VCO IC has exhibited a measured phase noise of -132.0 dBc/Hz at 10-MHz offset frequency from the 15.58 GHz carrier frequency and a measured FoMT of -197.5 dBc/Hz with a supply voltage of 0.45 V.

© 2018 IEICE This paper presents a high efficiency compact Doherty power amplifier (PA) with a novel harmonics termination for handset applications using a GaAs/InGaP heterojunction bipolar transistor (HBT) process. The novel harmonic termination circuit effectively reduces the insertion loss of the matching circuit with compact size. The Doherty PA adopts a lumped-element transformer which consists of metal insulator metal (MIM) capacitors on Silicon substrate, a bonding-wire inductor and short micro-strip lines on printed circuit board (PCB). The fabricated PA has exhibited an average output power of 25.5 dBm and a power added efficiency (PAE) as high as 50.1% under a 10MHz band width quadrature phase shift keying (QPSK) 6.16 dB peak-to-average-power-ratio (PAPR) LTE signal. The IC die size is 1mm by 1mm. The input and output Doherty transformer areas are 0.5 mm by 1.0 mm and 0.7 mm by 0.7 mm, respectively.

© 2018 IEICE A 16-GHz-band low-power and low-phase-noise PMOS VCO IC is presented in 40-nm SOI CMOS. The VCO IC includes a cross-coupled PMOS pair, an LC bias circuit, drain resistors, an LC tank circuit and novel feedback circuit. The feedback circuit which consists of a PMOS transistor, a resistor and a capacitor realizes robust start-up and low-power Class-C operation in the steady-state. The VCO IC is designed, fabricated and fully evaluated on wafer. The VCO IC has exhibited a measured phase noise of 㸫131.0 dBc/Hz at 10-MHz offset frequency from the 16.05 GHz carrier frequency with a supply voltage of only 0.43 V. The measured FOM is 㸫191.2 dBc/Hz.

© 2019 The Institute of Electronics, Information and Communication Engineers. This paper presents high efficiency Class-E and compact Doherty power amplifiers (PAs) with novel harmonics termination for handset applications using a GaAs/InGaP heterojunction bipolar transistor (HBT) process. The novel harmonics termination circuit effectively reduces the insertion loss of the matching circuit, allowing a device with a compact size. The Doherty PA uses a lumped-element transformer which consists of metal-insulator-metal (MIM) capacitors on an IC substrate, a bonding-wire inductor and short micro-strip lines on a printed circuit board (PCB). The fabricated Class-E PA exhibits a power added efficiency (PAE) as high as 69.0% at 1.95 GHz and as high as 67.6% at 2.535 GHz. The fabricated Doherty PA exhibits an average output power of 25.5 dBm and a PAE as high as 50.1% under a 10-MHz band width quadrature phase shift keying (QPSK) 6.16-dB peak-to-average-power-ratio (PAPR) LTE signal at 1.95 GHz. The fabricated chip size is smaller than 1 mm2. The input and output Doherty transformer areas are 0.5 mm by 1.0 mm and 0.7 mm by 0.7 mm, respectively.

Copyright © 2019 The Institute of Electronics. This paper presents two ultra-low voltage and high performance VCO ICs with novel harmonic tuned LC tank which provides different harmonic impedance and shapes the pseudo-square drain voltage waveform of transistors. In the novel tank, two additional inductors are connected between the drains of the cross-coupled pMOSFETs and the conventional LC tank, and they effectively decrease second harmonic load impedance and increase third harmonic load impedance of the transistors. In this paper, the novel harmonic tuned LC tank is applied to two different structure VCOs. These two VCOs exhibit over 2 dB better phase noise performance than conventional LC tank VCOs among all tuning range. The conventional and proposed VCO ICs are designed, fabricated and measured on wafer in 45-nm SOI CMOS technology. With novel harmonic tuned LC tank, the novel two VCOs exhibit measured best phase-noise of −125.7 and −129.3 dBc/Hz at 10 MHz offset and related FoM of −190.2 and −190.5 dBc/Hz at a supply voltage of 0.3 V and 0.35 V, respectively. Frequency tuning range of the two VCOs are from 13.01 to 14.34 GHz and from 15.02 to 16.03GHz, respectively.

© 2019 by the authors. Licensee MDPI, Basel, Switzerland. This paper presents a 2.5-GHz low-voltage, high-efficiency CMOS power amplifier (PA) IC in 0.18-µm CMOS technology. The combination of a dual-switching transistor (DST) and a third harmonic tuning technique is proposed. The DST effectively improves the gain at the saturation power region when the additional gain extension of the secondary switching transistor compensates for the gain compression of the primary one. To achieve high-efficiency performance, the third harmonic tuning circuit is connected in parallel to the output load. Therefore, the flattened drain current and voltage waveforms are generated, which in turn reduce the overlapping and the dc power consumption significantly. In addition, a 0.5-V back-gate voltage is applied to the primary switching transistor to realize the low-voltage operation. At 1 V of supply voltage, the proposed PA has achieved a power added efficiency (PAE) of 34.5% and a saturated output power of 10.1 dBm.

© 2018 European Microwave Association - EuMA. A high efficiency linear power amplifier (PA) IC is presented for 14 GHz-band wireless communication systems. A novel adaptive bias circuit with four-stacked MOSFET structure is proposed to enhance both the linearity and efficiency of the PA IC over the wide input power range. The PA IC is designed, fabricated and fully tested in 56-nm SOI CMOS. In linear mode, the PA IC has exhibited an output P1dB of 20.1 dBm at 14 GHz and a supply voltage of 4.0 V. The measured PAE at P1dB is as high as 40.1%. Moreover, the peak PAE of 41.6% is achieved in efficient mode.

© 2018 European Microwave Association - EuMA. This paper presents a 14-GHz band ultra-low-power low-phase-noise VCO IC with a novel harmonic tuned LC tank consisting of a conventional LC tank and additional series inductors. The additional inductor is connected between the drain of the cross-coupled pMOSFET and the conventional LC tank circuit to adjust the harmonic impedance and to shape the drain voltage waveform rectangular. The adjusted load impedance improves the phase noise of the VCO IC. The conventional and proposed VCOs are designed, fabricated and fully measured on-wafer in 56-nm SOI CMOS technology. The fabricated VCO IC has exhibited a measured phase-noise of - 125.7 dBc/Hz at 10 MHz offset from the 13.46 GHz carrier frequency at a supply voltage of only 0.3 V. The power consumption of the VCO IC core is 0.63 mW and the FoM is - 190.2 dBc/Hz.

© 2018 IEEE. An X-band voltage-controlled oscillator (VCO) IC is presented in this paper for low voltage operation. The LC-VCO IC consists of a cross-coupled pMOSFET pair, an LC tank circuit and buffer amplifiers. The LC-VCO IC is designed, fabricated and fully evaluated on-wafer using 56-nm SOI CMOS technology. The fabricated VCO IC has exhibited a measured phase noise of-119.02 dBc/Hz at 5 MHz offset from the 9.8 GHz carrier frequency at an operation voltage of only 0.5 V.

© 2017 IEEE. All rights reserved. This paper presents a highly linear 28-GHz band SOI CMOS power amplifier with an adaptive bias circuit for cascode MOSFET for next generation wireless communication. The power amplifier consists of a cascode MOSFET, the adaptive bias circuit and the input and output matching circuits. The power amplifier has exhibited a simulated output P1dB (1-dB gain compression point) of 19.2 dBm and a PAE of 39.0 %.

This paper presents a novel 18-GHz band 0.5 V Class-C pMOSFET LC-VCO IC. The LC-VCO IC consists of an oscillator core circuit with a cross-coupled pMOSFETs and an LC bias circuit, an amplitude feedback circuit for realizing Class-C operation and buffer amplifiers. The VCO IC starts to oscillate in Class AB mode and enters Class C mode in the steady-state by changing the gate bias voltage. Since the LC bias circuit increases the current amplitude of the VCO and Class-C operation prevents the pMOSFETs from entering into the deep-triode region, the novel VCO circuit topology is effective in improving the phase noise. The low-power LC biased VCO IC is designed, fabricated and fully evaluated on-wafer in 56-nm SOI CMOS technology. The fabricated VCO IC has exhibited a measured phase noise of -117.6 dBc/Hz at 5 MHz offset from the 18.88 GHz carrier frequency with a supply voltage of only 0.5-V. The power consumption of VCO core is 2.56 mW and that of the feedback loop is only 0.046 mW.

© 2017 IEEE. A DC-50 GHz Single-Pole Double-Throw (SPDT) switch IC is designed, fabricated and fully evaluated on wafer in 40-nm SOI CMOS. The insertion loss of the SPDT switch IC is 0.99 dB at 20 GHz and 1.68 dB at 40 GHz, respectively. From 100 MHz to 50 GHz, the measured isolation is better than 15.8 dB. The input-referred 1-dB compression point (P1dB) is over 20 dBm at 10 GHz.

In this paper, a second harmonic filtering technique is presented for improvement of phase noise performance of a Class-C LC-VCO IC. The second harmonic filter is employed to terminate the output port of the LC-VCO in low impedance at second harmonic frequency, which mainly prevents the noise modulated by the transistor nonlinearities. In addition, since the impedance of the second harmonic filter becomes capacitive at the fundamental frequency, the phase-noise performance is improved. Class-C operation is also effective for less power and better phase-noise performance. The LC-VCO IC was fabricated and evaluated in 130-nm SiGe BiCMOS technology. The LC-VCO IC has presented a measured phase noise of-118.1 dBc/Hz at 5 MHz offset from the 15.2 GHz carrier frequency with a dc power consumption of about 2.25 mW.

A high efficiency broadband power amplifier IC is proposed for wireless communication systems. The power amplifier IC integrates an adaptive bias circuit which can adjust the collector current of SiGe HBT under large signal operation to improve the efficiency and temperature performance. The power amplifier IC is designed, fabricated and fully measured in 130-nm SiGe BiCMOS. The fabricated power amplifier IC has exhibited an output power of 14.6 dBm with a PAE of 43.8 % at a supply voltage of 1.4 V at 26 GHz. In addition, the power amplifier IC has an output power of over 12 dBm with a PAE of over 31.1 % from 20 to 30 GHz.

A high efficiency broadband power amplifier IC is proposed for wireless communication systems. The power amplifier IC integrates an adaptive bias circuit which can adjust the collector current of SiGe HBT under large signal operation to improve the efficiency and temperature performance. The power amplifier IC is designed, fabricated and fully measured in 130-nm SiGe BiCMOS. The fabricated power amplifier IC has exhibited an output power of 14.6 dBm with a PAE of 43.8 % at a supply voltage of 1.4 V at 26 GHz. In addition, the power amplifier IC has an output power of over 12 dBm with a PAE of over 31.1 % from 20 to 30 GHz.

In this paper, a W-band (80 GHz) sub-harmonic mixer (SHM) IC is designed, fabricated and measured in 130-nm SiGe BiCMOS technology. The presented SHM IC makes use of a common emitter common collector transistor pair structure with a bottom-LO-configuration to decrease the LO power requirement and a tail current source to flatten the conversion gain. On-chip Marchand balun is designed for W-band on-wafer measurements. The SHM IC presented in this paper has exhibited a conversion gain of 3.9 dB at 80 GHz RF signal with an LO power of only (-)7 dBm at 39.5 GHz. The mixer core consumes only 0.68 mA at a supply voltage of 3.3 V.

A novel 2.2-GHz-band ultra-low-voltage Class-C PMOS VCO IC with negative reference and amplitude feedback loop is proposed. The negative reference initially adapts a sufficient bias for the LC-VCO circuit to ensure a robust oscillation start-up. The feedback loop then adaptively controls the bias condition of LC-VCO for Class-C operation in steady-state. The reliability of the feedback loop is enhanced over PVT variation. The Class-C VCO IC has been designed, fabricated and fully evaluated in 180-nm CMOS technology. The fabricated VCO IC exhibits a measured phase noise of 113.2 dBc/Hz at 1 MHz offset from the 2.2 GHz carrier frequency with a supply voltage of only 0.3 V.

A novel 2.2-GHz-band ultra-low-voltage Class-C PMOS VCO IC with negative reference and amplitude feedback loop is proposed. The negative reference initially adapts a sufficient bias for the LC-VCO circuit to ensure a robust oscillation start-up. The feedback loop then adaptively controls the bias condition of LC-VCO for Class-C operation in steady-state. The reliability of the feedback loop is enhanced over PVT variation. The Class-C VCO IC has been designed, fabricated and fully evaluated in 180-nm CMOS technology. The fabricated VCO IC exhibits a measured phase noise of 113.2 dBc/Hz at 1 MHz offset from the 2.2 GHz carrier frequency with a supply voltage of only 0.3 V.

This paper presents a low-voltage and low phase noise LC-VCO IC with simplified noise filtering in 180-nm CMOS technology. The novel VCO IC includes a cross-coupled pMOSFET pair, an LC resonator, buffer amplifiers and a tail inductor for noise filtering. The novel and conventional LC-VCO ICs are designed, fabricated and fully tested on wafer. At a power supply voltage of only 0.5 V, the novel VCO IC has exhibited a phase noise of -119.4 dBc/Hz at 1 MHz offset from the 2.25 GHz carrier frequency, which is 2.6 dB better than the conventional one.

A 30-GHz band power amplifier (PA) IC is designed, fabricated and fully tested in 120-nm SiGe HBT process. The impedances of the output matching network are optimized at both the fundamental and second harmonic for a high power added efficiency (PAE). At a supply voltage of 1.4 V, the PA IC has exhibited a measured output P1dB of 10.8 dBm, a peak PAE of 32.4%, and a small-signal gain of 9.1 dB at 30 GHz.

A 30-GHz band Single-Pole Double-Throw (SPDT) switch IC is designed, fabricated and fully evaluated in 120-nm SiGe heterojunction bipolar transistor (HBT) process. The SPDT switch IC employs diode-connected HBTs and LC resonant circuits to improve the insertion loss and isolation. The fabricated SPDT switch IC has exhibited an insertion loss of 3.3 dB, an isolation of 21.8 dB and an input-referred 1-dB compression point (P1dB) of 16 dBm at 32 GHz.

A novel LC bias topology is proposed to improve the phase noise of VCO IC for ultra-low-voltage applications. The LC bias circuit works as an impedance transformation network, which improves the phase noise of VCO by delivering higher power to the gates of the cross-coupled transistors. A 2-GHz-band ultra-low-voltage VCO IC with the novel LC bias circuit has been designed, fabricated and fully evaluated in 180-nm CMOS technology. The fabricated novel VCO IC has exhibited a measured phase noise of -126.4 dBc/Hz at 1 MHz offset frequency from the 2.03 GHz carrier frequency with a supply voltage of 0.5 V.

In this paper, a second harmonic filtering technique is presented for improvement of phase noise performance of a Class-C LC-VCO IC. The second harmonic filter is employed to terminate the output port of the LC-VCO in low impedance at second harmonic frequency, which mainly prevents the noise modulated by the transistor nonlinearities. In addition, since the impedance of the second harmonic filter becomes capacitive at the fundamental frequency, the phase noise performance is improved. Class-C operation is also effective for less power and better phase-noise performance. The LC-VCO IC was fabricated and evaluated in 130-nm SiGe BiCMOS technology. The LC-VCO IC has presented a measured phase noise of -118.1 dBc/Hz at 5 MHz offset from the 15.2 GHz carrier frequency with a de power consumption of about 2.25 mW.

A novel LC bias topology is proposed to improve the phase noise of VCO IC for ultra-low-voltage applications. The LC bias circuit works as an impedance transformation network, which improves the phase noise of VCO by delivering higher power to the gates of the cross-coupled transistors. A 2-GHz-band ultra-low-voltage VCO IC with the novel LC bias circuit has been designed, fabricated and fully evaluated in 180-nm CMOS technology. The fabricated novel VCO IC has exhibited a measured phase noise of -126.4 dBc/Hz at 1 MHz offset frequency from the 2.03 GHz carrier frequency with a supply voltage of 0.5 V.

This paper presents a novel CMOS bias topology serving as not only a bias circuit but also an adaptive linearizer for SiGe HBT power amplifier (PA) IC. The novel bias circuit can well keep the base-to-emitter voltage (V-be) of RF amplifying HBT constant and adaptively increase the base current (I-b) with the increase of the input power. Therefore, the gain compression and phase distortion performance of the PA is improved. A three-stage 5-GHz band PA IC with the novel bias circuit for WLAN applications is designed and fabricated in IBM 0.35 mu m SiGe BiCMOS technology. Under 54Mbps OFDM signal at 5.4 GHz, the PA IC exhibits a measured small-signal gain of 29 dB, an EVM of 0.9% at 17 dBm output power and a DC current consumption of 284 mA.

This paper presents a novel CMOS bias topology serving as not only a bias circuit but also an adaptive linearizer for SiGe HBT power amplifier (PA) IC. The novel bias circuit can well keep the base-to-emitter voltage (Vbe) of RF amplifying HBT constant and adaptively increase the base current (Ib) with the increase of the input power. Therefore, the gain compression and phase distortion performance of the PA is improved. A three-stage 5-GHz band PA IC with the novel bias circuit for WLAN applications is designed and fabricated in IBM 0.35 μm SiGe BiCMOS technology. Under 54 Mbps OFDM signal at 5.4 GHz, the PA IC exhibits a measured small-signal gain of 29 dB, an EVM of 0.9% at 17 dBm output power and a DC current consumption of 284 mA.

This paper presents a broadband single-pole double throw (SPDT) switch IC in a 180-nm CMOS process. Floating body technique and stacked nMOSFETs are utilized to improve the power handling capability and isolation performance. The fabricated SPDT switch IC has exhibited an input referred 0.5 dB compression point of 21.8 dBm, an isolation of 42.4 dB and an insertion loss of 1.2 dB for transmit mode at an operation frequency of 5.0 GHz. The SPDT switch IC has an insertion loss of 2.1 dB and a return loss of 10.6 dB for receive mode at 5.0 GHz.

This paper presents a sub-harmonic mixer IC design for W-band automotive radar applications in 130-nm SiGe BiCMOS technology. The mixer makes use of a Common Emitter Common Collector Transistor Pair (CECCTP) structure mixer core with a Marchand balun for the W-band on-wafer measurement. The balun achieves a measured amplitude imbalanced of less than 0.9 dB and a phase imbalance of less than 2.5 degrees in a frequency range from 20 GHz to 66 GHz. The sub-harmonic mixer IC exhibits a conversion gain of 3.8 dB at 80 GHz with an LO power of 0 dBm at 39.5 GHz. And the mixer core only consumes 0.42 mA with a supply voltage of 2.5 V.

In this paper, a 2.5-GHz band fully integrated high efficiency CMOS power amplifier IC with third harmonic termination technique for low supply voltage was designed, fabricated and fully evaluated in 0.18-mu m CMOS technology. Since the proposed third harmonic termination technique effectively increases the PAE by reducing the rms drain current, the total dc power consumption is diminished. To control a threshold voltage for low supply voltage application, a 0.5-V back-gate voltage is applied for the transistor. The power amplifier IC exhibits an output power of 8.5 dBm and a peak PAE of 31.1 % at a supply voltage of only 0.75-V.

An ultra-low-voltage low phase noise LC-VCO IC has been demonstrated using 180-nin CMOS technology. The LC-VCO IC includes a cross-coupled pMOSFET pair, a symmetric three-port spiral inductor, MOS varactors and buffer amplifiers. The LC-VCO IC is designed, fabricated and fully tested on wafer. The VCO IC exhibits a phase noise of -118.9 dBc/Hz at 1 MHz offset front the 2.29 GHz carrier at a supply voltage of only 0.5 V. Moreover, minimum operation voltage of only 0.25 V has been achieved.

This paper presents a broadband single-pole double-throw (SPDT) switch IC in a 180-nm CMOS process. Back-gate voltage injection and floating body technique are utilized to improve the power handling capability, insertion loss and isolation performance, simultaneously. The fabricated SPDT switch IC has exhibited an input referred 0.3-dB compression point of 21.0 dBm, an isolation of 42.7 dB and an insertion loss of 1.1 dB for transmit mode at an operation frequency of 5.0 GHz.

This paper presents a fully integrated low-voltage CMOS power amplifier (PA) IC for 2.5-GHz band short range wireless applications. The amplifier IC is designed, fabricated and fully evaluated in 180-nm CMOS technology. To realize high efficiency performance, the parallel switching transistor is proposed and combined with third harmonic tuning technique. In addition, for low voltage operations, the positive body bias is injected to the main switching transistor. The proposed CMOS PA IC has exhibited a P1dB of 8.0 dBm, a saturated output power of 10.1 dBm and a peak PAE of 34.5 % at a supply voltage of 1.0 V.

This paper presents a novel sub-harmonic mixer (SHM) IC design for W-band automotive applications in 130-nm SiGe BiCMOS technology. The SHM makes use of a Common Emitter Common Collector Transistor Pair (CECCTP) structure with bottom-LO-configuration. On-chip Marchand balun is utilized for W-band on-wafer measurement. The novel SHM exhibits a conversion gain of 3.9 dB at 80 GHz RF signal with an LO power of -7 dBm at 39.5 GHz. The mixer core consumes only 0.68 mA with a supply voltage of 3.3 V.

This paper presents a fully integrated low-voltage CMOS power amplifier (PA) IC for 2.5-GHz band short range wireless applications. The amplifier IC is designed, fabricated and fully evaluated in 180-nm CMOS technology. To realize high efficiency performance, the parallel switching transistor is proposed and combined with third harmonic tuning technique. In addition, for low voltage operations, the positive body bias is injected to the main switching transistor. The proposed CMOS PA IC has exhibited a P1dB of 8.0 dBm, a saturated output power of 10.1 dBm and a peak PAE of 34.5 % at a supply voltage of 1.0 V.

A novel 2.4 GHz-band 0.5-V Class-C PMOS VCO IC with an amplitude feedback loop is proposed. The amplitude feedback loop circuit consists of a detector, an inverter and a bias control circuit. The feedback loop automatically changes the bias of LC-VCO and shifts the oscillation mode from initial Class-AB to Class-C in steady-state. The Class-C VCO IC is designed, fabricated and fully evaluated in 180-nm CMOS technology. The fabricated VCO IC has exhibited a measured phase noise of -117.4 dBc/Hz at 1 MHz offset from the 2.25 GHz carrier frequency with a supply voltage of only 0.5-V.

A Class-C voltage-control-oscillator (VCO) IC with an amplitude feedback loop for ultra-low-voltage application is proposed. The Class-C VCO consists of an LC-VCO circuit and an amplitude feedback loop to shift LC-VCO bias condition from initial Class-AB start-up to steady Class-C low current oscillation. The amplitude feedback loop is formed by a detector and a comparator with low voltage supply. The LC-VCO IC has been designed, fabricated and fully evaluated using 65-nm CMOS technology. The fabricated Class-C VCO IC exhibits a measured phase noise of 111 dBc/Hz at 1 MHz offset from the 2.43 GHz carrier frequency at a supply voltage of only 0.3 V.

A fully integrated class-E power amplifier IC in 180-nm CMOS is presented for 2.5-GHz band short range wireless communication systems. To realize high efficiency with low operation voltage, a class-E amplifier with back gate effect has been designed, fabricated and fully evaluated. The proposed amplifier IC can operate at a supply voltage from 0.5 V to 1.5 V. The amplifier IC exhibits a P1dB of 6.9 dBm and a saturated output power of 10.7 dBm with a maximum drain efficiency of 36.4 % at a 1.0 V power supply.

This paper presents a fully integrated class-E power amplifier IC with body effect to achieve high efficiency and high gain at low supply voltage for 2.5-GHz band short range wireless communication systems. The class-E amplifier IC is designed, fabricated and fully evaluated in 180-nm CMOS. The proposed power amplifier IC exhibits a small-signal gain of 10.8 dB and a saturated output power of 10.8 dBm with a drain efficiency of 35.0 % at a supply voltage of only 1-V.

This paper presents a highly linear 5-GHz band power amplifier IC with integrated novel CMOS active bias circuit in SiGe BiCMOS technology for wireless LAN applications. The power amplifier IC consists of three-stage amplifier, the CMOS active bias circuit for linearizing SiGe HBT and all matching circuits. The power amplifier IC has exhibited a measured output power of 17.0 dBm, an EVM of 0.9 % and a dc current consumption of 284 mA under 54 Mbps OFDM signal at 5.4 GHz.

This paper presents an ultra-wideband and ultra-low-voltage compact power detector IC for microwave and millimeter-wave applications. The power detector circuit includes an nMOSFET differential pair with resistive feedback and a pMOSFET buffer. The power detector IC was designed, fabricated and fully evaluated using Fujitsu 65-nm CMOS technology. The detector IC exhibits an operation frequency from 100 MHz to 44 GHz at an operation voltage of only 0.5 V. In addition, the detector IC exhibits a minimum detectable power of -15 dBm with high linearity.

A compact broadband balun on a silicon substrate is proposed for millimeter-wave applications. By utilizing a novel defected ground structure, it is expected that the balun exhibits an amplitude balance less than 0.5 dB and a phase balance less than 2 degrees in a frequency range from 26 GHz to 80 GHz. The insertion loss is less than 3 dB in the operational frequency band. The balun achieves a bandwidth of 108 % and the area occupies only 0.024 mm(2).

A miniaturized broadband balun IC in 180-nm CMOS is presented for millimeter-wave applications. The balun IC is designed so that high impedance ratio between the even and odd modes is achieved by utilizing Electro-magnetic solver suitable for planer structure. The fabricated balun IC in 180-nm CMOS process occupies only 0.03 mm(2). The balun IC exhibits an amplitude imbalance of less than 0.9 dB and a phase imbalance of less than 2.5 degrees in a frequency range from 20 GHz to 66 GHz.

This paper presents a highly linear 5-GHz band power amplifier IC with integrated novel CMOS active bias circuit in SiGe BiCMOS technology for wireless LAN applications. The power amplifier IC consists of three-stage amplifier, the CMOS active bias circuit for linearizing SiGe HBT and all matching circuits. The power amplifier IC has exhibited a measured output power of 17.0 dBm, an EVM of 0.9 % and a dc current consumption of 284 mA under 54 Mbps OFDM signal at 5.4 GHz.

Fully integrated 80GHz-band and 100GHz-band transceiver ICs using 65nm CMOS technology and on-board antennas for high-speed/short-range wireless communication system are demonstrated. To realize higher speed and lower power consumption than those of a 60GHz-band standard application such as IEEE802.11ad, a simple transceiver architecture with non-coherent amplitude shift keying (ASK) modulation method using W-band (75-110GHz) is adopted. The aggregate 80/100GHz-band transceiver modules demonstrate 23Gbps over 10mm wirelessly with power consumption of 216mW. The developed transceiver modules achieve the highest speed of wireless communications above 60GHz-band and show a potential for future applications of 100Gbps high-speed shortrange communications.

In this paper, a fully integrated Class-E amplifier IC using back-gate voltage injection is designed, fabricated and fully evaluated in 0.18-mu m CMOS technology. The body effect allows to achieve high efficiency under low supply voltage by efficiently controlling threshold voltage and on-resistance of switching transistor, simultaneously. The proposed amplifier IC has exhibited an output power of 11.0 dBm and a PAE of 30.5 % at 1-V supply voltage for 2.5 GHz applications.

An ultra-low-voltage LC-VCO IC has been demonstrated using 130nm CMOS technology. The LC-VCO IC includes a cross-coupled nMOSFET pair, a spiral inductor, MOS varactors and a buffer amplifier. The LC-VCO IC is designed, fabricated and fully evaluated on wafer. The VCO IC exhibits a phase noise of -137 dBc/Hz at 1 MHz offset from the 2.2 GHz carrier at a supply voltage of only 0.5 V.

This paper presents novel sub-harmonic mixer topologies for W-band automotive radar applications in 65nm CMOS technology. Working principle and performance of three kinds of topologies are analyzed and discussed with physical layout and EM simulation. The simulated performance shows a double side band noise figure of 20.8 dB and a voltage conversion gain of -8.7 dB at an RF frequency of 79.0001 GHz and a LO frequency of 39.5 GHz. The dc power consumption is only 10.4μW. © 2013 IEEE.

A novel LC-VCO IC is proposed to achieve low-voltage low-power operation even at a supply voltage below the threshold voltage. The LC-VCO consists of a VCO circuit, a power detector circuit and a comparator circuit. A feedback loop consisting of the power detector and the comparator can control the bias condition of the VCO. The LC-VCO IC has been designed, fabricated and fully evaluated using 65 nm CMOS technology. The fabricated VCO IC exhibits a measured phase noise of -111 dBc/Hz at 1 MHz offset from the 2.43 GHz carrier frequency at an operation voltage of only 0.3 V.

Fully integrated millimeter-wave transceiver ICs using 65nm CMOS technology and on-board antenna for high-speed/short-range wireless communication system are described. To realize high-speed and low power consumption for a mobile application, a simple transceiver architecture with non-coherent amplitude shift keying (ASK) modulation method is adopted. The transceiver ICs are flip-chip bonded on boards and connected with on-board antenna for a simple and low cost transceiver system. The developed transceiver system module demonstrates 5Gbps/3.8Gbps at wireless communication range of 5mm/10mm and power consumption of 79.6mW with a carrier frequency of 71GHz. To our best knowledge, this is the first report of a millimeter-wave, above 60GHz, CMOS transceiver module with on-board antenna for a high-speed/short-range wireless communication system.

In this paper, a CMOS Class-G supply modulation for polar power amplifiers with high average efficiency and low ripple noise is proposed. In the proposed Class-G supply modulation, the parallel supply modulations which are controlled by switch signals are utilized for low power and high power supplies to increase the average efficiency. A low dropout (LDO) is utilized to suppress the delta-modulated noise and provide a low ripple noise power supply. The proposed supply modulation has high efficiency at large output current as the conventional supply modulation, and it also has high efficiency and low ripple noise at the low output current. To verify the effectiveness of the proposed supply modulation, the proposed supply modulation was designed with 0.13 mu m CMOS process. The simulation results show that the proposed supply modulation achieves a maximum efficiency of 85.1%. It achieves an average efficiency of 29.3% and a 7.1% improvement compared with the conventional supply modulations with Class-E power amplifier. The proposed supply modulation also shows an excellent spurious free dynamic range (SFDR) of -73 dBc for output envelope signal.

In this paper, a 5.25GHz linear CMOS power amplifier (PA) with an integrated diode is presented. The proposed technique improves the linearity of the power amplifier by a diode-connected NMOS transistor. The NMOS diode is effective to suppress both the AM-AM distortion and AM-PM distortion. To verify this concept, the power amplifier is simulated with TSMC 0.13-μm CMOS process. With a power supply of 3.3 V, the proposed power amplifier exhibits a maximum IMD improvement of 25 dB with a PAE of 38.2 % at an output P1dB of 19.6 dBm. © 2012 IEEE.

This paper presents a low operation voltage ultrawideband power detector IC for microwave and millimeter-wave applications. The power detector circuit includes an nMOS transistor differential pair with a resistive feedback. The power detector IC was designed and fabricated using TSMC 130 nm CMOS technology. The detector IC exhibits an operation frequency from 100 MHz to 40 GHz at an operation voltage of 0.6 to 1.2 V. The minimum detectable power is -16 dBm at 40 GHz with a dc power consumption of only 0.116 mW. © 2012 IEEE.

In this paper, novel linearization technique is proposed to realize a 5-GHz band linear CMOS power amplifier IC for WLAN application. The novel linearizer which consists of a diode-connected PMOS bias circuit and a PMOS varactor connected in parallel with an NMOS amplifier is effectively to suppress the gain compression and phase distortion of the power amplifier. A CMOS power amplifier IC is designed, fabricated and fully tested using TSMC 0.13-mu m CMOS technology. With these proposed techniques, the measurement results show a third-order IMD improvement of 9 dB over wide output power range and the maximum improvement of 18 dB. The power amplifier IC exhibits an output P1dB of 19.5 dBm and a power gain of 9.5 dB at an operation voltage of 3.3 V.

A balanced push-push frequency doubler has been demonstrated in 0.25-mu m SOI (Silicon on Insulator) SiGe BiCMOS technology operating from 22 GHz 10 29 GHz with high fundamental frequency suppression and high conversion gain. A series LC resonator circuit is connected in parallel with the differential outputs of the doubler core circuit. The LC resonator is effective to improve the fundamental frequency suppression. In addition, the LC resonator works as a matching circuit between the output of the doubler core and the input of the output buffer amplifier, which increases the conversion gain of the whole circuit. A measured fundamental frequency suppression of greater than 46 dBc is achieved at an input power of -10 dBm in the output frequency band of 22-29 GHz. Moreover, maximum fundamental frequency suppression of 66 dBc is achieved at an input frequency of 13 GHz and an input power of -10 dBm. The frequency doubler works at a supply voltage of 3.3 V.

In this paper, a post-linearization technique of cascode CMOS power amplifier is presented. The proposed method adopts two cascode FET, one operates in class AB mode and the other works near class B mode, which absorbs the nonlinear current of third-order intermodulation distortion (IMD). The proposed method is investigated for 5.8 GHz Dedicated Short Range Communication (DSRC) applications, and fabricated by 0.13 μm CMOS process. The measured results show that the proposed power amplifier exhibited a power gain of 11.5 dB, an output power of 1 dB compression point (P1dB) of 17.3 dBm, a power added efficiency (PAE) of 32% at P1dB with a low voltage operation of 2.0 V. The improvement in IMD of 6 dB over large output power range and a maximum improvement of 12 dB were achieved. © 2011 IEEE.

In this paper, a voltage controlled oscillator (VCO) with ultra low dc power consumption and low phase noise is proposed for 2.4 GHz Bluetooth. To reduce the dc power consumption, a novel bias circuit is proposed instead of a conventional tail-current circuit to decrease the supply voltage. In addition, the proposed VCO is designed to operate in sub-threshold region for decreasing the operation current. Thus, the dc power consumption is largely reduced. To improve the phase noise, a modified LC-tank is proposed to suppress the harmonic noise modulation and to prevent the phase noise degradation by the down-converted Flick noise. The LC-VCO is simulated using 0.11 μm CMOS technology. The simulation results show a phase noise of -115dBc/Hz at 1MHz offset from the 2.4 GHz carrier frequency with only 0.35 mW power consumption. © 2010 IEEE.

A balanced frequency doubler has been measured fundamental frequency suppression demonstrated in 0.25-mu m SOI SiGe BiCMOS technology operating from 22GHz to 29GHz with high fundamental frequency suppression and high conversion gain. A LC resonator circuit is designed to improve the suppression and conversion gain. The measured fundamental frequency suppression of greater than 45dBc is achieved at an input power of -9dBm in the 22-29GHz. Moreover, measured maximum conversion gain of 12.6dB is obtained at an input power of -19dBm. The frequency doubler works on 3.3V and doubler core only consumes 7.9mW DC power.

A novel resonant circuit consisting of transformer-based variable inductors and MOS varactors is proposed to implement an ultra-wideband voltage-controlled-oscillator (VCO). The VCO is designed and fabricated using 0.13 mu m CMOS, and fully evaluated on wafer. The VCO IC exhibits a frequency tuning range as high as 92.6 % spanning from 1.2 GHz to 3.27 GHz. The measured phase noise of -120 dBc/Hz at 1 MHz offset from the 3.1 GHz carrier is obtained.

In this paper, a novel wideband amplifier is proposed for 22 - 29 GHz UWB applications in 0.13 um Si CMOS technology. In order to reduce the dc current of the amplifier, a novel current reuse technique is adopted in a cascode CMOS transistor. In addition, a low-pass type feedback circuit for the first stage and an inductive feedback circuit for the second stage are designed to make the bandwidth wider. It is expected that the wideband amplifier exhibits a gain of 11.3 dB +/- 1.2 dB with a dc power consumption as low as 9.8 mW.

In this paper, a novel technique is proposed to improve the phase-noise of an LC-VCO. The LC-VCO includes two series LC second harmonic filters which consist of a spiral inductor and two varactors. The resonant frequency of the series LC filter is tunable with the control voltage, and the resonator largely prevents the noise modulation in the LC-VCO, improving the phase-noise of the LC-VCO with wide frequency range. The LC-VCO is fabricated using 0.13 mu m CMOS technology, and fully evaluated on wafer. The measured phase-noise of - 112dBc/Hz at 1MHz offset from the 15 GHz carrier is obtained.

A novel switched-inductor based resonator is proposed to implement an ultra-wideband VCO. The VCO is designed and fabricated using 0.13 mu m CMOS and fully evaluated on wafer. The measured results show that the proposed VCO has a tuning range as high as 87.6% spanning from 1.81 GHz to 4.63 GHz. The measured phase noise of -124.4 dBc/Hz at 1 MHz offset from the 1.81 GHz carrier is obtained(1).

A fully integrated novel power amplifier (PA) using 130nm CMOS process is presented for Electric Toll Collection (ETC) applications. To obtain good efficiency and high linear gain performance, a novel cascode PA based on a class E PA has been designed, fabricated and fully measured. The proposed PA is a single-ended single-stage amplifier at an operating voltage of only 2 V. The power added efficiency (PAE) of the PA is as high as 42.6% with a gain of 11.4dB at P1dB of 13.4dBm. This CMOS PA includes all matching circuits and biasing circuits, and no external components are required.

A broadband balanced frequency doubler has been fabricated in 0.25-mu m SOI SiGe BiCMOS technology to operate from 22GHz to 30GHz with low input drive power. Its fundamental frequency suppression of better than 30dBc can be achieved by an internal low pass LC filter in the 22-30GHz; moreover, maximum suppression is 47dBc in the operation band. In addition, a pair of SLCC (Series LC Circuit) parallel with the up input can result in high suppression with low input drive power. Maximum conversion gain of -6dB can be obtained in the input drive power as low as -1dBm.

A 5.5-GHz Doherty amplifier using commercial 0.35-mu m SiGe HBT technology is proposed in this article. To improve the linearity, a predistortion using diode linearizer is adopted for biasing the peak amplifier. Moreover, to realize in fully on-chip with circuit reduction, a 90 degrees 3-dB hybrid coupler and quarter-wave transmission lines are implemented by lumped-elements. In this design, 819 mu m(2) HBTs are used for carried and peak amplifiers, respectively, and 26 mu m(2) HBT is used for linearizer. Results verify that the power gain, P(1dB), and power added efficiency (PAE) of the proposed Doherty amplifier at 5.5 GHz are 8.4 dB, 31 dBm, and 30%, respectively. Also, the adjacent channel power ratio (ACPR) and the output signal's spectrum mask are given using the 54Mcps 64QAM modulated signal at 10 MHz offset. (c) 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1554-1558, 2008.

The bow-tie loop printed antenna with high gain and broad beam width for 5.8GHz rectenna application is proposed, analyzed and measured. The high gain of 9.5 dBi can receive more power in a certain power density. And the broad beam width with 90 degrees HPBW (Half Power Beam Width) is able to avoid the precise main beam alignment. The proposed antenna still has the cross polarization level more than 30 dB, and the front-to-back ratio is about -20dB in the broadside direction. The details of the simulated and experimental results for the proposed design are presented and discussed. ©2008 IEEE.

This article presents a compact microstrip meander-line antenna for sensor network applications in the 290 MHz band. The antenna is fed by coplanar waveguide and its dimension is 15 mm x 15 mm x 2 mm. Because of the use of a very high relative permittivity substrate (epsilon(r) = 90) and meander-line structure simultaneously, the side length of the designed antenna is about lambda(g)/12 (lambda(g) is the guided wavelength) so that the circuit size is reduced greatly. Measurements verify that the proposed antenna has bandwidth of 12% at the resonant frequency of 293 MHz. Also the radiation patterns measured at resonance frequencies are very close to omnidirectional in the E-plane. (C) 2007 Wiley Periodicals, Inc.

An ultra-wideband amplifier MMIC has been demonstrated for the Ultra-Wide-Band (UWB) standard with InGaP/GaAs Heterojunction Bipolar Transistor (HBT) technology. The fabricated MMIC chip size is only 0.53 mm by 0.93mm. The amplifier MMIC includes all matching circuits on the chip. This amplifier MMIC is applicable to both a UWB low noise amplifier and a UWB transmitter amplifier by changing the collector current. The operating bias currents are 15 mA for a low noise amplifier and 30 mA for a transmitter amplifier. The collector bias voltage is 3.0 V. The MMIC as a transmitter amplifier exhibits a gain of 16 +/-1 dB and a third-order intercept point at the input (IIP3) of 0 dBm with 6.0 and 6.01 GHz signals with equal amplitude level. As a low noise amplifier, the MMIC exhibits a noise figure of less than 3.7 dB from 3.1 to 10.6 GHz.

A 5-GHz-band highly linear frequency tuning voltage-controlled oscillator (VCO) using 0.35 mu m SiGe BiCMOS technology is presented. The highly linear VCO has a novel resonant circuit that includes two spiral inductors, p-n junction diode varactor units and a voltagelevel- shift circuit. The fabricated VCO exhibits a VCO gain from 224 to 341 MHz/V, giving a Kvco ratio of 1.5, which is less than one-half of that of a conventional VCO. The measured phase noise is -116 dBc/Hz at 1MHz offset at an oscillation frequency of 5.5 GHz. The tuning range is from 5.45 to 5.95 GHz. The de current consumption is 3.4 mA at a supply voltage of 3.0 V.

This paper presents a 0.35-mu m SiCt BiCMOS VCO IC exhibiting a linear VCO gain (Kvco) for 5-GHz band application. To realize a linear Kvco, a novel resonant circuit is proposed. The measured Kvco changes from 224 MHz/V to 341 MHz/V The ratio of the maximum Kvco to the minimum one is 1.5 which is less than one-half of that of a conventional VCO. The VCO oscillation frequency range is from 5.45 GHz to 5.95 GHz, the tuning range is 8.8 % and the do current consumption is 3.4 mA at a supply voltage of 3.0 V The measured phase noise is -116 dBc/Hz at 1MHz offset, which is similar to the conventional VCO.

In this letter, a new multiple-frequency-tuned slot resonator is introduced in coplanar waveguide (CPW) technology. Its equivalent circuit model is built up and its frequency characteristics are explained by employing the equivalent circuit parameters and field analysis. Furthermore, one-dimensional (1-D) and 2-D CPW structures with the proposed slot resonator are designed. Measurements show that the proposed CPW structures with compact size exhibit good multiple-stopband behaviours.

This paper presents an ultra-wideband voltage controlled oscillator (VCO) IC using 0.35 mu m SiGe BiCMOS technology. The VCO IC exhibits an oscillation frequency from 2.67 to 4.37 GHz. To realize the wideband tuning range, a novel resonant circuit is proposed. The novel resonant circuit consists of three NMOS varactor pairs, p-n diodes, two spiral inductors and a control circuit which sequentially applies a control voltage to the NMOS varactor pairs and p-n diode pairs. The novel resonant circuit allows the VCO IC to have the wideband tuning range with a single analog control voltage. The dc current consumption of the VCO is 5.8 mA at a collector voltage of 4.0 V. The VCO has a phase noise of -111 dBc/Hz at 1 MHz offset at an oscillation frequnecy of 4.37 GHz.

One-dimensional (1-D) slot resonator-based electromagnetic bandgap coplanar waveguide (SR-EBG-CPW) is proposed in this Letter. First, the SR-EBG-CPW unit cell is discussed and exhibits bandstop performance without any periodic structure. Then, its circuit model is extracted from the full-wave simulations and the frequency characteristics are explained by employing the equivalent circuit parameters and field analysis. Finally, a miniaturized bandstop filter with SR-EBG-CPW is presented and fabricated. Measurement shows that the designed filter provides good bandstop and slow-wave performances as predicted and has potential applications to compact microwave designs. (c) 2006 Published by Elsevier B.V.

One-dimensional slot resonator-based photonic bandgap for coplanar waveguide (SR-PBG-CPW) is proposed in this paper. The SR-PBG-CPW unit is realized by replacing the conventional rectangular holes on ground plane with a slot resonator. The proposed SR-PBG-CPW unit exhibits more excellent bandgap and slow-wave characteristics and better selectivity at cut off frequency than the conventional PBG-CPW unit. Furthermore, the SR-PBG-CPW is applied effectively to design a bandstop, filter. Comparison between simulations and measurement confirms the validity of the proposed filter configuration and design procedure. (c) 2006 Wiley Periodicals, Inc.

In this paper, a novel diode linearizer to keep the base voltage of SiGe HBT power amplifier (PA) constant in the large-signal region is introduced. The results show that the output P(IdB), and power-added efficiency (PAE) are improved by 4.9 dBm and 22.8%, respectively. At an input power of 20 dBm, the gain compression and phase distortion of the linearized PA is 2.1 dB and 1.1 degrees, respectively, compared with 5.0 dB and 20.4 degrees for the conventional PA. Also, the improved ACPR is given. (c) 2006 Wiley Periodicals, Inc.

A new dual-spiral-shaped slot resonator in a coplanar waveguide (CPW-DSR) is studied. Also, its equivalent circuit model is introduced and used for multi-resonant performance analysis. Finally, a bandstop filter using periodically loaded CPW-DSRs is presented and verified by simulations and measurement.

We propose a unique wideband amplifier configuration. The new configuration adopts an improved Darlington amplifier to broaden the bandwidth and flatten the output gain. The low power consumption and matched impedances are also achieved in our amplifier. This circuit has been realized using Toshiba 0.35μm SiGe BiCMOS technology with the fT of 30GHz. The simulation result of the presented amplifier demonstrates 1-10GHz bandwidth and 11.3-dB maximum forward gain (S21) with less than ±0.5-dB gain flatness while it drains 8mA from a 3-V supply. A 1-dB compression point and an DP3 of -12.5dBm and 6dBm respectively also have been reported in this paper. © 2006 IEEE.

A novel microstrip dual-mode square loop bandpass filter with suppressed spurious passband is proposed. The degenerate modes are splitted by the embedded spur-lines easily. The spur-lines embedded in the output line suppress the second spurious passband effectively. The two-pole dual-mode filter operating at 2.59GHz with fractional bandwidth of 4.63% is designed, fabricated, and measured. The measured harmonic suppression ratio > 20dB is obtained.

This paper presents a design, simulation, implementation and measurement of a novel microstrip meander patch antenna for the application of sensor networks. The dimension of the microstrip chip antenna is 15mm X 15mm X 2mm. The meander-type radiating patch is constructed on the upper layer of the 2mm height substrate with 0.0 5mm height metallic conduct lines. Because of using the very high relative permittivity substrate (epsilon(r) = 90), the proposed antenna achieves 315MHz band operations.

A fully integrated voltage controlled oscillator (VCO) MMIC for millimeter-wave applications has been designed and implemented in InGaP/GaAs heterojunction bipolar transistor (HBT) technology. To achieve a fully integrated VCO, a base-emitter diode is employed as the tuning varactor, and microstrip lines are employed for the transmission lines. The fabricated VCO MMIC chip size is 0.86 turn x 1.34 nun and delivers an output power of 5.1 dBm at 28.7 GHz and a free-running phase noise of - 118 dBc/Hz at 1 MHz offset. The dc current consumption is only 20 mA.

A simple microstrip diplexer using defected groundstructure(DGS) is described in this letter. The diplexer has been designed, fabricated, and measured. Results show the new diplexer exhibits an isolation of greater than 26dB between channels.

A fast and direct method to estimate the stopband in microstrip lines with periodic defected ground structures(DGS) is introduced in this paper. Based on the equivalent circuit of single DGS unit, an approximate relationship between the stopband and DGS circuit dimensions is set up. Comparison between the estimated results and simulated results based on field analysis methods verifies the validity of the proposed method.

In traditional comparators especially for flash ADCs, one serious problem is the kick back noise, which disturbs the input signal voltages and consequently might cause errors at the outputs of the ADCs. In this paper, we propose a novel CMOS latched comparator with very low kickback noise for high-speed flash ADCs. The proposed comparator separates analog preamplifier from the positive feedback digital dynamic latch so as to reduce the influence of the kickback noise. Simulation results based on a mixed signal CMOS 0.35um technology show that, this comparator can work at a maximum clock frequency of 500MHz with very reduced kickback noise compared with conventional architectures.

高抵抗Si基板とSOI CMOS技術を組み合わせることで,ラッチアップの心配がない,高周波特性に優れたMOSFETと低損失スパイラルインダクタを実現した.0.25μm nMOSFETにおいては,低抵抗Si基板バルクnMOSFETのf_Tが23GHzに対して,高抵抗Si基板SOIでは35GHzのf_Tが得られた.スパイラルインダクタにおいては,低抵抗Si基板を用いた場合,そのQ値は5であり,高抵抗Si基板を用いた場合は,Q値が8まで改善できることを確認した.更に,本論文では,nMOSFETのソースに直列にインダクタを接続し,2GHz帯低雑音増幅器の設計を行った.試作したSOI低雑音増幅器は,周波数2.0GHzにおいて,利得16.6dB,NF1.9dBの特性を実現した.

The MOSFET parameters important for RF application at GHz frequencies: a) transition frequency, b) noise figure, and c) linearity are analyzed and correlated with substrate type. This work demonstrates that, without process changes, high-resistivity silicon-on-insulator (high-p SOI) substrates can successfully enhance the RF performance of on-chip inductors and fully depleted (FD)-SOI devices in terms of reducing substrate losses and parasitics. The linearity limitations of the SOI low-breakdown voltage and "kink" effect are addressed by judicious device and circuit design. Criteria for device optimization are derived. A NF = 1.7 dB at 2.5 GHz for a 0.25 mum FD-SOI low-noise amplifier (LNA) on high-p SOI substrate obtained the lowest noise figure for applications in the L and S-bands.

The tradeoffs in the ESD protection device for RFCMOS circuits are described, and the characteristics of an SCR-based ESD structure are presented. The parasitic capacitance of the ESD structure is reduced to similar to150fF. 3kV HBM and 750V CDM are achieved in a LNA working at 2.5GHz with NF<4dB, applicable for Bluetooth wireless transceiver.