2022/01/25 更新

写真a

ヨシマス トシヒコ
吉増 敏彦
所属
理工学術院 大学院情報生産システム研究科
職名
教授

兼担

  • 理工学術院   大学院基幹理工学研究科

  • 理工学術院   基幹理工学部

学内研究所等

  • 2020年
    -
    2022年

    理工学術院総合研究所   兼任研究員

学位

  • 神戸大学   博士(学術)

所属学協会

  •  
     
     

    IEEE

  •  
     
     

    電子情報通信学会

 

研究分野

  • 電子デバイス、電子機器

研究キーワード

  • マイクロ波IC、ミリ波IC、アナログIC、マイクロ波・ミリ波、電子デバイス・集積回路、パワーアンプ電圧制御発振器、スイッチ、低雑音アンプ、ミキサ、フィルタ

論文

  • A 26-GHz-band high back-off efficiency stacked-FET power amplifier IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI

    Toshihiko Yoshimasu, Mengchu Fang, Tsuyoshi Sugiura

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E104A ( 2 ) 477 - 483  2021年02月

     概要を見る

    This paper presents a 26-GHz-band high back-off efficiency power amplifier (PA) IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI. A 4-stacked-FET is employed to increase the output power and to conquer the low breakdown voltage issue of scaled MOSFET. The adaptive bias circuit is reviewed and the adaptive load circuit which consists of an inverter circuit and transformer-based inductors is described in detail. The measured performance of the PA IC is fully shown in this paper. The PA IC exhibits a saturated output power of 20.5 dBm and a peak power-added-efficiency (PAE) as high as 39.4% at a supply voltage of 4.0 V. Moreover, the PA IC has exhibited an excellent ITRS FoM of 82.0 dB.

    DOI

  • 0.3 V 15-GHz band VCO ICs with novel transformer-based harmonic tuned tanks in 45-nm SOI CMOS

    Xiao Xu, Tsuyoshi Sugiura, Toshihiko Yoshimasu

    IEICE Transactions on Electronics   E103.C ( 10 ) 417 - 425  2020年10月

     概要を見る

    Copyright © 2020 The Institute of Electronics, Information and Communication Engineers. This paper presents two ultra-low voltage and high performance VCO ICs with two novel transformer-based harmonic tuned tanks. The first proposed harmonic tuned tank effectively shapes the pseudo-square drain-node voltage waveform for close-in phase noise reduction. To compensate the voltage drop caused by the transformer, an improved second tank is proposed. It not only has tuned harmonic impedance but also provides a voltage gain to enlarge the output voltage swing over supply voltage limitation. The VCO with second tank exhibits over 3 dB better phase noise performance in 1/f2 region among all tuning range. The two VCO ICs are designed, fabricated and measured on wafer in 45-nm SOI CMOS technology. With only 0.3 V supply voltage, the proposed two VCO ICs exhibit best phase noise of -123.3 and -127.2 dBc/Hz at 10 MHz offset and related FoMs of -191.7 and -192.2 dBc/Hz, respectively. The frequency tuning ranges of them are from 14.05 to 15.14 GHz and from 14.23 to 15.68 GHz, respectively.

    DOI

  • A-197.3-dBc/Hz FoM<inf>T</inf>Wideband LC-VCO IC with a Single Voltage-Controlled IMOS-Based Novel Varactor in 40-nm CMOS SOI

    Mengchu Fang, Toshihiko Yoshimasu

    IEEE Transactions on Microwave Theory and Techniques   68 ( 10 ) 4116 - 4121  2020年10月

     概要を見る

    © 1963-2012 IEEE. A wideband LC-VCO IC with an Inversion-MOS (IMOS)-based novel varactor is proposed in this article. The novel varactor that consists of an IMOS and a fixed metal-insulator-metal (MIM) capacitor is able to provide a continuous tuning range with a single analog control voltage. The proposed VCO IC is designed, fabricated, and fully evaluated on the wafer in 40-nm CMOS SOI. The proposed wideband VCO IC has exhibited a tuning range of 40.3% from 4.14 to 6.23 GHz and a measured FoMT of-197.3 dBc/Hz under a supply voltage of only 0.34 V.

    DOI

  • High Linearity and High Efficiency Stacked-FET Millimeter-Wave Power Amplifier ICs

    Toshihiko Yoshimasu, Mengchu Fang, Tsuyoshi Sugiura

    2020 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2020     172 - 174  2020年09月

     概要を見る

    © 2020 IEEE. Recently reported CMOS power amplifier ICs for microwave and millimeter-wave communication systems such as 5G are summarized and reviewed in this paper. Stacked-FETs are widely utilized to increase the output power and to conquer low breakdown voltage issues. In addition, adaptive bias and load circuits are fully described to improve the linearity and back-off efficiency of the power amplifier ICs in this paper.

    DOI

  • A 28-GHz-band highly linear stacked-FET power amplifier IC with high back-off PAE in 56-nm SOI CMOS

    Cuilin Chen, Tsuyoshi Sugiura, Toshihiko Yoshimasu

    IEICE Transactions on Electronics   E103.C ( 4 ) 153 - 160  2020年

     概要を見る

    Copyright © 2020 The Institute of Electronics, Information and Communication Engineers. This paper presents a 28-GHz-band highly linear stacked- FET power amplifier (PA) IC. A 4-stacked-FET structure is employed for high output power considering the low breakdown voltage of scaled MOSFET transistors. A novel adaptive bias circuit is proposed to dynamically control the gate-to-source bias voltage for amplification MOSFETs. The novel adaptive bias allows the PA to attain high linearity with high back-off efficiency. In addition, the third-order intermodulation distortion (IM3) is improved by a multi-cascode structure. The PA IC is designed, fabricated and fully tested in 56-nm SOI CMOS technology. At a supply voltage of 4 V, the PA IC has achieved an output power of 20.0 dBm with a PAE as high as 38.1% at the 1-dB gain compression point (P1dB). Moreover, PAEs at 3-dB and 6-dB back-off from P1dB are 36.2% and 28.7%, respectively. The PA IC exhibits an output third-order intercept point (OIP3) of 25.0 dBm.

    DOI

  • A-197.3 dBc/Hz FoMT wideband LC-VCO IC with an I-MOS based novel varactor in 40-nm SOI CMOS

    Mengchu Fang, Akihiko Kumura, Toshihiko Yoshimasu

    Asia-Pacific Microwave Conference Proceedings, APMC   2019-December   783 - 785  2019年12月

     概要を見る

    © 2019 IEEE. This paper presents a wideband excellent FoMT LC-VCO IC with a novel varactor controlled by a single tuning voltage. The novel varactor includes an Inversion-MOS (IMOS) and an MIM capacitor to widen the capacitance variation. The proposed wideband VCO IC is designed, fabricated and fully evaluated on wafer in 40-nm SOI CMOS. The proposed VCO IC has a completely continuous frequency tuning range from 4.14 GHz to 6.23 GHz (40.3 %) and a-131.0-dBc/Hz measured phase noise at 10-MHz offset frequency from the oscillation frequency of 4.14 GHz. Moreover, the VCO IC has exhibited a measured FoMT of-197.3 dBc/Hz under a 0.34-V supply voltage.

    DOI

  • A 26-GHz-band high efficiency stacked-FET power amplifier ic with adaptively controlled load and bias circuits in 40-nm SOI CMOS

    Tsuyoshi Sugiura, Cuilin Chen, Toshihiko Yoshimasu

    Asia-Pacific Microwave Conference Proceedings, APMC   2019-December   1700 - 1702  2019年12月

     概要を見る

    © 2019 IEEE. This paper presents a 26 GHz band high efficiency power amplifier (PA) IC with adaptively controlled load and bias conditions. An adaptively controlled load matching circuit cooperating with an adaptive bias circuit is proposed to achieve a high efficiency PA IC in a broad range of input power. The chip of PA IC is fabricated using 40-nm silicon on insulator (SOI) CMOS process and evaluated on wafer. The fabricated PA IC has shown a peak PAE of 40.2% and a saturation output power (Psat) of 20.5 dBm with a 4.0 V applied voltage on Vdd at 26GHz. A PAE of over 35% at an input power between-2 dBm and 7 dBm has been realized.

    DOI

  • A 28-GHz-band stacked FET linear power amplifier IC with 36.2 % PAE at 3-dB back-off from P1dB in 56-nm SOI CMOS

    Cuilin Chen, Tsuyoshi Sugiura, Toshihiko Yoshimasu

    IEEE Radio and Wireless Symposium, RWS    2019年05月

     概要を見る

    © 2019 IEEE. This paper presents a high efficiency linear stacked FET power amplifier (PA) IC for 5G wireless communication systems. An adaptive bias circuit is used to enhance linearity and back-off efficiency. In addition, third-order trans-conductance component (gm3) is cancelled by multi-cascode structure. The PA IC is designed, fabricated and fully evaluated in 56-nm SOI CMOS. At a supply voltage of 4 V, the PA IC has exhibited an output power of 20.0 dBm and a PAE of 38.1% at 1-dB gain compression point (P1dB). The PAEs at 3 dB and 6 dB back-off from P1dB are 36.2 % and 28.7 %, respectively. The output IP3 of 25.0 dBm is obtained.

    DOI

  • A Low Supply Voltage LC-VCO IC with a Drain Harmonic Tuned Filter in 40-nm SOI CMOS

    Mengchu Fang, Xiao Xu, Toshihiko Yoshimasu

    2019 IEEE MTT-S International Wireless Symposium, IWS 2019 - Proceedings    2019年05月

     概要を見る

    © 2019 IEEE. A low-supply-voltage 15-GHz-band LC-VCO IC is presented in this paper to improve the phase noise and FoM performance. The proposed VCO IC adopts a drain harmonic tuned filter and an LC bias circuit to realize high load impedance at the third harmonics and to amplify carrier signal for improving the phase noise performance. The LC-VCO IC is designed, fabricated and fully evaluated on wafer in 40-nm SOI CMOS. The fabricated VCO IC has exhibited a measured phase noise of -132.0 dBc/Hz at 10-MHz offset frequency from the 15.58 GHz carrier frequency and a measured FoMT of -197.5 dBc/Hz with a supply voltage of 0.45 V.

    DOI

  • High efficiency compact Doherty power amplifier with novel harmonics termination for handset applications

    Tsuyoshi Sugiura, Satoshi Furuta, Tadamasa Murakami, Koki Tanji, Norihisa Otani, Toshihiko Yoshimasu

    Asia-Pacific Microwave Conference Proceedings, APMC   2018-November   455 - 457  2019年01月

     概要を見る

    © 2018 IEICE This paper presents a high efficiency compact Doherty power amplifier (PA) with a novel harmonics termination for handset applications using a GaAs/InGaP heterojunction bipolar transistor (HBT) process. The novel harmonic termination circuit effectively reduces the insertion loss of the matching circuit with compact size. The Doherty PA adopts a lumped-element transformer which consists of metal insulator metal (MIM) capacitors on Silicon substrate, a bonding-wire inductor and short micro-strip lines on printed circuit board (PCB). The fabricated PA has exhibited an average output power of 25.5 dBm and a power added efficiency (PAE) as high as 50.1% under a 10MHz band width quadrature phase shift keying (QPSK) 6.16 dB peak-to-average-power-ratio (PAPR) LTE signal. The IC die size is 1mm by 1mm. The input and output Doherty transformer areas are 0.5 mm by 1.0 mm and 0.7 mm by 0.7 mm, respectively.

    DOI

  • A 16-GHz-band low-supply-voltage class-C VCO IC with switching feedback circuit in 40-nm SOI CMOS

    Mengchu Fang, Xiao Xu, Toshihiko Yoshimasu

    Asia-Pacific Microwave Conference Proceedings, APMC   2018-November   1121 - 1123  2019年01月

     概要を見る

    © 2018 IEICE A 16-GHz-band low-power and low-phase-noise PMOS VCO IC is presented in 40-nm SOI CMOS. The VCO IC includes a cross-coupled PMOS pair, an LC bias circuit, drain resistors, an LC tank circuit and novel feedback circuit. The feedback circuit which consists of a PMOS transistor, a resistor and a capacitor realizes robust start-up and low-power Class-C operation in the steady-state. The VCO IC is designed, fabricated and fully evaluated on wafer. The VCO IC has exhibited a measured phase noise of 㸫131.0 dBc/Hz at 10-MHz offset frequency from the 16.05 GHz carrier frequency with a supply voltage of only 0.43 V. The measured FOM is 㸫191.2 dBc/Hz.

    DOI

  • High efficiency class-E and compact Doherty power amplifiers with novel harmonics termination for handset applications

    Tsuyoshi Sugiura, Satoshi Furuta, Tadamasa Murakami, Koki Tanji, Norihisa Otani, Toshihiko Yoshimasu

    IEICE Transactions on Electronics   E102C ( 10 ) 699 - 706  2019年

     概要を見る

    © 2019 The Institute of Electronics, Information and Communication Engineers. This paper presents high efficiency Class-E and compact Doherty power amplifiers (PAs) with novel harmonics termination for handset applications using a GaAs/InGaP heterojunction bipolar transistor (HBT) process. The novel harmonics termination circuit effectively reduces the insertion loss of the matching circuit, allowing a device with a compact size. The Doherty PA uses a lumped-element transformer which consists of metal-insulator-metal (MIM) capacitors on an IC substrate, a bonding-wire inductor and short micro-strip lines on a printed circuit board (PCB). The fabricated Class-E PA exhibits a power added efficiency (PAE) as high as 69.0% at 1.95 GHz and as high as 67.6% at 2.535 GHz. The fabricated Doherty PA exhibits an average output power of 25.5 dBm and a PAE as high as 50.1% under a 10-MHz band width quadrature phase shift keying (QPSK) 6.16-dB peak-to-average-power-ratio (PAPR) LTE signal at 1.95 GHz. The fabricated chip size is smaller than 1 mm2. The input and output Doherty transformer areas are 0.5 mm by 1.0 mm and 0.7 mm by 0.7 mm, respectively.

    DOI

  • Ultra-low voltage 15-GHz band best Fom &lt; −190 dBC/Hz LC-VCO ICs with novel harmonic tuned LC tank in 45-nm SOI CMOS

    Xiao Xu, Tsuyoshi Sugiura, Toshihiko Yoshimasu

    IEICE Transactions on Electronics   E102C ( 10 ) 673 - 681  2019年

     概要を見る

    Copyright © 2019 The Institute of Electronics. This paper presents two ultra-low voltage and high performance VCO ICs with novel harmonic tuned LC tank which provides different harmonic impedance and shapes the pseudo-square drain voltage waveform of transistors. In the novel tank, two additional inductors are connected between the drains of the cross-coupled pMOSFETs and the conventional LC tank, and they effectively decrease second harmonic load impedance and increase third harmonic load impedance of the transistors. In this paper, the novel harmonic tuned LC tank is applied to two different structure VCOs. These two VCOs exhibit over 2 dB better phase noise performance than conventional LC tank VCOs among all tuning range. The conventional and proposed VCO ICs are designed, fabricated and measured on wafer in 45-nm SOI CMOS technology. With novel harmonic tuned LC tank, the novel two VCOs exhibit measured best phase-noise of −125.7 and −129.3 dBc/Hz at 10 MHz offset and related FoM of −190.2 and −190.5 dBc/Hz at a supply voltage of 0.3 V and 0.35 V, respectively. Frequency tuning range of the two VCOs are from 13.01 to 14.34 GHz and from 15.02 to 16.03GHz, respectively.

    DOI

  • A 2.5-Ghz 1-V high efficiency CMOS power amplifier IC with a dual-switching transistor and third harmonic tuning technique

    Taufiq Alif Kurniawan, Toshihiko Yoshimasu

    Electronics (Switzerland)   8 ( 1 )  2019年01月

     概要を見る

    © 2019 by the authors. Licensee MDPI, Basel, Switzerland. This paper presents a 2.5-GHz low-voltage, high-efficiency CMOS power amplifier (PA) IC in 0.18-µm CMOS technology. The combination of a dual-switching transistor (DST) and a third harmonic tuning technique is proposed. The DST effectively improves the gain at the saturation power region when the additional gain extension of the secondary switching transistor compensates for the gain compression of the primary one. To achieve high-efficiency performance, the third harmonic tuning circuit is connected in parallel to the output load. Therefore, the flattened drain current and voltage waveforms are generated, which in turn reduce the overlapping and the dc power consumption significantly. In addition, a 0.5-V back-gate voltage is applied to the primary switching transistor to realize the low-voltage operation. At 1 V of supply voltage, the proposed PA has achieved a power added efficiency (PAE) of 34.5% and a saturated output power of 10.1 dBm.

    DOI

  • Highly Efficient, Flexible Wireless-Powered Circuit Printed on a Moist, Soft Contact Lens

    Advanced Materials Technology   4 ( 5 ) 1800671-1 - 1800671-8  2019年  [査読有り]

    DOI

  • A 14-GHz-Band Highly Linear Stacked FET Power Amplifier IC with 20.1 dBm P1dB and 40.1% PAE in 56-nm SOI CMOS

    Cuilin Chen, Tsuyoshi Sugiura, Toshihiko Yoshimasu

    EuMIC 2018 - 2018 13th European Microwave Integrated Circuits Conference     182 - 185  2018年11月

     概要を見る

    © 2018 European Microwave Association - EuMA. A high efficiency linear power amplifier (PA) IC is presented for 14 GHz-band wireless communication systems. A novel adaptive bias circuit with four-stacked MOSFET structure is proposed to enhance both the linearity and efficiency of the PA IC over the wide input power range. The PA IC is designed, fabricated and fully tested in 56-nm SOI CMOS. In linear mode, the PA IC has exhibited an output P1dB of 20.1 dBm at 14 GHz and a supply voltage of 4.0 V. The measured PAE at P1dB is as high as 40.1%. Moreover, the peak PAE of 41.6% is achieved in efficient mode.

    DOI

  • A 0.3 v -190.2 dBc/Hz FoM 14-GHz Band LC-VCO IC with Harmonic Tuned LC Tank in 56-nm SOI CMOS

    Xiao Xu, Tsuyoshi Sugiura, Toshihiko Yoshimasu

    EuMIC 2018 - 2018 13th European Microwave Integrated Circuits Conference     202 - 205  2018年11月

     概要を見る

    © 2018 European Microwave Association - EuMA. This paper presents a 14-GHz band ultra-low-power low-phase-noise VCO IC with a novel harmonic tuned LC tank consisting of a conventional LC tank and additional series inductors. The additional inductor is connected between the drain of the cross-coupled pMOSFET and the conventional LC tank circuit to adjust the harmonic impedance and to shape the drain voltage waveform rectangular. The adjusted load impedance improves the phase noise of the VCO IC. The conventional and proposed VCOs are designed, fabricated and fully measured on-wafer in 56-nm SOI CMOS technology. The fabricated VCO IC has exhibited a measured phase-noise of - 125.7 dBc/Hz at 10 MHz offset from the 13.46 GHz carrier frequency at a supply voltage of only 0.3 V. The power consumption of the VCO IC core is 0.63 mW and the FoM is - 190.2 dBc/Hz.

    DOI

  • An X-band low voltage cross-coupled voltage-controlled oscillator IC in 56-nm SOI CMOS

    Lei Sun, Xiao Xu, Toshihiko Yoshimasu

    2018 IEEE MTT-S International Wireless Symposium, IWS 2018 - Proceedings     1 - 3  2018年06月

     概要を見る

    © 2018 IEEE. An X-band voltage-controlled oscillator (VCO) IC is presented in this paper for low voltage operation. The LC-VCO IC consists of a cross-coupled pMOSFET pair, an LC tank circuit and buffer amplifiers. The LC-VCO IC is designed, fabricated and fully evaluated on-wafer using 56-nm SOI CMOS technology. The fabricated VCO IC has exhibited a measured phase noise of-119.02 dBc/Hz at 5 MHz offset from the 9.8 GHz carrier frequency at an operation voltage of only 0.5 V.

    DOI

  • A 28-GHz band highly linear power amplifier with novel adaptive bias circuit for cascode MOSFET in 56-nm SOI CMOS

    Hiroya Sato, Masao Yanagisawa, Toshihiko Yoshimasu

    EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits   2017-January   1 - 2  2017年12月  [査読有り]

     概要を見る

    © 2017 IEEE. All rights reserved. This paper presents a highly linear 28-GHz band SOI CMOS power amplifier with an adaptive bias circuit for cascode MOSFET for next generation wireless communication. The power amplifier consists of a cascode MOSFET, the adaptive bias circuit and the input and output matching circuits. The power amplifier has exhibited a simulated output P1dB (1-dB gain compression point) of 19.2 dBm and a PAE of 39.0 %.

    DOI

  • A DC-50 GHz, low insertion loss and high P1dB SPDT switch IC in 40-nm SOI CMOS

    Cuilin Chen, Xiao Xu, Toshihiko Yoshimasu

    Asia-Pacific Microwave Conference Proceedings, APMC     5 - 8  2017年06月  [査読有り]

     概要を見る

    © 2017 IEEE. A DC-50 GHz Single-Pole Double-Throw (SPDT) switch IC is designed, fabricated and fully evaluated on wafer in 40-nm SOI CMOS. The insertion loss of the SPDT switch IC is 0.99 dB at 20 GHz and 1.68 dB at 40 GHz, respectively. From 100 MHz to 50 GHz, the measured isolation is better than 15.8 dB. The input-referred 1-dB compression point (P1dB) is over 20 dBm at 10 GHz.

    DOI

  • A 28.1 GHz Ultra-Low-Power SHM with AC-DC Splitting LC-Tank and an Analysis of the Switch-Conversion Efficiency

    L. Wang, T. Yoshimasu

    IEEE International Conference on Communication Software and Networks (ICCSN)     1520 - 1523  2017年05月  [査読有り]

  • 15-GHz-band low-power and low phase-noise LC VCO IC with a second harmonic filter in 130-nm SiGe BiCMOS

    Xu Xiao, Xinyi Wang, Toshihiko Yoshimasu

    IEEE Region 10 Annual International Conference, Proceedings/TENCON     2525 - 2527  2017年02月

     概要を見る

    In this paper, a second harmonic filtering technique is presented for improvement of phase noise performance of a Class-C LC-VCO IC. The second harmonic filter is employed to terminate the output port of the LC-VCO in low impedance at second harmonic frequency, which mainly prevents the noise modulated by the transistor nonlinearities. In addition, since the impedance of the second harmonic filter becomes capacitive at the fundamental frequency, the phase-noise performance is improved. Class-C operation is also effective for less power and better phase-noise performance. The LC-VCO IC was fabricated and evaluated in 130-nm SiGe BiCMOS technology. The LC-VCO IC has presented a measured phase noise of-118.1 dBc/Hz at 5 MHz offset from the 15.2 GHz carrier frequency with a dc power consumption of about 2.25 mW.

    DOI

  • A 20-30 GHz High Efficiency Power Amplifier IC with an Adaptive Bias Circuit in 130-nm SiGe BiCMOS

    Cuilin Chen, Xiao Xu, Xin Yang, Tsuyoshi Sugiura, Toshihiko Yoshimasu

    2017 IEEE 17TH TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS (SIRF)     88 - 90  2017年  [査読有り]

     概要を見る

    A high efficiency broadband power amplifier IC is proposed for wireless communication systems. The power amplifier IC integrates an adaptive bias circuit which can adjust the collector current of SiGe HBT under large signal operation to improve the efficiency and temperature performance. The power amplifier IC is designed, fabricated and fully measured in 130-nm SiGe BiCMOS. The fabricated power amplifier IC has exhibited an output power of 14.6 dBm with a PAE of 43.8 % at a supply voltage of 1.4 V at 26 GHz. In addition, the power amplifier IC has an output power of over 12 dBm with a PAE of over 31.1 % from 20 to 30 GHz.

  • A 20-30 GHz High Efficiency Power Amplifier IC with an Adaptive Bias Circuit in 130-nm SiGe BiCMOS

    Cuilin Chen, Xiao Xu, Xin Yang, Tsuyoshi Sugiura, Toshihiko Yoshimasu

    2017 IEEE 17TH TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS (SIRF)     88 - 90  2017年  [査読有り]

     概要を見る

    A high efficiency broadband power amplifier IC is proposed for wireless communication systems. The power amplifier IC integrates an adaptive bias circuit which can adjust the collector current of SiGe HBT under large signal operation to improve the efficiency and temperature performance. The power amplifier IC is designed, fabricated and fully measured in 130-nm SiGe BiCMOS. The fabricated power amplifier IC has exhibited an output power of 14.6 dBm with a PAE of 43.8 % at a supply voltage of 1.4 V at 26 GHz. In addition, the power amplifier IC has an output power of over 12 dBm with a PAE of over 31.1 % from 20 to 30 GHz.

    DOI

  • 15-GHz-Bnad Low-Power and Low Phase-noise LC VCO IC with A Second Harmonic Filter in 130-nm SiGe BiCMOS

    X. Xu, X. Wang, T. Yoshimasu

    IEEE Region 10 Conference     2527 - 2529  2016年11月  [査読有り]

  • 80-GHz-band low-power sub-harmonic mixer IC with a bottom-LO-configuration in 130-nm SiGe BiCMOS

    Xin Yang, Xiao Xu, Takayuki Shibata, Toshihiko Yoshimasu

    INTERNATIONAL JOURNAL OF MICROWAVE AND WIRELESS TECHNOLOGIES   8 ( 4-5 ) 703 - 712  2016年06月  [査読有り]

     概要を見る

    In this paper, a W-band (80 GHz) sub-harmonic mixer (SHM) IC is designed, fabricated and measured in 130-nm SiGe BiCMOS technology. The presented SHM IC makes use of a common emitter common collector transistor pair structure with a bottom-LO-configuration to decrease the LO power requirement and a tail current source to flatten the conversion gain. On-chip Marchand balun is designed for W-band on-wafer measurements. The SHM IC presented in this paper has exhibited a conversion gain of 3.9 dB at 80 GHz RF signal with an LO power of only (-)7 dBm at 39.5 GHz. The mixer core consumes only 0.68 mA at a supply voltage of 3.3 V.

    DOI

  • Linearity Analysis of SiGe HBT and Novel Linearization Technique for Power Amplifier ICs for Wireless Communication Systems

    Toshihiko Yoshimasu

    BIT’s 2nd Annual World Congress of Smart Materials    2016年03月  [査読有り]  [招待有り]

  • An Ultra-Low-Voltage Class-C PMOS VCO IC with PVT Compensation in 180-nm CMOS

    Xin Yang, Xiao Xu, Toshihiko Yoshimasu

    2016 IEEE 16TH TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS (SIRF)     107 - 109  2016年  [査読有り]

     概要を見る

    A novel 2.2-GHz-band ultra-low-voltage Class-C PMOS VCO IC with negative reference and amplitude feedback loop is proposed. The negative reference initially adapts a sufficient bias for the LC-VCO circuit to ensure a robust oscillation start-up. The feedback loop then adaptively controls the bias condition of LC-VCO for Class-C operation in steady-state. The reliability of the feedback loop is enhanced over PVT variation. The Class-C VCO IC has been designed, fabricated and fully evaluated in 180-nm CMOS technology. The fabricated VCO IC exhibits a measured phase noise of 113.2 dBc/Hz at 1 MHz offset from the 2.2 GHz carrier frequency with a supply voltage of only 0.3 V.

  • An Ultra-Low-Voltage Class-C PMOS VCO IC with PVT Compensation in 180-nm CMOS

    Xin Yang, Xiao Xu, Toshihiko Yoshimasu

    2016 IEEE 16TH TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS (SIRF)     107 - 109  2016年  [査読有り]

     概要を見る

    A novel 2.2-GHz-band ultra-low-voltage Class-C PMOS VCO IC with negative reference and amplitude feedback loop is proposed. The negative reference initially adapts a sufficient bias for the LC-VCO circuit to ensure a robust oscillation start-up. The feedback loop then adaptively controls the bias condition of LC-VCO for Class-C operation in steady-state. The reliability of the feedback loop is enhanced over PVT variation. The Class-C VCO IC has been designed, fabricated and fully evaluated in 180-nm CMOS technology. The fabricated VCO IC exhibits a measured phase noise of 113.2 dBc/Hz at 1 MHz offset from the 2.2 GHz carrier frequency with a supply voltage of only 0.3 V.

    DOI

  • 2.4-GHz-Band Low-Voltage LC-VCO IC with Simplified Noise Filtering in 180-nm CMOS

    Xinyi Wang, Xin Yang, Xiao Xu, Toshihiko Yoshimasu

    2016 IEEE MTT-S INTERNATIONAL WIRELESS SYMPOSIUM (IWS)    2016年  [査読有り]

     概要を見る

    This paper presents a low-voltage and low phase noise LC-VCO IC with simplified noise filtering in 180-nm CMOS technology. The novel VCO IC includes a cross-coupled pMOSFET pair, an LC resonator, buffer amplifiers and a tail inductor for noise filtering. The novel and conventional LC-VCO ICs are designed, fabricated and fully tested on wafer. At a power supply voltage of only 0.5 V, the novel VCO IC has exhibited a phase noise of -119.4 dBc/Hz at 1 MHz offset from the 2.25 GHz carrier frequency, which is 2.6 dB better than the conventional one.

  • A 30-GHz Band High-Efficiency Class-J Power Amplifier IC in 120-nm SiGe HBT Technology

    Cuilin Chen, Xin Yang, Toshihiko Yoshimasu

    2016 IEEE INTERNATIONAL SYMPOSIUM ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY (RFIT)    2016年  [査読有り]

     概要を見る

    A 30-GHz band power amplifier (PA) IC is designed, fabricated and fully tested in 120-nm SiGe HBT process. The impedances of the output matching network are optimized at both the fundamental and second harmonic for a high power added efficiency (PAE). At a supply voltage of 1.4 V, the PA IC has exhibited a measured output P1dB of 10.8 dBm, a peak PAE of 32.4%, and a small-signal gain of 9.1 dB at 30 GHz.

  • A 30-GHz Band Low-Insertion Loss and High-Isolation SPDT Switch IC in 120-nm SiGe HBT

    Cuilin Chen, Fenfen Tuo, Xiao Xu, Toshihiko Yoshimasu

    2016 IEEE INTERNATIONAL SYMPOSIUM ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY (RFIT)    2016年  [査読有り]

     概要を見る

    A 30-GHz band Single-Pole Double-Throw (SPDT) switch IC is designed, fabricated and fully evaluated in 120-nm SiGe heterojunction bipolar transistor (HBT) process. The SPDT switch IC employs diode-connected HBTs and LC resonant circuits to improve the insertion loss and isolation. The fabricated SPDT switch IC has exhibited an insertion loss of 3.3 dB, an isolation of 21.8 dB and an input-referred 1-dB compression point (P1dB) of 16 dBm at 32 GHz.

  • A 2-GHz-band Low-Phase-Noise VCO IC with an LC Bias Circuit in 180-nm CMOS

    Xiao Xu, Xin Yang, Toshihiko Yoshimasu

    2016 11TH EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE (EUMIC)     197 - 200  2016年  [査読有り]

     概要を見る

    A novel LC bias topology is proposed to improve the phase noise of VCO IC for ultra-low-voltage applications. The LC bias circuit works as an impedance transformation network, which improves the phase noise of VCO by delivering higher power to the gates of the cross-coupled transistors. A 2-GHz-band ultra-low-voltage VCO IC with the novel LC bias circuit has been designed, fabricated and fully evaluated in 180-nm CMOS technology. The fabricated novel VCO IC has exhibited a measured phase noise of -126.4 dBc/Hz at 1 MHz offset frequency from the 2.03 GHz carrier frequency with a supply voltage of 0.5 V.

  • 15-GHz-Band Low-Power and Low Phase-Noise LC VCO IC with A Second Harmonic Filter in 130-nm SiGe BiCMOS

    Xu Xiao, Xinyi Wang, Toshihiko Yoshimasu

    PROCEEDINGS OF THE 2016 IEEE REGION 10 CONFERENCE (TENCON)     2525 - 2527  2016年  [査読有り]

     概要を見る

    In this paper, a second harmonic filtering technique is presented for improvement of phase noise performance of a Class-C LC-VCO IC. The second harmonic filter is employed to terminate the output port of the LC-VCO in low impedance at second harmonic frequency, which mainly prevents the noise modulated by the transistor nonlinearities. In addition, since the impedance of the second harmonic filter becomes capacitive at the fundamental frequency, the phase noise performance is improved. Class-C operation is also effective for less power and better phase-noise performance. The LC-VCO IC was fabricated and evaluated in 130-nm SiGe BiCMOS technology. The LC-VCO IC has presented a measured phase noise of -118.1 dBc/Hz at 5 MHz offset from the 15.2 GHz carrier frequency with a de power consumption of about 2.25 mW.

  • A 2-GHz-band Low-Phase-Noise VCO IC with an LC Bias Circuit in 180-nm CMOS

    Xiao Xu, Xin Yang, Toshihiko Yoshimasu

    2016 11TH EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE (EUMIC)     197 - 200  2016年  [査読有り]

     概要を見る

    A novel LC bias topology is proposed to improve the phase noise of VCO IC for ultra-low-voltage applications. The LC bias circuit works as an impedance transformation network, which improves the phase noise of VCO by delivering higher power to the gates of the cross-coupled transistors. A 2-GHz-band ultra-low-voltage VCO IC with the novel LC bias circuit has been designed, fabricated and fully evaluated in 180-nm CMOS technology. The fabricated novel VCO IC has exhibited a measured phase noise of -126.4 dBc/Hz at 1 MHz offset frequency from the 2.03 GHz carrier frequency with a supply voltage of 0.5 V.

    DOI

  • 2.4-GHz Band Low-Power PMOS VCO IC With Adaptive Bias Control Loop

    Xiao Xu, Xin Yang, Toshihiko Yoshimasu

    Asia Pacific Microwave Conference    2015年12月  [査読有り]

  • A 5-GHz Band WLAN SiGe HBT Power Amplifier IC with Novel Adaptive-Linearizing CMOS Bias Circuit

    Xin Yang, Tsuyoshi Sugiura, Norihisa Otani, Tadamasa Murakami, Eiichiro Otobe, Toshihiko Yoshimasu

    IEICE TRANSACTIONS ON ELECTRONICS   E98C ( 7 ) 651 - 658  2015年07月  [査読有り]

     概要を見る

    This paper presents a novel CMOS bias topology serving as not only a bias circuit but also an adaptive linearizer for SiGe HBT power amplifier (PA) IC. The novel bias circuit can well keep the base-to-emitter voltage (V-be) of RF amplifying HBT constant and adaptively increase the base current (I-b) with the increase of the input power. Therefore, the gain compression and phase distortion performance of the PA is improved. A three-stage 5-GHz band PA IC with the novel bias circuit for WLAN applications is designed and fabricated in IBM 0.35 mu m SiGe BiCMOS technology. Under 54Mbps OFDM signal at 5.4 GHz, the PA IC exhibits a measured small-signal gain of 29 dB, an EVM of 0.9% at 17 dBm output power and a DC current consumption of 284 mA.

    DOI

  • A 5-GHz band WLAN SiGe HBT power amplifier IC with novel adaptive-linearizing CMOS bias circuit

    Xin Yang, Tsuyoshi Sugiura, Norihisa Otani, Tadamasa Murakami, Eiichiro Otobe, Toshihiko Yoshimasu

    IEICE Transactions on Electronics   E98C ( 7 ) 651 - 658  2015年07月  [査読有り]

     概要を見る

    This paper presents a novel CMOS bias topology serving as not only a bias circuit but also an adaptive linearizer for SiGe HBT power amplifier (PA) IC. The novel bias circuit can well keep the base-to-emitter voltage (Vbe) of RF amplifying HBT constant and adaptively increase the base current (Ib) with the increase of the input power. Therefore, the gain compression and phase distortion performance of the PA is improved. A three-stage 5-GHz band PA IC with the novel bias circuit for WLAN applications is designed and fabricated in IBM 0.35 μm SiGe BiCMOS technology. Under 54 Mbps OFDM signal at 5.4 GHz, the PA IC exhibits a measured small-signal gain of 29 dB, an EVM of 0.9% at 17 dBm output power and a DC current consumption of 284 mA.

    DOI CiNii

  • Broadband Highly Linear High Isolation SPDT Switch IC with Floating Body Technique in 180-nm CMOS

    Xiao Xu, Xin Yang, Taufiq Alif Kurniawan, Toshihiko Yoshimasu

    PROCEEDINGS OF THE 2015 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC)     653 - 655  2015年  [査読有り]

     概要を見る

    This paper presents a broadband single-pole double throw (SPDT) switch IC in a 180-nm CMOS process. Floating body technique and stacked nMOSFETs are utilized to improve the power handling capability and isolation performance. The fabricated SPDT switch IC has exhibited an input referred 0.5 dB compression point of 21.8 dBm, an isolation of 42.4 dB and an insertion loss of 1.2 dB for transmit mode at an operation frequency of 5.0 GHz. The SPDT switch IC has an insertion loss of 2.1 dB and a return loss of 10.6 dB for receive mode at 5.0 GHz.

  • W-band Low Power Sub-harmonic Mixer IC in 130-nm SiGe BiCMOS

    Xin Yang, Zheng Sun, Takayuki Shibata, Toshihiko Yoshimasu

    2015 IEEE International Wireless Symposium (IWS 2015)    2015年  [査読有り]

     概要を見る

    This paper presents a sub-harmonic mixer IC design for W-band automotive radar applications in 130-nm SiGe BiCMOS technology. The mixer makes use of a Common Emitter Common Collector Transistor Pair (CECCTP) structure mixer core with a Marchand balun for the W-band on-wafer measurement. The balun achieves a measured amplitude imbalanced of less than 0.9 dB and a phase imbalance of less than 2.5 degrees in a frequency range from 20 GHz to 66 GHz. The sub-harmonic mixer IC exhibits a conversion gain of 3.8 dB at 80 GHz with an LO power of 0 dBm at 39.5 GHz. And the mixer core only consumes 0.42 mA with a supply voltage of 2.5 V.

  • A 2.5-GHz Band, 0.75-V High Efficiency CMOS Power Amplifier IC With Third Harmonic Termination Technique in 0.18-mu m CMOS

    Taufiq Alif Kurniawan, Xin Yang, Xiao Xui, Nobuyuki Itoh, Toshihiko Yoshimasu

    2015 IEEE 16TH ANNUAL WIRELESS AND MICROWAVE TECHNOLOGY CONFERENCE (WAMICON)    2015年  [査読有り]

     概要を見る

    In this paper, a 2.5-GHz band fully integrated high efficiency CMOS power amplifier IC with third harmonic termination technique for low supply voltage was designed, fabricated and fully evaluated in 0.18-mu m CMOS technology. Since the proposed third harmonic termination technique effectively increases the PAE by reducing the rms drain current, the total dc power consumption is diminished. To control a threshold voltage for low supply voltage application, a 0.5-V back-gate voltage is applied for the transistor. The power amplifier IC exhibits an output power of 8.5 dBm and a peak PAE of 31.1 % at a supply voltage of only 0.75-V.

  • 2.4-GHz Band Ultra-Low-Voltage LC-VCO IC in 180-nm CMOS

    Xiao Xu, Xin Yang, Toshihiko Yoshimasu

    PROCEEDINGS OF THE 2015 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC)     13 - 16  2015年  [査読有り]

     概要を見る

    An ultra-low-voltage low phase noise LC-VCO IC has been demonstrated using 180-nin CMOS technology. The LC-VCO IC includes a cross-coupled pMOSFET pair, a symmetric three-port spiral inductor, MOS varactors and buffer amplifiers. The LC-VCO IC is designed, fabricated and fully tested on wafer. The VCO IC exhibits a phase noise of -118.9 dBc/Hz at 1 MHz offset front the 2.29 GHz carrier at a supply voltage of only 0.5 V. Moreover, minimum operation voltage of only 0.25 V has been achieved.

  • Highly Linear High Isolation SPDT Switch IC with Back-gate Effect and Floating Body Technique in 180-nm CMOS

    Xiao Xu, Xin Yang, Zheng Sun, Taufiq Alif Kurniawan, Toshihiko Yoshimasu

    2015 IEEE INTERNATIONAL SYMPOSIUM ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY (RFIT)     106 - 108  2015年  [査読有り]

     概要を見る

    This paper presents a broadband single-pole double-throw (SPDT) switch IC in a 180-nm CMOS process. Back-gate voltage injection and floating body technique are utilized to improve the power handling capability, insertion loss and isolation performance, simultaneously. The fabricated SPDT switch IC has exhibited an input referred 0.3-dB compression point of 21.0 dBm, an isolation of 42.7 dB and an insertion loss of 1.1 dB for transmit mode at an operation frequency of 5.0 GHz.

  • A 2.5-GHz Band Low Voltage High Efficiency CMOS Power Amplifier IC Using Parallel Switching Transistor for Short Range Wireless Applications

    Taufiq Alif Kurniawan, Xin Yang, Xiao Xu, Toshihiko Yoshimasu

    2015 45TH EUROPEAN MICROWAVE CONFERENCE (EUMC)     219 - 222  2015年  [査読有り]

     概要を見る

    This paper presents a fully integrated low-voltage CMOS power amplifier (PA) IC for 2.5-GHz band short range wireless applications. The amplifier IC is designed, fabricated and fully evaluated in 180-nm CMOS technology. To realize high efficiency performance, the parallel switching transistor is proposed and combined with third harmonic tuning technique. In addition, for low voltage operations, the positive body bias is injected to the main switching transistor. The proposed CMOS PA IC has exhibited a P1dB of 8.0 dBm, a saturated output power of 10.1 dBm and a peak PAE of 34.5 % at a supply voltage of 1.0 V.

  • A Novel W-band Bottom-LO-Configured Sub-harmonic Mixer IC in 130-nm SiGe BiCMOS

    Xin Yang, Xiao Xu, Zheng Sun, Takayuki Shibata, Toshihiko Yoshimasu

    2015 10TH EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE (EUMIC)     172 - 175  2015年  [査読有り]

     概要を見る

    This paper presents a novel sub-harmonic mixer (SHM) IC design for W-band automotive applications in 130-nm SiGe BiCMOS technology. The SHM makes use of a Common Emitter Common Collector Transistor Pair (CECCTP) structure with bottom-LO-configuration. On-chip Marchand balun is utilized for W-band on-wafer measurement. The novel SHM exhibits a conversion gain of 3.9 dB at 80 GHz RF signal with an LO power of -7 dBm at 39.5 GHz. The mixer core consumes only 0.68 mA with a supply voltage of 3.3 V.

    DOI

  • A 2.5-GHz Band Low Voltage High Efficiency CMOS Power Amplifier IC Using Parallel Switching Transistor for Short Range Wireless Applications

    Taufiq Alif Kurniawan, Xin Yang, Xiao Xu, Toshihiko Yoshimasu

    2015 45TH EUROPEAN MICROWAVE CONFERENCE (EUMC)     219 - 222  2015年  [査読有り]

     概要を見る

    This paper presents a fully integrated low-voltage CMOS power amplifier (PA) IC for 2.5-GHz band short range wireless applications. The amplifier IC is designed, fabricated and fully evaluated in 180-nm CMOS technology. To realize high efficiency performance, the parallel switching transistor is proposed and combined with third harmonic tuning technique. In addition, for low voltage operations, the positive body bias is injected to the main switching transistor. The proposed CMOS PA IC has exhibited a P1dB of 8.0 dBm, a saturated output power of 10.1 dBm and a peak PAE of 34.5 % at a supply voltage of 1.0 V.

    DOI

  • 2.4-GHz Band Low-Voltage Class-C PMOS VCO IC with Amplitude Feedback Loop

    Xiao Xu, Xin Yang, Toshihiko Yoshimasu

    2015 ASIA-PACIFIC MICROWAVE CONFERENCE (APMC), VOLS 1-3   3  2015年  [査読有り]

     概要を見る

    A novel 2.4 GHz-band 0.5-V Class-C PMOS VCO IC with an amplitude feedback loop is proposed. The amplitude feedback loop circuit consists of a detector, an inverter and a bias control circuit. The feedback loop automatically changes the bias of LC-VCO and shifts the oscillation mode from initial Class-AB to Class-C in steady-state. The Class-C VCO IC is designed, fabricated and fully evaluated in 180-nm CMOS technology. The fabricated VCO IC has exhibited a measured phase noise of -117.4 dBc/Hz at 1 MHz offset from the 2.25 GHz carrier frequency with a supply voltage of only 0.5-V.

    DOI

  • A 0.3-V power supply 2.4-GHz-band Class-C VCO IC with amplitude feedback loop in 65-nm CMOS

    Xin Yang, Yorikatsu Uchida, Kangyang Xu, Wei Wang, Toshihiko Yoshimasu

    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING   81 ( 3 ) 583 - 591  2014年12月  [査読有り]

     概要を見る

    A Class-C voltage-control-oscillator (VCO) IC with an amplitude feedback loop for ultra-low-voltage application is proposed. The Class-C VCO consists of an LC-VCO circuit and an amplitude feedback loop to shift LC-VCO bias condition from initial Class-AB start-up to steady Class-C low current oscillation. The amplitude feedback loop is formed by a detector and a comparator with low voltage supply. The LC-VCO IC has been designed, fabricated and fully evaluated using 65-nm CMOS technology. The fabricated Class-C VCO IC exhibits a measured phase noise of 111 dBc/Hz at 1 MHz offset from the 2.43 GHz carrier frequency at a supply voltage of only 0.3 V.

    DOI

  • A 2.5-GHz Band Low-Voltage Class-E Power Amplifier IC for Short-Range Wireless Communications in 180-nm CMOS

    Xiao Xu, Zheng Sun, Kangyang Xu, Xin Yang, Taufiq Kurniawan, Toshihiko Yoshimasu

    2014 IEEE INTERNATIONAL SYMPOSIUM ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY (RFIT): SILICON TECHNOLOGY HEATS UP FOR THZ    2014年  [査読有り]

     概要を見る

    A fully integrated class-E power amplifier IC in 180-nm CMOS is presented for 2.5-GHz band short range wireless communication systems. To realize high efficiency with low operation voltage, a class-E amplifier with back gate effect has been designed, fabricated and fully evaluated. The proposed amplifier IC can operate at a supply voltage from 0.5 V to 1.5 V. The amplifier IC exhibits a P1dB of 6.9 dBm and a saturated output power of 10.7 dBm with a maximum drain efficiency of 36.4 % at a 1.0 V power supply.

  • A 2.5-GHz Band Low-Voltage High Efficiency Class-E Power Amplifier IC With Body Effect

    Taufiq Alif Kurniawan, Xin Yang, Xiao Xu, Zheng Sun, Toshihiko Yoshimasu

    2014 14TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC)     160 - 163  2014年  [査読有り]

     概要を見る

    This paper presents a fully integrated class-E power amplifier IC with body effect to achieve high efficiency and high gain at low supply voltage for 2.5-GHz band short range wireless communication systems. The class-E amplifier IC is designed, fabricated and fully evaluated in 180-nm CMOS. The proposed power amplifier IC exhibits a small-signal gain of 10.8 dB and a saturated output power of 10.8 dBm with a drain efficiency of 35.0 % at a supply voltage of only 1-V.

  • 5-GHz Band SiGe HBT Linear Power Amplifier IC With Novel CMOS Active Bias Circuit For WLAN Applications

    Xin Yang, Tsuyoshi Sugiura, Norihisa Otani, Tadamasa Murakami, Eiichiro Otobe, Toshihiko Yoshimasu

    2014 9TH EUROPEAN MICROWAVE INTEGRATED CIRCUIT CONFERENCE (EUMIC)     428 - 431  2014年  [査読有り]

     概要を見る

    This paper presents a highly linear 5-GHz band power amplifier IC with integrated novel CMOS active bias circuit in SiGe BiCMOS technology for wireless LAN applications. The power amplifier IC consists of three-stage amplifier, the CMOS active bias circuit for linearizing SiGe HBT and all matching circuits. The power amplifier IC has exhibited a measured output power of 17.0 dBm, an EVM of 0.9 % and a dc current consumption of 284 mA under 54 Mbps OFDM signal at 5.4 GHz.

  • 44-GHz, 0.5-V Compact Power Detector IC in 65-nm CMOS

    Kangyang Xu, Xin Yang, Wei Wang, Toshihiko Yoshimasu

    2014 IEEE INTERNATIONAL WIRELESS SYMPOSIUM (IWS)    2014年  [査読有り]

     概要を見る

    This paper presents an ultra-wideband and ultra-low-voltage compact power detector IC for microwave and millimeter-wave applications. The power detector circuit includes an nMOSFET differential pair with resistive feedback and a pMOSFET buffer. The power detector IC was designed, fabricated and fully evaluated using Fujitsu 65-nm CMOS technology. The detector IC exhibits an operation frequency from 100 MHz to 44 GHz at an operation voltage of only 0.5 V. In addition, the detector IC exhibits a minimum detectable power of -15 dBm with high linearity.

  • 24-80 GHz, 0.024 mm(2) Miniaturized Balun Using Defected Ground Structure for Si-based RF IC Applications

    Hang Xiao, Xin Yang, Toshihiko Yoshimasu

    2014 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC)    2014年  [査読有り]

     概要を見る

    A compact broadband balun on a silicon substrate is proposed for millimeter-wave applications. By utilizing a novel defected ground structure, it is expected that the balun exhibits an amplitude balance less than 0.5 dB and a phase balance less than 2 degrees in a frequency range from 26 GHz to 80 GHz. The insertion loss is less than 3 dB in the operational frequency band. The balun achieves a bandwidth of 108 % and the area occupies only 0.024 mm(2).

  • A 0.03mm(2) Highly Balanced Balun IC For Millimeter-Wave Applications in 180-nm CMOS

    Zheng Sun, Xiao Xu, Xin Yang, Takayuki Shibata, Toshihiko Yoshimasu

    2014 IEEE INTERNATIONAL SYMPOSIUM ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY (RFIT): SILICON TECHNOLOGY HEATS UP FOR THZ    2014年  [査読有り]

     概要を見る

    A miniaturized broadband balun IC in 180-nm CMOS is presented for millimeter-wave applications. The balun IC is designed so that high impedance ratio between the even and odd modes is achieved by utilizing Electro-magnetic solver suitable for planer structure. The fabricated balun IC in 180-nm CMOS process occupies only 0.03 mm(2). The balun IC exhibits an amplitude imbalance of less than 0.9 dB and a phase imbalance of less than 2.5 degrees in a frequency range from 20 GHz to 66 GHz.

  • 5-GHz Band SiGe HBT Linear Power Amplifier IC With Novel CMOS Active Bias Circuit For WLAN Applications

    Xin Yang, Tsuyoshi Sugiura, Norihisa Otani, Tadamasa Murakami, Eiichiro Otobe, Toshihiko Yoshimasu

    2014 44TH EUROPEAN MICROWAVE CONFERENCE (EUMC)     1372 - 1375  2014年  [査読有り]

     概要を見る

    This paper presents a highly linear 5-GHz band power amplifier IC with integrated novel CMOS active bias circuit in SiGe BiCMOS technology for wireless LAN applications. The power amplifier IC consists of three-stage amplifier, the CMOS active bias circuit for linearizing SiGe HBT and all matching circuits. The power amplifier IC has exhibited a measured output power of 17.0 dBm, an EVM of 0.9 % and a dc current consumption of 284 mA under 54 Mbps OFDM signal at 5.4 GHz.

  • 23Gbps 9.4pJ/bit 80/100GHz band CMOS transceiver with on-board antenna for short-range communication

    Kensuke Nakajima, Akihiro Maruyama, Masato Kohtani, Tsuyoshi Sugiura, Eiichiro Otobe, Jaejin Lee, Shinhee Cho, Kyusub Kwak, Jeongseok Lee, Toshihiko Yoshimasu, Minoru Fujishima

    2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)     173 - 176  2014年  [査読有り]

     概要を見る

    Fully integrated 80GHz-band and 100GHz-band transceiver ICs using 65nm CMOS technology and on-board antennas for high-speed/short-range wireless communication system are demonstrated. To realize higher speed and lower power consumption than those of a 60GHz-band standard application such as IEEE802.11ad, a simple transceiver architecture with non-coherent amplitude shift keying (ASK) modulation method using W-band (75-110GHz) is adopted. The aggregate 80/100GHz-band transceiver modules demonstrate 23Gbps over 10mm wirelessly with power consumption of 216mW. The developed transceiver modules achieve the highest speed of wireless communications above 60GHz-band and show a potential for future applications of 100Gbps high-speed shortrange communications.

  • A 2.5-GHz 1-V High Efficiency CMOS Class-E Amplifier IC Using Back-gate Voltage Injection

    Taufiq Alif Kurniawan, Xin Yang, Zheng Sun, Xiao Xu, Toshihiko Yoshimasu

    2014 ASIA-PACIFIC MICROWAVE CONFERENCE (APMC)     744 - 746  2014年  [査読有り]

     概要を見る

    In this paper, a fully integrated Class-E amplifier IC using back-gate voltage injection is designed, fabricated and fully evaluated in 0.18-mu m CMOS technology. The body effect allows to achieve high efficiency under low supply voltage by efficiently controlling threshold voltage and on-resistance of switching transistor, simultaneously. The proposed amplifier IC has exhibited an output power of 11.0 dBm and a PAE of 30.5 % at 1-V supply voltage for 2.5 GHz applications.

  • 2-GHz Band Ultra-Low-Voltage LC-VCO IC in 130nm CMOS Technology

    Xin Yang, Kangyang Xu, Wei Wang, Yorikatsu Uchida, Toshihiko Yoshimasu

    2013 IEEE INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC)    2013年  [査読有り]

     概要を見る

    An ultra-low-voltage LC-VCO IC has been demonstrated using 130nm CMOS technology. The LC-VCO IC includes a cross-coupled nMOSFET pair, a spiral inductor, MOS varactors and a buffer amplifier. The LC-VCO IC is designed, fabricated and fully evaluated on wafer. The VCO IC exhibits a phase noise of -137 dBc/Hz at 1 MHz offset from the 2.2 GHz carrier at a supply voltage of only 0.5 V.

  • W-band ultra-low-power sub-harmonic mixer for automotive radar in 65nm CMOS

    Xin Yang, Wei Wang, Kangyang Xu, Takayuki Shibata, Toshihiko Yoshimasu

    IEEE Region 10 Annual International Conference, Proceedings/TENCON     325 - 327  2013年  [査読有り]

     概要を見る

    This paper presents novel sub-harmonic mixer topologies for W-band automotive radar applications in 65nm CMOS technology. Working principle and performance of three kinds of topologies are analyzed and discussed with physical layout and EM simulation. The simulated performance shows a double side band noise figure of 20.8 dB and a voltage conversion gain of -8.7 dB at an RF frequency of 79.0001 GHz and a LO frequency of 39.5 GHz. The dc power consumption is only 10.4μW. © 2013 IEEE.

    DOI

  • 2.4 GHz-Band Ultra-Low-Voltage Class-C LC-VCO IC in 65 nm CMOS Technology

    Xin Yang, Yorikatsu Uchida, Kangyang Xu, Wei Wang, Toshihiko Yoshimasu

    2013 ASIA-PACIFIC MICROWAVE CONFERENCE PROCEEDINGS (APMC 2013)     325 - 327  2013年  [査読有り]

     概要を見る

    A novel LC-VCO IC is proposed to achieve low-voltage low-power operation even at a supply voltage below the threshold voltage. The LC-VCO consists of a VCO circuit, a power detector circuit and a comparator circuit. A feedback loop consisting of the power detector and the comparator can control the bias condition of the VCO. The LC-VCO IC has been designed, fabricated and fully evaluated using 65 nm CMOS technology. The fabricated VCO IC exhibits a measured phase noise of -111 dBc/Hz at 1 MHz offset from the 2.43 GHz carrier frequency at an operation voltage of only 0.3 V.

  • A low-power 71GHz-band CMOS transceiver module with on-board antenna for multi-Gbps wireless interconnect

    Kensuke Nakajima, Akihiro Maruyama, Tadamasa Murakami, Masato Kohtani, Tsuyoshi Sugiura, Eiichiro Otobe, Jaejin Lee, Shinhee Cho, Kyusub Kwak, Jeongseok Lee, Minoru Fujishima, Toshihiko Yoshimasu

    2013 ASIA-PACIFIC MICROWAVE CONFERENCE PROCEEDINGS (APMC 2013)     357 - 359  2013年  [査読有り]

     概要を見る

    Fully integrated millimeter-wave transceiver ICs using 65nm CMOS technology and on-board antenna for high-speed/short-range wireless communication system are described. To realize high-speed and low power consumption for a mobile application, a simple transceiver architecture with non-coherent amplitude shift keying (ASK) modulation method is adopted. The transceiver ICs are flip-chip bonded on boards and connected with on-board antenna for a simple and low cost transceiver system. The developed transceiver system module demonstrates 5Gbps/3.8Gbps at wireless communication range of 5mm/10mm and power consumption of 79.6mW with a carrier frequency of 71GHz. To our best knowledge, this is the first report of a millimeter-wave, above 60GHz, CMOS transceiver module with on-board antenna for a high-speed/short-range wireless communication system.

  • A CMOS Class-G Supply Modulation for Polar Power Amplifiers with High Average Efficiency and Low Ripple Noise

    Qing Liu, Jiangtao Sun, YongJu Suh, Nobuyuki Itoh, Toshihiko Yoshimasu

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E95A ( 2 ) 487 - 497  2012年02月  [査読有り]

     概要を見る

    In this paper, a CMOS Class-G supply modulation for polar power amplifiers with high average efficiency and low ripple noise is proposed. In the proposed Class-G supply modulation, the parallel supply modulations which are controlled by switch signals are utilized for low power and high power supplies to increase the average efficiency. A low dropout (LDO) is utilized to suppress the delta-modulated noise and provide a low ripple noise power supply. The proposed supply modulation has high efficiency at large output current as the conventional supply modulation, and it also has high efficiency and low ripple noise at the low output current. To verify the effectiveness of the proposed supply modulation, the proposed supply modulation was designed with 0.13 mu m CMOS process. The simulation results show that the proposed supply modulation achieves a maximum efficiency of 85.1%. It achieves an average efficiency of 29.3% and a 7.1% improvement compared with the conventional supply modulations with Class-E power amplifier. The proposed supply modulation also shows an excellent spurious free dynamic range (SFDR) of -73 dBc for output envelope signal.

    DOI

  • 5.25 GHz linear CMOS power amplifier with a diode-connected NMOS bias circuit

    Shihai He, Yorikatsu Uchida, Xin Yang, Qing Liu, Toshihiko Yoshimasu

    2012 International Conference on Microwave and Millimeter Wave Technology, ICMMT 2012 - Proceedings   5   1912 - 1915  2012年

     概要を見る

    In this paper, a 5.25GHz linear CMOS power amplifier (PA) with an integrated diode is presented. The proposed technique improves the linearity of the power amplifier by a diode-connected NMOS transistor. The NMOS diode is effective to suppress both the AM-AM distortion and AM-PM distortion. To verify this concept, the power amplifier is simulated with TSMC 0.13-μm CMOS process. With a power supply of 3.3 V, the proposed power amplifier exhibits a maximum IMD improvement of 25 dB with a PAE of 38.2 % at an output P1dB of 19.6 dBm. © 2012 IEEE.

    DOI

  • Low-power ultra-wideband power detector IC in 130 nm CMOS technology

    Xin Yang, Yorikatsu Uchida, Qing Liu, Toshihiko Yoshimasu

    IEEE MTT-S International Microwave Workshop Series on Millimeter Wave Wireless Technology and Applications, IMWS 2012 - Proceeding     52 - 55  2012年

     概要を見る

    This paper presents a low operation voltage ultrawideband power detector IC for microwave and millimeter-wave applications. The power detector circuit includes an nMOS transistor differential pair with a resistive feedback. The power detector IC was designed and fabricated using TSMC 130 nm CMOS technology. The detector IC exhibits an operation frequency from 100 MHz to 40 GHz at an operation voltage of 0.6 to 1.2 V. The minimum detectable power is -16 dBm at 40 GHz with a dc power consumption of only 0.116 mW. © 2012 IEEE.

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  • 5-GHz Band Linear CMOS Power Amplifier IC with a Novel Integrated Linearizer for WLAN Applications

    Yorikatsu Uchida, Shihai He, Xin Yang, Qing Liu, Toshihiko Yoshimasu

    PROCEEDINGS OF THE 2012 IEEE INTERNATIONAL SYMPOSIUM ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY (RFIT)     240 - 242  2012年  [査読有り]

     概要を見る

    In this paper, novel linearization technique is proposed to realize a 5-GHz band linear CMOS power amplifier IC for WLAN application. The novel linearizer which consists of a diode-connected PMOS bias circuit and a PMOS varactor connected in parallel with an NMOS amplifier is effectively to suppress the gain compression and phase distortion of the power amplifier. A CMOS power amplifier IC is designed, fabricated and fully tested using TSMC 0.13-mu m CMOS technology. With these proposed techniques, the measurement results show a third-order IMD improvement of 9 dB over wide output power range and the maximum improvement of 18 dB. The power amplifier IC exhibits an output P1dB of 19.5 dBm and a power gain of 9.5 dB at an operation voltage of 3.3 V.

  • A High Efficiency Linear CMOS Power Amplifier for 5.8 GHz Dedicated Short Range Wireless Communication Systems

    Y. Suh, S. He, Q. Liu, K. Horie, T. Yoshimasu

    International Conference on Solid State Devices and Materials (SSDM)     1085 - 1086  2011年09月

  • A 66-dBc Fundamental Suppression Frequency Doubler IC for UWB Sensor Applications

    Jiangtao Sun, Qing Liu, Yong-Ju Suh, Takayuki Shibata, Toshihiko Yoshimasu

    IEICE TRANSACTIONS ON ELECTRONICS   E94C ( 4 ) 575 - 581  2011年04月  [査読有り]

     概要を見る

    A balanced push-push frequency doubler has been demonstrated in 0.25-mu m SOI (Silicon on Insulator) SiGe BiCMOS technology operating from 22 GHz 10 29 GHz with high fundamental frequency suppression and high conversion gain. A series LC resonator circuit is connected in parallel with the differential outputs of the doubler core circuit. The LC resonator is effective to improve the fundamental frequency suppression. In addition, the LC resonator works as a matching circuit between the output of the doubler core and the input of the output buffer amplifier, which increases the conversion gain of the whole circuit. A measured fundamental frequency suppression of greater than 46 dBc is achieved at an input power of -10 dBm in the output frequency band of 22-29 GHz. Moreover, maximum fundamental frequency suppression of 66 dBc is achieved at an input frequency of 13 GHz and an input power of -10 dBm. The frequency doubler works at a supply voltage of 3.3 V.

    DOI

  • A Novel Variable Inductor Uisng A Triple Transformer and MOS Switches in 0.13um CMOS Technology

    J. Sun, S. He, X. Zhu, Q.Liu, T. Yoshimasu

    China-Japan Joint Microwave Conference     296 - 299  2011年04月

  • Compact Broadband Marchand Bulun with Excellent Imbalance Performance for Si-Based Millimeter Wave IC Applications

    J. Sun, S. He, Q. Liu, H. Liu, T. Yoshimasu

    China-Japan Joint Microwave Conference     401 - 404  2011年04月

  • A 1.2-3.2 GHz CMOS VCO IC Utilizing Transformer-Based Variable Inductors and AMOS Varactors

    Qing Liu, Yusuke Takigawa, Satoshi Kurachi, Nobuyuki Itoh, Toshihiko Yoshimasu

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E94A ( 2 ) 568 - 573  2011年02月  [査読有り]

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  • A Broadband High Suppression Frequency Doubler IC for Sub-Millimeter-Wave UWB Applications

    Jiangtao Sun, Qing Liu, Yong-Ju Suh, Takayuki Shibata, Toshihiko Yoshimasu

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E94A ( 2 ) 603 - 610  2011年02月  [査読有り]

    DOI

  • A high efficiency and high linearity power amplifier utilizing postlinearization technique for 5.8 GHz DSRC applications

    Qing Liu, Sun Jiangtao, Yong Ju Shu, Koji Horie, Nobuyuki Itoh, Toshihiko Yoshimasu

    2011 IEEE Radio and Wireless Week, RWW 2011 - 2011 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications, PAWR 2011     45 - 48  2011年

     概要を見る

    In this paper, a post-linearization technique of cascode CMOS power amplifier is presented. The proposed method adopts two cascode FET, one operates in class AB mode and the other works near class B mode, which absorbs the nonlinear current of third-order intermodulation distortion (IMD). The proposed method is investigated for 5.8 GHz Dedicated Short Range Communication (DSRC) applications, and fabricated by 0.13 μm CMOS process. The measured results show that the proposed power amplifier exhibited a power gain of 11.5 dB, an output power of 1 dB compression point (P1dB) of 17.3 dBm, a power added efficiency (PAE) of 32% at P1dB with a low voltage operation of 2.0 V. The improvement in IMD of 6 dB over large output power range and a maximum improvement of 12 dB were achieved. © 2011 IEEE.

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  • An ultra low power consumption and low phase noise VCO operating in sub-threshold region

    Qing Liu, Yu Zhao, Jiangtao Sun, Satoshi Kurachi, Nobuyuki Itoh, Toshihiko Yoshimasu

    Conference Proceedings of the International Symposium on Signals, Systems and Electronics   1   257 - 260  2010年

     概要を見る

    In this paper, a voltage controlled oscillator (VCO) with ultra low dc power consumption and low phase noise is proposed for 2.4 GHz Bluetooth. To reduce the dc power consumption, a novel bias circuit is proposed instead of a conventional tail-current circuit to decrease the supply voltage. In addition, the proposed VCO is designed to operate in sub-threshold region for decreasing the operation current. Thus, the dc power consumption is largely reduced. To improve the phase noise, a modified LC-tank is proposed to suppress the harmonic noise modulation and to prevent the phase noise degradation by the down-converted Flick noise. The LC-VCO is simulated using 0.11 μm CMOS technology. The simulation results show a phase noise of -115dBc/Hz at 1MHz offset from the 2.4 GHz carrier frequency with only 0.35 mW power consumption. © 2010 IEEE.

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  • A Low DC Power High Conversion Gain Frequency Doubler IC for 22-29GHz UWB Applications

    Jiangtao Sun, Qing Liu, Yong-Ju Suh, Takayuki Shibata, Toshihiko Yoshimasu

    2010 ASIA-PACIFIC MICROWAVE CONFERENCE     944 - 947  2010年  [査読有り]

     概要を見る

    A balanced frequency doubler has been measured fundamental frequency suppression demonstrated in 0.25-mu m SOI SiGe BiCMOS technology operating from 22GHz to 29GHz with high fundamental frequency suppression and high conversion gain. A LC resonator circuit is designed to improve the suppression and conversion gain. The measured fundamental frequency suppression of greater than 45dBc is achieved at an input power of -9dBm in the 22-29GHz. Moreover, measured maximum conversion gain of 12.6dB is obtained at an input power of -19dBm. The frequency doubler works on 3.3V and doubler core only consumes 7.9mW DC power.

  • A 92.6 % Tuning Range VCO Utilizing Simultaneously Controlling of Transformers and MOS Varactors in 0.13 um CMOS Technology

    Y. Takigawa, H. Ohta, Q. Liu, S. Kurachi, N. Itoh, T. Yoshimasu

    IEEE RF IC Symposium Technical Digest     83 - 86  2009年06月

  • 24-52 GHz, 0.03mm2 Broadband Balun Using Defected Ground Structure for Si-Based RF IC Applications

    Jiang-Tao Sun, Qing Liu, Toshihiko Yoshimasu, Haiwen Liu

    Global Symposium on Millimeter Waves    2009年04月

  • A 92.6 % Tuning Range VCO Utilizing Simultaneously Controlling of Transformers and MOS Varactors in 0.13 mu m CMOS Technology\

    Yusuke Takigawa, Hiroshi Ohta, Qing Liu, Satoshi Kurachi, Nobuyuki Itoh, Toshihiko Yoshimasu

    RFIC: 2009 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM     71 - +  2009年  [査読有り]

     概要を見る

    A novel resonant circuit consisting of transformer-based variable inductors and MOS varactors is proposed to implement an ultra-wideband voltage-controlled-oscillator (VCO). The VCO is designed and fabricated using 0.13 mu m CMOS, and fully evaluated on wafer. The VCO IC exhibits a frequency tuning range as high as 92.6 % spanning from 1.2 GHz to 3.27 GHz. The measured phase noise of -120 dBc/Hz at 1 MHz offset from the 3.1 GHz carrier is obtained.

  • A Novel Current Reuse Wideband Amplifier using 130 nm Si CMOS Technology for 22-29 GHz Applications

    Q. Liu, J. Sun, Y. J. Suh, S. Kurachi, N. Itoh, T. Yoshimasu

    2009 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLUMES I & II     807 - +  2009年  [査読有り]

     概要を見る

    In this paper, a novel wideband amplifier is proposed for 22 - 29 GHz UWB applications in 0.13 um Si CMOS technology. In order to reduce the dc current of the amplifier, a novel current reuse technique is adopted in a cascode CMOS transistor. In addition, a low-pass type feedback circuit for the first stage and an inductive feedback circuit for the second stage are designed to make the bandwidth wider. It is expected that the wideband amplifier exhibits a gain of 11.3 dB +/- 1.2 dB with a dc power consumption as low as 9.8 mW.

  • 15 GHz-Band Low Phase-Noise LC-VCO with Second Harmonic Tunable Filtering Technique

    Qing Liu, Jiangtao Sun, Toshihiko Yoshimasu, Satoshi Kurachi, Nobuyuki Itoh

    2009 IEEE 20TH INTERNATIONAL SYMPOSIUM ON PERSONAL, INDOOR AND MOBILE RADIO COMMUNICATIONS     1592 - 1595  2009年  [査読有り]

     概要を見る

    In this paper, a novel technique is proposed to improve the phase-noise of an LC-VCO. The LC-VCO includes two series LC second harmonic filters which consist of a spiral inductor and two varactors. The resonant frequency of the series LC filter is tunable with the control voltage, and the resonator largely prevents the noise modulation in the LC-VCO, improving the phase-noise of the LC-VCO with wide frequency range. The LC-VCO is fabricated using 0.13 mu m CMOS technology, and fully evaluated on wafer. The measured phase-noise of - 112dBc/Hz at 1MHz offset from the 15 GHz carrier is obtained.

  • A Switched-Inductor Based VCO with An Ultra-Wideband Tuning Range of 87.6%

    Liu Qing, Sun Jiangtao, Satoshi Kurachi, Nobuyuki Itoh, Toshihiko Yoshimasu

    2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS     355 - +  2009年  [査読有り]

     概要を見る

    A novel switched-inductor based resonator is proposed to implement an ultra-wideband VCO. The VCO is designed and fabricated using 0.13 mu m CMOS and fully evaluated on wafer. The measured results show that the proposed VCO has a tuning range as high as 87.6% spanning from 1.81 GHz to 4.63 GHz. The measured phase noise of -124.4 dBc/Hz at 1 MHz offset from the 1.81 GHz carrier is obtained(1).

  • Fully-Integrated Novel High Efficiency Linear CMOS Power Amplifier for 5.8 GHz ETC Applications

    YongJu Suh, Jiangtao Sun, Koji Horie, Nobuyuki Itoh, Toshihiko Yoshimasu

    APMC: 2009 ASIA PACIFIC MICROWAVE CONFERENCE, VOLS 1-5     365 - +  2009年  [査読有り]

     概要を見る

    A fully integrated novel power amplifier (PA) using 130nm CMOS process is presented for Electric Toll Collection (ETC) applications. To obtain good efficiency and high linear gain performance, a novel cascode PA based on a class E PA has been designed, fabricated and fully measured. The proposed PA is a single-ended single-stage amplifier at an operating voltage of only 2 V. The power added efficiency (PAE) of the PA is as high as 42.6% with a gain of 11.4dB at P1dB of 13.4dBm. This CMOS PA includes all matching circuits and biasing circuits, and no external components are required.

  • A 22-30GHz Balanced SiGe BiCMOS Frequency Doubler with 47dBc Suppression and Low Input Drive Power

    Jiangtao Sun, Qing Liu, Yong-Ju Suh, Takayuki Shibata, Toshihiko Yoshimasu

    APMC: 2009 ASIA PACIFIC MICROWAVE CONFERENCE, VOLS 1-5     2260 - +  2009年  [査読有り]

     概要を見る

    A broadband balanced frequency doubler has been fabricated in 0.25-mu m SOI SiGe BiCMOS technology to operate from 22GHz to 30GHz with low input drive power. Its fundamental frequency suppression of better than 30dBc can be achieved by an internal low pass LC filter in the 22-30GHz; moreover, maximum suppression is 47dBc in the operation band. In addition, a pair of SLCC (Series LC Circuit) parallel with the up input can result in high suppression with low input drive power. Maximum conversion gain of -6dB can be obtained in the input drive power as low as -1dBm.

  • MOSFETとpn接合ダイオードにより構成される新しいバラクタ回路を用いた広帯域電圧制御発振器

    太田 宙志, 吉増 敏彦, 倉智 聡, 伊藤 信之, 米村 浩二

    電子情報通信学会論文誌 和文誌C   Vol.J91-C ( No.12 ) 702 - 710  2008年12月

  • A 5.5-Ghz SiGe HBT Doherty amplifier using diode linearizer and lumped-element hybrid coupler

    Haiwen Liu, Toshihiko Yoshimasu

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS   50 ( 6 ) 1554 - 1558  2008年06月

     概要を見る

    A 5.5-GHz Doherty amplifier using commercial 0.35-mu m SiGe HBT technology is proposed in this article. To improve the linearity, a predistortion using diode linearizer is adopted for biasing the peak amplifier. Moreover, to realize in fully on-chip with circuit reduction, a 90 degrees 3-dB hybrid coupler and quarter-wave transmission lines are implemented by lumped-elements. In this design, 819 mu m(2) HBTs are used for carried and peak amplifiers, respectively, and 26 mu m(2) HBT is used for linearizer. Results verify that the power gain, P(1dB), and power added efficiency (PAE) of the proposed Doherty amplifier at 5.5 GHz are 8.4 dB, 31 dBm, and 30%, respectively. Also, the adjacent channel power ratio (ACPR) and the output signal&apos;s spectrum mask are given using the 54Mcps 64QAM modulated signal at 10 MHz offset. (c) 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1554-1558, 2008.

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  • High Dynamic Range Variable Gain Amplifier Using 130 nm CMOS Technology for Triple-Band W-CDMA Applications

    S. YongJu, S. Ishikawa, H. Ohta, R. Fujimoto, N. Itoh, T. Yoshimasu

    International Conference on Microwave and Millimeter Wave Technology    2008年04月

  • Bow-tie loop printed antenna with high gain and broad beam width for 5.8GHz rectenna application

    Jiang-Tao Sun, Xue-Xia Yang, Toshihiko Yoshimasu, Xiao-Meng Sun

    2008 4th IEEE International Conference on Circuits and Systems for Communications, ICCSC     312 - 314  2008年

     概要を見る

    The bow-tie loop printed antenna with high gain and broad beam width for 5.8GHz rectenna application is proposed, analyzed and measured. The high gain of 9.5 dBi can receive more power in a certain power density. And the broad beam width with 90 degrees HPBW (Half Power Beam Width) is able to avoid the precise main beam alignment. The proposed antenna still has the cross polarization level more than 30 dB, and the front-to-back ratio is about -20dB in the broadside direction. The details of the simulated and experimental results for the proposed design are presented and discussed. ©2008 IEEE.

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  • Miniaturized microstrip meander-line antenna with very high-permittivity substrate for sensor applications

    Haiwen Liu, Shohei Ishikawa, An An, Satoshi Kurachi, Toshihiko Yoshimasu

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS   49 ( 10 ) 2438 - 2440  2007年10月  [査読有り]

     概要を見る

    This article presents a compact microstrip meander-line antenna for sensor network applications in the 290 MHz band. The antenna is fed by coplanar waveguide and its dimension is 15 mm x 15 mm x 2 mm. Because of the use of a very high relative permittivity substrate (epsilon(r) = 90) and meander-line structure simultaneously, the side length of the designed antenna is about lambda(g)/12 (lambda(g) is the guided wavelength) so that the circuit size is reduced greatly. Measurements verify that the proposed antenna has bandwidth of 12% at the resonant frequency of 293 MHz. Also the radiation patterns measured at resonance frequencies are very close to omnidirectional in the E-plane. (C) 2007 Wiley Periodicals, Inc.

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  • An Ultra-Wideband Amplifier MMIC for 3-10.6 GHz Wireless Applications with InGaP/GaAs HBT Technology

    S. Kurachi, T. Yoshimasu, H. Liu, J. Chen, Y. Shimamatsu

    電気学会論文誌C   Vol. 127 ( No.8 ) 1194 - 1198  2007年08月

  • A SiGeBiCMOS VCOIC with highly linear kvco for 5-GHz-Band wireless LANs

    Satoshi Kurachi, Toshihiko Yoshimasu, Haiwen Liu, Nobuyuki Itoh, Koji Yonemura

    IEICE TRANSACTIONS ON ELECTRONICS   E90C ( 6 ) 1228 - 1233  2007年06月  [査読有り]

     概要を見る

    A 5-GHz-band highly linear frequency tuning voltage-controlled oscillator (VCO) using 0.35 mu m SiGe BiCMOS technology is presented. The highly linear VCO has a novel resonant circuit that includes two spiral inductors, p-n junction diode varactor units and a voltagelevel- shift circuit. The fabricated VCO exhibits a VCO gain from 224 to 341 MHz/V, giving a Kvco ratio of 1.5, which is less than one-half of that of a conventional VCO. The measured phase noise is -116 dBc/Hz at 1MHz offset at an oscillation frequency of 5.5 GHz. The tuning range is from 5.45 to 5.95 GHz. The de current consumption is 3.4 mA at a supply voltage of 3.0 V.

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  • 5-GHz band highly linear VCOIC with a novel resonant circuit

    Satoshi Kurachi, Toshihiko Yoshimasu, Nobuyuki Itoh, Koji Yonemura

    2007 TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS, DIGEST OF PAPERS     285 - +  2007年  [査読有り]

     概要を見る

    This paper presents a 0.35-mu m SiCt BiCMOS VCO IC exhibiting a linear VCO gain (Kvco) for 5-GHz band application. To realize a linear Kvco, a novel resonant circuit is proposed. The measured Kvco changes from 224 MHz/V to 341 MHz/V The ratio of the maximum Kvco to the minimum one is 1.5 which is less than one-half of that of a conventional VCO. The VCO oscillation frequency range is from 5.45 GHz to 5.95 GHz, the tuning range is 8.8 % and the do current consumption is 3.4 mA at a supply voltage of 3.0 V The measured phase noise is -116 dBc/Hz at 1MHz offset, which is similar to the conventional VCO.

  • One- and two-dimensional coplanar waveguide structures with multiple-frequency-tuned slot resonators

    H. Liu, T. Yoshimasu, L. Sun

    INTERNATIONAL JOURNAL OF ELECTRONICS   94 ( 10 ) 897 - 903  2007年  [査読有り]

     概要を見る

    In this letter, a new multiple-frequency-tuned slot resonator is introduced in coplanar waveguide (CPW) technology. Its equivalent circuit model is built up and its frequency characteristics are explained by employing the equivalent circuit parameters and field analysis. Furthermore, one-dimensional (1-D) and 2-D CPW structures with the proposed slot resonator are designed. Measurements show that the proposed CPW structures with compact size exhibit good multiple-stopband behaviours.

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  • A 4-GHz band ultra-wideband voltage controlled oscillator IC using 0.35 mu m SiGeBiCMOS technology

    Satoshi Kurachi, Yusuke Murata, Shohei Ishikawa, Nobuyuki Itoh, Koji Yonemura, Toshihiko Yoshimasu

    PROCEEDINGS OF THE 2007 IEEE BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING (BCTM)     9 - +  2007年  [査読有り]

     概要を見る

    This paper presents an ultra-wideband voltage controlled oscillator (VCO) IC using 0.35 mu m SiGe BiCMOS technology. The VCO IC exhibits an oscillation frequency from 2.67 to 4.37 GHz. To realize the wideband tuning range, a novel resonant circuit is proposed. The novel resonant circuit consists of three NMOS varactor pairs, p-n diodes, two spiral inductors and a control circuit which sequentially applies a control voltage to the NMOS varactor pairs and p-n diode pairs. The novel resonant circuit allows the VCO IC to have the wideband tuning range with a single analog control voltage. The dc current consumption of the VCO is 5.8 mA at a collector voltage of 4.0 V. The VCO has a phase noise of -111 dBc/Hz at 1 MHz offset at an oscillation frequnecy of 4.37 GHz.

  • Slot resonator-based electromagnetic bandgap coplanar waveguide and its filter application

    Haiwen Liu, Lingling Sun, Toshihiko Yoshimasu

    PHYSICS LETTERS A   359 ( 3 ) 171 - 174  2006年11月  [査読有り]

     概要を見る

    One-dimensional (1-D) slot resonator-based electromagnetic bandgap coplanar waveguide (SR-EBG-CPW) is proposed in this Letter. First, the SR-EBG-CPW unit cell is discussed and exhibits bandstop performance without any periodic structure. Then, its circuit model is extracted from the full-wave simulations and the frequency characteristics are explained by employing the equivalent circuit parameters and field analysis. Finally, a miniaturized bandstop filter with SR-EBG-CPW is presented and fabricated. Measurement shows that the designed filter provides good bandstop and slow-wave performances as predicted and has potential applications to compact microwave designs. (c) 2006 Published by Elsevier B.V.

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  • Compact slot resonator-based photonic bandgap for coplanar waveguide and its application to bandstop filter

    Haiwen Liu, Toshihiko Yoshimasu, Satoshi Kurachi, Weiliang Hu, Koichi Yomaoka, Lingling Sun

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS   48 ( 8 ) 1602 - 1606  2006年08月  [査読有り]

     概要を見る

    One-dimensional slot resonator-based photonic bandgap for coplanar waveguide (SR-PBG-CPW) is proposed in this paper. The SR-PBG-CPW unit is realized by replacing the conventional rectangular holes on ground plane with a slot resonator. The proposed SR-PBG-CPW unit exhibits more excellent bandgap and slow-wave characteristics and better selectivity at cut off frequency than the conventional PBG-CPW unit. Furthermore, the SR-PBG-CPW is applied effectively to design a bandstop, filter. Comparison between simulations and measurement confirms the validity of the proposed filter configuration and design procedure. (c) 2006 Wiley Periodicals, Inc.

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  • A novel diode linearizer for SiGe HBT power amplifier

    Haiwen Liu, Toshihiko Yoshimasu, Satoshi Kurachi, Nobuyuki Ito, Koji Yonemura

    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS   48 ( 8 ) 1535 - 1537  2006年08月  [査読有り]

     概要を見る

    In this paper, a novel diode linearizer to keep the base voltage of SiGe HBT power amplifier (PA) constant in the large-signal region is introduced. The results show that the output P(IdB), and power-added efficiency (PAE) are improved by 4.9 dBm and 22.8%, respectively. At an input power of 20 dBm, the gain compression and phase distortion of the linearized PA is 2.1 dB and 1.1 degrees, respectively, compared with 5.0 dB and 20.4 degrees for the conventional PA. Also, the improved ACPR is given. (c) 2006 Wiley Periodicals, Inc.

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  • An Ultra-Wideband and Low-Power Amplifier Using 0.35 um SiGe BiCMOS Technology

    J. Chen, T. Yoshimasu, W. Hu, H. Liu, N. Itoh, K. Yonemura

    International Conference on Communications, Circuits and Systems    2006年06月

  • A Low Phase Noise MMIC VCO in InGaP/GaAs HBT

    Satoshi Kurachi, Haiwen Liu, Jia Chen, Toshihiko Yoshimasu

    International Journal of Microwave and Optical Technology   1 ( 2 ) 422 - 428  2006年06月

  • Ultra-Wideband SiGe VCO with a Novel Resonant Circuit

    S. Kurachi, M. Nakashima, T. Yoshimasu, N. Itoh, K. Yonemura

    International Conference on Computer and Communication Engineering     1269 - 1271  2006年05月

  • CPW bandstop filter using periodically loaded slot resonators

    HW Liu, T Yoshimasu, LL Sun

    ELECTRONICS LETTERS   42 ( 6 ) 352 - 353  2006年03月  [査読有り]

     概要を見る

    A new dual-spiral-shaped slot resonator in a coplanar waveguide (CPW-DSR) is studied. Also, its equivalent circuit model is introduced and used for multi-resonant performance analysis. Finally, a bandstop filter using periodically loaded CPW-DSRs is presented and verified by simulations and measurement.

    DOI

  • Propagation characteristics of microstrip lines with 2D defected ground structures

    H. Liu, X. Sun, Z. Li, T. Yoshimasu

    International Journal of RF and Microwave Computer-Aided Engineering, Wiley InterScience     280 - 286  2006年02月

  • An ultra-wideband and low-power amplifier using 0.35-μm SiGe BiCMOS technology

    Jia Chen, Toshihiko Yoshimasu, WeiLiang Hu, Haiwen Liu, Nobuyuki Itoh, Koji Yonemura

    2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings   4   2614 - 2617  2006年

     概要を見る

    We propose a unique wideband amplifier configuration. The new configuration adopts an improved Darlington amplifier to broaden the bandwidth and flatten the output gain. The low power consumption and matched impedances are also achieved in our amplifier. This circuit has been realized using Toshiba 0.35μm SiGe BiCMOS technology with the fT of 30GHz. The simulation result of the presented amplifier demonstrates 1-10GHz bandwidth and 11.3-dB maximum forward gain (S21) with less than ±0.5-dB gain flatness while it drains 8mA from a 3-V supply. A 1-dB compression point and an DP3 of -12.5dBm and 6dBm respectively also have been reported in this paper. © 2006 IEEE.

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  • A novel dual-mode square loop passband filter with second spurious passband suppression

    Weiliang Hu, Toshihiko Yoshimasu, Haiwen Liu

    2006 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1-4     2273 - 2276  2006年  [査読有り]

     概要を見る

    A novel microstrip dual-mode square loop bandpass filter with suppressed spurious passband is proposed. The degenerate modes are splitted by the embedded spur-lines easily. The spur-lines embedded in the output line suppress the second spurious passband effectively. The two-pole dual-mode filter operating at 2.59GHz with fractional bandwidth of 4.63% is designed, fabricated, and measured. The measured harmonic suppression ratio &gt; 20dB is obtained.

  • A novel microstrip meander-line antenna with a very high relative permittivity substrate for 315-MHz band applications

    An An, Toshihiko Yoshimasu, Kouichi Yamaoka, Satoshi Kurachi

    2006 7TH INTERNATIONAL SYMPOSIUM ON ANTENNAS, PROPAGATION AND EM THEORY, VOLS 1 AND 2, PROCEEDINGS     13 - 15  2006年  [査読有り]

     概要を見る

    This paper presents a design, simulation, implementation and measurement of a novel microstrip meander patch antenna for the application of sensor networks. The dimension of the microstrip chip antenna is 15mm X 15mm X 2mm. The meander-type radiating patch is constructed on the upper layer of the 2mm height substrate with 0.0 5mm height metallic conduct lines. Because of using the very high relative permittivity substrate (epsilon(r) = 90), the proposed antenna achieves 315MHz band operations.

  • Characteristic impedance of slow-wave microstrip lines with defected ground structure

    H.Liu, T. Yoshimasu, S. Kurachi, J. Chen

    International Symposium on Microwave and Optical Technology    2005年08月

  • A wide band amplifier MMIC with InGaP/GaAs HBT technology

    S. Kurachi, J. Chen, Y. Shimamatsu, H. Liu, T. Yoshimasu

    International Symposium on Microwave and Optical Technology    2005年08月

  • A low phase noise MMIC VCO in InGaP/GaAs HBT

    S. Kurachi, H. Liu, J. Chen, T. Yoshimasu

    International Symposium on Microwave and Optical Technology    2005年08月

  • Low phase noise, InGaP/GaAs HBT VCO MMIC for millimeter-wave applications

    S Kurachi, T Yoshimasu

    IEICE TRANSACTIONS ON ELECTRONICS   E88C ( 4 ) 678 - 682  2005年04月  [査読有り]

     概要を見る

    A fully integrated voltage controlled oscillator (VCO) MMIC for millimeter-wave applications has been designed and implemented in InGaP/GaAs heterojunction bipolar transistor (HBT) technology. To achieve a fully integrated VCO, a base-emitter diode is employed as the tuning varactor, and microstrip lines are employed for the transmission lines. The fabricated VCO MMIC chip size is 0.86 turn x 1.34 nun and delivers an output power of 5.1 dBm at 28.7 GHz and a free-running phase noise of - 118 dBc/Hz at 1 MHz offset. The dc current consumption is only 20 mA.

    DOI

  • Comparison of Energy Efficiency between Thin-Film Transistors and Single-Crystalline Silicon MOSFETs Considering Manufacture Energy

    N. Yamauchi, T. Yoshimasu, K. Kugimiya

    1st International TFT Conference Proceedings    2005年04月

  • A novel microstrip diplexer design using defected ground structure

    HW Liu, T Yoshimasu, S Kurachi, J Chen, ZF Li, XW Sun

    2005 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS     1099 - 1100  2005年  [査読有り]

     概要を見る

    A simple microstrip diplexer using defected groundstructure(DGS) is described in this letter. The diplexer has been designed, fabricated, and measured. Results show the new diplexer exhibits an isolation of greater than 26dB between channels.

  • Bandstop response of microstrip lines with periodic defected ground structures

    HW Liu, T Yoshimasu, S Kurachi, J Chen

    2005 SBMO/IEEE MTT-S International Microwave and Optoelectronics Conference (IMOC)     153 - 155  2005年  [査読有り]

     概要を見る

    A fast and direct method to estimate the stopband in microstrip lines with periodic defected ground structures(DGS) is introduced in this paper. Based on the equivalent circuit of single DGS unit, an approximate relationship between the stopband and DGS circuit dimensions is set up. Comparison between the estimated results and simulated results based on field analysis methods verifies the validity of the proposed method.

  • A low-kickback-noise latched comparator for high-speed flash analog-to-digital converters

    J Chen, S Kurachi, SM Shen, HW Liu, T Yoshimasu, YJ Suh

    INTERNATIONAL SYMPOSIUM ON COMMUNICATIONS AND INFORMATION TECHNOLOGIES 2005, VOLS 1 AND 2, PROCEEDINGS     250 - 253  2005年  [査読有り]

     概要を見る

    In traditional comparators especially for flash ADCs, one serious problem is the kick back noise, which disturbs the input signal voltages and consequently might cause errors at the outputs of the ADCs. In this paper, we propose a novel CMOS latched comparator with very low kickback noise for high-speed flash ADCs. The proposed comparator separates analog preamplifier from the positive feedback digital dynamic latch so as to reduce the influence of the kickback noise. Simulation results based on a mixed signal CMOS 0.35um technology show that, this comparator can work at a maximum clock frequency of 500MHz with very reduced kickback noise compared with conventional architectures.

  • Internally matched, ultra-low DC power consumption CMOS amplifier for L-band personal communications

    K. Ohsato, T. Yoshimasu

    IEEE Microwave and Wireless Components Letters   Vol.14 ( No.5 ) 204 - 206  2004年04月

  • ユビキタスネットワーク用機能融合システムLSI

    山内, 犬島, 吉増他

    第4回制御部門大会     719 - 722  2004年

  • 高抵抗Si基板を用いた2 GHz帯SOI低雑音増幅器

    吉増 敏彦, アルベルト アダン, 丹波 憲之

    電子情報通信学会論文誌   Vol.J85-C ( No.8 ) 737 - 744  2002年08月

  • Linearity and low-noise performance of SOI MOSFETs for RF applications

    AO Adan, T Yoshimasu, S Shitara, N Tanba, M Fukumi

    IEEE TRANSACTIONS ON ELECTRON DEVICES   49 ( 5 ) 881 - 888  2002年05月  [査読有り]

     概要を見る

    The MOSFET parameters important for RF application at GHz frequencies: a) transition frequency, b) noise figure, and c) linearity are analyzed and correlated with substrate type. This work demonstrates that, without process changes, high-resistivity silicon-on-insulator (high-p SOI) substrates can successfully enhance the RF performance of on-chip inductors and fully depleted (FD)-SOI devices in terms of reducing substrate losses and parasitics. The linearity limitations of the SOI low-breakdown voltage and "kink" effect are addressed by judicious device and circuit design. Criteria for device optimization are derived. A NF = 1.7 dB at 2.5 GHz for a 0.25 mum FD-SOI low-noise amplifier (LNA) on high-p SOI substrate obtained the lowest noise figure for applications in the L and S-bands.

  • ESD protection of RF circuits in standard CMOS process

    K Higashi, AO Adan, M Fukumi, N Tanba, T Yoshimasu, M Hayashi

    2002 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS 1-3     31 - 34  2002年  [査読有り]

     概要を見る

    The tradeoffs in the ESD protection device for RFCMOS circuits are described, and the characteristics of an SCR-based ESD structure are presented. The parasitic capacitance of the ESD structure is reduced to similar to150fF. 3kV HBM and 750V CDM are achieved in a LNA working at 2.5GHz with NF&lt;4dB, applicable for Bluetooth wireless transceiver.

  • Linearity and low-noise performance of SOI MOSFETs for RF applications

    A. Adan, S. Shitara, T. Yoshimasu

    IEEE International SOI Conference    2000年08月

  • Miniature, High Performance AlGaAs/GaAs HBTs for Low Voltage Cellular Phones in 900 MHz-Band

    T. Yoshimasu, N. Tanba, K. Osato, M. Akagi, S. Hara

    Asia Pacific Microwave Conference Technical Digest    1998年12月

  • An HBT MMIC Power Amplifier with an Integrated Diode Linearizer for Low-Voltage Portable Phone Applications

    T. Yoshimasu, M. Akagi, N. Tanba, S. Hara

    IEEE Journal of Solid-State Circuits   Vol. 33 ( No. 9 ) 1290 - 1296  1998年12月

▼全件表示

産業財産権

  • 高調波ミキサ

    6238400

    吉増 敏彦

    特許権

  • バイアス回路、および増幅装置

    吉増 敏彦

    特許権

  • バイアス回路及びこれを用いた増幅器

    吉増 敏彦

    特許権

  • 高周波電力増幅器

    吉増 敏彦

    特許権

  • 周波数逓倍器

    5646302

    吉増 敏彦

    特許権

受賞

  • 中国留日同学会 大阪市長賞

    2005年11月  

  • IEEE ICCCAS 2005 ベスト論文賞

    2005年05月  

共同研究・競争的資金等の研究課題

  • 太陽電池で駆動可能な無線通信用低消費電力パワーアンプと発振器の研究

    研究期間:

    2011年04月
    -
    2015年03月
     

     概要を見る

    Si CMOS技術を用いて、太陽電池で駆動可能な電圧(0.3~0.5 V)で動作するパワーアンプICと発振器ICの新規回路を考案し、チップ試作(大学外部に委託)後、特性評価を行った。パワーアンプICは、動作周波数=2.5 GHz、動作電圧=0.5 Vで出力パワー=5 dBm、電力効率=29 %を達成した。また、発振器ICは、最低動作電圧=0.28 Vで発振周波数=2.48 GHzを達成した。この動作電圧は世界トップレベルの低動作電圧である。また、動作電圧=0.5 Vにおいては、発振周波数=2.1~2.3 GHzを実現した。以上により、本研究課題の目標を上回る成果が得られた

  • 太陽電池で駆動可能な無線通信用低消費電力パワーアンプと発振器の研究

    科学研究費助成事業(早稲田大学)  科学研究費助成事業(基盤研究(B))

    研究期間:

    2011年
    -
    2014年
     

     概要を見る

    平成24年度に低動作電圧制御発振器回路を設計し、学外のファブで試作したチップの評価ならびに考察を行った。また、低動作電圧パワーアンプの回路方式を検討し、回路シミュレーションを行った。
    (1) 電圧制御発振器
    CMOSプロセスを用いて、0.3~0.5 Vで動作する発振器ICの評価を行った結果、次の結果が得られた。動作電圧=0.5 Vでは、制御電圧を0.0~0.5Vに可変することで、発振周波数=2.09~2.29 GHzの発振を確認した。この時の消費電力は2.6mWであった。動作電圧=0.3 Vにおいては、制御電圧を0.0~0.3Vに可変することで、発振周波数=2.22~2.43 GHzの発振を確認した。この時の消費電力はわずか0.576mWであり、また位相雑音は離調周波数=1MHz時に-111dBc/Hzであった。以上の結果は、CMOSFETのバックゲート効果を利用することで実現されたものである。また、平成24年度に回路考案し、回路設計並びにレイアウト設計した際に期待された発振周波数が得られており、設計精度の高さを確認した。これらの結果を国際学会(2014 Asia Pacific Microwave Conferenceなど)にて発表した。
    (2) パワーアンプ
    CMOSプロセスを用いて、0.5Vで動作するパワーアンプの回路設計並びに特性シミュレーションを実施した。回路方式は、高効率特性が期待されるE級アンプ方式を基本とし、低電圧においても高効率が得られるように改善した。その結果、動作周波数=2.4GHzにおいて、小信号ゲイン=10 dB、出力パワー=1mW、電力効率=18 %がシミュレーションで得られた。本効率は動作電圧が0.5Vであることを考慮すると非常に高効率と言える特性である。

特定課題研究

  • 線形性と消費電力を自己制御可能な24GHz帯低雑音増幅器ICの研究

    2020年  

     概要を見る

    低雑音増幅器は、入力が小信号の時は低雑音で動作し、大信号の時は高線形で動作することが求められる。この低雑音と高線形を両立することは従来困難であった。そこで、大信号入力時は、消費電力を上げることで線形性を高める制御回路を考案した。本制御回路は、出力パワー検出回路とFETのゲート電圧制御回路から構成される。この回路を組み込んだ低雑音増幅器と、従来のカレントミラー回路を使用した低雑音増幅器を設計し、回路シミュレーションにより性能比較した。その結果、新規低雑音増幅器は従来回路に比べて、24 GHzにおける総合性能指数(FoM:Figure of Merit)が約2倍向上することが確認された。

  • 線形性と消費電力を自立制御できる24GHz帯パワーアンプICの研究

    2019年  

     概要を見る

    高速・大容量無線通信や車の自動運転システムに応用可能な「線形性と消費電力を自己制御可能なパワーアンプIC」を実現することを目的に、56-nm SOI CMOSプロセスを用いて、新規バイアス電流制御回路を考案し、さらに回路シミュレーションにより、パワーアンプの特性を確認した。その結果、電源電圧=3.6 Vで線形出力=20 dBm (100 mW)、利得=13.2 dB、最大電力付加効率=41.4 %、入力側リターンロス=20 dBの良好な特性が得られた。

  • 無線伝送速度100Gb/s実現のための超広帯域・高線形フロントエンドLSIの研究

    2017年  

     概要を見る

    高速無線通信を実現するため、RFトランシーバの広帯域化と高線形化を進め、局部発振器と周波数ミキサ回路の新規回路を考案した。デバイス技術はSi CMOSを用いた。トランシーバは、RF周波数が28GHz帯、IF周波数が1GHzの広帯域である。また、局部発振器は発振周波数が14GHz帯で設計を行った。RFトランシーバの回路特性をシミュレーションした結果、送信系ではIFからRFへの変換利得が15dB以上、受信系ではRFからIFへの変換利得20dB以上が得られた。

  • 第5世代移動体通信用マイクロ波高線形・低消費電力CMOSパワーアンプ回路の研究

    2017年  

     概要を見る

    第5世代移動体通信に用いる電波の候補の一つに14GHz帯がある。本研究課題では、14GHz帯の電波を想定して、パワーアンプの新規回路方式を創出した。デバイス技術はSi CMOSを用いた。パワーアンプのバイアス回路として、従来のカレントミラー回路を改良し、入力パワーに応じて、適応的に電圧が可変する新たなバイアス回路を考案した。その結果、パワーアンプは線形パワー=20 dBm(100mW)、電力付加効率が40%以上、電力利得は13 dB以上、入出力反射係数は-10dB以下の良好な特性が得られた。

  • マイクロ波帯受信機用低位相雑音発振器ICの研究

    2016年  

     概要を見る

    0.18um CMOSプロセスを用いて、2GHz帯の電圧制御発振器(VCO)の低位相雑音化のための研究を実施した。基本となるcross-coupledトランジスタペアのバイアス回路にLC回路を応用することで、インピーダンス整合を取り、低位相雑音化と高出力化を実現した。VCO ICを評価した結果、発振周波数=2.03GHz、1MHz離調において、位相雑音=-126.4dBc/Hzの良好な特性が得られた。

  • SOI CMOS技術を用いた広帯域・低損失スイッチICの研究

    2015年  

     概要を見る

    45-nm SOI CMOS(Silicon On Insulator CMOS)技術を用いて、送受信切り替え用SPDTスイッチ回路方式の研究を実施した。その結果、回路シミュレーションにより、動作周波数=30 GHzにおいて、送信ポートの挿入損失=0.32 dB、線形出力電力=25 dBm (300 mW)、受信ポートの挿入損失=1.4 dB、送受信アイソレーション=28.7 dBの特性を得た。SOI構造はバルク構造CMOSに比べて、FETの寄生容量が小さいため、MOSFETのゲート幅を広くし、オン抵抗を低減することが挿入損失とアイソレーションのトレードオフに有効であることを確認した。

  • 第5世代移動通信用30GHz帯高線形・低雑音フロントエンドICの研究

    2015年  

     概要を見る

    130-nm SiGe BiCMOSプロセスを用いて、30GHz帯で動作するパワーアンプ、送受信切り替えスイッチと受信用低雑音増幅器の各回路を設計した。その結果、回路シミュレーションにより、パワーアンプの線形出力>10 dBm、電力付加効率>30 %が得られた。送受信切り替えスイッチ回路においては、動作周波数=26~32GHzにおいて、挿入損失<2.5dBが得られた。また、受信用低雑音増幅器においては、電力利得>20 dB、雑音指数<3.5 dBが得られた。

  • Si CMOS技術とアクティブ帰還回路を活用した超広帯域低電圧増幅器の 研究

    2014年  

     概要を見る

    (1)研究の目的超広帯域通信に用いられているUWB方式(Ultra-Wide Band)の周波数である、3.1~10.6 GHzにおいて動作する低電圧増幅器に適した回路方式を考案し、回路シミュレーションによって、その有効性を確認する。(2)回路方式の検討と結果まとめ増幅器回路は2段構成とし、各増幅器段にはソース接地nMOSFETを用いた。超広帯域化を実現するため、アクティブフィードバック回路と抵抗を用いた負帰還回路を検討した。また、回路シミュレータを用いて各素子値を最適化した結果、動作周波数=3.1~12.7 GHzの広帯域にわたって、平坦な利得と良好な整合特性が得られた。

  • SiCMOS技術を用いた高線形・超低消費電力パワーアンプの研究

    2013年  

     概要を見る

    (1) 研究目的Si CMOS技術を用いて、高線形で超低消費電力特性を有するパワーアンプ回路方式を考案する。(2) 動作周波数パワーアンプの動作周波数は、2.4GHzとした。この周波数は、工業や医療にライセンス無しで使用できるISMバンドであるため、研究成果を実用化する際に、多くの応用が考えられる利点を有する。(3) 動作条件と回路方式超低消費電力特性を実現するため、動作電圧を0.5 V~1.0 Vとした。また、消費電流を低減するために、スイッチング動作で電力を出力するE級動作回路の改善を実施した。動作電圧=0.5Vであるため、パワーアンプの出力電圧振幅を高くすることができない。しかし、E級動作を改善することで、動作電圧の2倍以上の電圧振幅が得られる回路方式を考案することに成功した。具体的には、ⅰ)トランジスタの負荷線を寝かせることで、小さい入力電力でトランジスタを飽和させること、ⅱ)トランジスタの出力側(ドレイン端)と電源間に通常より少し大きいインダクタを接続する、さらに、ⅲ)トランジスタのドレイン端子と接地間にキャパシタを接続し、トランジスタの出力電圧と出力電流波形が重なりにくい回路とした。これらの効果により、わずか0.5V動作で良好なスイッチング動作が期待できることを回路シミュレーションで確認した。(4) シミュレーションで得られた特性動作周波数=2.4 GHz.動作電圧=0.5 V、において、小信号利得>10 dB線形出力>2.0 dBm (1.6 mW)飽和出力>3.0 dBm (2.0 mW)電力効率>25.0 %が得られた。また、動作電圧=1.0 Vにおいては、小信号利得>11 dB線形出力>7.0 dBm (5.0 mW)飽和出力>9.0 dBm (7.9 mW)電力効率>30 %の良好な出力電力と効率が得られた。(5) まとめ超低動作電圧で良好な出力と効率がシミュレーションで確認された。これにより、新規考案のE級増幅器の有効性が確認された。

  • ウルトラワイドバンド高線形・高効率GaAsパワーアンプの研究・開発

    2004年  

     概要を見る

    1800 MHz~2700 MHzのワイドバンドにおいて動作する線形パワーアンプを実現するための回路方式の研究を行った。トランジスタには、高周波での利得が高いInGaP/GaAs HBT(ヘテロジャンクションバイポーラトランジスタ)を使用し、このHBTの非線形動作を補償するための回路を考案した。本補償回路は、ダイオードと抵抗から成り、HBTの出力が増加するにつれて生じる歪み(AM-AM歪み、AM-PM歪み)を補償する。この補償回路をGaAs HBTパワーアンプに適用することで、電力効率を約10%改善できることが回路シミュレーションにより得られた。そこで、本GaAs HBTパワーアンプのウエハ試作を行い、下記の性能を得た。1)周波数範囲 1800~2700 MHz2)出力 2 W (33 dBm)3)電力効率 30 %4)利得 27 dB出力、電力効率、利得ともに回路シミュレーションで予測された特性をほぼ実現し、補償回路の有効性が実証された。1800~2700 MHzの広周波数範囲で動作するパワーアンプは、種々の携帯機器(携帯電話、WLANなど)や基地局などの消費電力を低減できるものと期待され、本研究は成功を収めた。本技術ならびにGaAsチップは、現在、ベンチャー企業(ファブレスの設計会社:D-CLUE社)にて製品化にむけて、検討が進められている。本研究室においても、製品化のサポートを行っていく予定である。

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