Concurrent Post
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Faculty of Science and Engineering Graduate School of Information, Production, and Systems
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Faculty of Science and Engineering Graduate School of Fundamental Science and Engineering
Details of a Researcher
Updated on 2022/07/02
Faculty of Science and Engineering Graduate School of Information, Production, and Systems
Faculty of Science and Engineering Graduate School of Fundamental Science and Engineering
理工学術院総合研究所 兼任研究員
Waseda University Faculty of Science and Engineering Department of Electronics
早稲田大学 博士(工学)
Doctor of Engineering
Professor, Department of Computer Science and Engineering, Waseda University
Associate Professor, Department of Computer Science, Waseda University
Associate Professor, Department of Computer Science, Waseda University
Assistant Professor, Department of Computer Science, Waseda University
Visiting Assistant Professor, Advanced Research Institute for Science and Engineering, Waseda University
Research Associate, Department of Electrical, Electronics and Computer Engineering, Waseda University
Research Associate, Department of Electrical, Electronics and Computer Engineering, Waseda University
ACM
IEEE Computer Society
The institute of Electronics, Information and Communication Engineers
Information Processing Society of Japan
Computer system
Multiprocessor Architecture, Parallelizing Compiler
Method for speeding up simulations for assessing many-core performance
Information Communication
Parallelization of multimedia applications (MPEG2 encoders and decoders) by using the OSCAR compiler
Information Communication
Data stream clustering for low-cost machines
Christophe Cérin, Keiji Kimura, Mamadou Sow
Journal of Parallel and Distributed Computing 166 57 - 70 2022.08 [Refereed]
Accelerating Data Dependence Profiling Through Abstract Interpretation of Loop Instructions
Mostafa Abbas, Mostafa I. Soliman, Sherif I. Rabia, Keiji Kimura, Ahmed El-Mahdy
IEEE Access 10 31626 - 31640 2022 [Refereed]
Hironori Kasahara, Keiji Kimura, Toshiaki Kitamura, Hiroki Mikami, Kazutaka Morita, Kazuki Fujita, Kazuki Yamamoto, Tohma Kawasumi
2021 IEEE/ACM Programming Environments for Heterogeneous Computing (PEHC) 2021.11 [Refereed] [Invited]
Parallelizing Compiler Translation Validation Using Happens-Before and Task-Set
Jixin Han, Tomofumi Yuki, Michelle Mills Strout, Dan Umeda, Hironori Kasahara, Keiji Kimura
2021 Ninth International Symposium on Computing and Networking Workshops (CANDARW) 2021.11 [Refereed]
Performance Evaluation of OSCAR Multi-target Automatic Parallelizing Compiler on Intel, AMD, Arm and RISC-V Multicores
Birk M. Magnussen, Tohma Kawasumi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara
LCPC2021 2021.10 [Refereed]
Durable Queue Implementations Built on a Formally Defined Strand Persistency Model
Jixin Han, Keiji Kimura
Journal of Information Processing 29 823 - 838 2021 [Refereed]
Authorship:Last author
Secure Image Inference Using Pairwise Activation Functions
Jonas T. Agyepong, Mostafa Soliman, Yasutaka Wada, Keiji Kimura, Ahmed El-Mahdy
IEEE Access 9 118271 - 118290 2021 [Refereed]
Non-Volatile Main Memory Emulator for Embedded Systems Employing Three NVMM Behaviour Models
Yu OMORI, Keiji KIMURA
IEICE TRANSACTIONS on Information and Systems E104-D ( 5 ) 697 - 708 2021 [Refereed]
Authorship:Last author
Scalable and Fast Lazy Persistency on GPUs
Ardhi Wiratama, Baskara Yudha, Keiji Kimura, Huiyang Zhou, Yan Solihin
2020 IEEE International Symposium on Workload Characterization (IISWC 2020) 252 - 263 2020.10 [Refereed]
Local Memory Mapping of Multicore Processors on an Automatic Parallelizing Compiler
Yoshitake OKI, Yuto ABE, Kazuki YAMAMOTO, Kohei YAMAMOTO, Tomoya SHIRAKAWA, Akimasa YOSHIDA, Keiji KIMURA, Hironori KASAHARA
IEICE TRANSACTIONS on Electronics E103-C ( 3 ) 98 - 109 2020.03 [Refereed]
Compiler Software Coherent Control for Embedded High Performance Multicore
Boma A. ADHI, Tomoya KASHIMATA, Ken TAKAHASHI, Keiji KIMURA, Hironori KASAHARA
IEICE TRANSACTIONS on Electronics E103-C ( 3 ) 85 - 97 2020.03 [Refereed]
Compiler-support for Critical Data Persistence in NVM
Reem Elkhouly, Mohammad Alshboul, Akihiro Hayashi, Yan Solihin, Keiji Kimura
ACM Transactions on Architecture and Code Optimization (TACO) 16 ( 4 ) 2019.12 [Refereed]
Authorship:Last author
Software Cache Coherent Control by Parallelizing Compiler
Boma A. Adhi, Masayoshi Mase, Yuhei Hosokawa, Yohei Kishimoto, Taisuke Onishi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 11403 17 - 25 2019.11 [Refereed]
Cascaded DMA Controller for Speedup of Indirect Memory Access in Irregular Applications
Tomoya Kashimata, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara
9th Workshop on Irregular Applications: Architectures and Algorithms 71 - 76 2019.11 [Refereed]
Performance of Static and Dynamic Task Scheduling for Real-Time Control System on Embedded Multicore Processor
Yoshitake Oki, Hiroki Mikami, Hikaru Nishida, Dan Umeda, Keiji Kimura, Hironori Kasahara
32nd International Workshop on Languages and Compilers for Parallel Computing(LCPC) 2019.10 [Refereed]
Performance Evaluation on NVMM Emulator Employing Fine-Grain Delay Injection
Yu Omori, Keiji Kimura
The 8th IEEE Non-Volatile Memory Systems and Applications Symposium (IEEE NVMSA 2019) 1 - 6 2019.08 [Refereed]
Authorship:Last author
Fast and Highly Optimizing Separate Compilation for Automatic Parallelization
Tohma Kawasumi, Ryota Tamura, Yuya Asada, Jixin Han, Hiroki Mikami, Keiji Kimura, Hironori Kasahara
The 2019 International Conference on High Performance Computing & Simulation (HPCS 2019) 478 - 485 2019.07 [Refereed]
Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory
Mohammad Alshboul, Hussein Elnawawy, Reem Elkhouly, Keiji Kimura, James Tuck, Yan Solihin
ACM Transactions on Architecture and Code Optimization (TACO) 16 ( 2 ) 2019.05 [Refereed]
Multicore Cache Coherence Control by a Parallelizing Compiler
Hironori Kasahara, Keiji Kimura, Boma A. Adhi, Yuhei Hosokawa, Yohei Kishimoto, Masayoshi Mase
Proceedings - International Computer Software and Applications Conference 1 492 - 497 2017.09 [Refereed]
Automatic Local Memory Management for Multicores Having Global Address Space
Kouhei Yamamoto, Tomoya Shirakawa, Yoshitake Oki, Akimasa Yoshida, Keiji Kimura, Hironori Kasahara
LANGUAGES AND COMPILERS FOR PARALLEL COMPUTING, LCPC 2016 10136 282 - 296 2017 [Refereed]
Architecture design for the environmental monitoring system over the winter season
Koichiro Yamashita, Chen Ao, Takahisa Suzuki, Yi Xu, Hongchun Li, Jun Tian, Keiji Kimura, Hironori Kasahara
MobiWac 2016 - Proceedings of the 14th ACM International Symposium on Mobility Management and Wireless Access, co-located with MSWiM 2016 27 - 34 2016.11 [Refereed]
Reducing parallelizing compilation time by removing redundant analysis
Jixin Han, Rina Fujino, Ryota Tamura, Mamoru Shimaoka, Hiroki Mikami, Moriyuki Takamura, Sachio Kamiya, Kazuhiko Suzuki, Takahiro Miyajima, Keiji Kimura, Hironori Kasahara
SEPS 2016 - Proceedings of the 3rd International Workshop on Software Engineering for Parallel Systems, co-located with SPLASH 2016 1 - 9 2016.10 [Refereed]
An Android Systrace Extension for Tracing Wakelocks
Bui Duc Binh, Keiji Kimura
IEEE International Conference on Embedded and Ubiquitous Computing (EUC 2016) 146 - 149 2016.08 [Refereed]
Authorship:Corresponding author
Multigrain Parallelization Using Profile Information of Embedded Applications Generated by Model-based Development Tools on Multicore Processors
Dan Umeda, Takahiro Suzuki, Hiroki Mikami, Keiji Kimura, Hironori Kasahara
IPSJ Journal 57 ( 2 ) 1 - 12 2016.02 [Refereed]
Multigrain parallelization for model-based design applications using the OSCAR compiler
Dan Umeda, Takahiro Suzuki, Hiroki Mikami, Keiji Kimura, Hironori Kasahara
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 9519 125 - 139 2016 [Refereed]
Coarse grain task parallelization of earthquake simulator GMS using OSCAR compiler on various Cc-NUMA servers
Mamoru Shimaoka, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 9519 238 - 253 2016 [Refereed]
2-Step Power Scheduling with Adaptive Control Interval for Network Intrusion Detection Systems on Multicores
Lau Phi Tuong, Keiji Kimura
2016 IEEE 10TH INTERNATIONAL SYMPOSIUM ON EMBEDDED MULTICORE/MANY-CORE SYSTEMS-ON-CHIP (MCSOC) 69 - 76 2016 [Refereed]
Authorship:Last author
Accelerating Multicore Architecture Simulation Using Application Profile
Keiji Kimura, Gakuho Taguchi, Hironori Kasahara
2016 IEEE 10TH INTERNATIONAL SYMPOSIUM ON EMBEDDED MULTICORE/MANY-CORE SYSTEMS-ON-CHIP (MCSOC) 177 - 184 2016 [Refereed]
Authorship:Lead author
Annotatable systrace: An extended linux ftrace for tracing a parallelized program
Daichi Fukui, Mamoru Shimaoka, Hiroki Mikami, Dominic Hillenbrand, Hideo Yamamoto, Keiji Kimura, Hironori Kasahara
SEPS 2015 - Proceedings of the 2nd International Workshop on Software Engineering for Parallel Systems 21 - 25 2015.10 [Refereed]
Evaluation of Automatic Power Reduction with OSCAR Compiler on Intel Haswell and ARM Cortex-A9 Multicores
Tomohiro Hirano, Hideo Yamamoto, Shuhei Iizuka, Kohei Muto, Takashi Goto, Tamami Wake, Hiroki Mikami, Moriyuki Takamura, Keiji Kimura, Hironori Kasahara
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 8967 239 - 252 2015.05 [Refereed]
Automatic Parallelization of Designed Engine Control C Codes by MATLAB/Simulink
Dan Umeda, Youhei Kanehagi, Hiroki Mikami, Akihiro Hayashi, Mitsuhiro Tani, Hiroshi Mori, Keiji Kimura, Hironori Kasahara
IPSJ Journal 55 ( 8 ) 1817 - 1829 2014.08 [Refereed]
Multicore Technologies Realizing Low-Power Computing
Keiji Kimura, Hironori Kasahara
The Journal of IEICE 97 ( 2 ) 133 - 139 2014.02 [Invited]
Authorship:Lead author
OSCAR Compiler Controlled Multicore Power Reduction on Android Platform
Hideo Yamamoto, Tomohiro Hirano, Kohei Muto, Hiroki Mikami, Takashi Goto, Dominic Hillenbrand, Moriyuki Takamura, Keiji Kimura, Hironori Kasahara
LANGUAGES AND COMPILERS FOR PARALLEL COMPUTING, LCPC 2013 8664 155 - 168 2014 [Refereed]
モデルベース設計により自動生成されたエンジン制御Cコードのマルチコア用自動並列化
梅田弾, 金羽木洋平, 見神広紀, 谷充弘(デンソー, 森裕司(デンソー, 木村啓二, 笠原博徳
組み込みシステムシンポジウム(ESS2013) 2013.10
OSAR API v2.1: Extensions for an Advanced Accelerator Control Scheme to a Low-Power Multicore API
Keiji Kimura, Cecilia Gonzales-Alvarez, Akihiro Hayashi, Hiroki Mikami, Mamoru Shimaoka, Jun Shirako, Hironori Kasahara
17th Workshop on Compilers for Parallel Computing (CPC2013) 2013.07 [Refereed]
Authorship:Lead author
Automatic Parallelization of Hand Written Automotive Engine Control Codes Using OSCAR Compiler
Dan Umeda, Yohei Kanehagi, Hiroki Mikami, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara
17th Workshop on Compilers for Parallel Computing (CPC2013) 2013.07 [Refereed]
Evaluation of power consumption at execution of multiple automatically parallelized and power controlled media applications on the RP2 low-power multicore
Hiroki Mikami, Shumpei Kitaki, Masayoshi Mase, Akihiro Hayashi, Mamoru Shimaoka, Keiji Kimura, Masato Edahiro, Hironori Kasahara
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 7146 31 - 45 2013
Automatic Design Exploration Framework for Multicores with Reconfigurable Accelerators
Cecilia Gonzalez-Alvarez, Haruku Ishikawa, Akihiro Hayashi, Daniel Jimenez-Gonzalez, Carlos Alvarez, Keiji Kimura, Hironori Kasahara
th Workshop on Reconfigurable Computing (WRC) 2013, held in conjuction with HiPEAC conference 2013 2013.01 [Refereed]
Parallelization of Automotive Engine Control Software On Embedded Multi-core Processor Using OSCAR Compiler
Yohei Kanehagi, Dan Umeda, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara
2013 IEEE COOL CHIPS XVI (COOL CHIPS) 2013 [Refereed]
Automatic Parallelization, Performance Predictability and Power Control for Mobile-Applications
Dominic Hillenbrand, Akihiro Hayashi, Hideo Yamamoto, Keiji Kimura, Hironori Kasahara
2013 IEEE COOL CHIPS XVI (COOL CHIPS) 2013 [Refereed]
Reconciling application power control and operating systems for optimal power and performance
Dominic Hillenbrand, Yuuki Furuyama, Akihiro Hayashi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara
2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC 2013 2013
組込マルチコア用OSCAR APIを用いたTILEPro64上でのマルチメディアアプリケーションの 並列処理
岸本耀平, 見神広紀, 中野恵一, 林明宏, 木村啓二, 笠原博徳
組み込みシステムシンポジウム(ESS2012) 2012.10
OSCAR Parallelizing Compiler and API for Real-time Low Power Heterogeneous Multicores
kihiro Hayashi, Mamoru Shimaoka, Hiroki Mikami, Masayoshi Mase, Yasutaka Wada, Jun Shirako, Keiji Kimura, Hironori Kasahara
6th Workshop on Compilers for Parallel Computing(CPC2012) 2012.01 [Refereed]
重粒子線がん治療用線量計算エンジンの自動並列化
林明宏, 松本卓司, 見神広紀, 木村啓二, 山本啓二, 崎浩典, 高谷保行, 笠原博徳
HPCS2012 - ハイパフォーマンスコンピューティングと計算科学シンポジウム 2012.01
Enhancing the Performance of a Multiplayer Game by Using a Parallelizing Compiler
Yasir I. M. Al-Dosary, Keiji Kimura, Hironori Kasahara, Seinosuke Narita
2012 17TH INTERNATIONAL CONFERENCE ON COMPUTER GAMES (CGAMES) 67 - 75 2012 [Refereed]
Parallelizing Compiler Framework and API for Heterogeneous Multicores
Akihiro Hayashi, Yasutaka Wada, Takeshi Watanabe, Takeshi Sekiguchi, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara
IPSJ Transactions on Advanced Computing Systems 5 ( 1 ) 68 - 79 2011.11 [Refereed]
A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core
Osamu Nishii, Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima
IEICE TRANSACTIONS ON ELECTRONICS E94C ( 4 ) 663 - 669 2011.04 [Refereed]
Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-Time Heterogeneous Multicores
Akihiro Hayashi, Yasutaka Wada, Takeshi Watanabe, Takeshi Sekiguchi, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara
LANGUAGES AND COMPILERS FOR PARALLEL COMPUTING 6548 184 - 198 2011 [Refereed]
A parallelizing compiler cooperative heterogeneous multicore processor architecture
Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 6760 215 - 233 2011
Parallelizable C and Its Performance on Low Power High Performance Multicore Processors
Masayoshi Mase, Yuto Onozaki, Keiji Kimura, Hironori Kasahara
Proc. of 15th Workshop on Compilers for Parallel Computing (CPC 2010) 2010.07 [Refereed]
Element-Sensitive Pointer Analysis for Automatic Parallelization
Masayoshi Mase, Yuta Murata, Keiji Kimura, Hironori Kasahara
IPSJ Transactions on Programming (PRO) 3 ( 2 ) 36 - 47 2010.03 [Refereed]
A 45nm 37.3GOPS/W heterogeneous multi-core SoC
Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Shigezumi Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Makoto Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima
Digest of Technical Papers - IEEE International Solid-State Circuits Conference 53 100 - 101 2010
OSCAR API for Real-Time Low-Power Multicores and Its Performance on Multicores and SMP Servers
Keiji Kimura, Masayoshi Mase, Hiroki Mikami, Takamichi Miyamoto, Jun Shirako, Hironori Kasahara
LANGUAGES AND COMPILERS FOR PARALLEL COMPUTING 5898 188 - 202 2010 [Refereed]
Authorship:Lead author
A Power Reduction Scheme of Parallelizing Compiler Using OSCAR API on Multicore Processor
Masayoshi Mase, Ryo Nakagawa, Naoto Ohkuni, Jun Shirako, Keiji Kimura, Hironori Kasahara
IPSJ Transactions on Advanced Computing Systems 2 ( 3 ) 96 - 106 2009.09 [Refereed]
マルチコア上でのOSCAR APIを用いた並列化コンパイラによる低消費電力化手法
中川亮, 間瀬正啓, 大國直人, 白子準, 木村啓二, 笠原博徳
先進的計算基盤システムシンポジウム(SACSIS2009) 3 - 10 2009.05
Performance of OSCAR Multigrain Parallelizing Compiler on Multicore Processors
Hiroki Mikami, Jun Shirako, Masayoshi Mase, Takamichi Miyamoto, Hirofumi Nakano, Fumiyo Takano, Akihiro Hayashi, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
Proc. of 14th Workshop on Compilers for Parallel Computing(CPC 2009) 2009.01 [Refereed]
Green multicore-SoC software-execution framework with timely-power-gating scheme
Masafumi Onouchi, Keisuke Toyama, Toru Nojiri, Makoto Sato, Masayoshi Mase, Jun Shirako, Mikiko Sato, Masashi Takada, Masayuki Ito, Hiroyuki Mizuno, Mitaro Namiki, Keiji Kimura, Hironori Kasahara
Proceedings of the International Conference on Parallel Processing 510 - 517 2009
An Evaluation of Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API
Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Keiji Kimura, Hironori Kasahara
IPSJ Transactions on Advanced Computing Systems 1 ( 3 ) 83 - 95 2008.12 [Refereed]
Parallelizing Compiler Cooperative Heterogeneous Multicore
Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
Proc. of Workshop on Software and Hardware Challenges of Manycore Platforms (SHCMP 2008) 2008.06 [Refereed]
Parallelization of MP3 Encoder using Static Scheduling on a Heterogeneous Multicore
Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara
Trans. of IPSJ on Computing Systems 1 ( 1 ) 105 - 119 2008.06 [Refereed]
情報家電用マルチコア上におけるマルチメディア処理のコンパイラによる並列化
宮本孝道, 浅香沙織, 見神広紀, 間瀬正啓, 木村啓二, 笠原博徳
SACSIS2008 - 先進的計算基盤システムシンポジウム 2008.05
Power-aware compiler controllable chip multiprocessor
Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
IEICE TRANSACTIONS ON ELECTRONICS E91C ( 4 ) 432 - 439 2008.04 [Refereed]
Heterogeneous multi-core architecture that enables 54x AAC-LC stereo encoding
Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
IEEE JOURNAL OF SOLID-STATE CIRCUITS 43 ( 4 ) 902 - 910 2008.04 [Refereed]
An 8 CPU SoC with Independent Power-off Control of CPUs and Multicore Software Debug Function
Yutaka Yoshida, Masayuki Ito, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Toshihiro Hattori, Jun Sakiyama, Masashi Takada, Kunio Uchiyama, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara
Proc. of IEEE Cool Chips XI: Symposium on Low-Power and High-Speed Chips 2008 2008.04 [Refereed]
A 600MHz SoC with Compiler Power-off Control of 8 CPUs and 8 Onchip-RAMs
Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Masaki Ito, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara
Proc. of International Solid State Circuits Conference (ISSCC2008) 90 - 91 2008.02 [Refereed]
Performance evaluation of compiler controlled power saving scheme
Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofurni Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
HIGH-PERFORMANCE COMPUTING 4759 480 - 493 2008 [Refereed]
Software-cooperative power-efficient heterogeneous multi-core for media processing
Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 712 - + 2008 [Refereed]
Power Reduction Controll for Multicores in OSCAR Multigrain Parallelizing Compiler
Jun Shirako, Keiji Kimura, Hironori Kasahara
ISOCC: 2008 INTERNATIONAL SOC DESIGN CONFERENCE, VOLS 1-3 50 - 55 2008 [Refereed]
Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API
Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Yasutaka Wada, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara
PROCEEDINGS OF THE 2008 INTERNATIONAL SYMPOSIUM ON PARALLEL AND DISTRIBUTED PROCESSING WITH APPLICATIONS 600 - 607 2008 [Refereed]
情報家電用マルチコアSMP実行モードにおける制約付きCプログラムのマルチグレイン並列化
間瀬正啓, 馬場大介, 長山晴美, 田野裕秋, 益浦健, 宮本孝道, 白子準, 中野啓史, 木村啓二, 笠原博徳
組込みシステムシンポジウム2007 2007.10
Performance Evaluation of MP3 Audio Encoder on OSCAR Heterogeneous Chip Multicore Processor
Hiroaki Shikano, Yuki Suzuki, Yasutaka Wada, Jun Shirako, Keiji Kimura, Hioronori Kasahara
Trans. of IPSJ on Computing Systems Vol. 48, No. SIG8(ACS18), 141 - 152 2007.05 [Refereed]
A 4320MIPS four-processor core SMP/AMP with individually managed clock frequency for low power consumption
Yutaka Yoshida, Tatsuya Kamei, Kiyoshi Hayase, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara
Digest of Technical Papers - IEEE International Solid-State Circuits Conference 95 - 590 2007
Heterogeneous multiprocessor on a chip which enables 54x AAC-LC stereo encoding
Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Hiroshi Tanaka, Tomoyuki Kodama, Hiroaki Shikano, Masafumi Onouchi, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
2007 Symposium on VLSI Circuits, Digest of Technical Papers 18 - 19 2007 [Refereed]
Compiler Control Power Saving Scheme for Multicore Processors
Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
Trans. of IPSJ on Computing Systems Vol. 47(ACS15) 2006.09 [Refereed]
マルチコアプロセッサにおけるコンパイラ制御低消費電力化手法
白子準, 吉田宗広, 押山直人, 和田康孝, 中野啓史, 鹿野裕明, 木村啓二, 笠原博徳
先進的計算基盤システムシンポジウム(SACSIS2006) ( 467 ) 476 2006.05
Performance Evaluation of Heterogeneous Chip Multi-Processor with MP3 Audio Encoder
Hiroaki Shikano, Yuki Suzuki, Yasutaka Wada, Jun Shirako, Keiji Kimura, Hironori Kasahara
Proc. of IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips IX) 349 - 363 2006.05 [Refereed]
Compiler control power saving scheme for multi core processors
Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 4339 362 - 376 2006
Programing for Multicore Systems
Keiji Kimura, Hironori Kasahara
IPSJ MAGAZINE 47 ( 1 ) 17 - 23 2006.01 [Invited]
Authorship:Lead author
Multicores Emerge as Next Generation Microprocessors
Hironori Kasahara, Keiji Kimura
IPSJ MAGAZINE 47 ( 1 ) 10 - 16 2006.01 [Refereed]
Parallelizing Compilation Scheme for Reduction of Power Consumption of Chip Multiprocessors
Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
Proc. of 12th Workshop on Compilers for Parallel Computers (CPC 2006), 2006.01 [Refereed]
Compiler control power saving scheme for multi core processors
Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 4339 362 - 376 2006
マルチコアプロセッサ上でのデータローカライゼーション
中野啓文, 浅野尚一郎, 内藤陽介, 仁藤拓実, 田川友博, 宮本孝道, 小高剛, 木村啓二, 笠原博徳
情報処理学会研究報告 ARC2005-165-10 2005.12
arallel Processing of MPEG2 Encoding on a Chip Multiprocessor Architecture
Takeshi Kodaka, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara
Trans. of IPSJ 46 ( 9 ) 2311 - 2325 2005.09 [Refereed]
ホモジニアスマルチコアにおけるコンパイラ制御低消費電力化手法
白子準, 押山直人, 和田康孝, 鹿野裕明, 木村啓二, 笠原博徳
情報処理学会研究報告 ARC2005-164-10 (SWoPP205) 2005.08
Performance of OSCAR multigrain parallelizing compiler on SMP servers
K Ishizaka, T Miyamoto, J Shirako, M Obata, K Kimura, H Kasahara
LANGUAGES AND COMPILERS FOR HIGH PERFORMANCE COMPUTING 3602 319 - 331 2005 [Refereed]
Performance of OSCAR multigrain parallelizing compiler on SMP servers
K Ishizaka, T Miyamoto, J Shirako, M Obata, K Kimura, H Kasahara
LANGUAGES AND COMPILERS FOR HIGH PERFORMANCE COMPUTING 3602 319 - 331 2005 [Refereed]
Multigrain parallel processing on compiler cooperative chip multiprocessor
K Kimura, Y Wada, H Nakano, T Kodaka, J Shirako, K Ishizaka, H Kasahara
9TH ANNUAL WORKSHOP ON INTERACTION BETWEEN COMPILERS AND COMPUTER ARCHITECTURES, PROCEEDINGS 11 - 20 2005 [Refereed]
Authorship:Lead author
Memory management for data localization on OSCAR chip multiprocessor
H Nakano, T Kodaka, K Kimura, H Kasahara
INNOVATIVE ARCHITECTURE FOR FUTURE GENERATION HIGH-PERFORMANCE PROCESSORS AND SYSTEMS, PROCEEDINGS 82 - 88 2004 [Refereed]
Parallel processing using data localization for MPEG2 encoding on OSCAR chip multiprocessor
T Kodaka, H Nakano, K Kimura, H Kasahara
INNOVATIVE ARCHITECTURE FOR FUTURE GENERATION HIGH-PERFORMANCE PROCESSORS AND SYSTEMS, PROCEEDINGS 119 - 127 2004 [Refereed]
Static coarse grain task scheduling with cache optimization using OpenMP
H Nakano, K Ishizaka, M Obata, K Kimura, H Kasahara
INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING 31 ( 3 ) 211 - 223 2003.06 [Refereed]
Multigrain Parallel Processing on Compiler Cooperative OSCAR Chip Multiprocessor Architecture 'Jointly Worked'
Keiji Kimura, Yasutaka Wada, Hirofumi Nakano, Takeshi Kodaka, Jun Shirako, Kazuhisa Ishizaka, Hironori Kasahara
The IEICE Transactions on Electronics, Special Issue on High-Performance and Low-Power System LSIs and Related Technologies E86-C ( 4 ) 570 - 579 2003.02 [Refereed]
Authorship:Lead author
Multigrain parallel processing on OSCAR CMP
K Kimura, T Kodaka, M Obata, H Kasahara
INNOVATIVE ARCHITECTURE FOR FUTURE GENERATION HIGH-PERFORMANCE PROCESSORS AND SYSTEMS 56 - 65 2003 [Refereed]
Authorship:Lead author
JPEG Encoding Using Multigrain Parallel Processing on a Single Chip Multiprocessor
Takeshi Kodaka, Takayuki Uchida, Keiji Kimura, Hironori Kasahara
Trans. of IPSJ on High Performance Computing Systems 43 ( Sig 6(HPS5) ) 153 - 162 2002.09 [Refereed]
シングルチップマルチプロセッサにおける JPEGエンコーディングのマルチグレイン並列処理 (共著)
小高剛, 内田貴之, 木村啓二, 笠原博徳
情報処理学会並列処理シンポジウム(JSPP2002) 2002.05
Static coarse grain task scheduling with cache optimization using openMP
Hirofumi Nakano, Kazuhisa Ishizaka, Motoki Obata, Keiji Kimura, Hironori Kasahara
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 2327 479 - 489 2002
Multigrain parallel processing for JPEG encoding on a single chip multiprocessor
T Kodaka, K Kimura, H Kasahara
INTERNATIONAL WORKSHOP ON INNOVATIVE ARCHITECTURE FOR FUTURE GENERATION HIGH-PERFORMANCE PROCESSORS AND SYSTEMS 57 - 63 2002 [Refereed]
Multigrain automatic parallelization in Japanese Millennium Project IT21 Advanced Parallelizing Compiler
H Kasahara, M Obata, K Ishizaka, K Kimura, H Kaminaga, H Nakano, K Nagasawa, A Murai, H Itagaki, J Shirako
PAR ELEC 2002: INTERNATIONAL CONFERENCE ON PARALLEL COMPUTING IN ELECTRICAL ENGINEERING 105 - 111 2002 [Refereed]
Evaluation of Processor Core Architecture for Single Chip Multiprocessor with Near Fine Grain Parallel Processing
K. Kimura, T. Kato, H. Kasahara
Trans. of IPSJ 42 ( 4 ) 692 - 703 2001.04 [Refereed]
Authorship:Lead author
Evaluation of Single Chip Multiprocessor Core Architecture with Near Fine Grain Parallel Processing
Keiji Kimura, Hironori Kasahara
Proc. of International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'01) 2001.01 [Refereed]
Authorship:Lead author
Near Fine Grain Parallel Processing on Single Chip Multiprocessors
K. Kimura, W. Ogata, M. Okamoto, H. Kasahara
Trans. of IPSJ 40 ( 5 ) 1924 - 1934 1999.05 [Refereed]
Authorship:Lead author
Near fine grain parallel processing using static scheduling on single chip multiprocessors
Keiji Kimura, Hironori Kasahara
Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems 1999- 23 - 31 1999 [Refereed]
Authorship:Lead author
OSCAR multi-grain architecture and its evaluation
H Kasahara, W Ogata, K Kimura, G Matsui, H Matsuzaki, M Okamoto, A Yoshida, H Honda
INNOVATIVE ARCHITECTURE FOR FUTURE GENERATION HIGH-PERFORMANCE PROCESSORS AND SYSTEMS, PROCEEDINGS 106 - 115 1998 [Refereed]
Data-Localization among Doall and Sequential Loops in Coarse Grain Parallel Processing
Akimasa Yoshida, Yasushi Ujigawa, Motoki Obata, Keiji Kimura, Hironori Kasahara
Seventh Workshop on Compilers for Parallel Computers Linkoping Sweden 266 - 277 1998.01 [Refereed]
Near Fine Grain Parallel Processing without Explicit Synchronization on a Multiprocessor System
Wataru Ogata, Akimasa Yoshida, Masami Okamoto, Keiji Kimura, Hironori Kasahara
Proc. of Sixth Workshop on Compilers for Parallel Computers (Aachen Germany) 1996.12 [Refereed]
藤野 里奈, 韓 吉新, 島岡 護, 見神 広紀, 宮島 崇浩, 高村 守幸, 木村 啓二, 笠原 博徳
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 116 ( 510 ) 207 - 212 2017.03
自動車リアルタイム制御計算の複数クラスタ構成マルチコア上での並列化 (コンピュータシステム) -- (組込み技術とネットワークに関するワークショップETNET2017)
宮田 仁, 島岡 護, 見神 広紀, 西 博史, 鈴木 均, 木村 啓二, 笠原 博徳
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 116 ( 510 ) 177 - 182 2017.03
大規模システムを想定したGem5シミュレータの階層的インターコネクションネットワーク拡張 (コンピュータシステム) -- (組込み技術とネットワークに関するワークショップETNET2017)
小野口 達也, 林 綾音, 宇高 勝之, 松島 裕一, 木村 啓二, 笠原 博徳
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 116 ( 510 ) 147 - 152 2017.03
LLVMを用いたベクトルアクセラレータ用コードのコンパイル手法 (コンピュータシステム)
丸岡 晃, 無州 祐也, 狩野 哲史, 持山 貴司, 北村 俊明, 神谷 幸男, 高村 守幸, 木村 啓二, 笠原 博徳
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 116 ( 177 ) 19 - 24 2016.08
Bui Duc Binh, Tomohiro Hirano, Hiroki Mikami, Hideo Yamamoto, Keiji Kimura, Hironori Kasahara
57 ( 4 ) 2016.04
GOTO Takashi, MUTO Kohei, HIRANO Tomohiro, MIKAMI Hiroki, TAKAHASHI Uichiro, INOUE Sakae, KIMURA Keiji, KASAHARA Hironori
IEICE technical report. Computer systems 114 ( 506 ) 95 - 100 2015.03
OSCAR自動並列化コンパイラを用いたリアルタイム動画像アプリケーションのHaswellマルチコア上での低消費電力化 (コンピュータシステム)
飯塚 修平, 山本 英雄, 平野 智大, 岸本 耀平, 後藤 隆志, 見神 広紀, 木村 啓二, 笠原 博徳
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 114 ( 506 ) 219 - 224 2015.03
OSCAR自動並列化コンパイラを用いたリアルタイム動画像アプリケーションのHaswellマルチコア上での低消費電力化 (ディペンダブルコンピューティング)
飯塚 修平, 山本 英雄, 平野 智大, 岸本 耀平, 後藤 隆志, 見神 広紀, 木村 啓二, 笠原 博徳
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 114 ( 507 ) 219 - 224 2015.03
GOTO Takashi, MUTO Kohei, HIRANO Tomohiro, MIKAMI Hiroki, TAKAHASHI Uichiro, INOUE Sakae, KIMURA Keiji, KASAHARA Hironori
IEICE technical report. Dependable computing 114 ( 507 ) 95 - 100 2015.03
動画像デコーディングのIntelおよびARMマルチコア上での並列処理の評価 (ディペンダブルコンピューティング)
和気 珠実, 飯塚 修平, 見神 広紀, 木村 啓二, 笠原 博徳
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 114 ( 507 ) 263 - 268 2015.03
OSCAR自動並列化コンパイラを用いたリアルタイム動画像アプリケーションのHaswellマルチコア上での低消費電力化
飯塚 修平, 山本 英雄, 平野 智大, 岸本 耀平, 後藤 隆志, 見神 広紀, 木村 啓二, 笠原 博徳
研究報告組込みシステム(EMB) 2015 ( 20 ) 1 - 6 2015.02
動画像デコーディングのIntelおよびARMマルチコア上での並列処理の評価
和気 珠実, 飯塚 修平, 見神 広紀, 木村 啓二, 笠原 博徳
研究報告組込みシステム(EMB) 2015 ( 35 ) 1 - 6 2015.02
自動並列化コンパイラによるソフトウェアキャッシュコヒーレンシ制御手法の評価
岸本 耀平, 間瀬 正啓, 木村 啓二, 笠原 博徳
研究報告ハイパフォーマンスコンピューティング(HPC) 2014 ( 19 ) 1 - 7 2014.12
Automatic Parallelization of Designed Engine Control C Codes by MATLAB/Simulink
55 ( 8 ) 1817 - 1829 2014.08
Linux ftraceを用いたマルチコアプロセッサ上での並列化プログラムのトレース手法
福意 大智, 島岡 護, 見神 広紀, Dominic Hillenbrand, 木村 啓二, 笠原 博徳
研究報告計算機アーキテクチャ(ARC) 2014 ( 6 ) 1 - 6 2014.07
大規模無線センサネットワークにおける外乱を考慮したアーキテクチャ探索シミュレータの実装と評価
山下浩一郎, 鈴木貴久, 栗原康志, 大友俊也, 木村啓二, 笠原博徳
マルチメディア、分散協調とモバイルシンポジウム2014論文集 2014 1368 - 1377 2014.07
TAGUCHI Gakuho, KIMURA Keiji, KASAHARA Hironori
IEICE technical report. Dependable computing 113 ( 498 ) 289 - 294 2014.03
A Latency Reduction Technique for IDS by Allocating Decomposed Signature on Multi-core
Shohei Yamada, Hiroki Mikami, Keiji Kimura, Hironori Kasahara
IPSJ SIG Notes 2014 ( 2 ) 1 - 8 2014.02
Automatic Parallelization of Small Point FFT on Multicore Processor
Yuuki Furuyama, Hiroki Mikami, Keiji Kimura, Hironori Kasahara
IPSJ SIG Notes 2014 ( 3 ) 1 - 8 2014.02
プロファイル情報を用いたAndroid 2D描画ライブラリSKIAのOSCARコンパイラによる並列化
後藤隆志, 武藤康平, 山本英雄, 平野智大, 見神広紀, 木村啓二, 笠原博徳
研究報告ハイパフォーマンスコンピューティング(HPC) 2013 ( 12 ) 1 - 7 2013.12
プロファイル情報を用いたAndroid 2D描画ライブラリSKIAのOSCARコンパイラによる並列化
後藤隆志, 武藤康平, 山本英雄, 平野智大, 見神広紀, 木村啓二, 笠原博徳
研究報告計算機アーキテクチャ(ARC) 2013 ( 12 ) 1 - 7 2013.12
OSCAR API標準解釈系を用いた階層グルーピング対応ハードウェアバリア同期機構の評価
川島慧大, 金羽木洋平, 林明宏, 木村啓二, 笠原博徳
研究報告計算機アーキテクチャ(ARC) 2013 ( 16 ) 1 - 6 2013.07
山本 英雄, 後藤 隆志, 平野 智大, 武藤 康平, 見神 広紀, Dominic Hillenbrand, 林 明宏, 木村 啓二, 笠原 博徳
研究報告システムソフトウェアとオペレーティング・システム(OS) 2013 ( 2 ) 1 - 7 2013.02
TAGUCHI GAKUHO, ABE YOUICHI, KIMURA KEIJI, KASAHARA HIRONORI
Technical report of IEICE. ICD 112 ( 425 ) 65 - 71 2013.01
Abe Yoichi, Taguchi Gakuho, Kimura Keiji, Kasahara Hironori
Technical report of IEICE. ICD 112 ( 425 ) 57 - 63 2013.01
Parallelization of Automobile Engine Control Software on Multicore Processor
KANEHAGI YOUHEI, UMEDA DAN, MIKAMI HIROKI, HAYASHI AKIHIRO, SAWADA MITSUO, KIMURA KEIJI, KASAHARA HIRONORI
Technical report of IEICE. ICD 112 ( 425 ) 3 - 10 2013.01
Automatic parallelization with OSCAR API Analyzer: a cross-platform performance evaluation
2012 ( 10 ) 1 - 8 2012.12
Automatic parallelization with OSCAR API Analyzer: a cross-platform performance evaluation
2012 ( 10 ) 1 - 8 2012.12
Parallelization of Basic Engine Controll Software Model on Multicore Processor
2012 ( 22 ) 1 - 7 2012.07
Realization of 1 Watt Web Service with RP-X Low-power Multicore Processor
2012 ( 24 ) 1 - 6 2012.07
KIMURA KEIJI, MASE MASAYOSHI, KASAHARA HIRONORI
IEICE technical report. Dependable computing 111 ( 462 ) 127 - 132 2012.02
Evaluation of Parallelizable C Programs by the OSCAR API Standard Translator
SATO TAKUYA, MIKAMI HIROKI, HAYASHI AKIHIRO, MASE MASAYOSHI, KIMURA KEIJI, KASAHARA HIRONORI
2010 ( 2 ) 1 - 6 2010.10
WADA YASUTAKA, HAYASHI AKIHIRO, WATANABE TAKESHI, SEKIGUCHI TAKESHI, MASE MASAYOSHI, SHIRAKO JUN, KIMURA KEIJI, ITO MASAYUKI, HASEGAWA ATSUSHI, SATO MAKOTO, NOJIRI TOHRU, UCHIYAMA KUNIO, KASAHARA HIRONORI
2010 ( 8 ) 1 - 10 2010.07
An Acceleration Technique of Many Core Architecture Simulator Considering Program Structure
ISHIZUKA RYO, OOTOMO TOSHIYA, DAIGO RYOTA, KIMURA KEIJI, KASAHARA HIRONORI
2010 ( 20 ) 1 - 7 2010.07
A Compiler Framework for Heterogeneous Multicores for Consumer Electronics
HAYASHI AKIHIRO, WADA YASUTAKA, WATANABE TAKESHI, SEKIGUCHI TAKESHI, MASE MASAYOSHI, KIMURA KEIJI, ITO MASAYUKI, HASEGAWA ATSUSHI, SATO MAKOTO, NOJIRI TOHRU, UCHIYAMA KUNIO, KASAHARA HIRONORI
2010 ( 7 ) 1 - 9 2010.07
Parallelizing Compiler Directed Software Coherence
MASE MASAYOSHI, KIMURA KEIJI, KASAHARA HIRONORI
2010 ( 7 ) 1 - 10 2010.04
Multi Media Offload with Automatic Parallelization
ISHIZAKA KAZUHISA, SAKAI JUNJI, EDAHIRO MASATO, MIYAMOTO TAKAMICHI, MASE MASAYOSHI, KIMURA KEIJI, KASAHARA HIRONORI
2010 ( 59 ) 1 - 7 2010.03
MIYAMOTO TAKAMICHI, MASE MASAYOSHI, KIMURA KEIJI, ISHIZAKA KAZUHISA, SAKAI JUNJI, EDAHIRO MASATO, KASAHARA HIRONORI
2010 ( 9 ) 1 - 8 2010.02
Hierarchical Parallel Processing of H.264/AVC Encoder on an Multicore Processor
MIKAMI Hiroki, MIYAMOTO Takamichi, KIMURA Keiji, KASAHARA Hironori
2010 ( 22 ) 1 - 6 2010.01
Automatic Parallelization of Parallelizable C Programs on Multicore Processors
MASE MASAYOSHI, KIMURA KEIJI, KASAHARA HIRONORI
2009 ( 15 ) 1 - 10 2009.07
SHIMAOKA MAMORU, IMAIZUMI KAZUHIRO, TAKANO FUMIYO, KIMURA KEIJI, KASAHARA HIRONORI
IPSJ SIG Notes 2009 ( 14 ) 127 - 132 2009.02
SHIMAOKA MAMORU, IMAIZUMI KAZUHIRO, TAKANO FUMIYO, KIMURA KEIJI, KASAHARA HIRONORI
IPSJ SIG Notes 2009 ( 14 ) 127 - 132 2009.02
Local Memory Management Scheme by a Compiler for Multicore Processor
MOMOZONO Taku, NAKANO Hirofumi, MASE Masayoshi, KIMURA Keiji, KASAHARA Hironori
IEICE technical report 108 ( 375 ) 69 - 74 2009.01
A Power Saving Scheme on Multicore Processors Using OSCAR API
NAKAGAWA Ryo, MASE Masayoshi, SHIRAKO Jun, KIMURA Keiji, KASAHARA Hironori
IEICE technical report 108 ( 375 ) 93 - 98 2009.01
KAMIYAMA Teruo, WADA Yasutaka, HAYASHI Akihiro, MASE Masayoshi, NAKANO Hirohumi, WATANABE Takeshi, KIMURA Keiji, KASAHARA Hironori
IPSJ SIG Notes 2009 ( 1 ) 63 - 68 2009.01
KAMIYAMA Teruo, WADA Yasutaka, HAYASHI Akihiro, MASE Masayoshi, NAKANO Hirohumi, WATANABE Takeshi, KIMURA Keiji, KASAHARA Hironori
IEICE technical report 108 ( 375 ) 63 - 68 2009.01
KAMIYAMA Teruo, WADA Yasutaka, HAYASHI Akihiro, MASE Masayoshi, NAKANO Hirohumi, WATANABE Takeshi, KIMURA Keiji, KASAHARA Hironori
2009 ( 1 ) 63 - 68 2009.01
A Power Saving Scheme on Multicore Processors Using OSCAR API
NAKAGAWA Ryo, MASE Masayoshi, SHIRAKO Jun, KIMURA Keiji, KASAHARA Hironori
2009 ( 1 ) 93 - 98 2009.01
Local Memory Management Scheme by a Compiler for Multicore Processor
MOMOZONO Taku, NAKANO Hirofumi, MASE Masayoshi, KIMURA Keiji, KASAHARA Hironori
IPSJ SIG Notes 2009 ( 1 ) 69 - 74 2009.01
A Power Saving Scheme on Multicore Processors Using OSCAR API
NAKAGAWA Ryo, MASE Masayoshi, SHIRAKO Jun, KIMURA Keiji, KASAHARA Hironori
IPSJ SIG Notes 2009 ( 1 ) 93 - 98 2009.01
Local Memory Management Scheme by a Compiler for Multicore Processor
MOMOZONO Taku, NAKANO Hirofumi, MASE Masayoshi, KIMURA Keiji, KASAHARA Hironori
2009 ( 1 ) 69 - 74 2009.01
並列化コンパイラ、並列化コンパイル装置、及び並列プログラムの生成方法
6600888
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6335253
笠原 博徳, 木村 啓二
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6018022
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6319880
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木村 啓二, 笠原 博徳
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笠原 博徳, 木村 啓二
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4304347
笠原 博徳, 木村 啓二
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4784842
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ヘテロジニアスマルチプロセッサ向けグローバルコンパイラ
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4784792
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MEXT Award for Science and Technology (Research category)
2014.04 Ministry of Education、Culture、Sports、Science and Technology (MEXT)
A Study of Matrix Multiply by Homomorphic Encryption for Utilizing in Deep Learning Frameworks
Project Year :
A research on a heterogeneous multicore that enables flexible cooperation among CPUs, accelerators and data transfer units on a chip
Project Year :
Real-Time Optimization Algorithms and Their Applications for Control of Large-Scale Nonlinear Spatiotemporal Patterns
Project Year :
A Study of Acceleration Technique for Many-core Architecture Simulation Considering Global Program Structure
Project Year :
ソフトウェア協調整チップマルチプロセッサにおけるデータ利用最適化に関する研究
Prototype Implementation of Non-Volatile Memory Support for RISC-V Keystone Enclave
Lena Yu, Yu Omori, Keiji Kimura
Presentation date: 2021.07
Sparse Neural NetworkにおけるSpMMの並列/ベクトル化による高速化
田處 雄大, 木村 啓二, 笠原 博徳
情報処理学会第236回システム・アーキテクチャ・第194回システムとLSIの設計技術・第56回組込みシステム合同研究発表会(ETNET2021)
Presentation date: 2021.03
整合性ツリーおよび暗号化機構を持つ不揮発性メインメモリエミュレータの実装
林 知輝, 大森 侑, 木村 啓二
情報処理学会第236回システム・アーキテクチャ・第194回システムとLSIの設計技術・第56回組込みシステム合同研究発表会(ETNET2021)
Presentation date: 2021.03
OSCARコンパイラによるMATLAB/Simulinkアプリケーションの自動並列化
古山 凌, 津村 雄太, 川角 冬馬, 仲田 優哉, 梅田 弾, 木村 啓二, 笠原 博徳
情報処理学会第236回システム・アーキテクチャ・第194回システムとLSIの設計技術・第56回組込みシステム合同研究発表会(ETNET2021)
Presentation date: 2021.03
Linuxが動作可能なRISC-V NVMMエミュレータの実装
大森 侑, 木村 啓二
情報処理学会第236回システム・アーキテクチャ・第194回システムとLSIの設計技術・第56回組込みシステム合同研究発表会(ETNET2021)
Presentation date: 2021.03
Automatic Vector-Parallelization by Collaboration of Oscar Automatic Parallelizing Compiler and NEC Vectorizing Compiler
Yuta Tadokoro, Hiroki Mikami, Takeo Hosomi, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, 2020-ARC-240 IPSJ
Presentation date: 2020.03
Consideration of Accelerator Cost Estimation Method in Multi-Target Automatic Parallelizing Compiler
Kazuki Yamamoto, Kazuki Fujita, Tomoya Kashimata, Ken Takahashi, Boma A. Adhi, Toshiaki Kitamura, Akihiro Kawashima, Akira Nodomi, Yuji Mori, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, 2020-ARC-240 IPSJ
Presentation date: 2020.03
Extensions of OSCAR Compiler for Parallelizing C++ Programs
Toma Kawasumi, Tilman Priesner, Masato Noguchi, Jixin Han, Hiroki Mikami, Takahiro Miyajima, Keishiro Tanaka, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, 2020-ARC-240 IPSJ
Presentation date: 2020.03
NDCKPT: Transparent Check Pointing Mechanism on Non Volatile Memory by OS
Hikaru Nishida, Keiji Kimura
Technical Report of IEICE, CPSY2019-102 IEICE
Presentation date: 2020.03
Investigation into Acceleration of Matrix-multiply in Homomorphic Encryption
Tetsuya Makita, Teppei Shishido, Yasutaka Wada, Keiji Kimura
Technical Report of IEICE, CPSY2019-96 IEICE
Presentation date: 2020.03
Cascaded DMAC Enabling Efficient Data Transfer for Indirect Memory Access Applications
Keiji Kimura [Invited]
RECS
Presentation date: 2019.11
Automatic parallelizing and vectorizing compiler framework for OSCAR vector multicore processor.
Kazuki Miyamoto, Tetsuya Makita, Ken Takahashi, Tomoya Kashimata, Takumi Kawada, Satoshi Karino, Toshiaki Kitamura, Keiji Kimura, Hironori kasahara
Technical Report of IPSJ, 2018-ARC-230 IPSJ
Presentation date: 2018.03
Automatic Local Memory Management Using Hierarchical Adjustable Block for Multicores and Its Performance Evaluation
Tomoya Shirakawa, Yuto abe, Yoshitake Ooki, Akimasa Yoshida, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, 2017-ARC-220 IPSJ
Presentation date: 2017.11
A Reproducible Full Computer System emulator
Yuki Shimizu, Mineo Takai, Keiji Kimura
Multimedia, Distributed, Cooperative, and Mobile Symposium(DICOMO 2017) IPSJ
Presentation date: 2017.07
Hierarchical Interconnection Network Extension for Gen 5 Simulator Considering Large Scale Systems
Tatsuya Onoguchi, Ayane Hayashi, Katsuyuki Utaka, Yuichi Matsushima, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ,Vol.2017-ARC-221 IPSJ
Presentation date: 2017.03
Parallel Processing of Automobile Real-time Control on Multicore System with Multiple Clusters
Jin Miyata, Mamoru Shimaoka, Hiroki Mikami, Hirofumi Nishi, Hitoshi Suzuki, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ,Vol.2017-ARC-221 IPSJ
Presentation date: 2017.03
Code Generating Method with Profile Feedback for Reducing Compilation Time of Automatic Parallelizing Compiler
Rina Fujino, Jixin Han, Mamoru Shimaoka, Hiroki Mikami, Takahiro Miyajima, Moriyuki Takamura, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ,Vol.2017-ARC-221 IPSJ
Presentation date: 2017.03
Development of Compilation Flow and Evaluation of OSCAR Vector Multicore Architecture
Ken Takahashi, Satoshi Karino, Kazuki Miyamoto, Takumi Kawata, Tomoya Kashimata, Tetsuya Makita, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara
Proc. 80th Annual Convention IPSJ IPSJ
Presentation date: 2017.03
FPGA implementation of OSCAR Vector Accelerator
Tomoya Kashimata, Satoshi Karino, Kazuki Miyamoto, Takumi Kawata, Ken Takahashi, Tetsuya Makita, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara
Proc. 80th Annual Convention IPSJ IPSJ
Presentation date: 2017.03
A Compilation Framework for Multicores having Vector Accelerators using LLVM
Akira Maruoka, Yuya Mushu, Satoshi Karino, Takashi Mochiyama, Toshiaki Kitamura, Sachio Kamiya, Moriyuki Takamura, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ,Vol.2017-ARC-221 IPSJ
Presentation date: 2016.08
Multigrain Parallelization of Program for Medical Image Filtering
Mariko Okumura, Tomoyuki Shibasaki, Kohei Kuwajima, Hiroki Mikami, Keiji Kimura, Kohei Kadoshita, Keiichi Nakano, Hironori Kasahara
IPSJ SIG Technical Report Vol.2016-HPC0153 IPSJ
Presentation date: 2016.03
Automatic Multigrain Parallel Processing for 3D Noise Reduction Using OSCAR Compiler
Tomoyuki Shibasaki, Kohei Kuwajima, Mariko Okumura, Hiroki Mikami, Keiji Kimura, Kohei Kadoshita, Keiichi Nakano, Hironori Kasahara
IPSJ SIG Technical Report Vol.2016-HPC0153 IPSJ
Presentation date: 2016.03
The parallelism abstraction method with a data conversion at analysis in a OSCAR compiler
Naoto Kageura, Tamami Wake, Ji Xin Han, Keiji Kimura, Hironori Kasahara
IPSJ SIG Technical Report Vol.2016-HPC0153 IPSJ
Presentation date: 2016.03
Multicore Local Memory Management Scheme using Data Multidimensional Aligned Decomposition
Kohei Yamamoto, Tomoya Shirakawa, Akimasa Yoshida, Keiji Kimura, Hironori Kasahara
IPSJ SIG Technical Report Vol.2016-SLDM-174 IPSJ
Presentation date: 2016.01
An Evaluation of the Repeatability of Full Computer System Emulation
Daichi Fukui, Teruhiro Mizumoto, Shinsuke Nishimoto, Shigeru Kaneda, Mineo Takai, Keiji Kimura
Multimedia, Distributed, Cooperative, and Mobile Symposium(DICOMO 2015) IPSJ
Presentation date: 2015.07
Evaluation of Parallelization of video decoding on Intel and ARM Multicore
Tamami Wake, Shuhei Iizuka, Hiroki Mikami, Keiji Kimura, Hironori Kasahara
IPSJ SIG Technical Report Vol.2015-EMB-36 IPSJ
Presentation date: 2015.03
Dynamic Scheduling Algorithm for Automatically Parallelized and Power Reduced Applications on Multicore Systems
Takashi Goto, Kohei Muto, Tomohiro Hirano, Hiroki Mikami, Uichiro Takahashi(Fujitsu, Sakae Inoue(Fujitsu, Keiji Kimura, Hironori Kasahara
IPSJ SIG Technical Report Vol.2015-SLDM-170 IPSJ
Presentation date: 2015.03
Power Reduction of Real-time Dynamic Image Processing on Haswell Multicore Using OSCAR Compiler
Shuhei Iizuka, Hideo Yamamoto, Tomohiro Hirano, Youhei Kishimoto, Takashi Goto, Hiroki Mikami, Keiji Kimura, Hironori Kasahara
IPSJ SIG Technical Report Vol.2015-EMB-36 IPSJ
Presentation date: 2015.03
Evaluation of Software Cashe Coherency Cotrol Scheme by an Automatic Parallelizing Compiler
Yohei Kishimoto, Masayoshi Mase, Keiji Kimura, Hironori Kasahara
IPSJ SIG Technical Report Vol.2014-ARC-213 No.19 IPSJ
Presentation date: 2014.12
Android Demonstration System of Automatic Parallelization and Power Optimization by OSCAR Compiler
Bui Duc Binh, Tomohiro Hirano, Hiroki Mikami, Dominic Hillenbrand, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ,Vol.2014-ARC-211 No.6 IPSJ
Presentation date: 2014.07
Tracing method of a parallelized program using Linux ftrace on a multicore processor
Daichi Fukui, Mamoru Shimaoka, Hiroki Mikami, Dominic Hillenbrand, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ,Vol.2014-ARC-211 No.6 IPSJ
Presentation date: 2014.07
A Latency Reduction Technique for Network Intrusion Detection System on Multicores
Keiji Kimura [Invited]
MPSoC
Presentation date: 2014.07
Automatic Parallelization of Small Point FFT on Multicore Processor
Yuuki Furuyama, Hiroki Mikami, Keiji Kimura, Hironori Kasahara
IPSJ SIG Technical Report Vol.2013-ARC-201 IPSJ
Presentation date: 2014.03
A Latency Reduction Technique for IDS by Allocating Decomposed Signature on Multi-core
Shohei Yamada, Hiroki Mikami, Keiji Kimura, Hironori Kasahara
IPSJ SIG Technical Report Vol.2013-ARC-201 IPSJ
Presentation date: 2014.03
A Parallelizing Compiler Cooperative Acceleration Technique of Multicore Architecture Simulation using a Statistical Method
TAGUCHI Gakuho, KIMURA Keiji, KASAHARA Hironori
IPSJ SIG Technical Report IEICE
Presentation date: 2014.03
Profile-Based Automatic Parallelization for Android 2D Rendering by Using OSCAR Compiler
Takashi Goto, Kohei Muto, Hideo Yamamoto, Tomohiro Hirano, Hiroki Mikami, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, Vol.2013-ARC-207 No.12 IPSJ
Presentation date: 2013.12
Automatic Parallelization of Automatically Generated Engine Control C Codes by Model-based Design
Dan Umeda, Youhei Kanehagi, Hiroki Mikami, Mitsuhiro Tani(DENSO, Yuji Mori(DENSO, Keiji Kimura, Hironori Kasahara
Embedded System Symposium2013 IPSJ
Presentation date: 2013.10
An Evaluation of Hardware Barrier Synchronization Mechanism Considering Hierarchical Processor Grouping using OSCAR API Standard Translator
Akihiro Kawashima, Yohei Kanehagi, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, Vol.2013-ARC-206 No.16 IPSJ
Presentation date: 2013.08
Automatic Power Control on Multicore Android Devices
Tomohiro Hirano, Hideo Yamamoto, Kohei Muto, Hiroki Mikami, Takashi Goto, Dominic Hillenbrand, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, Vol.2013-ARC-206 No.23 IPSJ
Presentation date: 2013.08
OSCAR API v2.1 with Flexible Accelerator Control Facilities
Keiji Kimura [Invited]
MPSoC
Presentation date: 2013.07
マルチコア用並列化アプリケーション開発の基礎と実例
木村啓二 [Invited]
ESEC 2013 専門セミナー Reed Exhibition Japan
Presentation date: 2013.05
Enhancing the Performance of a Multiplayer Game by Using a Parallelizing Compiler
Yasir I. M. Al-Dosary, Yuki Furuyama, Dominic Hillenbrand, Keiji Kimura, Hironori Kasahara, Seinosuke Narita
Technical Report of IPSJ IPSJ
Presentation date: 2013.04
An Investigation of Parallelization and Evaluation on Commercial Multi-core Smart Device
Hideo Yamamoto, Takashi Goto, Tomohiro Hirano, Kouhei Muto, Hiroki Mikami, Dominic Hillenbrand, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, Vol. 2013-OS-124 No. 000310 IPSJ
Presentation date: 2013.02
Parallelization of Automobile Engine Control Software on Multicore Processor
KANEHAGI YOUHEI, UMEDA DAN, MIKAMI HIROKI, HAYASHI AKIHIRO, SAWADA MITSUO, KIMURA KEIJI, KASAHARA HIRONORI
Technical Report of IPSJ, Vol.2013-ARC-203 No.2 IPSJ
Presentation date: 2013.01
An Accelemtion Technique of Many-core Architecture Simulation with Parallelized Applications by Statistical Technique
Abe Yoichi, Taguchi Gakuho, Kimura Keiji, Kasahara Hironori
Technical Report of IPSJ, Vol.2012-ARC-203 N0.13 IPSJ
Presentation date: 2013.01
A Parallelizing Compiler Cooperative Multicore Architecture Simulator with Changeover Mechanism of Simulation Modes
TAGUCHI GAKUHO, ABE YOUICHI, KIMURA KEIJI, KASAHARA HIRONORI
Technical Report of IPSJ, Vol.2012-ARC-203 N0.14 IPSJ
Presentation date: 2013.01
Automatic parallelization with OSCAR API Analyzer: a cross-platform performance evaluation
Cecilia Gonzalez-Alvarez, Youhei Kanehagi, Kosei Takemoto, Yohei Kishimoto, Kohei Muto, Hiroki Mikami, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, Vol.2012-ARC-202HPC137 No.10 IPSJ
Presentation date: 2012.12
Automatic Parallelization of Ground Motion Simulator
Mamoru Shimaoka, Hiroki Mikami, Akihiro Hayashi, Yasutaka Wada, Keiji Kimura, Hidekazu Morita, HITACHI, Kunio Uchiyama, HITACHI, Hironori Kasahara
Technical Report of IPSJ, Vol.2012-ARC-202HPC137 No.11 IPSJ
Presentation date: 2012.12
Opportunities and Challenges of Application-Power Control in the Age of Dark Silicon
Dominic Hillenbrand, Yuuki Furuyama, Akihiro Hayashi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, Vol.2012-ARC-202HPC137 No.26 IPSJ
Presentation date: 2012.12
Parallel processing of multimedia applications on TILEPro64 using OSCAR API for embedded multicore
Yohei Kishimoto, Hiroki Mikami, Keiichi Nakano, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara
Embedded System Symposium2012 IPSJ
Presentation date: 2012.10
Parallelization of Basic Engine Controll Software Model on Multicore Processor
Dan Umeda, Youhei Kanehagi, Hiroki Mikami, Akihiro Hayashi, Mituhiro Tani, Yuji Mori, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, Vol.2012-ARC-201 No.22 IPSJ
Presentation date: 2012.08
Realization of 1 Watt Web Service with RP-X Low-power Multicore Processor
Yuuki Furuyama, Mamoru Shimaoka, Hiroki Mikami, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, Vol.2012-ARC-201 No.24 IPSJ
Presentation date: 2012.08
OSCAR API for Low-Power Multicores and Manycores, and API Standard Translator
Keiji Kimura [Invited]
MPSoC
Presentation date: 2012.07
並列化コンパイラを考慮したコーディング作法と並列化APIの現在
木村啓二 [Invited]
ESEC 2012 専門セミナー Reed Exhibition Japan
Presentation date: 2012.05
A Definition of Parallelizable C by JISX0180:2011 "Framework of establishing coding guidelines for embedded system development"
KIMURA KEIJI, MASE MASAYOSHI, KASAHARA HIRONORI
ETNET2012 IPSJ
Presentation date: 2012.03
Inlining Analysis of Exception Flow and Fast Method Dispatch on Automatic Parallelization of Java
Keiichi Tabata, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, Vol. 2012-ARC-199 IPSJ
Presentation date: 2012.03
An Examination of Accelerating Many-core Architecture Simulation for Parallelized Media Applications
Yoichi Abe, Ryo Ishizuka, Ryota Daigo, Gakuho Taguchi, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, Vol. 2012-ARC-199 IPSJ
Presentation date: 2012.03
Automatic Parallelization of Dose Calculation Engine for A Particle Therapy
Akihiro Hayashi, Takuji Matsumoto, Hiroki Mikami, Keiji Kimura, Keiji Yamamoto, Hironori Saki, Yasuyuki Takatani, Hironori Kasahara
Symposium on High-Performance Computing and Computer Science(HPCS2012) IPSJ
Presentation date: 2012.01
Automatic Parallelization of Dose Calculation Engine for A Particle Therapy on SMP Servers
Akihiro Hayashi, Takuji Matsumoto, Hiroki Mikami, Keiji Kimura, Keiji Yamamoto, Hironori Saki, Yasuyuki Takatani, Hironori Kasahara
Technical Report of IPSJ, Vol.2011-ARC189HPC132-2 IPSJ
Presentation date: 2011.11
Examination of Parallelization by CUDA in SPEC Benchmark Programs
Yuki Taira, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, 2011-HPC-130-16 IPSJ
Presentation date: 2011.07
An Evaluation of an Acceleration method of Many-core Architecture Simulation using Program Structures of Scientific Applications
Ryo Ishizuka, Yoichi Abe, Ryota Daigo, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, 2011-ARC-196-14 IPSJ
Presentation date: 2011.07
並列化APIとコンパイラによるマルチコア用アプリケーションの開発
木村啓二 [Invited]
ESEC 2011 専門セミナー Reed Exhibition Japan
Presentation date: 2011.05
Hiding I/O overheads with Parallelizing Compiler for Media Applications
Akihiro Hayashi, Takeshi Sekiguchi, Masayoshi Mase, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, 2011-ARC-195-14 IPSJ
Presentation date: 2011.04
Evaluation of Power Consumption by Executing Media Applications on Low-power Multicore RP2
Hiroki Mikami, Shumpei Kitaki, Takafumi Sato, Masayoshi Mase, Keiji Kimura, Kazuhisa Ishizaka, Junji Sakai, Masato Edahiro, Hironori Kasahara
Technical Report of IPSJ, 2011-ARC-194-1 IPSJ
Presentation date: 2011.03
Evaluation of Parallelizable C Programs by the OSCAR API Standard Translator
SATO TAKUYA, MIKAMI HIROKI, HAYASHI AKIHIRO, MASE MASAYOSHI, KIMURA KEIJI, KASAHARA HIRONORI
Technical Report of IPSJ, 2010-ARC-191-2 IPSJ
Presentation date: 2010.10
An Acceleration Technique of Many Core Architecture Simulator Considering Program Structure
ISHIZUKA RYO, OOTOMO TOSHIYA, DAIGO RYOTA, KIMURA KEIJI, KASAHARA HIRONORI
Technical Report of IPSJ, 2010-ARC-190 No. 20 IPSJ
Presentation date: 2010.08
Performance of Power Reduction Scheme by a Compiler on Heterogeneous Multicore for Consumer Electronics "RP-X"
WADA YASUTAKA, HAYASHI AKIHIRO, WATANABE TAKESHI, SEKIGUCHI TAKESHI, MASE MASAYOSHI, SHIRAKO JUN, KIMURA KEIJI, ITO MASAYUKI, HASEGAWA ATSUSHI, SATO MAKOTO, NOJIRI TOHRU, UCHIYAMA KUNIO, KASAHARA HIRONORI
Technical Report of IPSJ, 2010-ARC-190 No. 8 IPSJ
Presentation date: 2010.08
A Compiler Framework for Heterogeneous Multicores for Consumer Electronics
HAYASHI AKIHIRO, WADA YASUTAKA, WATANABE TAKESHI, SEKIGUCHI TAKESHI, MASE MASAYOSHI, KIMURA KEIJI, ITO MASAYUKI, HASEGAWA ATSUSHI, SATO MAKOTO, NOJIRI TOHRU, UCHIYAMA KUNIO, KASAHARA HIRONORI
Technical Report of IPSJ, 2010-ARC-190 No. 7 IPSJ
Presentation date: 2010.08
組込みマルチコア用並列化APIと並列化コンパイラの現在
木村啓二 [Invited]
ESEC 2010 専門セミナー Reed Exhibition Japan
Presentation date: 2010.05
Parallelizing Compiler Directed Software Coherence
MASE MASAYOSHI, KIMURA KEIJI, KASAHARA HIRONORI
Technical Report of IPSJ, 2010-ARC-189, 2010-OS-114 IPSJ
Presentation date: 2010.04
Multi Media Offload with Automatic Parallelization
ISHIZAKA KAZUHISA, SAKAI JUNJI, EDAHIRO MASATO, MIYAMOTO TAKAMICHI, MASE MASAYOSHI, KIMURA KEIJI, KASAHARA HIRONORI
Technical Report of IPSJ, 2010-SLDM144, 2010-EMB16 IPSJ
Presentation date: 2010.03
Processing Performance of Automatically Parallelized Applications on Embedded Multicore with Running Multiple Applications
Takamichi Miyamoto, Masayoshi Mase, Keiji Kimura, Kazuhisa Ishizaka, Junji Sakai, Masato Edahiro
Technical Report of IPSJ, 2010-ARC-188 No.9 IPSJ
Presentation date: 2010.03
Hierarchical Parallel Processing of H.264/AVC Encoder on an Multicore Processeor
Hiroki Mikami, Takamichi Miyamoto, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ Vol.2010-ARC-187 No.22 Vol.2010-EMB-15 No.22 IPSJ
Presentation date: 2010.01
Element-Sensitive Pointer Analysis for Automatic Parallelization
Masayoshi Mase, Yuta Murata, Keiji Kimura, Hironori Kasahara
IPSJ-SIGPRO IPSJ
Presentation date: 2009.10
メニーコア・プロセッサとそれを支える要素技術
井上 弘士, 木村 啓二, 松谷 宏紀 [Invited]
組込システムシンポジウム 2009 情報処理学会
Presentation date: 2009.10
Automatic Parallelization of Parallelizable C Programs on Multicore Processors
Masayoshi Mase, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, 2009-ARC-184-15 IPSJ
Presentation date: 2009.08
組込みソフトウェアの信頼性,開発効率向上のためのコーディングガイドライン
木村啓二 [Invited]
平成21年度 INSTAC成果報告会
Presentation date: 2009.07
A Power Reduction Scheme of Parallelizing Compiler Using OSCAR API on Multicore Processor
Ryo Nakagawa, Masayoshi Mase, Naoto Ohkuni, Jun Shirako, Keiji Kimura, Hironori Kasahara
Symposium on Advanced Computing Systems and Infrastructures (SACSIS 2009) IPSJ
Presentation date: 2009.05
最新の組込みマルチコア用コンパイラ技術と並列API
木村啓二 [Invited]
ESEC 2009 専門セミナー Reed Exhibition Japan
Presentation date: 2009.05
Performance Evaluation of Minimum Execution Time Multiprocessor Scheduling Algorithms Using Standard Task Graph Set Ver3 Consider Parallelism of Task Graphs and Deviation of Task Execution Time
Mamoru Shimaoka, Kazuhiro Imaizumi, Fumiyo Takano, Keiji Kimura, Hironori Kasahara
Technical Report of IEICE IPSJ
Presentation date: 2009.02
A Power Saving Scheme on Multicore Processors Using OSCAR API
Ryo Nakagawa, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara
TECHNICAL REPORT OF IEICE. (ICD2008/145) IEICE
Presentation date: 2009.01
Local Memory Management Scheme by a Compiler for Multicore Processor
Taku Momozono, Hirofumi Nakano, Masayoshi Mase, Keiji Kimura, Hironori Kasahara
TECHNICAL REPORT OF IEICE. (ICD2008/141) IEICE
Presentation date: 2009.01
Performance Evaluation of Parallelizing Compiler Cooperated Heterogeneous Multicore Architecture Using Media Applications
Teruo Kamiyama, Yasutaka Wada, Akihiro Hayashi, Masayoshi Mase, Hirofumi Nakano, Takeshi Watanabe, Keiji Kimura, Hironori Kasahara
TECHNICAL REPORT OF IEICE. (ICD2008/140) IEICE
Presentation date: 2009.01
マルチコアのソフトウェア開発
木村啓二 [Invited]
CEATEC JAPAN 2008 インダストリアルセッション(IS) JEITA
Presentation date: 2008.10
マルチコア用コンパイル技術の現在
木村啓二 [Invited]
第10回 組み込みシステム技術に関するサマーワークショップ (SWEST10) 情報処理学会
Presentation date: 2008.09
マルチコアプロセッサのソフトウェア
木村啓二 [Invited]
第31回STARCアドバンスト講座 システムアーキテクチャ セミナー - SoCシステムアーキテクチャ - STARC
Presentation date: 2008.07
An Evaluation of Barrier Synchronization Mechanism Considering Hierarchical Processor Grouping
Kaito Yamada, Masayoshi Mase, Jun Shirako, Keiji Kimura, Masayuki Ito, Toshihiro Hattori, Hiroyuki Mizuno, Kunio Uchiyama, Hironori Kasahara
Technical Report of IPSJ, IPSJ
Presentation date: 2008.05
Automatic Parallelization of Restricted C Programs using Pointer Analysis
Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Yuta Murata, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, 2008 IPSJ
Presentation date: 2008.05
Parallelization of Multimedia Applications by Compiler on Multicores for Consumer Electronics
Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Keiji Kimura, Hironori Kasahara
Symposium on Advanced Computing Systems and Infrastructures (SACSIS 2008) IPSJ
Presentation date: 2008.05
Parallelization for Multimedia Processing on Multicore Processors
Takamichi Miyamoto, Kei Tamura, Hiroaki Tano, Hiroki Mikami, Saori Asaka, Masayoshi Mase, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, 2007-ARC-175-05 IPSJ
Presentation date: 2007.11
最新の組み込みマルチコア用コンパイラ技術
木村啓二 [Invited]
システムLSIワークショップ 情報処理学会
Presentation date: 2007.11
Multigrain Parallelization of Restricted C Programs in SMP Execution Mode of a Multicore for Consumer Electronics
Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Hiroaki Tano, Takeshi Masuura, Takamichi Miyamoto, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara
Embedded Systems Symposium 2007 (ESS 2007) IPSJ
Presentation date: 2007.10
Compiler Control Power Saving for Heterogeneous Multicore Processor
Akihiro Hayashi, Taketo Iyoku, Ryo Nakagawa, Shigeru Matsumoto, Kaito Yamada, Naoto Oshiyama, Jun Shirako, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, 2007-ARC-174-18 IPSJ
Presentation date: 2007.08
A Hierarchical Coarse Grain Task Static Scheduling Scheme on a Heterogeneous Multicore
Yasutaka Wada, Akihiro Hayashi, Taketo Iyoku, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, 2007-ARC-174-17 IPSJ
Presentation date: 2007.08
Evaluation of Heterogeneous Multicore Architecture with AAC-LC Stereo Encoding
Hiroaki Shikano, Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Masafumi Onouchi, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
TECHNICAL REPORT OF IEICE. (ICD2007-71) IEICE
Presentation date: 2007.08
マルチコア用コンパイラ技術
木村啓二 [Invited]
165委員会主催研究会第46回研究会 「マルチコアプロセッサSoCの現状と今後の展望」
Presentation date: 2007.07
組込マルチコアの動向
木村啓二 [Invited]
JEITA 情報端末フェスティバル 2007 JEITA
Presentation date: 2007.06
A 4320MIPS four Processor-core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption
Kiyoshi hayase, Yutaka Yoshida, Tatsuya Kamei, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, 2007-ARC-173-06 IPSJ
Presentation date: 2007.05
Mutligrain Parallel Processing in SMP Execution Mode on a Multicore for Consumer Electronics
Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Hiroaki Tano, Takeshi Masuura, Takamichi Miyamoto, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Tatsuya Kamei, Toshihiro Hattori, Atsushi Hasegawa, Makoto Sato, Masaki Ito, Toshihiko Odaka, Hironori Kasahara
Technical Report of IPSJ, 2007-ARC-173-05 IPSJ
Presentation date: 2007.05
マルチコアプロセッサ活用の勘所
木村啓二 [Invited]
組み込みプロセッサ&プラットホームワークショップ
Presentation date: 2007.04
A Local Memory Management Scheme in Multigrain Parallelizing Compiler
Miura Tsuyoshi, Tomohiro Tagawa, Yusuke Muramatsu, Akinori Ikemi, Masahiro Nakagawa, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, 2007-ARC-172-11 IPSJ
Presentation date: 2007.03
Automatic Parallelization for Multimedia Applications on Multicore Processors
Takamichi Miyamoto, Saori Asaka, Nobuhito Kamakura, Hiromasa Yamauchi, Masayoshi Mase, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, 2007-ARC-171-13 IPSJ
Presentation date: 2007.01
Automati Parallelization of Restricted C Ptrograms in OSCAR Compiler
Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Hiroaki Tano, Takeshi Masuura, Koji Fukatsu, Takamichi Miyamoto, Jun Shirako, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, 2006-ARC-170-1 IPSJ
Presentation date: 2006.11
Performance of OSCAR Multigrain Parallelizaing Compiler on SMP Servers and Embedded Multicore
Jun Shirako, Tomohiro Tagawa, Tsuyoshi Miura, Takamichi Miyamoto, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, 2006-ARC-170-2 IPSJ
Presentation date: 2006.11
ソフトウェアもおもしろいこれからのプロセッサアーキテクチャ
木村啓二 [Invited]
FIT2006イベント企画「これからが面白いプロセッサアーキテクチャ」(パネル) 情報処理学会
Presentation date: 2006.09
Local Memory Management on OSCAR Multicore
Hirofumi Nakano, Takumi Nito, Takanori Maruyama, Masahiro Nakagawa, Yuki Suzuki, Yousuke Naito, Takamichi Miyamoto, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, 2006-ARC-169-28 IPSJ
Presentation date: 2006.08
Compiler Control Power Saving Scheme for Multicore Processors
un Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
Proc. of Symposium on Advanced Computing Systems and Infrastructures (SACSIS2006) IPSJ
Presentation date: 2006.05
Data Transfer Overlap of Coarse Grain Task Parallel Processing on a Multicore Processor
Takamichi Miyamoto, Masahiro Nakagawa, Shoichiro Asano, Yosuke Naito, Takumi Nito, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, ARC-2006-167, HPC-2006-105 IPSJ
Presentation date: 2006.02
A Static Scheduling Scheme for Coarse Grain Task on a Heterogeneous Chip Multi Processor
Yasutaka Wada, Naoto Oshiyama, Yuki Suzuki, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, ARC-2006-166 IPSJ
Presentation date: 2006.01
Preliminary Evaluation of Heterogeneous Chip Multi-Processor with MP3 Audio Encoder
Hiroaki Shikano, Yuki Suzuki, Yasutaka Wada, Jun Shirako, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, ARC-2006-166 IPSJ
Presentation date: 2006.01
Data Localization on a Multicore Processor
Hirofumi Nakano, Shoichiro Asano, Yosuke Naito, Takumi Nito, Tomohiro Tagawa, Takamichi Miyamoto, Takeshi Kodaka, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, ARC2005-165-10 IPSJ
Presentation date: 2005.12
Compiler Control Power Saving Scheme for Homogeneous Multiprocessor
Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, ARC2005-164-10 IPSJ
Presentation date: 2005.08
Performance of OSCAR Multigrain Parallelizing Compiler on Shared Memory Multiprocessor Serers
Jun Shirako, Takamichi Miyamoto, Kazuhisa Ishizaka, Motoki Obata, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, ARC2005-161-5 IPSJ
Presentation date: 2005.01
Performance Evaluation of Electronic Circuit Simulation Using Code Generation Method without Array Indirect Access
Akira Kuroda, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, ARC2005-161-1 IPSJ
Presentation date: 2005.01
Parallel Processing for MPEG2 Encoding on OSCAR Chip Multiprocessor
Takeshi Kodaka, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, ARC2004-160-10 IPSJ
Presentation date: 2004.12
Data Localization using Data Transfer Unit on OSCAR Chip Multiprocessor
Hirofumi Nakano, Yosuke Naito, Takahisa Suzuki, Takeshi Kodaka, Kazuhisa Ishizaka, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, ARC2004-159-20 IPSJ
Presentation date: 2004.08
Evaluation of Multigrain Parallelism on OSCAR Chip Multi Processor
Yasutaka Wada, Jun Shirako, Kazuhisa Ishizaka, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, ARC2004-159-11 IPSJ
Presentation date: 2004.08
Evaluation of OSCAR Multigrain Automatic Parallelizing Compiler on IBM pSeries 690
Kazuhisa Ishizaka, Jun Shirako, Motoki Obata, Keiji Kimura, Hironori Kasahara
Proc. 66th Annual Convention IPSJ IPSJ
Presentation date: 2004.03
Parallel Processing for MPEG2 Encoding using Data Localization
Takeshi Kodaka, Hirohumi Nakano, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, ARC2004-156-3 IPSJ
Presentation date: 2004.02
The Data Prefetching of Coarse Grain Task Parallel Processing on Symmetric Multi Proc essor Machine
akamichi Miyamoto, Takahiro Yamaguchi, Takao Tobita, Kazuhisa Ishizaka, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, ARC2003-155-06 IPSJ
Presentation date: 2003.11
Data Localization Scheme using Static Scheduling on Chip Multiprocessor
Hirofumi Nakano, Takeshi Kodaka, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, ARC2003-154-14 IPSJ
Presentation date: 2003.08
Parallel Processing on MPEG2 Encoding for OSCAR Chip Multiprocessor
Takeshi Kodaka, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, ARC2003-154-10 IPSJ
Presentation date: 2003.08
Data Localization using Coarse Grain Task Parallelism on Chip Multiprocessor
Hirofumi Nakano, Takeshi Kodaka, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, ARC2003-151-3 IPSJ
Presentation date: 2003.01
Multigrain Parallel Processing on Motion Vector Estimation for Single Chip Multiprocessor
Takeshi Kodaka, Takahisa Suzuki, Keiji Kimura, Hironori Kasahara
Technical Report of IPSJ, ARC2002-150-6 IPSJ
Presentation date: 2002.11
Multigrain Parallel Processing on OSCAR Chip Multiprocessor
Keiji Kimura, Takeshi Kodaka, Motoki Obata, Hironori Kasahara
Technical Report of IPSJ, ARC2002-150-7 IPSJ
Presentation date: 2002.11
Evaluation of Overhead with Coarse Grain Task Parallel Processing on SMP Machines
Yasutaka Wada, Hirofumi Nakano, Keiji Kimura, Motoki Obata, Hironori Kasahara
Technical Report of IPSJ, ARC2002-148-3 IPSJ
Presentation date: 2002.05
PEG Encoding using Multigrain Parallel Processing on a Shingle Chip Multiprocessor
Takeshi Kodaka, Takayuki Uchida, Keiji Kimura, Hironori Kasahara
Joint Symposium on Parallel Processing 2002 (JSPP2002) IPSJ
Presentation date: 2002.05
Multigrain Parallel Processing for JPEG Encoding Program on an OSCAR type Single Chip Multiprocessor
T. Kodaka, T. Uchida, K. Kimura, H. Kasahara
Technical Report of IPSJ, ARC2002-146-4 IPSJ
Presentation date: 2002.02
Multigrain Parallel Processing on Single Chip Multiprocessor
T. Uchida, T. Kodaka, K. Kimura, H. Kasahara
Technical Report of IPSJ, ARC2002-146-3 IPSJ
Presentation date: 2002.02
Near Fine Grain Parallel Processing on Multimedia Application for Single Chip Multiprocessor
T. Kodaka, N. Miyashita, K. Kimura, H. Kasahara
Technical Report of IPSJ, ARC2001-144-11 IPSJ
Presentation date: 2001.11
A Static Scheduling Scheme for Coarse Grain Tasks considering Cache Optimization on SMP
H. Nakano, K. Ishizaka, M. Obata, K. Kimura, H. Kasahara
Technical Report of IPSJ, ARC2001-144-12 IPSJ
Presentation date: 2001.08
A Static Scheduling Method for Coarse Grain Tasks considering Cache Optimization on Multiprocessor Systems
H. Nakano, K. Ishizaka, M. Obata, K. Kimura, H. Kasahara
Proc. 62nd Annual Convention IPSJ IPSJ
Presentation date: 2001.03
Near Fine Grain Parallel Processing on Multimedia Application for Single Chip Multiprocessor
T. Kodaka, K. Kimura, N. Miyashita, H. Kasahara
Proc. 62nd Annual Convention IPSJ IPSJ
Presentation date: 2001.03
Performance Evaluation of Single Chip Multiprocessor Memory Architecture for Near Fine Grain Parallel Processing
N. Matsumoto, K. Kimura, H. Kasahara
Proc. 62nd Annual Convention IPSJ IPSJ
Presentation date: 2001.03
A Data Transfer Unit on the Single Chip Multiprocessor for Multigrain Prallel Processing
N. Miyashita, K. Kimura, T. Kodaka, H. Kasahara
Proc. 62nd Annual Convention IPSJ IPSJ
Presentation date: 2001.03
Processor Core Architecture of Single Chip Multiprocessor for Near Fine Grain Parallel Processing
K. Kimura, T. Uhida, T. Kato, H. Kasahara
Technical Report of IPSJ, ARC-139-16 IPSJ
Presentation date: 2000.08
Performance Evaluation of Single Chip Multiprocessor for Near Fine Grain Parallel Processing
T. Kato, W. Ogata, K. Kimura, T. Uchida, H. Kasahara
Proc. 60th Annual Convention IPSJ IPSJ
Presentation date: 2000.03
Memory access analyzer for a Multi-grain parallel processing
K. Iwai, M. Obata, K. Kimura, H. Amano, H. Kasahara
Technical Report of IEICE, CPSY99-62 IEICE
Presentation date: 1999.08
Performance Evaluation of Near Fine Grain Parallel Processing on the Single Chip Multiprocessor
K. Kimura, K. Manaka, W. Ogata, M. Okamoto, H. Kasahara
Technical Report of IPSJ, ARC134-5 IPSJ
Presentation date: 1999.08
A Cache Optimization Scheme Using Earliest Executable Condition Analysis
D. Inaishi, K. Kimura, K. Fujimoto, W. Ogata, M. Okamoto, H. Kasahara
Proc. 58th Annual Convention IPSJ IPSJ
Presentation date: 1999.03
A Cache Optimization with Earliest Executable Condition Analysis
D. Inaishi, K. Kimura, K. Fujimoto, W. Ogata, M. Okamoto, H. Kasahara
Technical Report of IPSJ, ARC-130-6 IPSJ
Presentation date: 1998.08
Multigrain parallel Processing on the Single Chip Multiprocessor
K. Kimura, W. Ogata, M. Okamoto, H. Kasahara
Technical Report of IPSJ, ARC98-130-5 IPSJ
Presentation date: 1998.08
A Multigrain Parallelizing Compiler and Its Architectural Support
H. Kasahara, W. Ogata, K. Kimura, M. Obata, T. Tobita, D. Inaishi
TECHNICAL REPORT OF IEICE. (ICD98-10, CPSY98-10, FTS98-10) IEICE
Presentation date: 1998.04
Implementation of FPGA Based Architecture Test Bed For Multi Processor System
W. Ogata, T. Yamamoto, M. Mizuno, K. Kimura, H. Kasahara
IPSJ SIG Notes, 98-ARC-128-14, HPC70-14 IPSJ
Presentation date: 1998.03
Single Chip Multiprocessor Architecture for Multigrain Parallel Processing
K. Kimura, W. Ogata, M. Okamoto, H. Kasahara
Proc. 56th Annual Convention IPSJ IPSJ
Presentation date: 1998.03
A Cache Optimization with Macro-Task Earliest Execution Condition
D. Inaishi, K. Kimura, W. Ogata, M. Okamoto, H. Kasahara
Proc. 56th Annual Convention IPSJ IPSJ
Presentation date: 1998.03
Multi-processor system for Multi-grain Parallel Processing
K. Iwai, T. Fujiwara, T. Morimura, H. Amano, K. Kimura, W. Ogata, H. Kasahara
Technical Report of IEICE, CPSY97-46 IEICE
Presentation date: 1997.08
A Macro Task Dynamic Scheduling Algorithm with Overlapping of Task Processing and Data Transfer
K. Kimura, S. Hashimoto, M. Kogou, W. Ogata, H. Kasahara
Technical Report of IEICE, CPSY97-40 IEICE
Presentation date: 1997.08
新しいメモリ階層を考慮したソフトウェア・ハードウェアの構成法に関する研究
アメリカ North Carolina State University
Communications and Computer Engineering Laboratory
School of Fundamental Science and Engineering
2022 fall semester
Advanced Processor Architecture Technology
School of Fundamental Science and Engineering
2022 spring semester
Advanced Processor Architecture Technology
School of Fundamental Science and Engineering
2022 spring semester
Computer Science and Engineering Laboratory
School of Fundamental Science and Engineering
2022 fall semester
Computer Science and Engineering Laboratory
School of Fundamental Science and Engineering
2022 fall semester
Advanced Processor Architecture Technology
School of Fundamental Science and Engineering
2022 spring semester
Computer Science and Communications Engineering Laboratory A [S Grade]
School of Fundamental Science and Engineering
2022 fall semester
Computer Science and Communications Engineering Laboratory A
School of Fundamental Science and Engineering
2022 fall semester
Introduction to Computers and Networks
School of Fundamental Science and Engineering
2022 spring semester
Advanced Processor Architecture Technology
School of Fundamental Science and Engineering
2022 spring semester
Graduation Thesis A (Fall) [S Grade]
School of Fundamental Science and Engineering
2022 fall semester
Graduation Thesis B (Spring) [S Grade]
School of Fundamental Science and Engineering
2022 spring semester
Computer Science and Communications Engineering Laboratory B
School of Fundamental Science and Engineering
2022 spring semester
System Control Research (Spring)
Graduate School of Information, Production and Systems
2022 spring semester
Master's Thesis (Department of Computer Science and Communications Engineering)
Graduate School of Fundamental Science and Engineering
2022 full year
Special Laboratory B in Computer Science and Communications Engineering
Graduate School of Fundamental Science and Engineering
2022 fall semester
Advanced Processor Architecture
Graduate School of Fundamental Science and Engineering
2022 spring semester
Research on Advanced Processor Architecture
Graduate School of Fundamental Science and Engineering
2022 full year
Master's Thesis (Department of Computer Science and Communications Engineering)
Graduate School of Fundamental Science and Engineering
2022 full year
Special Laboratory A in Computer Science and Communications Engineering
Graduate School of Fundamental Science and Engineering
2022 spring semester
Seminar on Advanced Processor Architecture D
Graduate School of Fundamental Science and Engineering
2022 fall semester
Seminar on Advanced Processor Architecture C
Graduate School of Fundamental Science and Engineering
2022 spring semester
Seminar on Advanced Processor Architecture B
Graduate School of Fundamental Science and Engineering
2022 fall semester
Seminar on Advanced Processor Architecture A
Graduate School of Fundamental Science and Engineering
2022 spring semester
Seminar on Advanced Processor Architecture D
Graduate School of Fundamental Science and Engineering
2022 fall semester
Seminar on Advanced Processor Architecture C
Graduate School of Fundamental Science and Engineering
2022 spring semester
Seminar on Advanced Processor Architecture B
Graduate School of Fundamental Science and Engineering
2022 fall semester
Seminar on Advanced Processor Architecture A
Graduate School of Fundamental Science and Engineering
2022 spring semester
Special Laboratory B in Computer Science and Communications Engineering
Graduate School of Fundamental Science and Engineering
2022 fall semester
Special Laboratory A in Computer Science and Communications Engineering
Graduate School of Fundamental Science and Engineering
2022 spring semester
Advanced Processor Architecture
Graduate School of Fundamental Science and Engineering
2022 spring semester
Research on Advanced Processor Architecture
Graduate School of Fundamental Science and Engineering
2022 full year
Special Seminar B in Computer Science and Communications Engineering
Graduate School of Fundamental Science and Engineering
2022 fall semester
Research on Advanced Processor Architecture
Graduate School of Fundamental Science and Engineering
2022 full year
Research on Advanced Processor Architecture
Graduate School of Fundamental Science and Engineering
2022 full year
Special Seminar A in Computer Science and Communications Engineering
Graduate School of Fundamental Science and Engineering
2022 spring semester
Bachelor Thesis B(Spring Semester)
School of Fundamental Science and Engineering
2022 spring semester
Computer Science and Engineering Laboratory B
School of Fundamental Science and Engineering
2022 spring semester
Computer Science and Engineering Laboratory B [S Grade]
School of Fundamental Science and Engineering
2022 spring semester
Computer Science and Engineering Laboratory A [S Grade]
School of Fundamental Science and Engineering
2022 fall semester
Computer Science and Engineering Laboratory A (2)
School of Fundamental Science and Engineering
2022 fall semester
Advanced Processor Architecture Technology
School of Fundamental Science and Engineering
2022 spring semester
Computer Science and Engineering Laboratory C [S Grade]
School of Fundamental Science and Engineering
2022 fall semester
Computer Science and Engineering Laboratory C
School of Fundamental Science and Engineering
2022 fall semester
Bachelor Thesis B(Spring Semester)
School of Fundamental Science and Engineering
2022 spring semester
Communications and Computer Engineering Laboratory A [S Grade]
School of Fundamental Science and Engineering
2022 fall semester
Communications and Computer Engineering Laboratory A
School of Fundamental Science and Engineering
2022 fall semester
Bachelor Thesis B (Spring Semester)
School of Fundamental Science and Engineering
2022 spring semester
Bachelor Thesis B (Spring Semester)
School of Fundamental Science and Engineering
2022 spring semester
Communications and Computer Engineering Laboratory B
School of Fundamental Science and Engineering
2022 spring semester
Communications and Computer Engineering Laboratory B [S Grade]
School of Fundamental Science and Engineering
2022 spring semester
Advanced Processor Architecture Technology
School of Fundamental Science and Engineering
2022 spring semester
The 31st International Conference on Parallel Architectures and Compilation Techniques (PACT 2022)
The 30th International Conference on Parallel Architectures and Compilation Techniques (PACT 2021)
The 34th International Workshop on Languages and Compilers for Parallel Computing (LCPC 2021)
ACM Principles and Practice of Parallel Programming 2021 (PPoPP 2021), Extended Review Committee
The 26th IEEE International Symposium on High-Performance Computer Architecture Program Committee
IEEE International Parallel & Distributed Processing Symposium (IPDPS 2018-2020) Program Committee
The 37th IEEE International Conference on Computer Design (ICCD 2019) Program track Chair (Processor Architecture)
24th Asia and South Pacific Design Automation Conference (ASP-DAC 2019) Program Committee (On-chip Communication and Networks-on-Chip)
Principles and Practice of Parallel Programming 2018 (PPoPP 2018) Publicity Chair
IEEE COMPSAC 2018 Computer Architecture and Platforms Co-Chairs
The 22nd IEEE International Conference on Parallel and Distributed Systems (ICPADS 2016) Program Vice Chair (Parallel / Distributed Algorithms and Applications)
The 45th International Conference on Parallel Processing (ICPP-2016) Program Committee (Programming Models, Languages and Compilers)
The 3rd International Workshop on Software and Engineering for Parallel Sysmtems (SEPS 2016) Program Committee
The 24th International Conference on Parallel Architectures and Compilation Techniques (PACT 2015) Program Committee
27th International Symposium on Computer Architecture and High Performance Computing (SBAC PAD 2015) Program Committee (Software Track)
15th International Symposium on High-Performance Computer Architecture (HPCA-15) Publicity Co-Chairs
情報処理学会 計算機アーキテクチャ研究会 幹事
The 28th IEEE International Parallel & Distributed Processing Symposium (IPDPS) Program Committee
The 28th IEEE International Parallel & Distributed Processing Symposium (IPDPS) Program Committee
The 24--27th International Workshop on Languages and Compilers for Parallel Computing (LCPC ) Program Committee, Program Chair (2012)
情報処理学会 組込システム研究会 運営委員
The 13th International Forum on Embedded MPSoC and Multicore (MPSoC2013) Finace Co-Chairs
The 27th Internationcal Conference on Supercomputing (ICS 2013) Program Committee
IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XII--XVII) Program Committee
XXVII--XXXII IEEE International Conference on Computer Design (ICCD ) Program Committee (Computer System Design and Application Track)
The 12th International Forum on Embedded MPSoC and Multicore (MPSoC2012) Program Co-Chairs
Advanced Parallel Processing Technology Symposium (APPT ) Program Committee
The 17th IEEE International Conference on Parallel and Distributed Systems (ICPADS ) Program Committee (Multicore Computing and Parallel / Distributed Architecture)
情報処理学会 計算機アーキテクチャ研究会 運営委員
22nd International Symposium on Computer Architecture and High Performance Computing (SBAC PAD ) Program Committee (System Software Track)
IEEE International Symposium on Workload Characterization (IISWC-2010) Program Committee
情報処理学会 学会誌 編集委員 SWG
情報処理学会 システムLSI設計技術研究会(SLDM) 運営委員
情報処理学会論文誌 コンピューティングシステム ACS 論文誌編集委員会
The 38th International Conference on Parallel Processing (ICPP-2009) Program Committee (Programming Models, Languages and Compilers)
IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips IX--XI) Program Committee Vice Chair
IPSJ ComSys Program Committee
ComSys - コンピュータシステムシンポジウム プログラム委員
IPSJ DA Symposium University Chair
情報処理学会 DAシンポジウム 大学幹事
IPSJ SACSIS Program Committee Vice Chair
SACSIS 先進的計算基盤システムシンポジウム プログラム副委員長
IPSJ SACSIS , 2008--2013 Program Committee
SACSIS , 2008--2013 - 先進的計算基盤システムシンポジウム プログラム委員
並列/分散/協調処理に関するサマーワークショップ(SWoPP) 実行委員
情報処理学会 システムソフトウェアとオペレーティング・システム研究会 運営委員
情報処理学会 学会誌 編集委員 BWG, (最終年度主査)
SACSIS 先進的計算基盤システムシンポジウム 会計委員長・プログラム委員