This paper proposes a dynamic scheduling algorithm for multiple automatically parallelized or power reduced applications on a multicore smart devices to gain higher performance and lower power comsumption within the application's deadline. This scheduling algorithm uses the information such as time, power, deadline and number of cores for each application, and is composed of three type of scheduling. Using media codec applications as a benchmark, the proposed scheduling gained 18.5% speedup and 28.8% power reduction compared to FIFO scheduling.

スマートフォンやノートパソコンといったモバイル端末からデータセンタで利用されるサーバーマシンまで,あらゆる計算機において消費電力の削減が最重要課題となっている.これは、消費電力の削減によりモバイル機器においてはバッテリー持続時間の延長により利便性が大幅に向上し,またサーバーマシンにおいては膨大な電力コストや空調コストの削減が実現できるからである.これらの計算機は高性能かつ低消費電力を実現するためにマルチコアプロセッサを搭載したものが主流となっている.しかしながらマルチコアの資源を有効活用してこれらを実現するためには,プログラムの並列化が不可欠であり手動で行うには膨大な工数を必要とする.本稿では,医用・防犯・個人認証・車載などで広く利用されているリアルタイム物体認識処理に対して,OSCAR自動並列化コンパイラによるDVFS及びclock gatingによる電力制御を適用し,現在幅広く利用されているIntel Haswell Core i7-4770Kマルチコア上で評価した. Intel Haswellマルチコア上で,Webカメラからの画像の入力・人の顔の認識処理・画面描画というリアルタイムなシステム全域における消費電力の削減を行ったところ,1PE逐次実行では電力制御なしの場合の31.06[W]から電力制御ありの場合では28.74[W]に、3PEで並列化実行した場合では電力制御なし場合のの41.73[W]から電力制御の場合では17.78[W]に消費電力を削減したことが確認され,物体認識処理におけるマルチコア用のコンパイラ自動電力制御の有用性が確認できた.

スマートフォンやノートパソコンといったモバイル端末からデータセンタで利用されるサーバーマシンまで,あらゆる計算機において消費電力の削減が最重要課題となっている.これは、消費電力の削減によりモバイル機器においてはバッテリー持続時間の延長により利便性が大幅に向上し,またサーバーマシンにおいては膨大な電力コストや空調コストの削減が実現できるからである.これらの計算機は高性能かつ低消費電力を実現するためにマルチコアプロセッサを搭載したものが主流となっている.しかしながらマルチコアの資源を有効活用してこれらを実現するためには,プログラムの並列化が不可欠であり手動で行うには膨大な工数を必要とする.本稿では,医用・防犯・個人認証・車載などで広く利用されているリアルタイム物体認識処理に対して,OSCAR自動並列化コンパイラによるDVFS及びclock gatingによる電力制御を適用し,現在幅広く利用されているIntel Haswell Core i7-4770Kマルチコア上で評価した. Intel Haswellマルチコア上で,Webカメラからの画像の入力・人の顔の認識処理・画面描画というリアルタイムなシステム全域における消費電力の削減を行ったところ, 1PE逐次実行では電力制御なしの場合の31.06[W]から電力制御ありの場合では28.74[W]に、3PEで並列化実行した場合では電力制御なし場合のの41.73[W]から電力制御の場合では17.78[W]に消費電力を削減したことが確認され,物体認識処理におけるマルチコア用のコンパイラ自動電力制御の有用性が確認できた.

This paper proposes a dynamic scheduling algorithm for multiple automatically parallelized or power reduced applications on a multicore smart devices to gain higher performance and lower power comsumption within the application's deadline. This scheduling algorithm uses the information such as time, power, deadline and number of cores for each application, and is composed of three type of scheduling. Using media codec applications as a benchmark, the proposed scheduling gained 18.5% speedup and 28.8% power reduction compared to FIFO scheduling.

本稿では,マルチコアプロセッサを用いて動画像デコーディング処理の高速化を実現する手法として2種類の並列化手法について性能評価を行った.1つ目の並列化手法は並列化対象ループにループスキューイング/ループインターチェンジを適用する手法,2つ目の並列化手法はwave-front手法を適用する手法であり,どちらの場合もマクロブロック間の依存関係を満たしつつこれらの間の並列性を利用することで並列処理が可能となる.評価に用いる動画像コーデックは,MPEG2と比較して約2倍の符号化効率を持ちワンセグ放送等に用いられているH.264/AVCと,H.264/AVCと同等の品質を持ちYoutube等でも採用されている動画規格であるWebMのビデオコーデックVP8である.これらの規格により動画像デコーディングを行うプログラムに対して,上記2つの並列化手法をそれぞれ適用した.Snapdragon APQ8064 Krait 4コアを搭載したNexus7上で評価を行った結果,ループスキューイング/ループインターチェンジ手法で並列化した場合,並列化箇所のみで逐次実行に比べ3コアで1.33倍速度向上し,その一方でwave-front手法では3コアで2.86倍の速度向上が得られた.同様にIntel(R) Xeon(R) CPU X5670プロセッサを搭載したマシンで評価を行った結果,ループスキューイング/ループインターチェンジ手法で並列化した場合,並列化箇所のみで逐次実行に比べ6コアで1.82倍速度向上し,一方でwave-front手法では6コアで4.61倍の速度向上が得られた.

スマートフォンやノートパソコンといったモバイル端末からデータセンタで利用されるサーバーマシンまで，あらゆる計算機において消費電力の削減が最重要課題となっている．これは，消費電力の削減によりモバイル機器においてはバッテリー持続時間の延長により利便性が大幅に向上し，またサーバーマシンにおいては膨大な電力コストや空調コストの削減が実現できるからである．これらの計算機は高性能かつ低消費電力を実現するためにマルチコアプロセッサを搭載したものが主流となっている．しかしながらマルチコアの資源を有効活用してこれらを実現するためには，プログラムの並列化が不可欠であり手動で行うには膨大な工数を必要とする．本稿では，医用・防犯・個人認証・車載などで広く利用されているリアルタイム物体認識処理に対して，OSCAR 自動並列化コンパイラによる DVFS 及び clock gating による電力制御を適用し，現在幅広く利用されている Intel Haswell Core i7-4770K マルチコア上で評価した．Intel Haswell マルチコア上で，Web カメラからの画像の入力・人の顔の認識処理・画面描画というリアルタイムなシステム全域における消費電力の削減を行ったところ，1PE 逐次実行では電力制御なしの場合の 31.06[W] から電力制御ありの場合では 28.74[W] に，3PE で並列化実行した場合では電力制御なし場合のの 41.73[W] から電力制御の場合では 17.78[W] に消費電力を削減したことが確認され，物体認識処理におけるマルチコア用のコンパイラ自動電力制御の有用性が確認できた．

本稿では，マルチコアプロセッサを用いて動画像デコーディング処理の高速化を実現する手法として 2 種類の並列化手法について性能評価を行った．1 つ目の並列化手法は並列化対象ループにループスキューイング/ループインターチェンジを適用する手法，2 つ目の並列化手法は wave-front 手法を適用する手法であり，どちらの場合もマクロブロック間の依存関係を満たしつつこれらの間の並列性を利用することで並列処理が可能となる．評価に用いる動画像コーデックは，MPEG2 と比較して約 2 倍の符号化効率を持ちワンセグ放送等に用いられている H.264/AVC と，H.264/AVC と同等の品質を持ち Youtube 等でも採用されている動画規格である WebM のビデオコーデック VP8 である．これらの規格により動画像デコーディングを行うプログラムに対して，上記 2 つの並列化手法をそれぞれ適用した．Snapdragon APQ8064 Krait 4 コアを搭載した Nexus7 上で評価を行った結果，ループスキューイング/ループインターチェンジ手法で並列化した場合，並列化箇所のみで逐次実行に比べ 3 コアで 1.33 倍速度向上し，その一方で wave-front 手法では 3 コアで 2.86 倍の速度向上が得られた．同様に Intel(R) Xeon(R) CPU X5670 プロセッサを搭載したマシンで評価を行った結果，ループスキューイング/ループインターチェンジ手法で並列化した場合，並列化箇所のみで逐次実行に比べ 6 コアで 1.82 倍速度向上し，一方で wave-front 手法では 6 コアで 4.61 倍の速度向上が得られた．

This paper proposes a dynamic scheduling algorithm for multiple automatically parallelized or power reduced applications on a multicore smart devices to gain higher performance and lower power comsumption within the application's deadline. This scheduling algorithm uses the information such as time, power, deadline and number of cores for each application, and is composed of three type of scheduling. Using media codec applications as a benchmark, the proposed scheduling gained 18.5% speedup and 28.8% power reduction compared to FIFO scheduling.

主記憶共有型マルチコアプロセッサにおいて，一般にキャッシュコヒーレンシ制御はハードウェアにより実現されている．今後のプロセッサコア数の増加に伴いキャッシュコヒーレンシハードウェアの回路規模は大きくなり，チップへの実装が困難になること，電力消費が大きくなること，設計期間及び開発費用が増大することが懸念されている．本稿ではこのハードウェアコヒーレンシ制御の問題を解決するために，ハードウェアコヒーレンシ制御機構を持たない主記憶共有型ノンコヒーレントキャッシュマルチコアに対して，並列化コンパイラがソフトウェアに対し自動的にコヒーレンシ制御を行う手法を提案する．本手法を実装した OSCAR 自動並列化コンパイラと，4 コアのクラスタを 2 つ持ちクラスタ間ではハードウェアコヒーレンシを持たない情報家電用マルチコア RP2 を用い性能評価を行った．9 つの科学技術計算アプリケーションを対象として評価を行ったところ，4 コアのハードウェアコヒーレンシ制御使用時の性能は平均で 1 コア性能の 2.80 倍であったのに対し，ハードウェアコヒーレンシを使用せず本手法を適用した 4 コア実行時の性能は平均で 1 コア性能の 2.61 倍となりほぼ同等の速度向上が得られ，さらに 8 コアハードウェアコヒーレンシ制御無効時には平均で 1 コア性能の 3.66 倍とスケールアップすることが確認できた．

ソフトウェアの適切な並列化により，マルチコアを搭載したコンピュータシステム上でアプリケーションを高速に動作させることが可能である．並列化されたソフトウェアの挙動や性能を調査する手法として，ソースコードの解読や実行ダンプファイルの収集，プロファイラの利用，デバッガの利用といった方法が挙げられる．しかしこれらの手法ではどのようなタイミングにおいてコンテクストスイッチが発生したのか，システムで発生する事象に対してソフトウェアがどのような影響を受けているかといった情報を得ることは困難である．そこで，本稿では並列化されたプログラムが実際に並列実行される様子をソフトウェアからトレースに任意のアノテーションを挿入可能とする拡張を施した Linux ftrace を用いて解析する手法を提案する．提案手法を用いて，Intel Xeon X7560，ARMv7 の各々のプラットフォームにおいて equake，art，mpeg2enc というベンチマークのトレースを行い，これらのプログラムが実行時に OS からどのような影響を受けているか観測できることが確認できた．また，1 回のアノテーションの挿入を Intel Xeon で 1.07[us]，ARMで4.44[us] で可能であることが確認できた．

A parallelizing compiler cooperative acceleration technique for multicore architecture simulation is proposed in this paper. Profile data of a sequential execution of a target application on a real machine is decomposed into multiple clusters by x-means clustering. Then, sampling points for a detail simulation mode in each cluster are calculated. In addition, a parallelizing compiler generates a parallelized code by taking both of the clustering information and the source code of the target application. The evaluation results show, in the case of the simulation for 16 cores, 437 times speedup is achieved with 0.04% error for equake, and 28 times speedup is achieved with 0.04% error for mpeg2 encoder.

Cyber attacks targeting on companies and government organizations have been increasing and highly developed. An Intrusion Detection System (IDS) is one of efficient solutions to prevent those attacks. An IDS detects illegal network accesses in realtime by monitoring the network and filtering suspicious IP packets. Large processing performance is required for IDSs to process a large number of IP packets in realtime. In order to satisfy this requirement, a latency reduction technique for signature-based IDSs by allocating decomposed signature on multicores is proposed in this paper. The proposed technique is implemented in Suricata, which is an open source IDS, and evaluated it with several data sets, such as DARPA Intrusion Detection Evaluation Data Set. The evaluation results show the proposed techniques with four cores achieves 3.22 times performance improvement in maximum comparing with two cores without signature decomposition.

Fast Fourier Transorm (FFT) is one of the most frequently used algorihtms in many applications including digital signal processing and image processing to compute Descrite Fourier Transform (DFT). Although small size FFT programs must be used in baseband signal processing such as LTE and so on, it's difficult to use special hardwares like DSPs for computing such a small problem because of their relatively large data transfer and control overhead. This paper proposes an automatic parallelization method to generate parallelized programs with low overhead for small size FFTs suited for shared memory multicore processor by applying cache optimization to avoide false sharing between cores. The proposed method has been implemented in OSCAR automatic parallelizing compiler, parallelized small point FFT programs from 32 points to 256 points and evaluated them on RP2 multicore processor having 8 SH-4A cores. It achieved 1.97 times speedup on 2 SH-4A cores and 3.9 times speedup on 4 SH-4A cores in a 256 points FFT program. In addition to the FFT programs, the proposed approach is applied to Fast Hadamard Transform (FHT) which has similar computation to the FFT. The results are 1.91 times speedup on 2 SH-4A cores and 3.32 times speedup on 4 SH-4A cores. It shows effectiveness of the proposed method and easiness of applying the method to many kinds of programs.

本論文では，スマートフォンやタブレット等で広く用いられる Android において，従来マルチコアプロセッサ上での並列化が困難で，その高速化が望まれていた 2D 描画ライブラリ Skia を，OSCAR 自動並列化コンパイラにより，プロファイラ情報に基づいた自動並列化を行う手法を開発したのでその方法を説明する．OSCAR コンパイラは Parallelizable C により記述された逐次プログラムから様々な粒度で並列化解析を行い，自動的に並列化 C ソースを出力する．しかし，Skia は Android 内のライブラリであり，利用する描画命令ルーチンにより制御フローが大きく変化するため，最適な並列化解析を行うことが困難である．そこで，本論文では Skia のような制御フローがコンパイル時に特定できないプログラムに対し，Oprofile を用いて取得したプロファイル結果を OSCAR コンパイラにフィードバックすることで，並列化対象を特定の領域に絞り，高い性能向上が得られる手法を提案する．なお，並列化対象領域が Parallelizable C コードでない場合でも，解析結果により実行コストが大きい部分から Parallelizable C に変更し，チューニングを施すことで並列化が可能となる．本手法を，描画ベンチマークとして広く使われている 0xbench を NVIDIA Tegra3 チップ （ARM Cortex-A9 4 コア） を搭載した Nexus7 上で評価を行った．並列化 Skia の実行においては，並列化部分の速度向上を正確に評価するため， Android を core0 に割り当て，残り 3 コアを Skia が利用できる形とした．評価の結果として，DrawRect で従来の 1.91 倍である 43.57 [fps]，DrawArc で 1.32 倍の 50.98[fps]，DrawCircle2 では 1.5 倍の 50.77[fps] といずれも性能向上結果が得られた．

本論文では，スマートフォンやタブレット等で広く用いられる Android において，従来マルチコアプロセッサ上での並列化が困難で，その高速化が望まれていた 2D 描画ライブラリ Skia を，OSCAR 自動並列化コンパイラにより，プロファイラ情報に基づいた自動並列化を行う手法を開発したのでその方法を説明する．OSCAR コンパイラは Parallelizable C により記述された逐次プログラムから様々な粒度で並列化解析を行い，自動的に並列化 C ソースを出力する．しかし，Skia は Android 内のライブラリであり，利用する描画命令ルーチンにより制御フローが大きく変化するため，最適な並列化解析を行うことが困難である．そこで，本論文では Skia のような制御フローがコンパイル時に特定できないプログラムに対し，Oprofile を用いて取得したプロファイル結果を OSCAR コンパイラにフィードバックすることで，並列化対象を特定の領域に絞り，高い性能向上が得られる手法を提案する．なお，並列化対象領域が Parallelizable C コードでない場合でも，解析結果により実行コストが大きい部分から Parallelizable C に変更し，チューニングを施すことで並列化が可能となる．本手法を，描画ベンチマークとして広く使われている 0xbench を NVIDIA Tegra3 チップ （ARM Cortex-A9 4 コア） を搭載した Nexus7 上で評価を行った．並列化 Skia の実行においては，並列化部分の速度向上を正確に評価するため， Android を core0 に割り当て，残り 3 コアを Skia が利用できる形とした．評価の結果として，DrawRect で従来の 1.91 倍である 43.57 [fps]，DrawArc で 1.32 倍の 50.98[fps]，DrawCircle2 では 1.5 倍の 50.77[fps] といずれも性能向上結果が得られた．

1 チップ内に搭載されるコア数の増加に伴い，アプリケーションからより多くの並列性を抽出し，低オーバーヘッドで利用することがこれらのコアを有効利用するために重要となっている．OSCAR コンパイラによる自動並列化ではより多くの並列性を利用するため，ループやサブルーチン内部の粗粒度並列性を解析し，階層的にタスク定義を行う．この階層的に定義されたタスクをコアを階層的にグルーピングし，コアグループに対して割り当てることにより並列処理を実現する．この階層的なグループ間で独立かつ低コストでバリア同期を実現できるハードウェアが提案され，SH4A プロセッサ 8 コア搭載の情報家電用マルチコア RP2 に実装されている．本稿では，OSCAR API 標準解釈系の階層グループバリア同期 API を RP2 のハードウェアバリア同期機構に対応し評価を行った結果について述べる．8 コアを使用した SPEC CPU 2000 の ART による評価ではソフトウェアでのバリア同期に対し 1.16 倍の性能向上が得られた．

半導体プロセスの微細化に伴いスマートフォン，タブレットに代表される民生機器にも４コア程度のマルチコアSoCの採用が進んでいる．一方，ソフトウェアはマルチコアを活用するための並列化が十分に進んでおらず，対応が望まれている．本稿ではAndroidを搭載した商用スマートデバイスにおいて，一般的な利用範囲におけるマルチコアの活用状況を評価し，並列化されたベンチマークプログラムを用いて実行環境の課題と改善方式を述べた上で，標準APIの仕様を変更すること無く，アプリケーションがオフスクリーンバッファを描画バッファに書くBitBLT処理の並列化を試みた結果を報告する．この処理並列化の結果，アプリケーションから2D描画APIを呼び出すベンチマークテストで約3%のフレームレートの改善を確認した．

A parallelizing compiler cooperative multicore architecture simulation framework, which enables reducing simulation time by a flexible simulation-mode changeover mechanism, is proposed A multicore architecture simulator in this framework has two modes, namely, functional-and-fast simulation mode and cycle-accurate-and slow simulation modes This framework generates appropriate sampling points for cycle-accurate mode and runtime for mode changeover of the simulator depending on a parallelized application by cooperating with a parallelizing compiler The proposed framework is evaluated with EQUAKE from SPEC2000 The evaluation result shows 50 times to 500 times speedup can be achieved within 1 6% error

This paper proposes an automatic decision technique of the number of clusters and samplmg points for an acceleration technique of many-core architecture simulation by statistical methods This techinque, firstly, focuses on a structure of a benchmark program, especially loops The number of sampling points is exploited from iterations of a target loop by statistical methods If the variation of the cost of the iterations is large, these iterations are grouped into clusters Thus, this technique enables higher estimation accuracy with fewer sampling points However, the number of clusters must be decided by hand in our previous works The automatic decision technique of the number of clusters by "x means" is proposed m this paper As a preliminary evaluation of the proposed technique, sequential execution costs of several benchmark programs are estimated As a result, when MPEG2 encoder program with SIF16, which causes large variation among the cost of iterations, is used, 1 92% error is achieved with 14 iterations as sampling pomts of 450 iterations exploited by x-means

The calculation load in the automobile control system is increasing to achive more safety, comfort and energy-saving Accordingly, control processor cores needs high performance However, the improvement of clock frequency in processor cores is difficult, and it is important to use multicore processor Using the multicore for the engine control, performance, development cost, development period, etc are problems be-cause it is difficult to parallelize softwares This paper proposes a parallelization method of the automobile engine control software on the multicore processor, which has only functioned on single-core processors Con-cretely, it is applied restructuring the sequential program for extracting more parallelism, for example inlining functions and duplicating conditional branches, and the OSCAR compiler allows us perform automatic par-allelization and generation of a parallel C program Using proposed method, the automobile engine control software, which is difficult to parallelize manually because of very fine-grained program, is parallelized and give us 1 71x speedup using 2 cores on RP-X multicore It is confirmed that parallehzation of the automobile engine control software is effective

JISX0180:2011 "Framework of establishing coding guidelines for embedded system development" was decided to improve the quality of embeded systems. Parallelizable C has bee also proposed to support exploitation of parallelism by a parallelizing compiler. This paper proposes a definition of Parallelizable C by JISX0180:2011 aiming at the improvement of productivity for embeded multicore developers with parallelizing compilers. An evaluation has been carried out using rewritten programs by the defined coding guideline on ordinary SMPs and a consumer electronics multicore. As the result, 5.54x speedup on IBM p5 550Q (8core), 2.42x speedup on Intel Core i7 960 (4core), and 2.79x speedup on Renesas/Hitachi/Waseda RP2 (4core) have been achieved, respectively.

本稿ではキャッシュやパイプラインまでシミュレーションする詳細シミュレーションと命令実行のみの高速な機能シミュレーションの両方を用いたシミュレーション精度切り替えによるメニーコアシミュレータの高速化手法を提案する．本手法はメニーコアシミュレータ上で並列化プログラムを実行することを前提としており，このプログラムの一部のみを詳細シミュレーションを行うことにより高速化を図る．このとき，詳細シミュレーションを行うサンプリング部分を実機での逐次実行プロファイル情報とプログラム構造から判断し，その分量を統計的手法により決定する．本手法を比較的規則性の高い科学技術計算である SPEC CPU 95のTOMCATV，SWIM で及び SPEC CPU 2000 の ART，EQUAKE を用いて統計学的に算出したサンプリングサイズの値を堺に，実行サイクルが収束していくことを示した．これにより，評価したところ，64 コアかつ精度切換えを想定したシミュレーションで，各アプリケーションにおいて，誤差5%の範囲で約 100 倍の高速化が可能であることを示した．

We developed a software-execution framework for scalable increase of execution speed and low-power consumption based on an octo-core chip multiprocessor named RP2 and an automatic multigrain-parallelizing compiler named OSCAR. Keys to improvement of the performance are reduction of a communication overhead with parallelized tasks and frequent shutdown to waiting cores. For this framework, we developed two schemes: data mapping and timely-power gating. Measurement of the performance for the conventional framework and our proposed framework showed that normalized execution speedup becomes 5.00 when secure AAC-LC encoding is processed in 8-parallel execution. Moreover, applying our timely-power-gating scheme improves power efficiency by 10%.

This paper proposes the "Standard Task Graph Set Ver3" (STG Ver3) to evaluate performance of heuristic and optimization algorithms for the minimum execution time multiprocessor scheduling problem. The minimum execution time multiprocessor scheduling problem is known as a strong NP-hard combinational optimization problem to the public. The STG Ver2 was created by random task execution times and random predecessors. In addition, the STG Ver3 considers parallelism of task graphs and deviation of task execution times to let us understand characteristics of algrithms. This paper describes evaluation results by applying the STG Ver3 to several algorithms. Performance evaluation show that DF/IHS can give us optimal solutions for 87.25%, and PDF/IHS 92.25% within 600 seconds.

This paper proposes the "Standard Task Graph Set Ver3" (STG Ver3) to evaluate performance of heuristic and optimization algorithms for the minimum execution time multiprocessor scheduling problem. The minimum execution time multiprocessor scheduling problem is known as a strong NP-hard combinational optimization problem to the public. The STG Ver2 was created by random task execution times and random predecessors. In addition, the STG Ver3 considers parallelism of task graphs and deviation of task execution times to let us understand characteristics of algrithms. This paper describes evaluation results by applying the STG Ver3 to several algorithms. Performance evaluation show that DF/IHS can give us optimal solutions for 87.25%, and PDF/IHS 92.25% within 600 seconds.

This paper proposes a local memory management scheme for an automatic parallelizing compiler to realize effective use of a limited size of local memory. After the loop aligned decomposition and task scheduling considering data locality and parallelism, the compiler allocates data to the local memory effectively using the task scheduling result. This paper evaluates the proposed scheme on RP2 multicore for consumer electronics which has 8 SH4A processor cores. Each core integrates 32KB of local data memory and 64KB of distributed shared memory. As the results, the proposed scheme using 8 processors gives us about 6.20 times speedup for MPEG2 encoding program, 7.25 times speedup for AAC encoding program and 7.64 times speedup for susan against the sequential execution.

Effective power reduction of an application program on multicore processors requires appropriate power control for each on-chip resource by compilers or users. These low power techniques need an application program interface (API) to realize power control in a user program. This paper proposes a power saving scheme for multicore processors using OSCAR API developed in NEDO "Multicore for Realtime Consumer Electronics" project. The proposed scheme has been implemented in OSCAR compiler to realize the power reduction for fastest execution mode, which minimizes power consumption without performance degradation, and the realtime execution mode to minimize power consumption under realtime constrains. The proposed scheme is evaluated on an 8 cores SH4A multicore processor RP2, newly developed for consumer electronics by Renesas Technology Corp., Hitachi, Ltd. and Waseda University in the above project. For the fastest execution mode, consumed energy was reduced by 13.05% for SPEC2000 art and 3.99% for SPEC2000 equake. Also, for the realtime execution mode, consumed power was reduced by 87.9% for AAC encoder and 73.2% for MPEG2 decoder.

This paper describes a heterogeneous multicore architecture having accelerator cores in addition to general purpose cores, an automatic parallelizing compiler that cooperatively works with the heterogeneous multicore, a heterogeneous multicore architecture simulation environment, and performance evaluation results with the simulation environment. For the performance evaluation, multimedia applications written in C or Fortran, considered with parallelization by the compiler, are used. As a result, the evaluated heterogeneous multicore having two general purpose cores and two accelerator cores achieves 9.82 times speedup from MP3 encoder. This architecture also achieves 14.64 times speedup from JPEG2000 encoder.

This paper describes a heterogeneous multicore architecture having accelerator cores in addition to general purpose cores, an automatic parallelizing compiler that cooperatively works with the heterogeneous multicore, a heterogeneous multicore architecture simulation environment, and performance evaluation results with the simulation environment. For the performance evaluation, multimedia applications written in C or Fortran, considered with parallelization by the compiler, are used. As a result, the evaluated heterogeneous multicore having two general purpose cores and two accelerator cores achieves 9.82 times speedup from MP3 encoder. This architecture also achieves 14.64 times speedup from JPEG2000 encoder.

This paper describes a heterogeneous multicore architecture having accelerator cores in addition to general purpose cores, an automatic parallelizing compiler that cooperatively works with the heterogeneous multicore, a heterogeneous multicore architecture simulation environment, and performance evaluation results with the simulation environment. For the performance evaluation, multimedia applications written in C or Fortran, considered with parallelization by the compiler, are used. As a result, the evaluated heterogeneous multicore having two general purpose cores and two accelerator cores achieves 9.82 times speedup from MP3 encoder. This architecture also achieves 14.64 times speedup from JPEG2000 encoder.

Effective power reduction of an application program on multicore processors requires appropriate power control for each on-chip resource by compilers or users. These low power techniques need an application program interface (API) to realize power control in a user program. This paper proposes a power saving scheme for multicore processors using OSCAR API developed in NEDO "Multicore for Realtime Consumer Electronics" project. The proposed scheme has been implemented in OSCAR compiler to realize the power reduction for fastest execution mode, which minimizes power consumption without performance degradation, and the realtime execution mode to minimize power consumption under realtime constrains. The proposed scheme is evaluated on an 8 cores SH4A multicore processor RP2, newly developed for consumer electronics by Renesas Technology Corp., Hitachi, Ltd. and Waseda University in the above project. For the fastest execution mode, consumed energy was reduced by 13.05% for SPEC2000 art and 3.99% for SPEC2000 equake. Also, for the realtime execution mode, consumed power was reduced by 87.9% for AAC encoder and 73.2% for MPEG2 decoder.

This paper proposes a local memory management scheme for an automatic parallelizing compiler to realize effective use of a limited size of local memory. After the loop aligned decomposition and task scheduling considering data locality and parallelism, the compiler allocates data to the local memory effectively using the task scheduling result. This paper evaluates the proposed scheme on RP2 multicore for consumer electronics which has 8 SH4A processor cores. Each core integrates 32KB of local data memory and 64KB of distributed shared memory. As the results, the proposed scheme using 8 processors gives us about 6.20 times speedup for MPEG2 encoding program, 7.25 times speedup for AAC encoding program and 7.64 times speedup for susan against the sequential execution.

Effective power reduction of an application program on multicore processors requires appropriate power control for each on-chip resource by compilers or users. These low power techniques need an application program interface (API) to realize power control in a user program. This paper proposes a power saving scheme for multicore processors using OSCAR API developed in NEDO "Multicore for Realtime Consumer Electronics" project. The proposed scheme has been implemented in OSCAR compiler to realize the power reduction for fastest execution mode, which minimizes power consumption without performance degradation, and the realtime execution mode to minimize power consumption under realtime constrains. The proposed scheme is evaluated on an 8 cores SH4A multicore processor RP2, newly developed for consumer electronics by Renesas Technology Corp., Hitachi, Ltd. and Waseda University in the above project. For the fastest execution mode, consumed energy was reduced by 13.05% for SPEC2000 art and 3.99% for SPEC2000 equake. Also, for the realtime execution mode, consumed power was reduced by 87.9% for AAC encoder and 73.2% for MPEG2 decoder.

This paper proposes a local memory management scheme for an automatic parallelizing compiler to realize effective use of a limited size of local memory. After the loop aligned decomposition and task scheduling considering data locality and parallelism, the compiler allocates data to the local memory effectively using the task scheduling result. This paper evaluates the proposed scheme on RP2 multicore for consumer electronics which has 8 SH4A processor cores. Each core integrates 32KB of local data memory and 64KB of distributed shared memory. As the results, the proposed scheme using 8 processors gives us about 6.20 times speedup for MPEG2 encoding program, 7.25 times speedup for AAC encoding program and 7.64 times speedup for susan against the sequential execution.

In order to use a large number of processor cores in a chip, hierarchical coarse grain task parallel processing, which exploits whole program parallelism by analyzing hierarchical coarse grain task parallelism inside loops and subroutines, has been proposed and implemented in OSCAR automatic parallelizing compiler. This hierarchical coarse grain task parallel processing defines processor groups hierarchically and logically, and assigns hierarchical coarse grain tasks to each processor group. A light-weight and scalable barrier synchronization mechanism considering hierarchical processor grouping, which supports hierarchical coarse grain task parallel processing, is developed and implemented into RP2 multicore processor having eight SH4A cores with support by NEDO "Multicore Technology for Realtime Consumer Electronics". This barrier mechanism is proposed and evaluated in this paper. The evaluation using AAC encoder program by 8 cores shows our barrier mechanism achieves 16% better performance than software barrier.

This paper describes a restriction on pointer usage in C language for parallelism extraction by an automatic parallelizing compiler. By rewriting programs to satisfy the restriction, automatic parallelization using flow-sensitive, context-sensitive pointer analysis on an 8 cores SMP server achieved 3.80 times speedup for SPEC2000 art, 6.17 times speedup for SPEC2006 lbm and 5.14 times speedup for MediaBench mpeg2enc against the sequential execution, respectively.

This paper describes a restriction on pointer usage in C language for parallelism extraction by an automatic parallelizing compiler. By rewriting programs to satisfy the restriction, automatic parallelization using flow-sensitive, context-sensitive pointer analysis on an 8 cores SMP server achieved 3.80 times speedup for SPEC2000 art, 6.17 times speedup for SPEC2006 lbm and 5.14 times speedup for MediaBench mpeg2enc against the sequential execution, respectively.

In order to use a large number of processor cores in a chip, hierarchical coarse grain task parallel processing, which exploits whole program parallelism by analyzing hierarchical coarse grain task parallelism inside loops and subroutines, has been proposed and implemented in OSCAR automatic parallelizing compiler. This hierarchical coarse grain task parallel processing defines processor groups hierarchically and logically, and assigns hierarchical coarse grain tasks to each processor group. A light-weight and scalable barrier synchronization mechanism considering hierarchical processor grouping, which supports hierarchical coarse grain task parallel processing, is developed and implemented into RP2 multicore processor having eight SH4A cores with support by NEDO "Multicore Technology for Realtime Consumer Electronics". This barrier mechanism is proposed and evaluated in this paper. The evaluation using AAC encoder program by 8 cores shows our barrier mechanism achieves 16% better performance than software barrier.

Multicore processors have attracted much attention to handle the increase of power consumption, the slowdown of improvement of processor clock speed, and the increase of hardware/software developing period. Also, speeding up multimedia applications is required with the progress of the consumer electronics devices like mobile phones, digital TV and games. This paper describes parallelization methods of multimedia applications on the multicore processors. Especially in this paper, MPEG2 encoding and MPEG2 decoding are selected as examples of video sequence processing, MP3 encoding is selected as an example of audio processing, JPEG 2000 encoding is selected as an example of picture processing. OSCAR multigrain parallelizing compiler parallelizes these media applications using newly developed multicore API. This paper evaluates parallel processing performances of these multimedia applications on the FR1000 multicore processor developed by Fujitsu Ltd, and the RP1 multicore processor jointly-developed by Waseda University, Renesas Technology Corp. and Hitachi Ltd.

This paper describes a heterogeneous multi-core processor (HMCP) architecture which integrates general purpose processors (CPU) and accelerators (ACC) to achieve high-performance as well as low-power consumption for SoCs of embedded systems. Memory architecture of CPUs and ACCs were unified to improve programming and compiling efficiency. For preliminary evaluation of the HMCP architecture, AAC-LC stereo audio encoding is parallelized on a heterogeneous multi-core having homogeneous processor cores and dynamic reconfigurable processor (DRP) accelerator cores. The performance evaluation shows that 54x AAC encoding is achieved on the chip with two CPUs at 600MHz and two DRPs at 300MHz, which realizes encoding of a whole CD in 1-2 minutes.

This paper proposes a static scheduling scheme for hierarchical coarse grain task parallel processing on a heterogeneous multicore processor. A heterogeneous multicore processor integrates not only general purpose processors but also accelerators like dynamically reconfigurable processors (DRPs) or digital signal processors (DSPs). Effective usage of these accelerators allows us to get high performance and low power consumption at the same time. In the proposed scheme, the compiler extracts parallelism using coarse grain parallel processing and assigns tasks considering characteristics of each core to minimize the execution time of an application. Performance of the proposed scheme is evaluated on a heterogeneous multicore processor using MP3 encoder. Hetero-geneous configurations give us 12.64 times speedup with two SH4As and two DRPs and 24.48 times speedup with four SH4As and four DRPs against sequential execution with one SH4A core.

Multicore processors are getting introduced for performance improvement and reduction of power dissipation in various IT fields, such as consumer electronics, PCs, servers and super-computers. Especially, heterogeneous multicores have attracted much attention in consumer electronics to achieve higher performance per watt. In order to satisfy the demand for the high performance, low power dissipation and high software productivity, Parallelizing compilers for both parallelization and Frequency and Voltage control are required. This paper describes the evaluation results of compiler control power saving for a heterogeneous multicore processor which integrates upto 4 general purpose embedded processor Renesas SH4As and 4 accelerator core like dynamically reconfigureable processors Hitachi FE-GAs. Performance evaluation shows the heterogeneous multicore gave us 24.32 times speed up against sequential processing and 28.43% energy savings for MP3 encoding program without performance degradation.

4320MIPS 4-processor SoC that provides with low power consumption and high performance was designed using 90nm process. The 32KB-data cache is built into each processor, and the module to maintain the coherency of the data cache between processors is built into. A low electric power is achieved by frequency control of each processor according to amount of processing and adopting sleep mode that maintains coherency of the data cache between processors.

Currently, multicore processors are becoming ubiquitous in various computing domains, namely consumer electronics such as games, car navigation systems and mobile phones, PCs, and supercomputers. This paper describes parallelization of media processing programs written in restricted C language by OSCAR multigrain parallelizing compiler and SMP processing performance on RP1 4-core SH-4A (SH-X3) multicore processor developed by Renesas Technology Corp. and Hitachi, Ltd. based on standard OSCAR multicore memory architecture as a part of NEDO "Research and Development of Multicore Technology for Real Time Consumer Electronics Project". Performance evaluation shows OSCAR compiler achieved 3.34 times speedup using 4 cores against using 1 core for AAC audio encoder.

4320MIPS 4-processor SoC that provides with low power consumption and high performance was designed using 90nm process. The 32KB-data cache is built into each processor, and the module to maintain the coherency of the data cache between processors is built into. A low electric power is achieved by frequency control of each processor according to amount of processing and adopting sleep mode that maintains coherency of the data cache between processors.

Currently, multicore processors are becoming ubiquitous in various computing domains, namely consumer electronics such as games, car navigation systems and mobile phones, PCs, and supercomputers. This paper describes parallelization of media processing programs written in restricted C language by OSCAR multigrain parallelizing compiler and SMP processing performance on RP1 4-core SH-4A (SH-X3) multicore processor developed by Renesas Technology Corp. and Hitachi, Ltd. based on standard OSCAR multicore memory architecture as a part of NEDO "Research and Development of Multicore Technology for Real Time Consumer Electronics Project". Performance evaluation shows OSCAR compiler achieved 3.34 times speedup using 4 cores against using 1 core for AAC audio encoder.

Multicore systems have been attracting much attention for performance, low power consumption and short hardware/software development period. To take the full advantage of multiprocessor systems, parallelizing compilers serve important roles. On multicore processor, a memory wall caused by the speed gap between processor core and memory is also serious problem. Therefore, it is important for performance improvement to use fast memolies like cache and local memory nearby a processor effectively. This paper proposes a local memory management scheme for coarse grain task parallel processing. In the evaluation using SPeC 95fp tomcatv, the proposed scheme using 8 processors achieved 19.6 times speedup against the sequantial execution without the proposed scheme on the OSCAR multicore processor by the effective use of local memories.

Multicore processors have attracted much attention to handle the increase of power consumption along with the increase of integration degree of semiconductor devices, the slowdown of improvement of processor clocks, and the increase of hardware/software developing period. Also, speeding up multimedia applications is required with the progress of the consumer electronics like mobile phones, digital TV and games. This paper describes parallelization methods of multimedia applications on the multicore processors. Especially in this paper, MPEG2 encoding and MPEG2 decoding are selected as examples of video sequence processing, MP3 encoding is selected as an example of audio processing, JPEG 2000 encoding is selected as an example of picture processing. OSCAR multigrain parallelizing compiler automatically parallelizes these media applications. This paper evaluates parallel processing performances of these multimedia applications on the OSCAR multicore processor, and the IBM p5 550Q Power5+ 8 processors SMP server. On the OSCAR multicore processor, the parallel execution with the proposed method of managing local memory and optimizing data transfer using 4 processors, gives us 3.81 times speedup for MPEG2 encoding, 3.04 times speedup for MPEG2 decoding, 3.09 times speedup for MP3 encoding, 3.79 times speedup for JPEG 2000 encoding against the sequential execution. On the IBM p5 550Q Power5+ 8 processors server, the parallel execution using 8 processors gives us 5.19 times speedup for MPEG2 encoding, 5.12 times speedup for MPEG2 decoding, 3.69 times speedup for MP3 encoding, 4.32 times speedup for JPEG 2000 encoding against the sequential execution.

Along with the popularization of multiprocessors and multicore architectures, automatic parallelizing compiler, which can realize high effective performance and low power comsumption, becomes more and more important in various areas from high performance computing to embedded computing. OSCAR compiler realizes multigrain automatic parallelization, which can exploit parallelism and data locality from the whole of the program. This paper describes C language support in OSCAR compiler. For rapid support of C language, restricted C language is proposed. In the preliminary performance evaluation of automatic parallelization using following media applications as MPEG2 encode, MP3 encode, and AAC encode, Susan (smoothing) derived from MiBench, and Art from SPEC2000, OSCAR compiler achieved 7.49 times speed up in maximum for susan (smoothing) against sequential execution on IBM p5 550 server having 8 processors, and 3.75 times speed up in maximum for susan (smoothing) too against sequential execution on Sun Ultra80 workstation having 4 processors.

Currently, multiprocessor systems, especially multicore processors, are attracting much attention for performance, low power consumption and short hardware/software development period. To take the full advantage of multiprocessor systems, parallelizing compilers serve important roles. This paper describes the execution performance of OSCAR multigrain parallelizing compiler using coarse grain task parallelization and near fine grain parallelization in addition to loop parallelization, on the latest SMP servers and a SMP embedded multicore. The OSCAR compiler has realized the automatic determination of parallelizing layer, which decides the suitable number of processors and parallelizing technique for each nested part of the program, and global cache memory optimization over loops and coarse grain tasks. In the performance evaluation using 10 SPEC CFP95 benchmark programs and 4 SPEC CFP2000, OSCAR compiler gave us 2.74 times speedup compared with IBM XL Fortran compiler 10.1 on IBM p5 550Q Power5+8 processors server, 4.82 times speedup compared with IBM XL Fortran compiler 8.1 on IBM pSeries690 Power4 24 processors server. OSCAR compiler can be also applied for NEC/ARM MPCore ARMv6 4 processors low power embedded multicore, using subset of OpenMP libraries and g77 compiler. In the evaluation using SPEC CFP95 benchmarks with reduced data sets, OSCAR compiler achieved 4.08 times speedup for tomcatv, 3.90 times speedup for swim, 2.21 times speedup for su2cor, 3.53 times speedup for hydro2d, 3.85 times speedup for mgrid, 3.62 times speedup for applu and 3.20 times speedup for turb3d against the sequential execution.

Along with the advancement of integration technology of semiconductor devices, to overcome the increase of power consumption, the slowdown of processor effective performance improvement rate, and the increase of period for hardware/software developing transistors integrated on to a chip, multicore processors have attracted much attention as a next-generation microprocessor architecture. However, the memory wall caused by the gap between memory access speed and processor core speed is getting a serious problem also on the multicore processors. Therefore, the effective use of fast memories like cache and local memory nearby a processor is important. Considering these problems, the authors have proposed the OSCAR multicore processor architecture which cooperates with OSCAR multigrain parallelizing compiler and aims at developing a processor with high effective performance and good cost performance. The OSCAR multicore processor has local data memory (LDM) for processor private data, distributed shared memory (DSM) having two ports for synchronization and data transfer among processor cores, centralized shared memory (CSM) to support dynamic task scheduling, and data transfer unit (DTU) which transfers data asynchronously and aims at overlapping data transfer overhead. This paper describes data localization scheme that aimed at improving the effective use of LDM and DSM using coarse grain task parallel processing and compiler-controlled LDM and DSM management scheme. As the results, the proposed scheme gives us 7.1 times speedup for MP3 encoding program, 6.3 for MPEG2 encoding program and 3.8 for JPEG2000 encoding program against the sequential execution without the proposed scheme on 8 processors automatically.

Along with the increase of integration degree of semiconductor devices, to overcome the increase of power consumption, the slowdown of improvement of processor effective performance, and the increase of period for hardware/software developing transistors integrated on to a chip, multicore processors, have attracted much attention as a next-generation microprocessor architecture. However, the memory wall caused by the gap between memory access speed and processor core speed is still a serious problem also on the multicore processors. Therefore, the effective use of fast memories like cache and local memory nearby processor is important for reducing large memory access overhead. Futhermore, hiding data transfer overhead among local or distributed shared memories of processors and centralized shared memory is important. On the memory architechture, the data transfer is specified. Considering these problems, the authors have proposed the OSCAR multicore processor architecture which cooperates with OSCAR multigrain parallelizing compiler and aims at developing a processor with high effective performance and good cost performance computer system. The OSCAR multicore processor has local data memory (LDM) for processor private data, distributed shared memory (DSM) having two ports for synchronization and data transfer among processor cores, centralized shared memory (CSM) to support dynamic task scheduling, and data transfer unit (DTU) which transfers data asynchronously and aims at overlapping data transfer overhead. This paper proposes and evaluates a static data transfer scheduling algorithm aiming at overlapping data transfer overhead. As the results, the proposed scheme controlled by OSCAR compiler gives us 2.86 times speedup using 4 processors for JPEG2000 encoding program against the ideal sequential execution assuming that the all data can be assigned to the local memory.

This paper proposes a static scheduling scheme for coarse grain tasks on a heterogeneous chip multi processor which integrates not only general purpose processors but also accelerators like DRP or DSP. A heterogeneous chip multi processor allows us to get high performance by using the accelerators and to save energy by frequency/voltage control by the compiler. In this scheme, the compiler aim to minimize the execution time of an application in consideration of the characteristic in each core. Performance of the proposed scheme is evaluated on a heterogeneous chip multi processor which has 4 general purpose processors and 2 accelerators using MP3 encoder and gives us 8.8 times speedup against sequencial execution without the proposed scheme.

This paper proposes a heterogeneous chip multi-processor (HCMP) that possesses different types of processing elements (PEs) such as CPUs as general-purpose processors, as well as digital signal processors or dynamic reconfigurable processors (DRPs) as special-purpose processors. The HCMP realizes higher performance than conventional single-core processors or even homogeneous multi-processors in some specific applications such as media processing, with low operating frequency supplied, which results in lower power consumption. In this paper, the performance of the HCMP is analyzed by studying parallelizing scheme and power control scheme of an MP3 audio encoding program and by scheduling the program onto the HCMP using these two schemes. As a result, it is confirmed that an HCMP, consisting of three CPUs and two DRPs, outperforms a single-core processor with one CPU by a speed-up factor of 16.3, and a homogeneous multi-processor with 5 CPUs by a speed-up factor of 4.0. It is also confirmed that the power control on the HCMP results in 24% power reduction.

This paper evaluates performance of a fast sequential circuit simulation scheme using the loop free code without the array indirect accesses. This scheme allows us to get several tens of times higher processing performance than SPICE version 3f5 on a WS and a PC. The array indirect accesses for the sparse matrix solution in SPICE have been one of the factors that prevents from efficient processing. This paper describes the circuit simulation scheme using loop free code without any array indirect accesses and its performance evaluation shows the scheme gives us 2 to 110 times better performance than SPICE3f5 on a WS and a PC. The performance by reducing the memory accesses overhead significantly.

The needs for automatic parallelizing compilers are getting larger with widly use of multiprocessor systems. However, the loop parallelization techniques are almost matured and new generation of parallelization methods like multi-grain parallelization are required to achieve higher effective performance. This paper describes the performance of OSCAR multigrain parallelizing compiler that uses the coarse grain task parallelization and the near fine grain parallelization in addition to the loop parallelization. OSCAR compiler realizes the following two important techniques. The first is the automatic determination scheme of parallelizing layer, which decides the number of processors and parallelizing technique for each part of the program. The other is global cache memory optimization among loops and coarse grain tasks. In the evaluation using SPEC95FP benchmarks, OSCAR compiler gave us 4.78 times speedup compared with IBM XL Fortran compiler 8.1 on IBM pSeries690 Power4 24 processors server, 2.40 times speedup compared with Intel Fortran Itanium Compiler 7.1 on SGI Altix3700 Itanium2 16 processors server, 1.90 times speedup compared with Sun Forte compiler 7.1 on Sun Fire V880 Ultra SPARC III Cu 8 processors server.

This paper proposes a coarse grain task parallel processing scheme for MPEG2 encoding using data localization which optimizes execution efficiency assigning coarse grain tasks accessing the same array data on the same processor consecutively on a chip multiprocessor and data transfer overlapping technique which minimize the data transfer overhead by overlapping task execution and data transfer. Performance of the proposed scheme is evaluated. As the evaluation result on an OSCAR chip multiprocessor architecture, the proposed scheme gave us 1.24 times speedup for 1 processor, 2.47 times speedup for 2 processors. 4.57 times speedup for 4 processors, 7.97 times speedup for 8 processors and 11.93 times speedup for 16 processors respectively against the sequential execution on a single processor without the proposed scheme.

Recently, Chip Multiprocessor (CMP) architecture has attracted much attention as a next-generation micro-processor architecture, and many kinds of CMP have widely developed. However, these CMP architectures still have the problem of effective use of memory system nearby processor cores such as cache and local memory. On the other hand, the authors have proposed OSCAR CMP, which cooperatively works with multigrain parallel processing, to achieve high effective performance and good cost effectiveness. To overcome the problem of effective use of cache and local memory, OSCAR CMP has local data memory (LDM) for processor private data and distributed shared memory (DSM) having two ports for synchronization and data transfer among processor cores, centralized shared memory (CSM) to support dynamic task scheduling, and data transfer unit(DTU) for asynchronous data transfer. The multigrain parallelizing compiler uses such memory architecture of OSCAR CMP with data localization scheme that fully uses compile time information. This paper proposes a coarse grain task static scheduling scheme considering data localization using live variable analysis. Data is transferred in burst mode using automatically generated DTU instructions.

This paper describes performance of multigrain parallel processing of SPEC CFP 95 on OSCAR Chip Multi Processor (OSCAR CMP). OSCAR multigrain parallelizing compiler, which exploits statement level near-fine grain parallelism, loop iteration level parallelism and coarse grain parallelism hierarchically, allows us to fully control hardware on OSCAR CMP. Also, this cooperation realizes high software productivity and effective use of hardware resources. Performance of multigrain parallel processing of SPEC CFP 95 benchmark programs on OSCAR CMP with 8 processor cores and centralized shared memory were 2.03 to 7.79 times speedup against sequential execution using 400MHz clock cycles for embedded use and 1.89 to 7.05 times speedup against sequential execution using 2.8GHz clock cycles for high-end use.

Recently, many people are getting to enjoy multimedia applications with image and audio processing on PCs, mobile phones and PDAs. For this situation, development of low cost, low power consumption and high performance processors for multimedia applications has been expected. To satisfy these demands, chip multiprocessor architectures which allows us to attain scalability using coarse grain level parallelism and loop level parallelism in addition to instruction level parallelism are attracting much attention. However, in order to extract much performance from chip multiprocessor architectures efficiently, highly sophisticated technique is required such as decomposing a program into adequate grain of tasks and assigning them onto processors considering parallelism and data locality of target applications. This paper describes a parallel processing scheme for MPEG2 encoding using data localization which improve execution efficiency assigning coarse grain tasks sharing same data on a same processor consecutively for a chip multiprocessor, and evaluate its performance. As the evaluation result on OSCAR CMP using 8 processors, proposed scheme gives us 1.64 times speedup against loop parallel processing, and 6.82 times speedup against sequential execution time.

On the shared multi processor system used in current computing servers, the increase of memory access overhead with the speedup of CPU interfere to get the scalable performance improvement with the increase of the processors. In order to get scalable performance improvement, this paper proposes and evaluates the static scheduling algorithm which reduces the memory access overhead by using cache prefetch to overlap of data transfer and task processing. The proposed algorithm is used in static scheduling stage in a compiler, moreover the compiler generates a OpenMP parallelized Fortran program with prefetch directives for SUN Forte compiler for Sun Fire V880 server. Performance evaluation shows that the proposed algorithm gave us super linear speedup compared with sequential processing without prefetching by Sun Forte compiler such as 13.9 times speedup on 8 processors for SPEC95fp tomcatv program and 22.3 times speedup on 8 processors for SPEC95fp swim program. Futhermore, compared with automatic prefetching by SUN Forte compiler using the same number of processors, this algorithm shows that 1.1 times speedup on 1 processor, 3.86 times speedup on 8 processors for SPEC95fp tomcatv and 1.44 times speedup on 1processor, 1.85 times speedup on 8 processors for SPEC95fp swim.

Recently, chip multiprocessor architecture that contains multiple processors on a chip becomes popular approach even in commercial area. The authors have proposed OSCAR chip multiprocessor (OSCAR CMP) that is aimed at exploiting multiple grains of parallelism hierarchically from a sequential program on a chip. OSCAR CMP has local data memory (LDM) for processor private data and distributed shared memory having two ports for processor shared data to control data allocation by a compiler appropriately. This paper describes data localization scheme for OSCAR CMP which exploits data locality by assigning coarse grain tasks sharing same data on a same processor consecutively. In addition, OSCAR CMP using data localization scheme is compared with shared cache architecture and snooping cache architecture. Then, current naive code generation for OSCAR CMP is considered using evaluation results.

Recently, multimedia applications with visual and sound processing are popular on mobile phones and PDAs. To satisfy the needs for efficient multimedia processing, development of low cost, low power consumption and high performance processors for multimedia applications has been expected. Chip multiprocessor architectures which allows us to attain scalability using coarse grain level parallelism and loop level parallelism in addition to instruction level parallelism are attracting much attention. However, to realize efficient processing on chip multiprocessor architectures, parallel processing techniques such as decomposing a program into adequate tasks considering characteristics of a program and assigning these tasks onto processors are essential. This paper describes a parallel processing scheme for MPEG2 encoding for a chip multiprocessor and its performance.

Recently. Chip Multiprocessor(GMP)architecture has attracted much attention as a next-generation microprocessor architecture. and many kinds of GMP have widely developed. However, these GMP architectures still have the problem of effective use of memory system nearby processor cores such as cache and local memory. On the other hand, the authors have proposed OSCAR GMP. which cooperatively works with multigrain parallel processing, to achieve high effective performance and good cost effectiveness. To overcome the problem of effective use of cache and local memory. OSCAR GMP has local data memory(LDM)for processor private data and distributed shared memory(DSN) having two por for synchronization and data transfer among processor cores, in addition to centralized shared memory (CSM). The multigrain parallelizing compiler uses such memory architecture of OSCAR GMP with data localization scheme that fully uses compile time information. This paper proposes a coarse grain task static scheduling scheme considering data localization using live variable analysis. Furthermore, data transfer between CSM and LDM insertion scheme using information of live variable analysis is also described. This data localization scheme is implemented on OSCAR FORTRAN multigrain parallelizing compiler and is evaluated on OSCAR GMP using Tomcatv form SPEC fp 95 benchmark suite. As the results, the proposed scheme gives us about 1.3 times speedup using 20 clocks as the access latency of CSM, and about 1.6 times using 40 clocks as the access latency of CSM respectively against without data localization scheme.

This paper describes multigrain parallel processing on OSCAR Chip Multiprocessor (OSCAR CMP). The aim of OSCAR CMP is to achieve both of scalable performance improvement with effective use of huge number of transistors on a chip and high efficiency of application development with compiler supports. OSCAR CMP integrates simple single issue processors having local data memory for private data recognized by compiler, distributed shared data memory for optimal use of data locality over different loops. The compiler controllable data transfer unit for overlapping data transfer, and the multigrain parallelizing compiler, which exploits statement level near-fine grain parallelism, loop iteration level parallelism and coarse grain task parallelism hierarchically, fully controls these hardwares. Performance of multigrain parallel processing on OSCAR CMP is evaluated using SPEC fp 2000/95 benchmark suite. When microSPARC like single issue core is used, OSCAR CMP having four CPU cores gives us 2.98 times speedup in HYDRO2D, 3.84 times in TOMCATV, 3.84 times in MGRID, 3.97 times in SWIM, 2.36 times in FPPPP, 2.88 times in TURB3D, 2.64 times in SU2COR, 2.29 times in APPLU and 1.77 times in APSI.

With the recent increase of multimedia contents using JPEG and MPEG, low cost, low power consumption and high performance processors for multimedia application have been expected. Particularly, single chip multiprocessor architectures having simple processor cores that will be able to attain scalability and cost effectiveness are attracting much attention to develop such processors. Single chip multiprocessor architectures allow us to exploit coarse grain task level and loop level parallelism in addition to the instruction level parallelism, so parallel processing technology is indispensable to allow us scalable performance improvement. This paper describes a multigrain parallel processing scheme for motion vector estimation for a single chip multiprocessor and its performance is evaluated.

Coarse grain task parallel processing, which exploits parallelism among loops, subroutines and basic blocks, is getting more important to attain performance improvement on multiprocessor architectures. To efficiently implement the coarse grain task parallel processing. it is important to analyze various processor overhead quantitatively. This paper evaluates overheads of barrier synchronization, thread fork/join and L2 cache miss penalty are using performance measurement mechanisms to analyze the performance improvements by OSCAR Fortran compiler on Sun Ultra80, IBM RS6000 and SGI Origin2000.

With the recent increase of multimedia contests using JPEG and MPEG, low cost, low power consumption and high performance processors for multimedia have been expected. Particularly, single chip multiprocessor architecture having simple processor cores is attracting much attention to develop such processors. This paper describes multigrain parallel processing scheme for a JPEG encoding program for OSCAR type single chip multiprocessor and its performance. The evaluation shows an OSCAR type single chip multiprocessor having four single-issue simple processor cores gave us 3.59 times speed-up than sequencial execution and 2.87 times speed-up than OSCAR type single chip multiprocessor that has a four-issue UltraSPARC-II type super-scaler processor core.

With the recent increase of multimedia contents, such as JPEG and MPEG data, low cost and low power consumption processors that can process these multimedia contents efficiently are expected. In such microprocessors, single chip multiprocessor architecture having simple processor cores is attracting much attention. Considering the above facts, this paper evaluate a JPEG encoding program on OSCAR type single chip multiprocessor architecture using near fine grain parallel processing for 8×8 pixel block that is a fundamental part of JPEG algorithm. The evaluation shows an OSCAR type single chip multiprocessor having four single-issue simple processor cores gives 2.32 times speedup than four-issue UltraSPARC-II type super-scaler processor.

Effective use of cache memory based on data locality is getting more important with increasing gap between the processor speed and memory access speed. As to parallel processing on multiprocessor systems, it seems to be difficult to achieve large performance improvement only with the conventional loop iteration level parallelism. This paper proposes a coarse grain task static scheduling scheme considering cache optimization. The proposed scheme is based on the macro data flow parallel processing that uses coarse grain task parallelism among tasks such as loop blocks, subroutines and basic blocks. It is implemented on OSCAR Fortran multigrain parallelizing compiler and evaluated on Sun Ultra80 four-processor SMP machine, using swim and tomcatv from the SPEC fp 95 benchmark suite. As the results, the proposed scheme gives us 4.56 times speedup for swim and 2.37 times for tomcatv respectively against the Sun Forte HPC 6 loop parallelizing compiler on 4 processors.

With continuously increase of transistors integrated onto a chip, it has been a very important how to achieve scalable performance improvement using these transistors effectively. Especially, exploiting different grains of parallelism in addition to instruction level parallelism and effective use of this parallelism in a single chip is getting more important. To this end, a single chip multiprocessor(SCM)architecture that contains multiple processor cores has been attracted much attention. To decide suitable SCM processor core architecture for multigrain parallel processing, this paper evaluates several SCM architectures which have different instruction issue widths and numbers of global shared register file for near fine grain parallel processing, which is one of the key issues in multigrain parallel processing.

Multi-grain parallel processing is proposed to exploit an inherent parallelism in application programs as much as possible. Although this method can be realized on various architectures, a dedicated multiprocessor architecture is required for achieving the maximum performance. Multiprocessor system ASCA (Advanced Scheduling oriented Computer Architecture) is proposed for efficient execution of multi-grain parallel processing. It provides various mechanisms for this purpose including a dedicated memory structure which is used efficiently both for multi-grain parallel processing A memory access analyzer is developed for investigating memory access characteristics in multi-grain parallel processing. Based on a result of analysis on a real application with multi-grain parallel processing efficient memory structure for ASCA is discussed.

Advances in semiconductor technology allows us to integrate a lot of integer and floating point execution units, memory or processors on a single chip. To use these resources effectively, many researches on next generation microprocessor architectures and its software, especially compilers have been performed. In these next generation microprocessor architectures, a single chip multiprocessor (SCM) using multigrain parallel processing, which hierarchically exploits different level of parallelism from the whole program, is one of the most promising architectures. This paper evaluates performance of the SCM architectures for near fine grain parallel processing, which is one of the key issues in multigrain parallel processing, using several real application programs.

Currently, peak performances of supercomputers attain TELOPS order. It seems that the peak performances will continue by increase.However, supercomputers have a problem that enlargement of the world is very difficult because of relatively low cost performance and difficulty of use. In microprocessor, limitations of extraction of instruction level parallelism being used by super scalar and VLIW architecture are getting clear and single chip multiprocessor is received much attention as one of next generation processor architechture.In order to improve effective performance or cost performance, and ease of use, the authors have been proposing a Multigrain Automatic Parallelizing Compilation scheme. The multigrain parallel processing is a method which extract all parallelism from a program, such as coarse grain parallelism among subroutines, loops, and basic blocks, medium grain parallelism among loop iterations, and fine grain parallelism among instructions and statements.This paper shows effectiveness of multigrain parallel processing using OSCAR multigrain FORTRAN parallelization compiler using fluid flow problem solver ARC2D(Perfect Benchmark)as an example.

With the increase of the number of transistors integrated on a chip, how to use transistors efficiently and improve effective performance of a processor is getting an important problem. However, it has been thought that superscalar and VLIW which have been popular architectures would have difficulty to obtain scalable improvement of effective performance because of limitation of instruction level parallelism.To cope with this problem, the authors have been proposing a single chip multiprocessor(SCM)approach to use multi grain parallelism inside a chip, which hierarchicaly exproits loop parallelism with large parallelism and coarse grain parallelism among subroutines, loops and basic blocks in addition to instruction level parallelism.This paper describes preliminary evaluation of effectiveness of single chip multiprocessor architecture with a shared cache, global registers, distributed shared memory and/or local memory as the first step of research on SCM architecture for supporting effective realization of multi grain parallel processing.

Cache optimizations by a compiler for a single processor machine have been mainly applied to a singlenested loop.On the contrary, this paper proposes a cache optimization scheme using earliest executable condition analysis for FORTRAN programs on a single processor system.OSCAR FORTRAN multi-grain automatic parallelizing compiler decomposes a FORTRAN program into three types of macrotasks(MT), such as loops, subroutines and basic blocks, and analyzes the earliest executable condition of each MT to extract coarse grain parallelism among MTs and generates a macrotask graph(MTG).The MTG represents data dependence and extended control dependence among MTs and an information of shared data among MTs.By using this MTG, a compiler realizes global code motion to use cache effectively.The code motion technique moves a MT, which accesses data accessed by a precedent MT on MTG, immediately after the precedent MT to increase a cache hit rate. This optimization is realized using OSCAR multi-grain compiler as a preprocessor to output an optimized sequential FORTRAN code.A performance evaluation shows about 62% speed up compared with original program on 167MHz UltraSPARC.

Currently, difficulty of enlargement of the world market for supercomputers caused by cost-performance, which does not seem excellent for real effective performance, and need of high experience for parallel tuning is getting a problem. Also, in general purpose microprocessors, limitations of extraction of instruction level parallelism being used by super-scalar and VLIW architectures are getting clear. This paper describes a multigrain compilation technology and architectural support for it as an approach to cope with the above difficulites and develop user friendly and excellent cors performance supercomputers and single chip multiprocesors.

Multi-grain parallel processing is proposed to exploit an inherent parallelism in application programs as much as possible. Although this method can be realized on various architectures, a dedicated multiprocessor architecture is required for achieving the maximum performance. Multiprocessor system ASCA (Advanced Scheduling oriented Computer Architecture) is proposed for efficient execution of multigrain parallel processing. It provides various mechanisms for this purpose including a dedicated communication mechanism which is used efficiently both for coarse grain and near fine grain parallel processing, and a custom designed processor for static scheduling.

Resently, multiprocessor systems having data transfer unit which can transfer data asynchronously with CPU are getting popular. We can hide data transfer overhead by using these data transfer unit. However, it is difficult by users to write a optimized program considering overlapping of data transfers and task processing. To hide overhead caused by data transfers, this paper proposes dynamic scheduling algorithm considering data pre-loading and post-storing for overlapping of data transfers and task processing. Preliminary performance evaluations by simulation show that the proposed scheduling scheme can reduce execution time 26% comparing with the scheduling scheme without pre-loading and post-storing.